diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index 9974c977..4ca0f3c8 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE C */ -/* 6.2.0 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -94,6 +94,9 @@ /* update EPK typedef, */ /* update version numbers, */ /* resulting in version 6.2.0 */ +/* 03-08-2023 Tiejun Zhou Modified comment(s), */ +/* update patch number, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -133,7 +136,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 2 -#define THREADX_PATCH_VERSION 0 +#define THREADX_PATCH_VERSION 1 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/common/src/tx_thread_wait_abort.c b/common/src/tx_thread_wait_abort.c index e5fbffae..9c3b268f 100644 --- a/common/src/tx_thread_wait_abort.c +++ b/common/src/tx_thread_wait_abort.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_wait_abort PORTABLE C */ -/* 6.1 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,9 +68,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ /* resulting in version 6.1 */ +/* 03-08-2023 Scott Larson Check if thread is coming out */ +/* of suspension elsewhere, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) @@ -131,6 +134,18 @@ ULONG suspension_sequence; /* Restore interrupts. */ TX_RESTORE #endif + } + else if(thread_ptr -> tx_thread_suspend_cleanup == TX_NULL) + { + /* Thread is coming out of suspension elsewhere. */ + +#ifndef TX_NOT_INTERRUPTABLE + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif } else { @@ -167,13 +182,8 @@ ULONG suspension_sequence; TX_RESTORE #endif - /* Call any cleanup routines. */ - if (suspend_cleanup != TX_NULL) - { - - /* Yes, there is a function to call. */ - (suspend_cleanup)(thread_ptr, suspension_sequence); - } + /* Call cleanup routine. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); } /* If the abort of the thread wait was successful, if so resume the thread. */ diff --git a/common_modules/module_manager/src/txm_module_manager_stop.c b/common_modules/module_manager/src/txm_module_manager_stop.c index 35206423..ec3385f7 100644 --- a/common_modules/module_manager/src/txm_module_manager_stop.c +++ b/common_modules/module_manager/src/txm_module_manager_stop.c @@ -64,7 +64,7 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance) /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_stop PORTABLE C */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -116,8 +116,8 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance) /* 03-02-2021 Scott Larson Modified comments, fix */ /* object delete underflow, */ /* resulting in version 6.1.5 */ -/* xx-xx-xxxx Scott Larson Added tx_trace.h include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Added tx_trace.h include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance) diff --git a/common_modules/module_manager/src/txm_module_manager_thread_create.c b/common_modules/module_manager/src/txm_module_manager_thread_create.c index dea68da8..95075bec 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_create.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_create.c @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_thread_create PORTABLE C */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -91,9 +91,9 @@ /* added 64-bit support, */ /* added SMP support, */ /* resulting in version 6.1.3 */ -/* xx-xx-xxxx Scott Larson Check module stack for */ +/* 03-08-2023 Scott Larson Check module stack for */ /* overlap, */ -/* resulting in version 6.x */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index ba2ba0a7..568d48c9 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE SMP */ -/* 6.2.0 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,6 +82,9 @@ /* add extension macros, */ /* update version numbers, */ /* resulting in version 6.2.0 */ +/* 03-08-2023 Tiejun Zhou Modified comment(s), */ +/* update patch number, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -134,7 +137,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 2 -#define THREADX_PATCH_VERSION 0 +#define THREADX_PATCH_VERSION 1 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/common_smp/src/tx_thread_wait_abort.c b/common_smp/src/tx_thread_wait_abort.c index e5fbffae..9c3b268f 100644 --- a/common_smp/src/tx_thread_wait_abort.c +++ b/common_smp/src/tx_thread_wait_abort.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_wait_abort PORTABLE C */ -/* 6.1 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,9 +68,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ /* resulting in version 6.1 */ +/* 03-08-2023 Scott Larson Check if thread is coming out */ +/* of suspension elsewhere, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) @@ -131,6 +134,18 @@ ULONG suspension_sequence; /* Restore interrupts. */ TX_RESTORE #endif + } + else if(thread_ptr -> tx_thread_suspend_cleanup == TX_NULL) + { + /* Thread is coming out of suspension elsewhere. */ + +#ifndef TX_NOT_INTERRUPTABLE + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif } else { @@ -167,13 +182,8 @@ ULONG suspension_sequence; TX_RESTORE #endif - /* Call any cleanup routines. */ - if (suspend_cleanup != TX_NULL) - { - - /* Yes, there is a function to call. */ - (suspend_cleanup)(thread_ptr, suspension_sequence); - } + /* Call cleanup routine. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); } /* If the abort of the thread wait was successful, if so resume the thread. */ diff --git a/ports/arc_em/metaware/inc/tx_port.h b/ports/arc_em/metaware/inc/tx_port.h index 5cc0be6b..382868a3 100644 --- a/ports/arc_em/metaware/inc/tx_port.h +++ b/ports/arc_em/metaware/inc/tx_port.h @@ -322,7 +322,7 @@ void _tx_initialize_start_interrupts(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_em/metaware/src/tx_thread_context_restore.s b/ports/arc_em/metaware/src/tx_thread_context_restore.s index 6879b355..07cb2a3b 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_em/metaware/src/tx_thread_context_restore.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ BTA, 0x412 .equ KSTACK_TOP, 0x264 @@ -29,7 +32,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARCv2_EM/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +72,9 @@ ;/* support for disabling the */ ;/* loop control feature, */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arc_em/metaware/src/tx_thread_context_save.s b/ports/arc_em/metaware/src/tx_thread_context_save.s index 81cc4d8a..f8dfdec7 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_save.s +++ b/ports/arc_em/metaware/src/tx_thread_context_save.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ BTA, 0x412 .equ KSTACK_TOP, 0x264 @@ -29,7 +32,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARCv2_EM/MetaWare */ -;/* 6.1.6 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,6 +67,9 @@ ;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ ;/* r25/r30 are caller saved, */ ;/* resulting in version 6.1.6 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s index 59a078fa..3378546d 100644 --- a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s @@ -18,13 +18,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARCv2_EM/MetaWare */ -;/* 6.1.6 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,6 +60,9 @@ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* 04-02-2021 Andres Mlinar Modified comments, */ ;/* resulting in version 6.1.6 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arc_em/metaware/src/tx_thread_schedule.s b/ports/arc_em/metaware/src/tx_thread_schedule.s index 04e8fe57..b85e8ae1 100644 --- a/ports/arc_em/metaware/src/tx_thread_schedule.s +++ b/ports/arc_em/metaware/src/tx_thread_schedule.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ BTA, 0x412 .equ KSTACK_TOP, 0x264 @@ -29,7 +32,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARCv2_EM/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ diff --git a/ports/arc_em/metaware/src/tx_thread_stack_build.s b/ports/arc_em/metaware/src/tx_thread_stack_build.s index b6550712..d4b05045 100644 --- a/ports/arc_em/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_em/metaware/src/tx_thread_stack_build.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ LONG_ALIGN_MASK, 0xFFFFFFFC .equ INT_ENABLE_BITS, 0x8000001E @@ -27,7 +30,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARCv2_EM/MetaWare */ -;/* 6.1.6 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -62,6 +65,9 @@ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* 04-02-2021 Andres Mlinar Modified comments, */ ;/* resulting in version 6.1.6 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arc_em/metaware/src/tx_thread_system_return.s b/ports/arc_em/metaware/src/tx_thread_system_return.s index 74bfc7b4..1e5eebee 100644 --- a/ports/arc_em/metaware/src/tx_thread_system_return.s +++ b/ports/arc_em/metaware/src/tx_thread_system_return.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ KSTACK_TOP, 0x264 .equ KSTACK_BASE, 0x265 @@ -28,7 +31,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARCv2_EM/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,6 +69,9 @@ ;/* 10-15-2021 Andres Mlinar Modified comments, */ ;/* use schedule reenter, */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arc_em/metaware/src/tx_timer_interrupt.s b/ports/arc_em/metaware/src/tx_timer_interrupt.s index 6e0aa417..9851f51d 100644 --- a/ports/arc_em/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_em/metaware/src/tx_timer_interrupt.s @@ -18,13 +18,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARCv2_EM/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +72,9 @@ ;/* fixed possible race */ ;/* condition on preemption */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arc_hs/metaware/inc/tx_port.h b/ports/arc_hs/metaware/inc/tx_port.h index 5d61c45c..4c38652a 100644 --- a/ports/arc_hs/metaware/inc/tx_port.h +++ b/ports/arc_hs/metaware/inc/tx_port.h @@ -336,7 +336,7 @@ VOID tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s index 7a2c8549..b3375746 100644 --- a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s +++ b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s @@ -19,23 +19,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_initialize.h" -; -; +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_fast_interrupt_setup ARC_HS/MetaWare */ -;/* 6.1 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,6 +60,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_fast_interrupt_setup(VOID *stack_ptr) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s index 1181d9e3..c5345f24 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s @@ -19,25 +19,18 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .equ BTA, 0x412 -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_fast_restore ARC_HS/MetaWare */ -;/* 6.1 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,6 +63,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_fast_restore(VOID) @@ -115,7 +111,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s index ceb1cb44..9cce0879 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s @@ -19,24 +19,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_fast_save ARC_HS/MetaWare */ -;/* 6.1 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,6 +65,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_fast_save(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_restore.s index f7ce8f10..8f22684b 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_restore.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ BTA, 0x412 @@ -26,7 +29,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARC_HS/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -63,6 +66,9 @@ ;/* r25/r30 are caller saved, */ ;/* use schedule_reenter, */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_save.s b/ports/arc_hs/metaware/src/tx_thread_context_save.s index eaebbe13..654928c1 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_save.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_save.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ BTA, 0x412 @@ -26,7 +29,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARC_HS/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,6 +64,9 @@ ;/* 10-15-2021 Andres Mlinar Modified comment(s), and */ ;/* r25/r30 are caller saved, */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s index 6e1adb89..10bf1d62 100644 --- a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s @@ -18,13 +18,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARC_HS/MetaWare */ -;/* 6.1.6 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,6 +60,9 @@ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* 04-02-2021 Andres Mlinar Modified comments, */ ;/* resulting in version 6.1.6 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s index 560afc7f..4082fd6e 100644 --- a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s +++ b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s @@ -19,23 +19,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_register_bank_assign ARC_HS/MetaWare */ -;/* 6.1 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +62,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank) diff --git a/ports/arc_hs/metaware/src/tx_thread_schedule.s b/ports/arc_hs/metaware/src/tx_thread_schedule.s index c5633c71..3291cb8a 100644 --- a/ports/arc_hs/metaware/src/tx_thread_schedule.s +++ b/ports/arc_hs/metaware/src/tx_thread_schedule.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ BTA, 0x412 @@ -26,7 +29,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARC_HS/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -63,6 +66,9 @@ ;/* 10-15-2021 Andres Mlinar Modified comment(s), */ ;/* use schedule reenter, */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_stack_build.s b/ports/arc_hs/metaware/src/tx_thread_stack_build.s index a0564577..225cdd62 100644 --- a/ports/arc_hs/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_hs/metaware/src/tx_thread_stack_build.s @@ -18,6 +18,9 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .equ LONG_ALIGN_MASK, 0xFFFFFFFC .equ INT_ENABLE_BITS, 0x8000001E @@ -27,7 +30,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARC_HS/MetaWare */ -;/* 6.1.6 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -62,6 +65,9 @@ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* 04-02-2021 Andres Mlinar Modified comments, */ ;/* resulting in version 6.1.6 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arc_hs/metaware/src/tx_thread_system_return.s b/ports/arc_hs/metaware/src/tx_thread_system_return.s index 25642499..affd3b54 100644 --- a/ports/arc_hs/metaware/src/tx_thread_system_return.s +++ b/ports/arc_hs/metaware/src/tx_thread_system_return.s @@ -18,13 +18,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARC_HS/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,6 +63,9 @@ ;/* 10-15-2021 Andres Mlinar Modified comments, */ ;/* use schedule reenter, */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arc_hs/metaware/src/tx_timer_interrupt.s b/ports/arc_hs/metaware/src/tx_timer_interrupt.s index 1ae05e76..959281f4 100644 --- a/ports/arc_hs/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_hs/metaware/src/tx_timer_interrupt.s @@ -18,13 +18,16 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARC_HS/MetaWare */ -;/* 6.1.9 */ +;/* 6.2.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,6 +72,9 @@ ;/* fixed possible race */ ;/* condition on preemption */ ;/* resulting in version 6.1.9 */ +;/* 03-08-2023 Cindy Deng Modified comment(s), added */ +;/* #include tx_user.h, */ +;/* resulting in version 6.2.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm11/ac5/inc/tx_port.h b/ports/arm11/ac5/inc/tx_port.h index 995ad2c3..eea3d4a0 100644 --- a/ports/arm11/ac5/inc/tx_port.h +++ b/ports/arm11/ac5/inc/tx_port.h @@ -320,7 +320,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/ac5/src/tx_thread_context_restore.s b/ports/arm11/ac5/src/tx_thread_context_restore.s index 8074c6b3..09cefebc 100644 --- a/ports/arm11/ac5/src/tx_thread_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_context_restore.s @@ -139,7 +139,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s index 1747d38a..7495487e 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s @@ -141,7 +141,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm11/gnu/inc/tx_port.h b/ports/arm11/gnu/inc/tx_port.h index 85f8f6e4..da02498a 100644 --- a/ports/arm11/gnu/inc/tx_port.h +++ b/ports/arm11/gnu/inc/tx_port.h @@ -309,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/gnu/src/tx_thread_context_restore.S b/ports/arm11/gnu/src/tx_thread_context_restore.S index 307bbee8..ee41226f 100644 --- a/ports/arm11/gnu/src/tx_thread_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_context_restore.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm #ifdef TX_ENABLE_FIQ_SUPPORT @@ -60,7 +53,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -93,6 +86,9 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -138,7 +134,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/arm11/gnu/src/tx_thread_context_save.S b/ports/arm11/gnu/src/tx_thread_context_save.S index 29da6606..906bd013 100644 --- a/ports/arm11/gnu/src/tx_thread_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled #else @@ -53,7 +46,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -85,6 +78,9 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S index 6db8a024..ab0560e0 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts @@ -61,7 +53,7 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,6 +86,9 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -140,7 +135,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S index a2b1ee3d..035460cc 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_fiq_processing_return @@ -47,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,6 +72,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S index 8fb04d73..82a66724 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else @@ -50,7 +43,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +83,9 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S index 9cc647b6..95493ca1 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + FIQ_DISABLE = 0x40 @ FIQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits @@ -46,7 +39,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +76,9 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_control.S b/ports/arm11/gnu/src/tx_thread_interrupt_control.S index fa19f085..b84fabeb 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_control.S @@ -19,15 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" */ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + INT_MASK = 0x03F @@ -56,7 +51,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -87,6 +82,9 @@ $_tx_thread_interrupt_control: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S index 471eb459..72d1c230 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled #else @@ -60,7 +54,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +84,9 @@ $_tx_thread_interrupt_disable: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S index d3b01c55..c6ef2705 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + @/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for @ applications calling this function from to 16-bit Thumb mode. */ @ @@ -53,7 +47,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -84,6 +78,9 @@ $_tx_thread_interrupt_restore: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S index 397be0ed..cc757616 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else @@ -50,7 +43,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +83,9 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S index 0d04422f..4443f181 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + IRQ_DISABLE = 0x80 @ IRQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits @@ -46,7 +39,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +76,9 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_schedule.S b/ports/arm11/gnu/src/tx_thread_schedule.S index 2f386b0d..20f95d9c 100644 --- a/ports/arm11/gnu/src/tx_thread_schedule.S +++ b/ports/arm11/gnu/src/tx_thread_schedule.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask #else @@ -68,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -102,6 +95,9 @@ $_tx_thread_schedule: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_stack_build.S b/ports/arm11/gnu/src/tx_thread_stack_build.S index 9117d22e..d471ae98 100644 --- a/ports/arm11/gnu/src/tx_thread_stack_build.S +++ b/ports/arm11/gnu/src/tx_thread_stack_build.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 @ SVC mode @@ -64,7 +58,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -97,6 +91,9 @@ $_tx_thread_stack_build: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm11/gnu/src/tx_thread_system_return.S b/ports/arm11/gnu/src/tx_thread_system_return.S index 05024c46..5f021f87 100644 --- a/ports/arm11/gnu/src/tx_thread_system_return.S +++ b/ports/arm11/gnu/src/tx_thread_system_return.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm #ifdef TX_ENABLE_FIQ_SUPPORT @@ -70,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -103,6 +97,9 @@ $_tx_thread_system_return: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S index 515bd9ca..c92dd20a 100644 --- a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled #else @@ -54,7 +47,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +79,9 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm11/gnu/src/tx_timer_interrupt.S b/ports/arm11/gnu/src/tx_timer_interrupt.S index 66705b94..7754ffa4 100644 --- a/ports/arm11/gnu/src/tx_timer_interrupt.S +++ b/ports/arm11/gnu/src/tx_timer_interrupt.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @ @@ -71,7 +64,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt ARM11/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -106,6 +99,9 @@ $_tx_timer_interrupt: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm11/iar/inc/tx_port.h b/ports/arm11/iar/inc/tx_port.h index b33a81f0..23f4d374 100644 --- a/ports/arm11/iar/inc/tx_port.h +++ b/ports/arm11/iar/inc/tx_port.h @@ -375,7 +375,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm11/iar/src/tx_thread_context_restore.s b/ports/arm11/iar/src/tx_thread_context_restore.s index c4a67206..9e011176 100644 --- a/ports/arm11/iar/src/tx_thread_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_context_restore.s @@ -138,7 +138,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s index b3a06804..283ee381 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s @@ -139,7 +139,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm9/ac5/inc/tx_port.h b/ports/arm9/ac5/inc/tx_port.h index 2238acc1..9fe78533 100644 --- a/ports/arm9/ac5/inc/tx_port.h +++ b/ports/arm9/ac5/inc/tx_port.h @@ -322,7 +322,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/ac5/src/tx_thread_context_restore.s b/ports/arm9/ac5/src/tx_thread_context_restore.s index c85a219d..986b7034 100644 --- a/ports/arm9/ac5/src/tx_thread_context_restore.s +++ b/ports/arm9/ac5/src/tx_thread_context_restore.s @@ -139,7 +139,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s index af55e3a7..6aea5df5 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s @@ -141,7 +141,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm9/gnu/inc/tx_port.h b/ports/arm9/gnu/inc/tx_port.h index a34cfb25..f4f17d20 100644 --- a/ports/arm9/gnu/inc/tx_port.h +++ b/ports/arm9/gnu/inc/tx_port.h @@ -309,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/gnu/src/tx_thread_context_restore.S b/ports/arm9/gnu/src/tx_thread_context_restore.S index 325ec259..9f7ab30b 100644 --- a/ports/arm9/gnu/src/tx_thread_context_restore.S +++ b/ports/arm9/gnu/src/tx_thread_context_restore.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm #ifdef TX_ENABLE_FIQ_SUPPORT @@ -60,7 +53,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -93,6 +86,9 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -138,7 +134,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/arm9/gnu/src/tx_thread_context_save.S b/ports/arm9/gnu/src/tx_thread_context_save.S index 9ec36b9b..a971d10a 100644 --- a/ports/arm9/gnu/src/tx_thread_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled #else @@ -53,7 +46,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -85,6 +78,9 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S index 06d7723f..4a1d9ef8 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts @@ -61,7 +53,7 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,6 +86,9 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -140,7 +135,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S index e3a033ec..a5564025 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_fiq_processing_return @@ -47,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,6 +72,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S index dffe020a..6874c7dc 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else @@ -50,7 +43,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +83,9 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S index ced2cfff..eac42836 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + FIQ_DISABLE = 0x40 @ FIQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits @@ -46,7 +39,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +76,9 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_control.S b/ports/arm9/gnu/src/tx_thread_interrupt_control.S index c8dfb2e3..bd85cc70 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_control.S @@ -19,15 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" */ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + INT_MASK = 0x03F @@ -56,7 +51,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -87,6 +82,9 @@ $_tx_thread_interrupt_control: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S index be4541b9..a897e6cd 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled #else @@ -60,7 +54,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +84,9 @@ $_tx_thread_interrupt_disable: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S index 6665fde2..2df7d44a 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + @/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for @ applications calling this function from to 16-bit Thumb mode. */ @ @@ -53,7 +47,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -84,6 +78,9 @@ $_tx_thread_interrupt_restore: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S index 7d6c2d7b..16fb14db 100644 --- a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else @@ -50,7 +43,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,6 +83,9 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S index bad43158..5fe1be41 100644 --- a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + IRQ_DISABLE = 0x80 @ IRQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits @@ -46,7 +39,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,6 +76,9 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_schedule.S b/ports/arm9/gnu/src/tx_thread_schedule.S index 726943e8..f3075250 100644 --- a/ports/arm9/gnu/src/tx_thread_schedule.S +++ b/ports/arm9/gnu/src/tx_thread_schedule.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask #else @@ -68,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -102,6 +95,9 @@ $_tx_thread_schedule: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_stack_build.S b/ports/arm9/gnu/src/tx_thread_stack_build.S index 7f691a42..93cf47a0 100644 --- a/ports/arm9/gnu/src/tx_thread_stack_build.S +++ b/ports/arm9/gnu/src/tx_thread_stack_build.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 @ SVC mode @@ -64,7 +58,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -97,6 +91,9 @@ $_tx_thread_stack_build: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm9/gnu/src/tx_thread_system_return.S b/ports/arm9/gnu/src/tx_thread_system_return.S index 6e442ad8..12e10c23 100644 --- a/ports/arm9/gnu/src/tx_thread_system_return.S +++ b/ports/arm9/gnu/src/tx_thread_system_return.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm #ifdef TX_ENABLE_FIQ_SUPPORT @@ -70,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -103,6 +97,9 @@ $_tx_thread_system_return: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S index 76db3030..2e0230e8 100644 --- a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled #else @@ -54,7 +47,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,6 +79,9 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm9/gnu/src/tx_timer_interrupt.S b/ports/arm9/gnu/src/tx_timer_interrupt.S index a44f9b10..8e621e7a 100644 --- a/ports/arm9/gnu/src/tx_timer_interrupt.S +++ b/ports/arm9/gnu/src/tx_timer_interrupt.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @ @@ -71,7 +64,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt ARM9/GNU */ -@/* 6.1 */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -106,6 +99,9 @@ $_tx_timer_interrupt: @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-08-2023 Cindy Deng Modified comment(s), added */ +@/* #include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm9/iar/inc/tx_port.h b/ports/arm9/iar/inc/tx_port.h index 99c24c96..97da5a94 100644 --- a/ports/arm9/iar/inc/tx_port.h +++ b/ports/arm9/iar/inc/tx_port.h @@ -375,7 +375,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm9/iar/src/tx_thread_context_restore.s b/ports/arm9/iar/src/tx_thread_context_restore.s index d118a511..aa5827d1 100644 --- a/ports/arm9/iar/src/tx_thread_context_restore.s +++ b/ports/arm9/iar/src/tx_thread_context_restore.s @@ -136,7 +136,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s index cee2a251..41377106 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s @@ -138,7 +138,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/c667x/ccs/inc/tx_port.h b/ports/c667x/ccs/inc/tx_port.h index 0f56b180..dc18c628 100644 --- a/ports/c667x/ccs/inc/tx_port.h +++ b/ports/c667x/ccs/inc/tx_port.h @@ -271,7 +271,7 @@ unsigned int _tx_thread_interrupt_control(unsigned int); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/c667x/ccs/src/tx_thread_context_restore.asm b/ports/c667x/ccs/src/tx_thread_context_restore.asm index 7bf3a215..18a4aaad 100644 --- a/ports/c667x/ccs/src/tx_thread_context_restore.asm +++ b/ports/c667x/ccs/src/tx_thread_context_restore.asm @@ -189,7 +189,7 @@ _tx_thread_context_restore: _tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a12/ac6/inc/tx_port.h b/ports/cortex_a12/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a12/ac6/inc/tx_port.h +++ b/ports/cortex_a12/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a12/gnu/inc/tx_port.h b/ports/cortex_a12/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a12/gnu/inc/tx_port.h +++ b/ports/cortex_a12/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..759421e8 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..a02846e6 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a12/gnu/src/tx_thread_schedule.S b/ports/cortex_a12/gnu/src/tx_thread_schedule.S index 8330e9df..e36e01ed 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a12/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a12/gnu/src/tx_thread_system_return.S b/ports/cortex_a12/gnu/src/tx_thread_system_return.S index cb7d62ce..13475407 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a12/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S index d846223f..f9ba7889 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a15/ac6/inc/tx_port.h +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/gnu/inc/tx_port.h b/ports/cortex_a15/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a15/gnu/inc/tx_port.h +++ b/ports/cortex_a15/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..759421e8 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..a02846e6 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index 8330e9df..e36e01ed 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S index cb7d62ce..13475407 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S index d846223f..f9ba7889 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a15/iar/inc/tx_port.h b/ports/cortex_a15/iar/inc/tx_port.h index 5efca40f..49fac13d 100644 --- a/ports/cortex_a15/iar/inc/tx_port.h +++ b/ports/cortex_a15/iar/inc/tx_port.h @@ -385,7 +385,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a15/iar/src/tx_thread_context_restore.s b/ports/cortex_a15/iar/src/tx_thread_context_restore.s index 952e8e3c..db92386b 100644 --- a/ports/cortex_a15/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a15/iar/src/tx_thread_context_restore.s @@ -138,7 +138,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s index 964713b2..193b076c 100644 --- a/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s @@ -135,7 +135,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a17/ac6/inc/tx_port.h b/ports/cortex_a17/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a17/ac6/inc/tx_port.h +++ b/ports/cortex_a17/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a17/gnu/inc/tx_port.h b/ports/cortex_a17/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a17/gnu/inc/tx_port.h +++ b/ports/cortex_a17/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..759421e8 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..a02846e6 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a17/gnu/src/tx_thread_schedule.S b/ports/cortex_a17/gnu/src/tx_thread_schedule.S index 8330e9df..e36e01ed 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a17/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a17/gnu/src/tx_thread_system_return.S b/ports/cortex_a17/gnu/src/tx_thread_system_return.S index cb7d62ce..13475407 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a17/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S index d846223f..f9ba7889 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a34/ac6/inc/tx_port.h b/ports/cortex_a34/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a34/ac6/inc/tx_port.h +++ b/ports/cortex_a34/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/gnu/inc/tx_port.h b/ports/cortex_a34/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a34/gnu/inc/tx_port.h +++ b/ports/cortex_a34/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/gnu/src/tx_initialize_low_level.S b/ports/cortex_a34/gnu/src/tx_initialize_low_level.S index 42800e0d..83792755 100644 --- a/ports/cortex_a34/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a34/gnu/src/tx_initialize_low_level.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text .align 3 @@ -62,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a34/gnu/src/tx_thread_context_restore.S b/ports/cortex_a34/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a34/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a34/gnu/src/tx_thread_context_save.S b/ports/cortex_a34/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a34/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a34/gnu/src/tx_thread_schedule.S b/ports/cortex_a34/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a34/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a34/gnu/src/tx_thread_stack_build.S b/ports/cortex_a34/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a34/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a34/gnu/src/tx_thread_system_return.S b/ports/cortex_a34/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a34/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a34/gnu/src/tx_timer_interrupt.S b/ports/cortex_a34/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a34/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a34/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a35/ac6/inc/tx_port.h b/ports/cortex_a35/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a35/ac6/inc/tx_port.h +++ b/ports/cortex_a35/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/gnu/inc/tx_port.h b/ports/cortex_a35/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a35/gnu/inc/tx_port.h +++ b/ports/cortex_a35/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/gnu/src/tx_initialize_low_level.S b/ports/cortex_a35/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a35/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a35/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a35/gnu/src/tx_thread_context_restore.S b/ports/cortex_a35/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a35/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a35/gnu/src/tx_thread_context_save.S b/ports/cortex_a35/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a35/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a35/gnu/src/tx_thread_schedule.S b/ports/cortex_a35/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a35/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a35/gnu/src/tx_thread_stack_build.S b/ports/cortex_a35/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a35/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a35/gnu/src/tx_thread_system_return.S b/ports/cortex_a35/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a35/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a35/gnu/src/tx_timer_interrupt.S b/ports/cortex_a35/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a35/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a35/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a5/ac5/inc/tx_port.h b/ports/cortex_a5/ac5/inc/tx_port.h index 3e73e330..bcbb80cb 100644 --- a/ports/cortex_a5/ac5/inc/tx_port.h +++ b/ports/cortex_a5/ac5/inc/tx_port.h @@ -327,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s index d0b82fbb..6a2f7517 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s index 9a7bc396..63109fcc 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a5/ac6/inc/tx_port.h b/ports/cortex_a5/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a5/ac6/inc/tx_port.h +++ b/ports/cortex_a5/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ghs/inc/tx_port.h b/ports/cortex_a5/ghs/inc/tx_port.h index b50dcfdc..1cebddb5 100644 --- a/ports/cortex_a5/ghs/inc/tx_port.h +++ b/ports/cortex_a5/ghs/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/gnu/inc/tx_port.h b/ports/cortex_a5/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a5/gnu/inc/tx_port.h +++ b/ports/cortex_a5/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..759421e8 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..a02846e6 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S index 8330e9df..e36e01ed 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a5/gnu/src/tx_thread_system_return.S b/ports/cortex_a5/gnu/src/tx_thread_system_return.S index cb7d62ce..13475407 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a5/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S index d846223f..f9ba7889 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a5/iar/inc/tx_port.h b/ports/cortex_a5/iar/inc/tx_port.h index 23a5701a..a43a5e4f 100644 --- a/ports/cortex_a5/iar/inc/tx_port.h +++ b/ports/cortex_a5/iar/inc/tx_port.h @@ -383,7 +383,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a5/iar/src/tx_thread_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_context_restore.s index e1694202..8f7aa2eb 100644 --- a/ports/cortex_a5/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s index 593bdcda..78dd54e1 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s @@ -141,7 +141,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a53/ac6/inc/tx_port.h b/ports/cortex_a53/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a53/ac6/inc/tx_port.h +++ b/ports/cortex_a53/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a53/gnu/inc/tx_port.h b/ports/cortex_a53/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a53/gnu/inc/tx_port.h +++ b/ports/cortex_a53/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a53/gnu/src/tx_initialize_low_level.S b/ports/cortex_a53/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a53/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a53/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a53/gnu/src/tx_thread_context_restore.S b/ports/cortex_a53/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a53/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a53/gnu/src/tx_thread_context_save.S b/ports/cortex_a53/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a53/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a53/gnu/src/tx_thread_schedule.S b/ports/cortex_a53/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a53/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a53/gnu/src/tx_thread_stack_build.S b/ports/cortex_a53/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a53/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a53/gnu/src/tx_thread_system_return.S b/ports/cortex_a53/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a53/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a53/gnu/src/tx_timer_interrupt.S b/ports/cortex_a53/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a53/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a53/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a55/ac6/inc/tx_port.h b/ports/cortex_a55/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a55/ac6/inc/tx_port.h +++ b/ports/cortex_a55/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a55/gnu/inc/tx_port.h b/ports/cortex_a55/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a55/gnu/inc/tx_port.h +++ b/ports/cortex_a55/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a55/gnu/src/tx_initialize_low_level.S b/ports/cortex_a55/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a55/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a55/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a55/gnu/src/tx_thread_context_restore.S b/ports/cortex_a55/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a55/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a55/gnu/src/tx_thread_context_save.S b/ports/cortex_a55/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a55/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a55/gnu/src/tx_thread_schedule.S b/ports/cortex_a55/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a55/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a55/gnu/src/tx_thread_stack_build.S b/ports/cortex_a55/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a55/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a55/gnu/src/tx_thread_system_return.S b/ports/cortex_a55/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a55/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a55/gnu/src/tx_timer_interrupt.S b/ports/cortex_a55/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a55/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a55/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a57/ac6/inc/tx_port.h b/ports/cortex_a57/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a57/ac6/inc/tx_port.h +++ b/ports/cortex_a57/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a57/gnu/inc/tx_port.h b/ports/cortex_a57/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a57/gnu/inc/tx_port.h +++ b/ports/cortex_a57/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a57/gnu/src/tx_initialize_low_level.S b/ports/cortex_a57/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a57/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a57/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a57/gnu/src/tx_thread_context_restore.S b/ports/cortex_a57/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a57/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a57/gnu/src/tx_thread_context_save.S b/ports/cortex_a57/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a57/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a57/gnu/src/tx_thread_schedule.S b/ports/cortex_a57/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a57/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a57/gnu/src/tx_thread_stack_build.S b/ports/cortex_a57/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a57/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a57/gnu/src/tx_thread_system_return.S b/ports/cortex_a57/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a57/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a57/gnu/src/tx_timer_interrupt.S b/ports/cortex_a57/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a57/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a57/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a5x/ac6/inc/tx_port.h b/ports/cortex_a5x/ac6/inc/tx_port.h index 8473879d..7edcbc45 100644 --- a/ports/cortex_a5x/ac6/inc/tx_port.h +++ b/ports/cortex_a5x/ac6/inc/tx_port.h @@ -357,7 +357,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S index c3dbf1e8..473376d0 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S @@ -139,7 +139,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) || (_tx_thread_preempt_disable)) { */ diff --git a/ports/cortex_a65/ac6/inc/tx_port.h b/ports/cortex_a65/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a65/ac6/inc/tx_port.h +++ b/ports/cortex_a65/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65/gnu/inc/tx_port.h b/ports/cortex_a65/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a65/gnu/inc/tx_port.h +++ b/ports/cortex_a65/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65/gnu/src/tx_initialize_low_level.S b/ports/cortex_a65/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a65/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a65/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a65/gnu/src/tx_thread_context_restore.S b/ports/cortex_a65/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a65/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a65/gnu/src/tx_thread_context_save.S b/ports/cortex_a65/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a65/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a65/gnu/src/tx_thread_schedule.S b/ports/cortex_a65/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a65/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a65/gnu/src/tx_thread_stack_build.S b/ports/cortex_a65/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a65/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a65/gnu/src/tx_thread_system_return.S b/ports/cortex_a65/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a65/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a65/gnu/src/tx_timer_interrupt.S b/ports/cortex_a65/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a65/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a65/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a65ae/ac6/inc/tx_port.h b/ports/cortex_a65ae/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a65ae/ac6/inc/tx_port.h +++ b/ports/cortex_a65ae/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65ae/gnu/inc/tx_port.h b/ports/cortex_a65ae/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a65ae/gnu/inc/tx_port.h +++ b/ports/cortex_a65ae/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S b/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S b/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S b/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S b/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S b/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S b/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S b/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a7/ac5/inc/tx_port.h b/ports/cortex_a7/ac5/inc/tx_port.h index 57876e1e..f2c2118e 100644 --- a/ports/cortex_a7/ac5/inc/tx_port.h +++ b/ports/cortex_a7/ac5/inc/tx_port.h @@ -327,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s index 39a45530..b9df3df9 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s index 9fba762b..320ba56d 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a7/ac6/inc/tx_port.h +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ghs/inc/tx_port.h b/ports/cortex_a7/ghs/inc/tx_port.h index 58b04237..8248f05d 100644 --- a/ports/cortex_a7/ghs/inc/tx_port.h +++ b/ports/cortex_a7/ghs/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/gnu/inc/tx_port.h b/ports/cortex_a7/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a7/gnu/inc/tx_port.h +++ b/ports/cortex_a7/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..759421e8 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..a02846e6 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S index 8330e9df..e36e01ed 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a7/gnu/src/tx_thread_system_return.S b/ports/cortex_a7/gnu/src/tx_thread_system_return.S index cb7d62ce..13475407 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a7/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S index d846223f..2272b754 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S @@ -19,7 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ - +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_execution_isr_enter @@ -74,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a7/iar/inc/tx_port.h b/ports/cortex_a7/iar/inc/tx_port.h index 42ef8c57..316033e6 100644 --- a/ports/cortex_a7/iar/inc/tx_port.h +++ b/ports/cortex_a7/iar/inc/tx_port.h @@ -383,7 +383,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/iar/src/tx_thread_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_context_restore.s index 8bfd7120..076299ee 100644 --- a/ports/cortex_a7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s index 63927f30..eaaa7996 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s @@ -141,7 +141,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a72/ac6/inc/tx_port.h b/ports/cortex_a72/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a72/ac6/inc/tx_port.h +++ b/ports/cortex_a72/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/gnu/inc/tx_port.h b/ports/cortex_a72/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a72/gnu/inc/tx_port.h +++ b/ports/cortex_a72/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/gnu/src/tx_initialize_low_level.S b/ports/cortex_a72/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a72/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a72/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a72/gnu/src/tx_thread_context_restore.S b/ports/cortex_a72/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a72/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a72/gnu/src/tx_thread_context_save.S b/ports/cortex_a72/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a72/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a72/gnu/src/tx_thread_schedule.S b/ports/cortex_a72/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a72/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a72/gnu/src/tx_thread_stack_build.S b/ports/cortex_a72/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a72/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a72/gnu/src/tx_thread_system_return.S b/ports/cortex_a72/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a72/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a72/gnu/src/tx_timer_interrupt.S b/ports/cortex_a72/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a72/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a72/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a73/ac6/inc/tx_port.h b/ports/cortex_a73/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a73/ac6/inc/tx_port.h +++ b/ports/cortex_a73/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a73/gnu/inc/tx_port.h b/ports/cortex_a73/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a73/gnu/inc/tx_port.h +++ b/ports/cortex_a73/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a73/gnu/src/tx_initialize_low_level.S b/ports/cortex_a73/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a73/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a73/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a73/gnu/src/tx_thread_context_restore.S b/ports/cortex_a73/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a73/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a73/gnu/src/tx_thread_context_save.S b/ports/cortex_a73/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a73/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a73/gnu/src/tx_thread_schedule.S b/ports/cortex_a73/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a73/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a73/gnu/src/tx_thread_stack_build.S b/ports/cortex_a73/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a73/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a73/gnu/src/tx_thread_system_return.S b/ports/cortex_a73/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a73/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a73/gnu/src/tx_timer_interrupt.S b/ports/cortex_a73/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a73/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a73/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a75/ac6/inc/tx_port.h b/ports/cortex_a75/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a75/ac6/inc/tx_port.h +++ b/ports/cortex_a75/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a75/gnu/inc/tx_port.h b/ports/cortex_a75/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a75/gnu/inc/tx_port.h +++ b/ports/cortex_a75/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a75/gnu/src/tx_initialize_low_level.S b/ports/cortex_a75/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a75/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a75/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a75/gnu/src/tx_thread_context_restore.S b/ports/cortex_a75/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a75/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a75/gnu/src/tx_thread_context_save.S b/ports/cortex_a75/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a75/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a75/gnu/src/tx_thread_schedule.S b/ports/cortex_a75/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a75/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a75/gnu/src/tx_thread_stack_build.S b/ports/cortex_a75/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a75/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a75/gnu/src/tx_thread_system_return.S b/ports/cortex_a75/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a75/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a75/gnu/src/tx_timer_interrupt.S b/ports/cortex_a75/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a75/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a75/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a76/ac6/inc/tx_port.h b/ports/cortex_a76/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a76/ac6/inc/tx_port.h +++ b/ports/cortex_a76/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76/gnu/inc/tx_port.h b/ports/cortex_a76/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a76/gnu/inc/tx_port.h +++ b/ports/cortex_a76/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76/gnu/src/tx_initialize_low_level.S b/ports/cortex_a76/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a76/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a76/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a76/gnu/src/tx_thread_context_restore.S b/ports/cortex_a76/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a76/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a76/gnu/src/tx_thread_context_save.S b/ports/cortex_a76/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a76/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a76/gnu/src/tx_thread_schedule.S b/ports/cortex_a76/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a76/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a76/gnu/src/tx_thread_stack_build.S b/ports/cortex_a76/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a76/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a76/gnu/src/tx_thread_system_return.S b/ports/cortex_a76/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a76/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a76/gnu/src/tx_timer_interrupt.S b/ports/cortex_a76/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a76/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a76/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a76ae/ac6/inc/tx_port.h b/ports/cortex_a76ae/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a76ae/ac6/inc/tx_port.h +++ b/ports/cortex_a76ae/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76ae/gnu/inc/tx_port.h b/ports/cortex_a76ae/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a76ae/gnu/inc/tx_port.h +++ b/ports/cortex_a76ae/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S b/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S b/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S b/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S b/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S b/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S b/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S b/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a77/ac6/inc/tx_port.h b/ports/cortex_a77/ac6/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a77/ac6/inc/tx_port.h +++ b/ports/cortex_a77/ac6/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a77/gnu/inc/tx_port.h b/ports/cortex_a77/gnu/inc/tx_port.h index 33bccbf1..4d844cb6 100644 --- a/ports/cortex_a77/gnu/inc/tx_port.h +++ b/ports/cortex_a77/gnu/inc/tx_port.h @@ -370,7 +370,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a77/gnu/src/tx_initialize_low_level.S b/ports/cortex_a77/gnu/src/tx_initialize_low_level.S index bf04784e..b3f5bfa0 100644 --- a/ports/cortex_a77/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a77/gnu/src/tx_initialize_low_level.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -64,6 +67,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a77/gnu/src/tx_thread_context_restore.S b/ports/cortex_a77/gnu/src/tx_thread_context_restore.S index 994c404d..94123af9 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a77/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a77/gnu/src/tx_thread_context_save.S b/ports/cortex_a77/gnu/src/tx_thread_context_save.S index 859a1e44..7637dd8f 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a77/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S index 6a5a7741..85f8302b 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S index d0062ef8..315b8d7d 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -60,6 +63,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S index 1b6261ba..3ddef57e 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a77/gnu/src/tx_thread_schedule.S b/ports/cortex_a77/gnu/src/tx_thread_schedule.S index 9a7a7262..8674d93a 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a77/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -65,6 +68,9 @@ /* 01-31-2022 Andres Mlinar Updated comments, */ /* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a77/gnu/src/tx_thread_stack_build.S b/ports/cortex_a77/gnu/src/tx_thread_stack_build.S index 5b7e945a..b1926717 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a77/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a77/gnu/src/tx_thread_system_return.S b/ports/cortex_a77/gnu/src/tx_thread_system_return.S index 7d42b63d..7bdfcf97 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a77/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -61,6 +64,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a77/gnu/src/tx_timer_interrupt.S b/ports/cortex_a77/gnu/src/tx_timer_interrupt.S index 5810b5c2..3ccea961 100644 --- a/ports/cortex_a77/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a77/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .text @@ -63,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a8/ac5/inc/tx_port.h b/ports/cortex_a8/ac5/inc/tx_port.h index ac629c35..cb6b514d 100644 --- a/ports/cortex_a8/ac5/inc/tx_port.h +++ b/ports/cortex_a8/ac5/inc/tx_port.h @@ -327,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s index c4ad07ba..0ea092b1 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s index 9efb6142..4ce439a0 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a8/ac6/inc/tx_port.h +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ghs/inc/tx_port.h b/ports/cortex_a8/ghs/inc/tx_port.h index 133cc208..951558b1 100644 --- a/ports/cortex_a8/ghs/inc/tx_port.h +++ b/ports/cortex_a8/ghs/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/gnu/inc/tx_port.h b/ports/cortex_a8/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a8/gnu/inc/tx_port.h +++ b/ports/cortex_a8/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..759421e8 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..a02846e6 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S index 8330e9df..e36e01ed 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +92,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a8/gnu/src/tx_thread_system_return.S b/ports/cortex_a8/gnu/src/tx_thread_system_return.S index cb7d62ce..13475407 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a8/gnu/src/tx_thread_system_return.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -92,6 +95,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S index d846223f..f9ba7889 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a8/iar/inc/tx_port.h b/ports/cortex_a8/iar/inc/tx_port.h index e8060631..f03ea9ea 100644 --- a/ports/cortex_a8/iar/inc/tx_port.h +++ b/ports/cortex_a8/iar/inc/tx_port.h @@ -384,7 +384,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a8/iar/src/tx_thread_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_context_restore.s index e200cc72..2c188a39 100644 --- a/ports/cortex_a8/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s index 5bf3454b..40bf61a6 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s @@ -141,7 +141,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a9/ac5/inc/tx_port.h b/ports/cortex_a9/ac5/inc/tx_port.h index e11f204a..ce879a67 100644 --- a/ports/cortex_a9/ac5/inc/tx_port.h +++ b/ports/cortex_a9/ac5/inc/tx_port.h @@ -327,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s index da09cb49..6814b064 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s index 3826b296..f56c5d3f 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a9/ac6/inc/tx_port.h +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ghs/inc/tx_port.h b/ports/cortex_a9/ghs/inc/tx_port.h index d6238ba5..3c58ae6c 100644 --- a/ports/cortex_a9/ghs/inc/tx_port.h +++ b/ports/cortex_a9/ghs/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/gnu/inc/tx_port.h b/ports/cortex_a9/gnu/inc/tx_port.h index 2155a2f6..6d5ee608 100644 --- a/ports/cortex_a9/gnu/inc/tx_port.h +++ b/ports/cortex_a9/gnu/inc/tx_port.h @@ -321,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S index fae7e72d..2d6e1566 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -88,6 +91,9 @@ IRQ_MODE = 0x92 // Disable IRQ, IRQ mode /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_restore diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_context_save.S index 7ac48c2e..7f88280f 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -73,6 +76,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_context_save diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S index 006be973..17ad02bf 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif SVC_MODE = 0xD3 // SVC mode FIQ_MODE = 0xD1 // FIQ mode @@ -86,6 +89,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S index 7db6a4c2..7ab2ee94 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_context_save diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S index b34d881e..52282fc9 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +85,9 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_end diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S index c9cd5a06..3fd8c001 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif FIQ_DISABLE = 0x40 // FIQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +78,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S index 63b1609a..092e9a31 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F @@ -80,6 +83,9 @@ $_tx_thread_interrupt_control: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_control diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S index 13258808..f6ff7824 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for applications calling this function from to 16-bit Thumb mode. */ @@ -76,6 +79,9 @@ $_tx_thread_interrupt_disable: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_disable diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S index 2d582511..6543798e 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif /* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for applications calling this function from to 16-bit Thumb mode. */ @@ -77,6 +80,9 @@ $_tx_thread_interrupt_restore: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_interrupt_restore diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S index ec7e63c6..ec64a2ae 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts @@ -82,6 +86,9 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_end diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S index c69976ed..6835ef1e 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + IRQ_DISABLE = 0x80 // IRQ disable bit MODE_MASK = 0x1F // Mode mask @@ -75,6 +79,9 @@ SYS_MODE_BITS = 0x1F // System mode bits /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_irq_nesting_start diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S index 8330e9df..2bd6548b 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr @@ -89,6 +93,9 @@ $_tx_thread_schedule: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_schedule diff --git a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S index f413e673..624670b4 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 // SVC mode @@ -89,6 +93,9 @@ $_tx_thread_stack_build: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_stack_build diff --git a/ports/cortex_a9/gnu/src/tx_thread_system_return.S b/ports/cortex_a9/gnu/src/tx_thread_system_return.S index cb7d62ce..0c549f13 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a9/gnu/src/tx_thread_system_return.S @@ -19,6 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @@ -92,6 +96,9 @@ $_tx_thread_system_return: /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_system_return diff --git a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S index d846223f..f9ba7889 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .global _tx_thread_system_state .global _tx_thread_current_ptr @@ -74,6 +77,9 @@ /* resulting in version 6.1.9 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_thread_vectored_context_save diff --git a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S index 7337ed0c..717d2620 100644 --- a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S @@ -19,6 +19,9 @@ /** */ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif .arm @@ -98,6 +101,9 @@ $_tx_timer_interrupt: /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Cindy Deng Modified comment(s), added */ +/* #include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ .global _tx_timer_interrupt diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h index e5277cbf..4ccc6d6d 100644 --- a/ports/cortex_a9/iar/inc/tx_port.h +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -385,7 +385,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a9/iar/src/tx_thread_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_context_restore.s index 8b494c30..acc8b8a4 100644 --- a/ports/cortex_a9/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s index bedfec0d..f5f4c8e3 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s @@ -141,7 +141,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index 7dfaa192..8bea608d 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -324,7 +324,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h index 7492d49c..a98439da 100644 --- a/ports/cortex_m0/ac6/inc/tx_port.h +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -367,7 +367,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S index 48909e8d..1c8dff91 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S @@ -42,7 +42,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,8 +77,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_save.S b/ports/cortex_m0/ac6/src/tx_thread_context_save.S index 366fdd16..a5da1d8e 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_save.S @@ -37,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,8 +71,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S index 4dc1497e..ae7704a5 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S @@ -31,7 +31,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,8 +62,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S index 4aa702ab..f831d8d5 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S @@ -31,7 +31,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,8 +61,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S index 716e5461..5898f88e 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S @@ -31,7 +31,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,8 +62,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S index 05d9ccfb..a7879995 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S @@ -44,7 +44,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -81,8 +81,8 @@ @/* 03-02-2021 Scott Larson Modified comment(s), add */ @/* low power code, */ @/* resulting in version 6.1.5 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S index fdc751b7..f4030079 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S index 67f9f012..238c41ec 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S index 5d61a6d2..615c59b1 100644 --- a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S @@ -41,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M0/AC6 */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,8 +76,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index c5e2c447..b7b521ae 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -369,7 +369,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/GNU Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S index 2c1bfb90..213d1e44 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S @@ -43,7 +43,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -81,8 +81,8 @@ @/* 09-30-2020 Scott Larson Modified comment(s), and */ @/* cleaned up whitespace, */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S index 98b8f763..9cf5e722 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S @@ -35,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -72,8 +72,8 @@ @/* 09-30-2020 Scott Larson Modified comment(s), and */ @/* cleaned up whitespace, */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S index 4dc83045..cf8cfcb8 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S @@ -31,7 +31,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -64,8 +64,8 @@ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ @/* 09-30-2020 William E. Lamie Modified comment(s), */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S index 02ae20fe..a725c12f 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S @@ -31,7 +31,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,8 @@ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ @/* 09-30-2020 William E. Lamie Modified comment(s), */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S index bfb424c9..d9ddad11 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S @@ -31,7 +31,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -64,8 +64,8 @@ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ @/* 09-30-2020 William E. Lamie Modified comment(s), */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S index b30bf2b1..5ea8a75e 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S @@ -42,7 +42,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -81,8 +81,8 @@ @/* 03-02-2021 Scott Larson Modified comment(s), add */ @/* low power code, */ @/* resulting in version 6.1.5 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S index 7f764093..d900fd5c 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -69,8 +69,8 @@ @/* to stack frame, clean up */ @/* whitespace, resulting */ @/* in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index d8201f0e..d8318b3b 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -65,8 +65,8 @@ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ @/* 09-30-2020 William E. Lamie Modified comment(s), */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S index e75fbb12..dbb6b112 100644 --- a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S @@ -41,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M0/GNU */ -@/* 6.x */ +@/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,8 +78,8 @@ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ @/* 09-30-2020 William E. Lamie Modified comment(s), */ @/* resulting in version 6.1 */ -@/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -@/* resulting in version 6.x */ +@/* 03-08-2023 Scott Larson Include tx_user.h, */ +@/* resulting in version 6.2.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index d78f7e74..c553183d 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -350,7 +350,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h index 8f0699ab..9f668117 100644 --- a/ports/cortex_m0/keil/inc/tx_port.h +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -324,7 +324,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 333710d4..c8b556bd 100644 --- a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,8 +69,8 @@ HEAP_SIZE = 0x00000000 /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index 5de6c143..ebb961d2 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -415,7 +415,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_restore.S b/ports/cortex_m23/ac6/src/tx_thread_context_restore.S index 27a3f2cb..3db0ab0e 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m23/ac6/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_save.S b/ports/cortex_m23/ac6/src/tx_thread_context_save.S index a8397aa7..2bef4702 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m23/ac6/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S index b25d1eea..543dfe2f 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S index 9259d949..cf2b6119 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S index b089f5e5..f155e448 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m23/ac6/src/tx_thread_schedule.S b/ports/cortex_m23/ac6/src/tx_thread_schedule.S index d9dc0f83..cf71a25f 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m23/ac6/src/tx_thread_schedule.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,8 +70,8 @@ /* 06-02-2021 Scott Larson Added secure stack initialize */ /* in SVC handler, */ /* resulting in version 6.1.7 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S index c3320e07..3e5b5d18 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S index d7f42eab..bd22bc91 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S index 53fd3370..1c340c73 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m23/ac6/src/tx_thread_stack_build.S b/ports/cortex_m23/ac6/src/tx_thread_stack_build.S index e9fb2961..4919de9d 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m23/ac6/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m23/ac6/src/tx_thread_system_return.S b/ports/cortex_m23/ac6/src/tx_thread_system_return.S index 9009bc4f..d9d71bdf 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m23/ac6/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m23/ac6/src/tx_timer_interrupt.S b/ports/cortex_m23/ac6/src/tx_timer_interrupt.S index 4a75eb45..93d0ce95 100644 --- a/ports/cortex_m23/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m23/ac6/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M23/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index 5cf9896b..acdf7c26 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -447,7 +447,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S index bdcf9058..2b2a80e8 100644 --- a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,8 +69,8 @@ HEAP_SIZE = 0x00000000 /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_restore.S b/ports/cortex_m23/gnu/src/tx_thread_context_restore.S index 8774ee44..30a89ad4 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m23/gnu/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_save.S b/ports/cortex_m23/gnu/src/tx_thread_context_save.S index c0cb7b10..44d7ba94 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m23/gnu/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S index c7b1c7c1..69c69b0e 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S index fdbc3c93..67099b70 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S index fc93bb70..d4b972af 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m23/gnu/src/tx_thread_schedule.S b/ports/cortex_m23/gnu/src/tx_thread_schedule.S index 19fbce7a..89abcf00 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m23/gnu/src/tx_thread_schedule.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,8 +66,8 @@ /* 06-02-2021 Scott Larson Added secure stack initialize */ /* in SVC handler, */ /* resulting in version 6.1.7 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S index d252af2e..d568d931 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S index 2e207eac..152b88af 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S index e1d30198..62404b94 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_thread_stack_build.S b/ports/cortex_m23/gnu/src/tx_thread_stack_build.S index a2cbcad9..cabbdc78 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m23/gnu/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m23/gnu/src/tx_thread_system_return.S b/ports/cortex_m23/gnu/src/tx_thread_system_return.S index 807af2c6..689aea5f 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m23/gnu/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m23/gnu/src/tx_timer_interrupt.S b/ports/cortex_m23/gnu/src/tx_timer_interrupt.S index f1b86104..da3d02ac 100644 --- a/ports/cortex_m23/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m23/gnu/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M23/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index ba65d9be..73a0d7a5 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -437,7 +437,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h index b446fc83..edeb9d7c 100644 --- a/ports/cortex_m3/ac5/inc/tx_port.h +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index ebbe5133..2b92216e 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac6/src/tx_misra.S b/ports/cortex_m3/ac6/src/tx_misra.S index 155512be..a11bcca9 100644 --- a/ports/cortex_m3/ac6/src/tx_misra.S +++ b/ports/cortex_m3/ac6/src/tx_misra.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #define SHT_PROGBITS 0x1 .global __aeabi_memset diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S index 9dbe0204..6240faef 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_save.S b/ports/cortex_m3/ac6/src/tx_thread_context_save.S index 5061b512..4238df92 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -31,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S index 1f6a3f11..fb6a0379 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S index 93159485..aa3c2f06 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S index c060ec5f..40d707d9 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S index 2dd3922d..742484bf 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -39,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M3/AC6 */ -/* 6.1.11 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +76,8 @@ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S index 70aec7a7..17d50ac2 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S index 3a24f007..a83abf4f 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S index 1e61de61..9059d0d0 100644 --- a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M3/AC6 */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m3/ghs/inc/tx_port.h b/ports/cortex_m3/ghs/inc/tx_port.h index eec58145..78ca582d 100644 --- a/ports/cortex_m3/ghs/inc/tx_port.h +++ b/ports/cortex_m3/ghs/inc/tx_port.h @@ -380,7 +380,7 @@ asm void restore_ints(int a) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index 7d94c5d5..ce9d0610 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/gnu/src/tx_misra.S b/ports/cortex_m3/gnu/src/tx_misra.S index 155512be..c84d8576 100644 --- a/ports/cortex_m3/gnu/src/tx_misra.S +++ b/ports/cortex_m3/gnu/src/tx_misra.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #define SHT_PROGBITS 0x1 .global __aeabi_memset diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S index 4b62c21c..04d540c0 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_save.S b/ports/cortex_m3/gnu/src/tx_thread_context_save.S index 13283881..1801fcc0 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_save.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S index 309053a8..1a69f677 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S index 7da1fe8a..d60039bc 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S index 136b56b7..e9cb513c 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S index 5c1f4767..a4dc8298 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -37,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M3/GNU */ -/* 6.1.11 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +78,8 @@ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S index e6a1da3f..77efc56c 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m3/gnu/src/tx_thread_system_return.S b/ports/cortex_m3/gnu/src/tx_thread_system_return.S index 8a1f4a29..f10efece 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m3/gnu/src/tx_thread_system_return.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S index 5c3d6a2e..781f8019 100644 --- a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M3/GNU */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +79,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index 0781aecd..f1d26619 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h index 59a1b36c..fcfbf42d 100644 --- a/ports/cortex_m3/keil/inc/tx_port.h +++ b/ports/cortex_m3/keil/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index ffb316e0..2d82881a 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S index c4c2d4ba..7f1cf170 100644 --- a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,8 +69,8 @@ HEAP_SIZE = 0x00000000 /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S index db631b3a..bd769a76 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S index f73fa06c..c30dded8 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S index fbf6e3bc..04a67657 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S index 031efa37..408aebc3 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S index aee4db6c..306d9383 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index 52740b24..bf86364d 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,9 +72,9 @@ /* resulting in version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ /* included tx_user.h, */ -/* resulting in version 6.x */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S index fc527b38..b67350cf 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S index c6fef52b..965c9dae 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S index 09a3c67f..21c2c633 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S index b9d77633..7ea5dc5a 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index a96b6373..9281e8de 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S index 164aec36..d5a5c171 100644 --- a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index 417da841..8c85a78c 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S index 2fdee2a4..e531f6a2 100644 --- a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,8 +71,8 @@ HEAP_SIZE = 0x00000000 /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 01-31-2022 Scott Larson Fixed predefined macro name, */ /* resulting in version 6.1.10 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S index 7507a1eb..ad98dc6b 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_save.S b/ports/cortex_m33/gnu/src/tx_thread_context_save.S index 4c5c1e8b..d442bdfa 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m33/gnu/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S index adea4649..9a80b5ce 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S index b24bb515..4a38bc16 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S index d3672be9..2912c395 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m33/gnu/src/tx_thread_schedule.S b/ports/cortex_m33/gnu/src/tx_thread_schedule.S index 5c33dfc4..77e6a64c 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m33/gnu/src/tx_thread_schedule.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,8 +70,8 @@ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S index d4264a73..57bff58e 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S index ecf58dde..087225fc 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S index 406284eb..7656502b 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S index 26a8cb3b..63ca5a41 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m33/gnu/src/tx_thread_system_return.S b/ports/cortex_m33/gnu/src/tx_thread_system_return.S index f5a14492..3ff5cab1 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m33/gnu/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S index 5b0a39e1..e4feddcc 100644 --- a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M33/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index cf22805b..ae2898bb 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/IAR */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s index 5cfc7d8b..ae4bea6c 100644 --- a/ports/cortex_m33/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/IAR */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,8 +84,8 @@ /* resulting in version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h index 0eec634b..2d066a55 100644 --- a/ports/cortex_m4/ac5/inc/tx_port.h +++ b/ports/cortex_m4/ac5/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index 71b66372..e18d6d52 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac6/src/tx_misra.S b/ports/cortex_m4/ac6/src/tx_misra.S index 155512be..a11bcca9 100644 --- a/ports/cortex_m4/ac6/src/tx_misra.S +++ b/ports/cortex_m4/ac6/src/tx_misra.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #define SHT_PROGBITS 0x1 .global __aeabi_memset diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S index 6e1fe7cf..b28d5cf0 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_save.S b/ports/cortex_m4/ac6/src/tx_thread_context_save.S index 15ad1292..df3406fc 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -31,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S index b79a59c1..83fa1216 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S index 2adec1d8..d7c8208f 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S index a920cdbf..0541495b 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S index 9bae029f..20f88f07 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -39,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/AC6 */ -/* 6.1.11 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +76,8 @@ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S index 5e4eddb2..a55ed875 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S index a8b6dc97..237dd5e0 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S index 9385e1cb..9f22f66b 100644 --- a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M4/AC6 */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m4/ghs/inc/tx_port.h b/ports/cortex_m4/ghs/inc/tx_port.h index e028bdda..f7741466 100644 --- a/ports/cortex_m4/ghs/inc/tx_port.h +++ b/ports/cortex_m4/ghs/inc/tx_port.h @@ -387,7 +387,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GHS Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GHS Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index 7d3cb280..4cce10b9 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/gnu/src/tx_misra.S b/ports/cortex_m4/gnu/src/tx_misra.S index 155512be..c84d8576 100644 --- a/ports/cortex_m4/gnu/src/tx_misra.S +++ b/ports/cortex_m4/gnu/src/tx_misra.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #define SHT_PROGBITS 0x1 .global __aeabi_memset diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S index 852d8302..020ec47a 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_save.S b/ports/cortex_m4/gnu/src/tx_thread_context_save.S index 1c8a2ebf..789e49d4 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_save.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S index 30960b56..1c6334a9 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S index d2945f08..e8f38680 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S index a2efd882..1f8930ef 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m4/gnu/src/tx_thread_schedule.S b/ports/cortex_m4/gnu/src/tx_thread_schedule.S index 77e63398..82c75285 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m4/gnu/src/tx_thread_schedule.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -37,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/GNU */ -/* 6.1.11 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +78,8 @@ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S index 536d815b..060f6eeb 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m4/gnu/src/tx_thread_system_return.S b/ports/cortex_m4/gnu/src/tx_thread_system_return.S index 3783ccd7..33d89d14 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m4/gnu/src/tx_thread_system_return.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S index 043921be..302eef58 100644 --- a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M4/GNU */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +79,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index 93f0651a..ec77710b 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h index ae7954aa..76eccb59 100644 --- a/ports/cortex_m4/keil/inc/tx_port.h +++ b/ports/cortex_m4/keil/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/inc/tx_port.h b/ports/cortex_m55/ac6/inc/tx_port.h index 0993e31f..2fb2051d 100644 --- a/ports/cortex_m55/ac6/inc/tx_port.h +++ b/ports/cortex_m55/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/src/tx_initialize_low_level.S b/ports/cortex_m55/ac6/src/tx_initialize_low_level.S index 8adf9958..a48b3034 100644 --- a/ports/cortex_m55/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m55/ac6/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,8 +69,8 @@ HEAP_SIZE = 0x00000000 /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_thread_context_restore.S b/ports/cortex_m55/ac6/src/tx_thread_context_restore.S index 6f85d3fd..f9a176c9 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m55/ac6/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_thread_context_save.S b/ports/cortex_m55/ac6/src/tx_thread_context_save.S index fa310ceb..f38b5ed0 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m55/ac6/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S index f32ac7f1..2dfa3833 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S index ee86865d..44100dca 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S index 46809b6e..1b2f4883 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m55/ac6/src/tx_thread_schedule.S b/ports/cortex_m55/ac6/src/tx_thread_schedule.S index 55ce02a8..7ad1e86e 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m55/ac6/src/tx_thread_schedule.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,9 +72,9 @@ /* resulting in version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ /* included tx_user.h, */ -/* resulting in version 6.x */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S index d539ef0b..d57a4c30 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S index ee65a6ad..dc7c9f16 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S index fc417fe2..b4ca1d3f 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_thread_stack_build.S b/ports/cortex_m55/ac6/src/tx_thread_stack_build.S index 34d6f57e..0c647806 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m55/ac6/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m55/ac6/src/tx_thread_system_return.S b/ports/cortex_m55/ac6/src/tx_thread_system_return.S index 4e3569b4..c089500f 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m55/ac6/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m55/ac6/src/tx_timer_interrupt.S b/ports/cortex_m55/ac6/src/tx_timer_interrupt.S index 4969f0c1..2f2a7da4 100644 --- a/ports/cortex_m55/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m55/ac6/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M55/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m55/gnu/inc/tx_port.h b/ports/cortex_m55/gnu/inc/tx_port.h index 63110e85..83e009ff 100644 --- a/ports/cortex_m55/gnu/inc/tx_port.h +++ b/ports/cortex_m55/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/gnu/src/tx_initialize_low_level.S b/ports/cortex_m55/gnu/src/tx_initialize_low_level.S index 3d7736eb..2bd6bcee 100644 --- a/ports/cortex_m55/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m55/gnu/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,8 +71,8 @@ HEAP_SIZE = 0x00000000 /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 01-31-2022 Scott Larson Fixed predefined macro name, */ /* resulting in version 6.1.10 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_thread_context_restore.S b/ports/cortex_m55/gnu/src/tx_thread_context_restore.S index 31fb733f..a857658d 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m55/gnu/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_thread_context_save.S b/ports/cortex_m55/gnu/src/tx_thread_context_save.S index d4a362e9..69721a50 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m55/gnu/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S index 681e60cd..c153fb3f 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S index e50d13a4..7bf70717 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S index 246a81d5..10fe18da 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m55/gnu/src/tx_thread_schedule.S b/ports/cortex_m55/gnu/src/tx_thread_schedule.S index 0bb687fd..9bf19f5d 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m55/gnu/src/tx_thread_schedule.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,8 +70,8 @@ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S index f0750517..25b27bf5 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S index 13242a97..ee112151 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S index 5f48e0a2..74946e40 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_thread_stack_build.S b/ports/cortex_m55/gnu/src/tx_thread_stack_build.S index e2b16358..cb17019c 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m55/gnu/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m55/gnu/src/tx_thread_system_return.S b/ports/cortex_m55/gnu/src/tx_thread_system_return.S index 2bf6f8f5..10642e07 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m55/gnu/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m55/gnu/src/tx_timer_interrupt.S b/ports/cortex_m55/gnu/src/tx_timer_interrupt.S index 757881aa..c21ff5cb 100644 --- a/ports/cortex_m55/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m55/gnu/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M55/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m55/iar/inc/tx_port.h b/ports/cortex_m55/iar/inc/tx_port.h index 505f9f8a..5fdfd4d7 100644 --- a/ports/cortex_m55/iar/inc/tx_port.h +++ b/ports/cortex_m55/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M55/IAR */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/iar/src/tx_thread_schedule.s b/ports/cortex_m55/iar/src/tx_thread_schedule.s index 378438fb..8f151560 100644 --- a/ports/cortex_m55/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m55/iar/src/tx_thread_schedule.s @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M55/IAR */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,8 +84,8 @@ /* resulting in version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h index 7de2ee6d..6153d888 100644 --- a/ports/cortex_m7/ac5/inc/tx_port.h +++ b/ports/cortex_m7/ac5/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index 302bbc7d..1d2cb4a2 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac6/src/tx_misra.S b/ports/cortex_m7/ac6/src/tx_misra.S index 155512be..a11bcca9 100644 --- a/ports/cortex_m7/ac6/src/tx_misra.S +++ b/ports/cortex_m7/ac6/src/tx_misra.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #define SHT_PROGBITS 0x1 .global __aeabi_memset diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S index 341e8a16..d68f5340 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_save.S b/ports/cortex_m7/ac6/src/tx_thread_context_save.S index 62d8b329..4aa6d7d9 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -31,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S index 0843f69e..88299092 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S index 3f36a36a..5225ad5c 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S index 924fa21d..6f3f3f67 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S index e4a34ac8..b2c27266 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -39,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M7/AC6 */ -/* 6.1.11 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +76,8 @@ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S index 52c2c207..3b8cca0e 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S index c1b3b9e8..97d20aaa 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S index bde18d04..84f73e25 100644 --- a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M7/AC6 */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m7/ghs/inc/tx_port.h b/ports/cortex_m7/ghs/inc/tx_port.h index 3096f2e4..27f30481 100644 --- a/ports/cortex_m7/ghs/inc/tx_port.h +++ b/ports/cortex_m7/ghs/inc/tx_port.h @@ -387,7 +387,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GHS Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GHS Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 7d14ac82..4c4e4255 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/gnu/src/tx_misra.S b/ports/cortex_m7/gnu/src/tx_misra.S index 155512be..c84d8576 100644 --- a/ports/cortex_m7/gnu/src/tx_misra.S +++ b/ports/cortex_m7/gnu/src/tx_misra.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #define SHT_PROGBITS 0x1 .global __aeabi_memset diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S index 888d5442..29b37e25 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_save.S b/ports/cortex_m7/gnu/src/tx_thread_context_save.S index 6111ffee..f0af0738 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_save.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S index 2ea849dc..79f13a22 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S index 16935d55..fead3645 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S index 27f8c5bd..7b4aef61 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m7/gnu/src/tx_thread_schedule.S b/ports/cortex_m7/gnu/src/tx_thread_schedule.S index 12343ad4..a0ea7d8c 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m7/gnu/src/tx_thread_schedule.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice @@ -37,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M7/GNU */ -/* 6.1.11 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +78,8 @@ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S index 7c2cb83a..4337648e 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m7/gnu/src/tx_thread_system_return.S b/ports/cortex_m7/gnu/src/tx_thread_system_return.S index 307af29e..bf1cc0b2 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m7/gnu/src/tx_thread_system_return.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .text 32 .align 4 .syntax unified @@ -28,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S index d0fc6929..c578781d 100644 --- a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M7/GNU */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +79,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index 191ad569..302d9780 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -716,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/ac6/inc/tx_port.h b/ports/cortex_m85/ac6/inc/tx_port.h index 4498e405..4e4b9bff 100644 --- a/ports/cortex_m85/ac6/inc/tx_port.h +++ b/ports/cortex_m85/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S index 6834e950..863f5ffe 100644 --- a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,8 +69,8 @@ HEAP_SIZE = 0x00000000 /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_thread_context_restore.S b/ports/cortex_m85/ac6/src/tx_thread_context_restore.S index 20525bb8..e3d2c880 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m85/ac6/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_thread_context_save.S b/ports/cortex_m85/ac6/src/tx_thread_context_save.S index 71d8037d..745f34ad 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m85/ac6/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S index 9d4c7380..321e8b39 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S index 83a43bac..627dacd6 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S index a595a5e3..f1400960 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m85/ac6/src/tx_thread_schedule.S b/ports/cortex_m85/ac6/src/tx_thread_schedule.S index afae27c7..6e22e1d0 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m85/ac6/src/tx_thread_schedule.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,9 +72,9 @@ /* resulting in version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ /* included tx_user.h, */ -/* resulting in version 6.x */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S index 89282a39..76f912ef 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S index 346ddace..9f5d01d9 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S index 19a95c80..2c6e93e2 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_thread_stack_build.S b/ports/cortex_m85/ac6/src/tx_thread_stack_build.S index ca10dfe0..f17966de 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m85/ac6/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m85/ac6/src/tx_thread_system_return.S b/ports/cortex_m85/ac6/src/tx_thread_system_return.S index 636f89e3..65f68b60 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m85/ac6/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m85/ac6/src/tx_timer_interrupt.S b/ports/cortex_m85/ac6/src/tx_timer_interrupt.S index b4b357e5..5823bb45 100644 --- a/ports/cortex_m85/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m85/ac6/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M85/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h index 9f198276..b89e55ab 100644 --- a/ports/cortex_m85/gnu/inc/tx_port.h +++ b/ports/cortex_m85/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/gnu/src/tx_initialize_low_level.S b/ports/cortex_m85/gnu/src/tx_initialize_low_level.S index 518e25e9..b115ed57 100644 --- a/ports/cortex_m85/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m85/gnu/src/tx_initialize_low_level.S @@ -35,7 +35,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,8 +71,8 @@ HEAP_SIZE = 0x00000000 /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 01-31-2022 Scott Larson Fixed predefined macro name, */ /* resulting in version 6.1.10 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_thread_context_restore.S b/ports/cortex_m85/gnu/src/tx_thread_context_restore.S index b49c7520..94e2ea62 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m85/gnu/src/tx_thread_context_restore.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_thread_context_save.S b/ports/cortex_m85/gnu/src/tx_thread_context_save.S index e045cf8f..2d2b9d13 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m85/gnu/src/tx_thread_context_save.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S index 582461ef..3cf69ccc 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S index 0e9a15e1..7e3f263d 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S index aa656006..ef51653a 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,8 +58,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports/cortex_m85/gnu/src/tx_thread_schedule.S b/ports/cortex_m85/gnu/src/tx_thread_schedule.S index 0a6fa4c7..17c2f3c7 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m85/gnu/src/tx_thread_schedule.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,8 +70,8 @@ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S index d68a37bb..8d9906c8 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,8 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S index 57a6d831..5f678dca 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,8 +57,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S index aaba96f6..a7cb87b8 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* secure stack initialization */ /* macro to port-specific, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_thread_stack_build.S b/ports/cortex_m85/gnu/src/tx_thread_stack_build.S index 43cb65e5..67c46b75 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m85/gnu/src/tx_thread_stack_build.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m85/gnu/src/tx_thread_system_return.S b/ports/cortex_m85/gnu/src/tx_thread_system_return.S index a9f997c0..309def64 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m85/gnu/src/tx_thread_system_return.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,8 +60,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m85/gnu/src/tx_timer_interrupt.S b/ports/cortex_m85/gnu/src/tx_timer_interrupt.S index ec311400..f5e8aaea 100644 --- a/ports/cortex_m85/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m85/gnu/src/tx_timer_interrupt.S @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M85/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,8 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-xxxx Scott Larson Include tx_user.h, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h index de027715..3fb4f874 100644 --- a/ports/cortex_m85/iar/inc/tx_port.h +++ b/ports/cortex_m85/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M85/IAR */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -76,8 +76,8 @@ /* macro to port-specific, */ /* described BASEPRI usage, */ /* resulting in version 6.1.12 */ -/* xx-xx-xxxx Scott Larson Removed unneeded #include, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Removed unneeded #include, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -646,7 +646,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/iar/src/tx_thread_schedule.s b/ports/cortex_m85/iar/src/tx_thread_schedule.s index f2575847..2286a53b 100644 --- a/ports/cortex_m85/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m85/iar/src/tx_thread_schedule.s @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M85/IAR */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,8 +84,8 @@ /* resulting in version 6.1.7 */ /* 04-25-2022 Scott Larson Added BASEPRI support, */ /* resulting in version 6.1.11 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r4/ac5/inc/tx_port.h b/ports/cortex_r4/ac5/inc/tx_port.h index 51a8f375..dcd6b609 100644 --- a/ports/cortex_r4/ac5/inc/tx_port.h +++ b/ports/cortex_r4/ac5/inc/tx_port.h @@ -327,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s index 5b42a7d3..2071c5d6 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s index ed350323..03896acf 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_r4/ac6/inc/tx_port.h b/ports/cortex_r4/ac6/inc/tx_port.h index 4b8334ce..67a8b1b1 100644 --- a/ports/cortex_r4/ac6/inc/tx_port.h +++ b/ports/cortex_r4/ac6/inc/tx_port.h @@ -330,7 +330,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S index c480e844..5d21f062 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S @@ -139,7 +139,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr))*/ /* (_tx_thread_preempt_disable)) */ /* { */ diff --git a/ports/cortex_r4/ghs/inc/tx_port.h b/ports/cortex_r4/ghs/inc/tx_port.h index ab32b974..9f12a354 100644 --- a/ports/cortex_r4/ghs/inc/tx_port.h +++ b/ports/cortex_r4/ghs/inc/tx_port.h @@ -385,7 +385,7 @@ asm void restore_ints(int a) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/gnu/inc/tx_port.h b/ports/cortex_r4/gnu/inc/tx_port.h index c69fa298..be947b26 100644 --- a/ports/cortex_r4/gnu/inc/tx_port.h +++ b/ports/cortex_r4/gnu/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S index 1eb935e4..65bd7965 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm #ifdef TX_ENABLE_FIQ_SUPPORT @@ -141,7 +134,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_context_save.S index 5b358301..fe020f93 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_context_save.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_irq_processing_return diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S index 74ffa84d..67ddeb4f 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode MODE_MASK = 0x1F @ Mode mask @@ -136,7 +128,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S index c3775b36..07eae7c4 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_fiq_processing_return diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S index a4b9b893..8aea2a66 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S index da5b3930..b5a48e77 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + FIQ_DISABLE = 0x40 @ FIQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S index 84ca0823..d7d19c27 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S @@ -19,15 +19,9 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" */ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif INT_MASK = 0x03F diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S index 8b160fe5..17ad5fff 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + @/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for @ applications calling this function from to 16-bit Thumb mode. */ @ diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S index d963c5d9..6c788d2e 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + @/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for @ applications calling this function from to 16-bit Thumb mode. */ @ diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S index ffe7384d..a0f50356 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S index ff5c4c64..91098b0e 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + IRQ_DISABLE = 0x80 @ IRQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits diff --git a/ports/cortex_r4/gnu/src/tx_thread_schedule.S b/ports/cortex_r4/gnu/src/tx_thread_schedule.S index 8691fa87..63f8dfc7 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_r4/gnu/src/tx_thread_schedule.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice diff --git a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S index 0f36b5f3..25698fe0 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 @ SVC mode diff --git a/ports/cortex_r4/gnu/src/tx_thread_system_return.S b/ports/cortex_r4/gnu/src/tx_thread_system_return.S index e4d2612a..371ac45f 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_r4/gnu/src/tx_thread_system_return.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @ @ diff --git a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S index 37a1ef93..9b4914fe 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_execution_isr_enter diff --git a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S index 53cd6b4e..43ed057d 100644 --- a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @ diff --git a/ports/cortex_r4/iar/inc/tx_port.h b/ports/cortex_r4/iar/inc/tx_port.h index bf627f70..165baee6 100644 --- a/ports/cortex_r4/iar/inc/tx_port.h +++ b/ports/cortex_r4/iar/inc/tx_port.h @@ -367,7 +367,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r4/iar/src/tx_thread_context_restore.s b/ports/cortex_r4/iar/src/tx_thread_context_restore.s index f5dfdbfc..b9fd8dc5 100644 --- a/ports/cortex_r4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_r4/iar/src/tx_thread_context_restore.s @@ -131,7 +131,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_r5/ac5/inc/tx_port.h b/ports/cortex_r5/ac5/inc/tx_port.h index 21c1b82d..f09108d6 100644 --- a/ports/cortex_r5/ac5/inc/tx_port.h +++ b/ports/cortex_r5/ac5/inc/tx_port.h @@ -320,7 +320,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s index d4114be6..d30a2d7d 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s @@ -140,7 +140,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s index e5e9b8d7..c78d3383 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h index 7eccfe75..97c9969f 100644 --- a/ports/cortex_r5/ac6/inc/tx_port.h +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S index ca89d5b0..5a2ac00d 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S @@ -140,7 +140,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S index 54a33e29..8c99c348 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S @@ -135,7 +135,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/cortex_r5/ghs/inc/tx_port.h b/ports/cortex_r5/ghs/inc/tx_port.h index 4ffe1455..3805d89a 100644 --- a/ports/cortex_r5/ghs/inc/tx_port.h +++ b/ports/cortex_r5/ghs/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h index d477c188..49249fd1 100644 --- a/ports/cortex_r5/gnu/inc/tx_port.h +++ b/ports/cortex_r5/gnu/inc/tx_port.h @@ -312,7 +312,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S index 9b6409ec..f4fe4fcd 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm #ifdef TX_ENABLE_FIQ_SUPPORT @@ -141,7 +134,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_context_save.S index 4b392465..97856d7a 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_context_save.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_irq_processing_return diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S index 021144db..4d0625ad 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode MODE_MASK = 0x1F @ Mode mask @@ -136,7 +128,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) @ || (_tx_thread_preempt_disable)) @ { @ diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S index e3a94fe8..806699ff 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global __tx_fiq_processing_return diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S index c7e326d4..cd8e4d50 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S index 8a53e6dd..4e5d06d1 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + FIQ_DISABLE = 0x40 @ FIQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S index fae99ffe..a8506c70 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S @@ -19,15 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" */ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + INT_MASK = 0x03F diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S index 4fa3d25e..e60fc343 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + @/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for @ applications calling this function from to 16-bit Thumb mode. */ @ diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S index 5cd41268..2bf80c3c 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + @/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for @ applications calling this function from to 16-bit Thumb mode. */ @ diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S index 16a6ce01..f40716b6 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + #ifdef TX_ENABLE_FIQ_SUPPORT DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S index 36cdcd44..86ba2bf9 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + IRQ_DISABLE = 0x80 @ IRQ disable bit MODE_MASK = 0x1F @ Mode mask SYS_MODE_BITS = 0x1F @ System mode bits diff --git a/ports/cortex_r5/gnu/src/tx_thread_schedule.S b/ports/cortex_r5/gnu/src/tx_thread_schedule.S index d7b6ebce..446f15a9 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_r5/gnu/src/tx_thread_schedule.S @@ -19,18 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_execute_ptr .global _tx_thread_current_ptr .global _tx_timer_time_slice diff --git a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S index 2e7a01da..229ddda8 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm SVC_MODE = 0x13 @ SVC mode diff --git a/ports/cortex_r5/gnu/src/tx_thread_system_return.S b/ports/cortex_r5/gnu/src/tx_thread_system_return.S index 438a2298..a975b823 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_r5/gnu/src/tx_thread_system_return.S @@ -19,16 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @ @ diff --git a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S index d9e6c0ae..dd7c54c7 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .global _tx_thread_system_state .global _tx_thread_current_ptr .global _tx_execution_isr_enter diff --git a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S index a69a4b81..8262ba82 100644 --- a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S @@ -19,17 +19,10 @@ @/** */ @/**************************************************************************/ @/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_timer.h" -@#include "tx_thread.h" -@ -@ +#ifdef TX_INCLUDE_USER_DEFINE_FILE +#include "tx_user.h" +#endif + .arm @ diff --git a/ports/cortex_r5/iar/inc/tx_port.h b/ports/cortex_r5/iar/inc/tx_port.h index ddccbcab..81d19954 100644 --- a/ports/cortex_r5/iar/inc/tx_port.h +++ b/ports/cortex_r5/iar/inc/tx_port.h @@ -367,7 +367,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r5/iar/src/tx_thread_context_restore.s b/ports/cortex_r5/iar/src/tx_thread_context_restore.s index deb16b8e..24e7eefb 100644 --- a/ports/cortex_r5/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/iar/src/tx_thread_context_restore.s @@ -131,7 +131,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports/cortex_r7/ghs/inc/tx_port.h b/ports/cortex_r7/ghs/inc/tx_port.h index 6518d89e..dc3e48ac 100644 --- a/ports/cortex_r7/ghs/inc/tx_port.h +++ b/ports/cortex_r7/ghs/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R7/Green Hills Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R7/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/linux/gnu/inc/tx_port.h b/ports/linux/gnu/inc/tx_port.h index 024b12bd..c50aceb3 100644 --- a/ports/linux/gnu/inc/tx_port.h +++ b/ports/linux/gnu/inc/tx_port.h @@ -545,7 +545,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/risc-v32/iar/inc/tx_port.h b/ports/risc-v32/iar/inc/tx_port.h index 2693df08..67877794 100644 --- a/ports/risc-v32/iar/inc/tx_port.h +++ b/ports/risc-v32/iar/inc/tx_port.h @@ -266,7 +266,7 @@ unsigned int _tx_thread_interrupt_control(uns #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RISC-V32/IAR Version G6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RISC-V32/IAR Version G6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/risc-v32/iar/src/tx_thread_context_restore.s b/ports/risc-v32/iar/src/tx_thread_context_restore.s index 8a23b6e8..3d497f26 100644 --- a/ports/risc-v32/iar/src/tx_thread_context_restore.s +++ b/ports/risc-v32/iar/src/tx_thread_context_restore.s @@ -180,7 +180,7 @@ _tx_thread_context_restore: /* } */ _tx_thread_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) || (_tx_thread_preempt_disable)) { */ diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h new file mode 100644 index 00000000..d5cb5e70 --- /dev/null +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -0,0 +1,298 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RISC-V64/GNU */ +/* 6.2.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +#ifdef __ASSEMBLER__ + + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#else /*not __ASSEMBLER__ */ + +/* Include for memset. */ +#include + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED +#define ALIGN_TYPE_DEFINED +#define ALIGN_TYPE ULONG64 + + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +ULONG64 _tx_thread_interrupt_control(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register ULONG64 interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA ULONG64 interrupt_save; +/* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus. */ +#define TX_DISABLE {__asm__ ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : );}; +/* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus. */ +#define TX_RESTORE {register ULONG64 __tempmask = interrupt_save & 0x08; \ + __asm__ ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : );}; + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RISC-V64/GNU Version 6.2.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + +#endif /*not __ASSEMBLER__ */ +#endif diff --git a/ports/risc-v64/gnu/src/tx_initialize_low_level.S b/ports/risc-v64/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..d99ec144 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .data + .global __tx_free_memory_start +__tx_free_memory_start: + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level +_tx_initialize_low_level: + sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer + + la t0, __tx_free_memory_start // Pickup first free address + sd t0, _tx_initialize_unused_memory, t1 // Save unused memory address + +#ifdef __riscv_flen + fscsr x0 +#endif + + ret + + + /* Define the actual timer interrupt/exception handler. */ + + .global timer1_plic_IRQHandler + //.global __minterrupt_000007 + //EXTWEAK __require_minterrupt_vector_table +timer1_plic_IRQHandler: +//__minterrupt_000007: + //REQUIRE __require_minterrupt_vector_table + + + /* Before calling _tx_thread_context_save, we have to allocate an interrupt + stack frame and save the current value of x1 (ra). */ +//#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) +// addi sp, sp, -520 // Allocate space for all registers - with floating point enabled +//#else +// addi sp, sp, -256 // Allocate space for all registers - without floating point enabled +//#endif +// sd x1, 224(sp) // Store RA +// call _tx_thread_context_save // Call ThreadX context save + + /* Call the ThreadX timer routine. */ + call _tx_timer_interrupt // Call timer interrupt handler + call timer1_interrupt + ret + /* Timer interrupt processing is done, jump to ThreadX context restore. */ +// j _tx_thread_context_restore // Jump to ThreadX context restore function. Note: this does not return! diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..55ba6ac0 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,375 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_port.h" + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_exit // Call the ISR execution exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + la t0, _tx_thread_system_state // Pickup addr of nested interrupt count + LOAD t1, 0(t0) // Pickup nested interrupt count + addi t1, t1, -1 // Decrement the nested interrupt counter + STORE t1, 0(t0) // Store new nested count + beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*REGBYTES(sp) // Recover ft0 + flw f1, 32*REGBYTES(sp) // Recover ft1 + flw f2, 33*REGBYTES(sp) // Recover ft2 + flw f3, 34*REGBYTES(sp) // Recover ft3 + flw f4, 35*REGBYTES(sp) // Recover ft4 + flw f5, 36*REGBYTES(sp) // Recover ft5 + flw f6, 37*REGBYTES(sp) // Recover ft6 + flw f7, 38*REGBYTES(sp) // Recover ft7 + flw f10,41*REGBYTES(sp) // Recover fa0 + flw f11,42*REGBYTES(sp) // Recover fa1 + flw f12,43*REGBYTES(sp) // Recover fa2 + flw f13,44*REGBYTES(sp) // Recover fa3 + flw f14,45*REGBYTES(sp) // Recover fa4 + flw f15,46*REGBYTES(sp) // Recover fa5 + flw f16,47*REGBYTES(sp) // Recover fa6 + flw f17,48*REGBYTES(sp) // Recover fa7 + flw f28,59*REGBYTES(sp) // Recover ft8 + flw f29,60*REGBYTES(sp) // Recover ft9 + flw f30,61*REGBYTES(sp) // Recover ft10 + flw f31,62*REGBYTES(sp) // Recover ft11 + lw t0, 63*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#elif defined(__riscv_float_abi_double) + fld f0, 31*REGBYTES(sp) // Recover ft0 + fld f1, 32*REGBYTES(sp) // Recover ft1 + fld f2, 33*REGBYTES(sp) // Recover ft2 + fld f3, 34*REGBYTES(sp) // Recover ft3 + fld f4, 35*REGBYTES(sp) // Recover ft4 + fld f5, 36*REGBYTES(sp) // Recover ft5 + fld f6, 37*REGBYTES(sp) // Recover ft6 + fld f7, 38*REGBYTES(sp) // Recover ft7 + fld f10,41*REGBYTES(sp) // Recover fa0 + fld f11,42*REGBYTES(sp) // Recover fa1 + fld f12,43*REGBYTES(sp) // Recover fa2 + fld f13,44*REGBYTES(sp) // Recover fa3 + fld f14,45*REGBYTES(sp) // Recover fa4 + fld f15,46*REGBYTES(sp) // Recover fa5 + fld f16,47*REGBYTES(sp) // Recover fa6 + fld f17,48*REGBYTES(sp) // Recover fa7 + fld f28,59*REGBYTES(sp) // Recover ft8 + fld f29,60*REGBYTES(sp) // Recover ft9 + fld f30,61*REGBYTES(sp) // Recover ft10 + fld f31,62*REGBYTES(sp) // Recover ft11 + LOAD t0, 63*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#endif + + /* Recover standard registers. */ + + /* Restore registers, + Skip global pointer because that does not change. + Also skip the saved registers since they have been restored by any function we called, + except s0 since we use it ourselves. */ + + LOAD t0, 30*REGBYTES(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + li t0, 0x1880 // Prepare MPIP + csrw mstatus, t0 // Enable MPIP + + LOAD x1, 28*REGBYTES(sp) // Recover RA + LOAD x5, 19*REGBYTES(sp) // Recover t0 + LOAD x6, 18*REGBYTES(sp) // Recover t1 + LOAD x7, 17*REGBYTES(sp) // Recover t2 + LOAD x8, 12*REGBYTES(sp) // Recover s0 + LOAD x10, 27*REGBYTES(sp) // Recover a0 + LOAD x11, 26*REGBYTES(sp) // Recover a1 + LOAD x12, 25*REGBYTES(sp) // Recover a2 + LOAD x13, 24*REGBYTES(sp) // Recover a3 + LOAD x14, 23*REGBYTES(sp) // Recover a4 + LOAD x15, 22*REGBYTES(sp) // Recover a5 + LOAD x16, 21*REGBYTES(sp) // Recover a6 + LOAD x17, 20*REGBYTES(sp) // Recover a7 + LOAD x28, 16*REGBYTES(sp) // Recover t3 + LOAD x29, 15*REGBYTES(sp) // Recover t4 + LOAD x30, 14*REGBYTES(sp) // Recover t5 + LOAD x31, 13*REGBYTES(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } */ +_tx_thread_not_nested_restore: + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LOAD t1, _tx_thread_current_ptr // Pickup current thread pointer + beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore + + LOAD t2, _tx_thread_preempt_disable // Pickup preempt disable flag + bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread + + LOAD t2, _tx_thread_execute_ptr // Pickup thread execute pointer + bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt + + +_tx_thread_no_preempt_restore: + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* SP = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LOAD sp, 2*REGBYTES(t1) // Switch back to thread's stack + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*REGBYTES(sp) // Recover ft0 + flw f1, 32*REGBYTES(sp) // Recover ft1 + flw f2, 33*REGBYTES(sp) // Recover ft2 + flw f3, 34*REGBYTES(sp) // Recover ft3 + flw f4, 35*REGBYTES(sp) // Recover ft4 + flw f5, 36*REGBYTES(sp) // Recover ft5 + flw f6, 37*REGBYTES(sp) // Recover ft6 + flw f7, 38*REGBYTES(sp) // Recover ft7 + flw f10,41*REGBYTES(sp) // Recover fa0 + flw f11,42*REGBYTES(sp) // Recover fa1 + flw f12,43*REGBYTES(sp) // Recover fa2 + flw f13,44*REGBYTES(sp) // Recover fa3 + flw f14,45*REGBYTES(sp) // Recover fa4 + flw f15,46*REGBYTES(sp) // Recover fa5 + flw f16,47*REGBYTES(sp) // Recover fa6 + flw f17,48*REGBYTES(sp) // Recover fa7 + flw f28,59*REGBYTES(sp) // Recover ft8 + flw f29,60*REGBYTES(sp) // Recover ft9 + flw f30,61*REGBYTES(sp) // Recover ft10 + flw f31,62*REGBYTES(sp) // Recover ft11 + lw t0, 63*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#elif defined(__riscv_float_abi_double) + fld f0, 31*REGBYTES(sp) // Recover ft0 + fld f1, 32*REGBYTES(sp) // Recover ft1 + fld f2, 33*REGBYTES(sp) // Recover ft2 + fld f3, 34*REGBYTES(sp) // Recover ft3 + fld f4, 35*REGBYTES(sp) // Recover ft4 + fld f5, 36*REGBYTES(sp) // Recover ft5 + fld f6, 37*REGBYTES(sp) // Recover ft6 + fld f7, 38*REGBYTES(sp) // Recover ft7 + fld f10,41*REGBYTES(sp) // Recover fa0 + fld f11,42*REGBYTES(sp) // Recover fa1 + fld f12,43*REGBYTES(sp) // Recover fa2 + fld f13,44*REGBYTES(sp) // Recover fa3 + fld f14,45*REGBYTES(sp) // Recover fa4 + fld f15,46*REGBYTES(sp) // Recover fa5 + fld f16,47*REGBYTES(sp) // Recover fa6 + fld f17,48*REGBYTES(sp) // Recover fa7 + fld f28,59*REGBYTES(sp) // Recover ft8 + fld f29,60*REGBYTES(sp) // Recover ft9 + fld f30,61*REGBYTES(sp) // Recover ft10 + fld f31,62*REGBYTES(sp) // Recover ft11 + LOAD t0, 63*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#endif + + /* Recover the saved context and return to the point of interrupt. */ + + /* Recover standard registers. */ + /* Restore registers, + Skip global pointer because that does not change */ + + LOAD t0, 240(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + li t0, 0x1880 // Prepare MPIP + csrw mstatus, t0 // Enable MPIP + + LOAD x1, 28*REGBYTES(sp) // Recover RA + LOAD x5, 19*REGBYTES(sp) // Recover t0 + LOAD x6, 18*REGBYTES(sp) // Recover t1 + LOAD x7, 17*REGBYTES(sp) // Recover t2 + LOAD x8, 12*REGBYTES(sp) // Recover s0 + LOAD x10, 27*REGBYTES(sp) // Recover a0 + LOAD x11, 26*REGBYTES(sp) // Recover a1 + LOAD x12, 25*REGBYTES(sp) // Recover a2 + LOAD x13, 24*REGBYTES(sp) // Recover a3 + LOAD x14, 23*REGBYTES(sp) // Recover a4 + LOAD x15, 22*REGBYTES(sp) // Recover a5 + LOAD x16, 21*REGBYTES(sp) // Recover a6 + LOAD x17, 20*REGBYTES(sp) // Recover a7 + LOAD x28, 16*REGBYTES(sp) // Recover t3 + LOAD x29, 15*REGBYTES(sp) // Recover t4 + LOAD x30, 14*REGBYTES(sp) // Recover t5 + LOAD x31, 13*REGBYTES(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } + else + { */ +_tx_thread_preempt_restore: + /* Instead of directly activating the thread again, ensure we save the + entire stack frame by saving the remaining registers. */ + + LOAD t0, 2*REGBYTES(t1) // Pickup thread's stack pointer + ori t3, x0, 1 // Build interrupt stack type + STORE t3, 0(t0) // Store stack type + + /* Store floating point preserved registers. */ +#ifdef __riscv_float_abi_single + fsw f8, 39*REGBYTES(t0) // Store fs0 + fsw f9, 40*REGBYTES(t0) // Store fs1 + fsw f18, 49*REGBYTES(t0) // Store fs2 + fsw f19, 50*REGBYTES(t0) // Store fs3 + fsw f20, 51*REGBYTES(t0) // Store fs4 + fsw f21, 52*REGBYTES(t0) // Store fs5 + fsw f22, 53*REGBYTES(t0) // Store fs6 + fsw f23, 54*REGBYTES(t0) // Store fs7 + fsw f24, 55*REGBYTES(t0) // Store fs8 + fsw f25, 56*REGBYTES(t0) // Store fs9 + fsw f26, 57*REGBYTES(t0) // Store fs10 + fsw f27, 58*REGBYTES(t0) // Store fs11 +#elif defined(__riscv_float_abi_double) + fsd f8, 39*REGBYTES(t0) // Store fs0 + fsd f9, 40*REGBYTES(t0) // Store fs1 + fsd f18, 49*REGBYTES(t0) // Store fs2 + fsd f19, 50*REGBYTES(t0) // Store fs3 + fsd f20, 51*REGBYTES(t0) // Store fs4 + fsd f21, 52*REGBYTES(t0) // Store fs5 + fsd f22, 53*REGBYTES(t0) // Store fs6 + fsd f23, 54*REGBYTES(t0) // Store fs7 + fsd f24, 55*REGBYTES(t0) // Store fs8 + fsd f25, 56*REGBYTES(t0) // Store fs9 + fsd f26, 57*REGBYTES(t0) // Store fs10 + fsd f27, 58*REGBYTES(t0) // Store fs11 +#endif + + /* Store standard preserved registers. */ + + STORE x9, 11*REGBYTES(t0) // Store s1 + STORE x18, 10*REGBYTES(t0) // Store s2 + STORE x19, 9*REGBYTES(t0) // Store s3 + STORE x20, 8*REGBYTES(t0) // Store s4 + STORE x21, 7*REGBYTES(t0) // Store s5 + STORE x22, 6*REGBYTES(t0) // Store s6 + STORE x23, 5*REGBYTES(t0) // Store s7 + STORE x24, 4*REGBYTES(t0) // Store s8 + STORE x25, 3*REGBYTES(t0) // Store s9 + STORE x26, 2*REGBYTES(t0) // Store s10 + STORE x27, 1*REGBYTES(t0) // Store s11 + // Note: s0 is already stored! + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + la t0, _tx_timer_time_slice // Pickup time slice variable address + LOAD t2, 0(t0) // Pickup time slice + beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice + _tx_timer_time_slice = 0; */ + + STORE t2, 6*REGBYTES(t1) // Save current time slice + STORE x0, 0(t0) // Clear global time slice + + + /* } */ +_tx_thread_dont_save_ts: + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + STORE x0, _tx_thread_current_ptr, t0 // Clear current thread pointer*/ + /* } */ + +_tx_thread_idle_system_restore: + /* Just return back to the scheduler! */ + j _tx_thread_schedule // Return to scheduler + +/* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..5e0e4be0 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -0,0 +1,284 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_port.h" + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that interrupts are locked + out and the interrupt stack fame has been allocated and x1 (ra) has + been saved on the stack. */ + + STORE x5, 19*REGBYTES(sp) // First store t0 and t1 + STORE x6, 18*REGBYTES(sp) + + la x5, _tx_thread_system_state // Pickup address of system state + LOAD x6, 0(x5) // Pickup system state + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + beqz x6, _tx_thread_not_nested_save // If 0, first interrupt condition + addi x6, x6, 1 // Increment the interrupt counter + STORE x6, 0(x5) // Store the interrupt counter + + /* Nested interrupt condition. + Save the reset of the scratch registers on the stack and return to the + calling ISR. */ + + STORE x7, 17*REGBYTES(sp) // Store t2 + STORE x8, 12*REGBYTES(sp) // Store s0 + STORE x10, 27*REGBYTES(sp) // Store a0 + STORE x11, 26*REGBYTES(sp) // Store a1 + STORE x12, 25*REGBYTES(sp) // Store a2 + STORE x13, 24*REGBYTES(sp) // Store a3 + STORE x14, 23*REGBYTES(sp) // Store a4 + STORE x15, 22*REGBYTES(sp) // Store a5 + STORE x16, 21*REGBYTES(sp) // Store a6 + STORE x17, 20*REGBYTES(sp) // Store a7 + STORE x28, 16*REGBYTES(sp) // Store t3 + STORE x29, 15*REGBYTES(sp) // Store t4 + STORE x30, 14*REGBYTES(sp) // Store t5 + STORE x31, 13*REGBYTES(sp) // Store t6 + csrr t0, mepc // Load exception program counter + STORE t0, 30*REGBYTES(sp) // Save it on the stack + + /* Save floating point scratch registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*REGBYTES(sp) // Store ft0 + fsw f1, 32*REGBYTES(sp) // Store ft1 + fsw f2, 33*REGBYTES(sp) // Store ft2 + fsw f3, 34*REGBYTES(sp) // Store ft3 + fsw f4, 35*REGBYTES(sp) // Store ft4 + fsw f5, 36*REGBYTES(sp) // Store ft5 + fsw f6, 37*REGBYTES(sp) // Store ft6 + fsw f7, 38*REGBYTES(sp) // Store ft7 + fsw f10,41*REGBYTES(sp) // Store fa0 + fsw f11,42*REGBYTES(sp) // Store fa1 + fsw f12,43*REGBYTES(sp) // Store fa2 + fsw f13,44*REGBYTES(sp) // Store fa3 + fsw f14,45*REGBYTES(sp) // Store fa4 + fsw f15,46*REGBYTES(sp) // Store fa5 + fsw f16,47*REGBYTES(sp) // Store fa6 + fsw f17,48*REGBYTES(sp) // Store fa7 + fsw f28,59*REGBYTES(sp) // Store ft8 + fsw f29,60*REGBYTES(sp) // Store ft9 + fsw f30,61*REGBYTES(sp) // Store ft10 + fsw f31,62*REGBYTES(sp) // Store ft11 + csrr t0, fcsr + STORE t0, 63*REGBYTES(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*REGBYTES(sp) // Store ft0 + fsd f1, 32*REGBYTES(sp) // Store ft1 + fsd f2, 33*REGBYTES(sp) // Store ft2 + fsd f3, 34*REGBYTES(sp) // Store ft3 + fsd f4, 35*REGBYTES(sp) // Store ft4 + fsd f5, 36*REGBYTES(sp) // Store ft5 + fsd f6, 37*REGBYTES(sp) // Store ft6 + fsd f7, 38*REGBYTES(sp) // Store ft7 + fsd f10,41*REGBYTES(sp) // Store fa0 + fsd f11,42*REGBYTES(sp) // Store fa1 + fsd f12,43*REGBYTES(sp) // Store fa2 + fsd f13,44*REGBYTES(sp) // Store fa3 + fsd f14,45*REGBYTES(sp) // Store fa4 + fsd f15,46*REGBYTES(sp) // Store fa5 + fsd f16,47*REGBYTES(sp) // Store fa6 + fsd f17,48*REGBYTES(sp) // Store fa7 + fsd f28,59*REGBYTES(sp) // Store ft8 + fsd f29,60*REGBYTES(sp) // Store ft9 + fsd f30,61*REGBYTES(sp) // Store ft10 + fsd f31,62*REGBYTES(sp) // Store ft11 + csrr t0, fcsr + STORE t0, 63*REGBYTES(sp) // Store fcsr +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to calling ISR + +_tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + addi x6, x6, 1 // Increment the interrupt counter + STORE x6, 0(x5) // Store the interrupt counter + + /* Not nested: Find the user thread that was running and load our SP */ + + LOAD x5, _tx_thread_current_ptr // Pickup current thread pointer + beqz x5, _tx_thread_idle_system_save // If NULL, idle system was interrupted + + /* Save the standard scratch registers. */ + + STORE x7, 17*REGBYTES(sp) // Store t2 + STORE x8, 12*REGBYTES(sp) // Store s0 + STORE x10, 27*REGBYTES(sp) // Store a0 + STORE x11, 26*REGBYTES(sp) // Store a1 + STORE x12, 25*REGBYTES(sp) // Store a2 + STORE x13, 24*REGBYTES(sp) // Store a3 + STORE x14, 23*REGBYTES(sp) // Store a4 + STORE x15, 22*REGBYTES(sp) // Store a5 + STORE x16, 21*REGBYTES(sp) // Store a6 + STORE x17, 20*REGBYTES(sp) // Store a7 + STORE x28, 16*REGBYTES(sp) // Store t3 + STORE x29, 15*REGBYTES(sp) // Store t4 + STORE x30, 14*REGBYTES(sp) // Store t5 + STORE x31, 13*REGBYTES(sp) // Store t6 + + csrr t0, mepc // Load exception program counter + STORE t0, 30*REGBYTES(sp) // Save it on the stack + + /* Save floating point scratch registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*REGBYTES(sp) // Store ft0 + fsw f1, 32*REGBYTES(sp) // Store ft1 + fsw f2, 33*REGBYTES(sp) // Store ft2 + fsw f3, 34*REGBYTES(sp) // Store ft3 + fsw f4, 35*REGBYTES(sp) // Store ft4 + fsw f5, 36*REGBYTES(sp) // Store ft5 + fsw f6, 37*REGBYTES(sp) // Store ft6 + fsw f7, 38*REGBYTES(sp) // Store ft7 + fsw f10,41*REGBYTES(sp) // Store fa0 + fsw f11,42*REGBYTES(sp) // Store fa1 + fsw f12,43*REGBYTES(sp) // Store fa2 + fsw f13,44*REGBYTES(sp) // Store fa3 + fsw f14,45*REGBYTES(sp) // Store fa4 + fsw f15,46*REGBYTES(sp) // Store fa5 + fsw f16,47*REGBYTES(sp) // Store fa6 + fsw f17,48*REGBYTES(sp) // Store fa7 + fsw f28,59*REGBYTES(sp) // Store ft8 + fsw f29,60*REGBYTES(sp) // Store ft9 + fsw f30,61*REGBYTES(sp) // Store ft10 + fsw f31,62*REGBYTES(sp) // Store ft11 + csrr t0, fcsr + STORE t0, 63*REGBYTES(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*REGBYTES(sp) // Store ft0 + fsd f1, 32*REGBYTES(sp) // Store ft1 + fsd f2, 33*REGBYTES(sp) // Store ft2 + fsd f3, 34*REGBYTES(sp) // Store ft3 + fsd f4, 35*REGBYTES(sp) // Store ft4 + fsd f5, 36*REGBYTES(sp) // Store ft5 + fsd f6, 37*REGBYTES(sp) // Store ft6 + fsd f7, 38*REGBYTES(sp) // Store ft7 + fsd f10,41*REGBYTES(sp) // Store fa0 + fsd f11,42*REGBYTES(sp) // Store fa1 + fsd f12,43*REGBYTES(sp) // Store fa2 + fsd f13,44*REGBYTES(sp) // Store fa3 + fsd f14,45*REGBYTES(sp) // Store fa4 + fsd f15,46*REGBYTES(sp) // Store fa5 + fsd f16,47*REGBYTES(sp) // Store fa6 + fsd f17,48*REGBYTES(sp) // Store fa7 + fsd f28,59*REGBYTES(sp) // Store ft8 + fsd f29,60*REGBYTES(sp) // Store ft9 + fsd f30,61*REGBYTES(sp) // Store ft10 + fsd f31,62*REGBYTES(sp) // Store ft11 + csrr t0, fcsr + STORE t0, 63*REGBYTES(sp) // Store fcsr +#endif + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LOAD t1, _tx_thread_current_ptr // Pickup current thread pointer + STORE sp, 2*REGBYTES(t1) // Save stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* _tx_execution_isr_enter is called with thread stack pointer */ + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + + LOAD sp, _tx_thread_system_stack_ptr // Switch to system stack + ret // Return to calling ISR + + /* } + else + { */ + +_tx_thread_idle_system_save: + + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + /* Interrupt occurred in the scheduling loop. */ + + /* } +} */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*REGBYTES // Recover the reserved stack space +#endif + ret // Return to calling ISR diff --git a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..d0a07636 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + RETURN_MASK = 0x000000000000000F + SET_SR_MASK = 0xFFFFFFFFFFFFFFF0 + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control +_tx_thread_interrupt_control: + /* Pickup current interrupt lockout posture. */ + + csrr t0, mstatus + mv t1, t0 // Save original mstatus for return + + /* Apply the new interrupt posture. */ + + li t2, SET_SR_MASK // Build set SR mask + and t0, t0, t2 // Isolate interrupt lockout bits + or t0, t0, a0 // Put new lockout bits in + csrw mstatus, t0 + andi a0, t1, RETURN_MASK // Return original mstatus. + ret +/* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..2a2d4479 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -0,0 +1,302 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_port.h" + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + csrsi mstatus, 0x08 // Enable interrupts + + /* Wait for a thread to execute. */ + /* do + { */ + + la t0, _tx_thread_execute_ptr // Pickup address of execute ptr +_tx_thread_schedule_loop: + LOAD t1, 0(t0) // Pickup next thread to execute + beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + csrci mstatus, 0x08 // Lockout interrupts + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + STORE t1, 0(t0) // Set current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LOAD t2, 1*REGBYTES(t1) // Pickup run count + LOAD t3, 6*REGBYTES(t1) // Pickup time slice value + addi t2, t2, 1 // Increment run count + STORE t2, 1*REGBYTES(t1) // Store new run count + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + la t2, _tx_timer_time_slice // Pickup time-slice variable address + + /* Switch to the thread's stack. */ + /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + LOAD sp, 2*REGBYTES(t1) // Switch to thread's stack + STORE t3, 0(t2) // Store new time-slice*/ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_enter // Call the thread execution enter function +#endif + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LOAD t2, 0(sp) // Pickup stack type + beqz t2, _tx_thread_synch_return // If 0, solicited thread return + + /* Determine if floating point registers need to be recovered. */ + +#if defined(__riscv_float_abi_single) + flw f0, 31*REGBYTES(sp) // Recover ft0 + flw f1, 32*REGBYTES(sp) // Recover ft1 + flw f2, 33*REGBYTES(sp) // Recover ft2 + flw f3, 34*REGBYTES(sp) // Recover ft3 + flw f4, 35*REGBYTES(sp) // Recover ft4 + flw f5, 36*REGBYTES(sp) // Recover ft5 + flw f6, 37*REGBYTES(sp) // Recover ft6 + flw f7, 38*REGBYTES(sp) // Recover ft7 + flw f8, 39*REGBYTES(sp) // Recover fs0 + flw f9, 40*REGBYTES(sp) // Recover fs1 + flw f10,41*REGBYTES(sp) // Recover fa0 + flw f11,42*REGBYTES(sp) // Recover fa1 + flw f12,43*REGBYTES(sp) // Recover fa2 + flw f13,44*REGBYTES(sp) // Recover fa3 + flw f14,45*REGBYTES(sp) // Recover fa4 + flw f15,46*REGBYTES(sp) // Recover fa5 + flw f16,47*REGBYTES(sp) // Recover fa6 + flw f17,48*REGBYTES(sp) // Recover fa7 + flw f18,49*REGBYTES(sp) // Recover fs2 + flw f19,50*REGBYTES(sp) // Recover fs3 + flw f20,51*REGBYTES(sp) // Recover fs4 + flw f21,52*REGBYTES(sp) // Recover fs5 + flw f22,53*REGBYTES(sp) // Recover fs6 + flw f23,54*REGBYTES(sp) // Recover fs7 + flw f24,55*REGBYTES(sp) // Recover fs8 + flw f25,56*REGBYTES(sp) // Recover fs9 + flw f26,57*REGBYTES(sp) // Recover fs10 + flw f27,58*REGBYTES(sp) // Recover fs11 + flw f28,59*REGBYTES(sp) // Recover ft8 + flw f29,60*REGBYTES(sp) // Recover ft9 + flw f30,61*REGBYTES(sp) // Recover ft10 + flw f31,62*REGBYTES(sp) // Recover ft11 + LOAD t0, 63*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#elif defined(__riscv_float_abi_double) + fld f0, 31*REGBYTES(sp) // Recover ft0 + fld f1, 32*REGBYTES(sp) // Recover ft1 + fld f2, 33*REGBYTES(sp) // Recover ft2 + fld f3, 34*REGBYTES(sp) // Recover ft3 + fld f4, 35*REGBYTES(sp) // Recover ft4 + fld f5, 36*REGBYTES(sp) // Recover ft5 + fld f6, 37*REGBYTES(sp) // Recover ft6 + fld f7, 38*REGBYTES(sp) // Recover ft7 + fld f8, 39*REGBYTES(sp) // Recover fs0 + fld f9, 40*REGBYTES(sp) // Recover fs1 + fld f10,41*REGBYTES(sp) // Recover fa0 + fld f11,42*REGBYTES(sp) // Recover fa1 + fld f12,43*REGBYTES(sp) // Recover fa2 + fld f13,44*REGBYTES(sp) // Recover fa3 + fld f14,45*REGBYTES(sp) // Recover fa4 + fld f15,46*REGBYTES(sp) // Recover fa5 + fld f16,47*REGBYTES(sp) // Recover fa6 + fld f17,48*REGBYTES(sp) // Recover fa7 + fld f18,49*REGBYTES(sp) // Recover fs2 + fld f19,50*REGBYTES(sp) // Recover fs3 + fld f20,51*REGBYTES(sp) // Recover fs4 + fld f21,52*REGBYTES(sp) // Recover fs5 + fld f22,53*REGBYTES(sp) // Recover fs6 + fld f23,54*REGBYTES(sp) // Recover fs7 + fld f24,55*REGBYTES(sp) // Recover fs8 + fld f25,56*REGBYTES(sp) // Recover fs9 + fld f26,57*REGBYTES(sp) // Recover fs10 + fld f27,58*REGBYTES(sp) // Recover fs11 + fld f28,59*REGBYTES(sp) // Recover ft8 + fld f29,60*REGBYTES(sp) // Recover ft9 + fld f30,61*REGBYTES(sp) // Recover ft10 + fld f31,62*REGBYTES(sp) // Recover ft11 + LOAD t0, 63*REGBYTES(sp) // Recover fcsr +#endif + + /* Recover standard registers. */ + + LOAD t0, 30*REGBYTES(sp) // Recover mepc + csrw mepc, t0 // Store mepc + li t0, 0x1880 // Prepare MPIP + csrw mstatus, t0 // Enable MPIP + + LOAD x1, 28*REGBYTES(sp) // Recover RA + LOAD x5, 19*REGBYTES(sp) // Recover t0 + LOAD x6, 18*REGBYTES(sp) // Recover t1 + LOAD x7, 17*REGBYTES(sp) // Recover t2 + LOAD x8, 12*REGBYTES(sp) // Recover s0 + LOAD x9, 11*REGBYTES(sp) // Recover s1 + LOAD x10, 27*REGBYTES(sp) // Recover a0 + LOAD x11, 26*REGBYTES(sp) // Recover a1 + LOAD x12, 25*REGBYTES(sp) // Recover a2 + LOAD x13, 24*REGBYTES(sp) // Recover a3 + LOAD x14, 23*REGBYTES(sp) // Recover a4 + LOAD x15, 22*REGBYTES(sp) // Recover a5 + LOAD x16, 21*REGBYTES(sp) // Recover a6 + LOAD x17, 20*REGBYTES(sp) // Recover a7 + LOAD x18, 10*REGBYTES(sp) // Recover s2 + LOAD x19, 9*REGBYTES(sp) // Recover s3 + LOAD x20, 8*REGBYTES(sp) // Recover s4 + LOAD x21, 7*REGBYTES(sp) // Recover s5 + LOAD x22, 6*REGBYTES(sp) // Recover s6 + LOAD x23, 5*REGBYTES(sp) // Recover s7 + LOAD x24, 4*REGBYTES(sp) // Recover s8 + LOAD x25, 3*REGBYTES(sp) // Recover s9 + LOAD x26, 2*REGBYTES(sp) // Recover s10 + LOAD x27, 1*REGBYTES(sp) // Recover s11 + LOAD x28, 16*REGBYTES(sp) // Recover t3 + LOAD x29, 15*REGBYTES(sp) // Recover t4 + LOAD x30, 14*REGBYTES(sp) // Recover t5 + LOAD x31, 13*REGBYTES(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point registers +#else + addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point registers +#endif + mret // Return to point of interrupt + +_tx_thread_synch_return: + +#if defined(__riscv_float_abi_single) + flw f8, 15*REGBYTES(sp) // Recover fs0 + flw f9, 16*REGBYTES(sp) // Recover fs1 + flw f18,17*REGBYTES(sp) // Recover fs2 + flw f19,18*REGBYTES(sp) // Recover fs3 + flw f20,19*REGBYTES(sp) // Recover fs4 + flw f21,20*REGBYTES(sp) // Recover fs5 + flw f22,21*REGBYTES(sp) // Recover fs6 + flw f23,22*REGBYTES(sp) // Recover fs7 + flw f24,23*REGBYTES(sp) // Recover fs8 + flw f25,24*REGBYTES(sp) // Recover fs9 + flw f26,25*REGBYTES(sp) // Recover fs10 + flw f27,26*REGBYTES(sp) // Recover fs11 + LOAD t0, 27*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#elif defined(__riscv_float_abi_double) + fld f8, 15*REGBYTES(sp) // Recover fs0 + fld f9, 16*REGBYTES(sp) // Recover fs1 + fld f18,17*REGBYTES(sp) // Recover fs2 + fld f19,18*REGBYTES(sp) // Recover fs3 + fld f20,19*REGBYTES(sp) // Recover fs4 + fld f21,20*REGBYTES(sp) // Recover fs5 + fld f22,21*REGBYTES(sp) // Recover fs6 + fld f23,22*REGBYTES(sp) // Recover fs7 + fld f24,23*REGBYTES(sp) // Recover fs8 + fld f25,24*REGBYTES(sp) // Recover fs9 + fld f26,25*REGBYTES(sp) // Recover fs10 + fld f27,26*REGBYTES(sp) // Recover fs11 + LOAD t0, 27*REGBYTES(sp) // Recover fcsr + csrw fcsr, t0 // +#endif + + /* Recover standard preserved registers. */ + /* Recover standard registers. */ + + LOAD x1, 13*REGBYTES(sp) // Recover RA + LOAD x8, 12*REGBYTES(sp) // Recover s0 + LOAD x9, 11*REGBYTES(sp) // Recover s1 + LOAD x18, 10*REGBYTES(sp) // Recover s2 + LOAD x19, 9*REGBYTES(sp) // Recover s3 + LOAD x20, 8*REGBYTES(sp) // Recover s4 + LOAD x21, 7*REGBYTES(sp) // Recover s5 + LOAD x22, 6*REGBYTES(sp) // Recover s6 + LOAD x23, 5*REGBYTES(sp) // Recover s7 + LOAD x24, 4*REGBYTES(sp) // Recover s8 + LOAD x25, 3*REGBYTES(sp) // Recover s9 + LOAD x26, 2*REGBYTES(sp) // Recover s10 + LOAD x27, 1*REGBYTES(sp) // Recover s11 + LOAD t0, 14*REGBYTES(sp) // Recover mstatus + csrw mstatus, t0 // Store mstatus, enables interrupt +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 29*REGBYTES // Recover stack frame +#else + addi sp, sp, 16*REGBYTES // Recover stack frame +#endif + ret // Return to thread + +/* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_stack_build.S b/ports/risc-v64/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..32c36c6c --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,229 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_port.h" + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build +_tx_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the RISC-V should look like the following after it is built: + Reg Index + Stack Top: 1 0 Interrupt stack frame type + x27 1 Initial s11 + x26 2 Initial s10 + x25 3 Initial s9 + x24 4 Initial s8 + x23 5 Initial s7 + x22 6 Initial s6 + x21 7 Initial s5 + x20 8 Initial s4 + x19 9 Initial s3 + x18 10 Initial s2 + x9 11 Initial s1 + x8 12 Initial s0 + x31 13 Initial t6 + x30 14 Initial t5 + x29 15 Initial t4 + x28 16 Initial t3 + x7 17 Initial t2 + x6 18 Initial t1 + x5 19 Initial t0 + x17 20 Initial a7 + x16 21 Initial a6 + x15 22 Initial a5 + x14 23 Initial a4 + x13 24 Initial a3 + x12 25 Initial a2 + x11 26 Initial a1 + x10 27 Initial a0 + x1 28 Initial ra + -- 29 reserved + mepc 30 Initial mepc +If floating point support: + f0 31 Inital ft0 + f1 32 Inital ft1 + f2 33 Inital ft2 + f3 34 Inital ft3 + f4 35 Inital ft4 + f5 36 Inital ft5 + f6 37 Inital ft6 + f7 38 Inital ft7 + f8 39 Inital fs0 + f9 40 Inital fs1 + f10 41 Inital fa0 + f11 42 Inital fa1 + f12 43 Inital fa2 + f13 44 Inital fa3 + f14 45 Inital fa4 + f15 46 Inital fa5 + f16 47 Inital fa6 + f17 48 Inital fa7 + f18 49 Inital fs2 + f19 50 Inital fs3 + f20 51 Inital fs4 + f21 52 Inital fs5 + f22 53 Inital fs6 + f23 54 Inital fs7 + f24 55 Inital fs8 + f25 56 Inital fs9 + f26 57 Inital fs10 + f27 58 Inital fs11 + f28 59 Inital ft8 + f29 60 Inital ft9 + f30 61 Inital ft10 + f31 62 Inital ft11 + fscr 63 Inital fscr + + Stack Bottom: (higher memory address) */ + + LOAD t0, 4*REGBYTES(a0) // Pickup end of stack area + li t1, ~15 // Build 16-byte alignment mask + and t0, t0, t1 // Make sure 16-byte alignment + + /* Actually build the stack frame. */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, t0, -65*REGBYTES +#else + addi t0, t0, -32*REGBYTES // Allocate space for the stack frame +#endif + li t1, 1 // Build stack type + STORE t1, 0*REGBYTES(t0) // Place stack type on the top + STORE x0, 1*REGBYTES(t0) // Initial s11 + STORE x0, 2*REGBYTES(t0) // Initial s10 + STORE x0, 3*REGBYTES(t0) // Initial s9 + STORE x0, 4*REGBYTES(t0) // Initial s8 + STORE x0, 5*REGBYTES(t0) // Initial s7 + STORE x0, 6*REGBYTES(t0) // Initial s6 + STORE x0, 7*REGBYTES(t0) // Initial s5 + STORE x0, 8*REGBYTES(t0) // Initial s4 + STORE x0, 9*REGBYTES(t0) // Initial s3 + STORE x0, 10*REGBYTES(t0) // Initial s2 + STORE x0, 11*REGBYTES(t0) // Initial s1 + STORE x0, 12*REGBYTES(t0) // Initial s0 + STORE x0, 13*REGBYTES(t0) // Initial t6 + STORE x0, 14*REGBYTES(t0) // Initial t5 + STORE x0, 15*REGBYTES(t0) // Initial t4 + STORE x0, 16*REGBYTES(t0) // Initial t3 + STORE x0, 17*REGBYTES(t0) // Initial t2 + STORE x0, 18*REGBYTES(t0) // Initial t1 + STORE x0, 19*REGBYTES(t0) // Initial t0 + STORE x0, 20*REGBYTES(t0) // Initial a7 + STORE x0, 21*REGBYTES(t0) // Initial a6 + STORE x0, 22*REGBYTES(t0) // Initial a5 + STORE x0, 23*REGBYTES(t0) // Initial a4 + STORE x0, 24*REGBYTES(t0) // Initial a3 + STORE x0, 25*REGBYTES(t0) // Initial a2 + STORE x0, 26*REGBYTES(t0) // Initial a1 + STORE x0, 27*REGBYTES(t0) // Initial a0 + STORE x0, 28*REGBYTES(t0) // Initial ra + STORE a1, 30*REGBYTES(t0) // Initial mepc +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + STORE x0, 31*REGBYTES(t0) // Inital ft0 + STORE x0, 32*REGBYTES(t0) // Inital ft1 + STORE x0, 33*REGBYTES(t0) // Inital ft2 + STORE x0, 34*REGBYTES(t0) // Inital ft3 + STORE x0, 35*REGBYTES(t0) // Inital ft4 + STORE x0, 36*REGBYTES(t0) // Inital ft5 + STORE x0, 37*REGBYTES(t0) // Inital ft6 + STORE x0, 38*REGBYTES(t0) // Inital ft7 + STORE x0, 39*REGBYTES(t0) // Inital fs0 + STORE x0, 40*REGBYTES(t0) // Inital fs1 + STORE x0, 41*REGBYTES(t0) // Inital fa0 + STORE x0, 42*REGBYTES(t0) // Inital fa1 + STORE x0, 43*REGBYTES(t0) // Inital fa2 + STORE x0, 44*REGBYTES(t0) // Inital fa3 + STORE x0, 45*REGBYTES(t0) // Inital fa4 + STORE x0, 46*REGBYTES(t0) // Inital fa5 + STORE x0, 47*REGBYTES(t0) // Inital fa6 + STORE x0, 48*REGBYTES(t0) // Inital fa7 + STORE x0, 49*REGBYTES(t0) // Inital fs2 + STORE x0, 50*REGBYTES(t0) // Inital fs3 + STORE x0, 51*REGBYTES(t0) // Inital fs4 + STORE x0, 52*REGBYTES(t0) // Inital fs5 + STORE x0, 53*REGBYTES(t0) // Inital fs6 + STORE x0, 54*REGBYTES(t0) // Inital fs7 + STORE x0, 55*REGBYTES(t0) // Inital fs8 + STORE x0, 56*REGBYTES(t0) // Inital fs9 + STORE x0, 57*REGBYTES(t0) // Inital fs10 + STORE x0, 58*REGBYTES(t0) // Inital fs11 + STORE x0, 59*REGBYTES(t0) // Inital ft8 + STORE x0, 60*REGBYTES(t0) // Inital ft9 + STORE x0, 61*REGBYTES(t0) // Inital ft10 + STORE x0, 62*REGBYTES(t0) // Inital ft11 + csrr a1, fcsr // Read fcsr and use it for initial value for each thread + STORE a1, 63*REGBYTES(t0) // Initial fscr + STORE x0, 64*REGBYTES(t0) // Reserved word (0) +#else + STORE x0, 31*REGBYTES(t0) // Reserved word (0) +#endif + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = t0; */ + + STORE t0, 2*REGBYTES(a0) // Save stack pointer in thread's + ret // control block and return +/* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_system_return.S b/ports/risc-v64/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..c2b239da --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_thread_system_return.S @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_port.h" + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -29*REGBYTES // Allocate space on the stack - with floating point enabled +#else + addi sp, sp, -16*REGBYTES // Allocate space on the stack - without floating point enabled +#endif + + /* Store floating point preserved registers. */ +#if defined(__riscv_float_abi_single) + fsw f8, 15*REGBYTES(sp) // Store fs0 + fsw f9, 16*REGBYTES(sp) // Store fs1 + fsw f18, 17*REGBYTES(sp) // Store fs2 + fsw f19, 18*REGBYTES(sp) // Store fs3 + fsw f20, 19*REGBYTES(sp) // Store fs4 + fsw f21, 20*REGBYTES(sp) // Store fs5 + fsw f22, 21*REGBYTES(sp) // Store fs6 + fsw f23, 22*REGBYTES(sp) // Store fs7 + fsw f24, 23*REGBYTES(sp) // Store fs8 + fsw f25, 24*REGBYTES(sp) // Store fs9 + fsw f26, 25*REGBYTES(sp) // Store fs10 + fsw f27, 26*REGBYTES(sp) // Store fs11 + csrr t0, fcsr + STORE t0, 27*REGBYTES(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f8, 15*REGBYTES(sp) // Store fs0 + fsd f9, 16*REGBYTES(sp) // Store fs1 + fsd f18, 17*REGBYTES(sp) // Store fs2 + fsd f19, 18*REGBYTES(sp) // Store fs3 + fsd f20, 19*REGBYTES(sp) // Store fs4 + fsd f21, 20*REGBYTES(sp) // Store fs5 + fsd f22, 21*REGBYTES(sp) // Store fs6 + fsd f23, 22*REGBYTES(sp) // Store fs7 + fsd f24, 23*REGBYTES(sp) // Store fs8 + fsd f25, 24*REGBYTES(sp) // Store fs9 + fsd f26, 25*REGBYTES(sp) // Store fs10 + fsd f27, 26*REGBYTES(sp) // Store fs11 + csrr t0, fcsr + STORE t0, 27*REGBYTES(sp) // Store fcsr +#endif + + STORE x0, 0(sp) // Solicited stack type + STORE x1, 13*REGBYTES(sp) // Save RA + STORE x8, 12*REGBYTES(sp) // Save s0 + STORE x9, 11*REGBYTES(sp) // Save s1 + STORE x18, 10*REGBYTES(sp) // Save s2 + STORE x19, 9*REGBYTES(sp) // Save s3 + STORE x20, 8*REGBYTES(sp) // Save s4 + STORE x21, 7*REGBYTES(sp) // Save s5 + STORE x22, 6*REGBYTES(sp) // Save s6 + STORE x23, 5*REGBYTES(sp) // Save s7 + STORE x24, 4*REGBYTES(sp) // Save s8 + STORE x25, 3*REGBYTES(sp) // Save s9 + STORE x26, 2*REGBYTES(sp) // Save s10 + STORE x27, 1*REGBYTES(sp) // Save s11 + csrr t0, mstatus // Pickup mstatus + STORE t0, 14*REGBYTES(sp) // Save mstatus + + + /* Lockout interrupts. - will be enabled in _tx_thread_schedule */ + + csrci mstatus, 0xF + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_exit // Call the thread execution exit function +#endif + + la t0, _tx_thread_current_ptr // Pickup address of pointer + LOAD t1, 0(t0) // Pickup current thread pointer + la t2,_tx_thread_system_stack_ptr // Pickup stack pointer address + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; + SP = _tx_thread_system_stack_ptr; */ + + STORE sp, 2*REGBYTES(t1) // Save stack pointer + LOAD sp, 0(t2) // Switch to system stack + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + la t4, _tx_timer_time_slice // Pickup time slice variable addr + LOAD t3, 0(t4) // Pickup time slice value + la t2, _tx_thread_schedule // Pickup address of scheduling loop + beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STORE t3, 6*REGBYTES(t1) // Save current time-slice for thread + STORE x0, 0(t4) // Clear time-slice variable + + /* } */ +_tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STORE x0, 0(t0) // Clear current thread pointer + jr t2 // Return to thread scheduler + +/* } */ diff --git a/ports/risc-v64/gnu/src/tx_timer_interrupt.c b/ports/risc-v64/gnu/src/tx_timer_interrupt.c new file mode 100644 index 00000000..a92eb5e9 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_timer_interrupt.c @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_interrupt(VOID) +{ + /* Increment system clock. */ + _tx_timer_system_clock++; + + /* Test for time-slice expiration. */ + if (_tx_timer_time_slice) + { + /* Decrement the time_slice. */ + _tx_timer_time_slice--; + + /* Check for expiration. */ + if (_tx_timer_time_slice == 0) + { + + /* Set the time-slice expired flag. */ + _tx_timer_expired_time_slice = TX_TRUE; + } + } + + /* Test for timer expiration. */ + if (*_tx_timer_current_ptr) + { + + /* Set expiration flag. */ + _tx_timer_expired = TX_TRUE; + } + else + { + + /* No timer expired, increment the timer pointer. */ + _tx_timer_current_ptr++; + + /* Check for wrap-around. */ + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + + /* Wrap to beginning of list. */ + _tx_timer_current_ptr = _tx_timer_list_start; + } + } + + /* See if anything has expired. */ + if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { + + /* Did a timer expire? */ + if (_tx_timer_expired) + { + + /* Process timer expiration. */ + _tx_timer_expiration_process(); + } + + /* Did time slice expire? */ + if (_tx_timer_expired_time_slice) + { + + /* Time slice interrupted thread. */ + _tx_thread_time_slice(); + } + } +} diff --git a/ports/rxv1/ccrx/inc/tx_port.h b/ports/rxv1/ccrx/inc/tx_port.h index 46e14bf9..84c955e3 100644 --- a/ports/rxv1/ccrx/inc/tx_port.h +++ b/ports/rxv1/ccrx/inc/tx_port.h @@ -273,7 +273,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv1/CCRX Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv1/CCRX Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/ccrx/src/tx_thread_context_restore.src b/ports/rxv1/ccrx/src/tx_thread_context_restore.src index 2813bb1e..9b156a93 100644 --- a/ports/rxv1/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv1/ccrx/src/tx_thread_context_restore.src @@ -123,7 +123,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports/rxv1/gnu/inc/tx_port.h b/ports/rxv1/gnu/inc/tx_port.h index c103aa92..03ea10ca 100644 --- a/ports/rxv1/gnu/inc/tx_port.h +++ b/ports/rxv1/gnu/inc/tx_port.h @@ -269,7 +269,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv1/GNURX Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv1/GNURX Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/iar/inc/tx_port.h b/ports/rxv1/iar/inc/tx_port.h index fb917438..c2ab0e87 100644 --- a/ports/rxv1/iar/inc/tx_port.h +++ b/ports/rxv1/iar/inc/tx_port.h @@ -270,7 +270,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv1/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv1/IAR Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/iar/src/tx_thread_context_restore.s b/ports/rxv1/iar/src/tx_thread_context_restore.s index 7c5b071e..55359c19 100644 --- a/ports/rxv1/iar/src/tx_thread_context_restore.s +++ b/ports/rxv1/iar/src/tx_thread_context_restore.s @@ -111,7 +111,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h index 1038f156..431159ea 100644 --- a/ports/rxv2/ccrx/inc/tx_port.h +++ b/ports/rxv2/ccrx/inc/tx_port.h @@ -275,7 +275,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/CCRX Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/CCRX Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/ccrx/src/tx_thread_context_restore.src b/ports/rxv2/ccrx/src/tx_thread_context_restore.src index ad045bb2..a2a6e749 100644 --- a/ports/rxv2/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv2/ccrx/src/tx_thread_context_restore.src @@ -124,7 +124,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports/rxv2/gnu/inc/tx_port.h b/ports/rxv2/gnu/inc/tx_port.h index 676cd64f..6e672fac 100644 --- a/ports/rxv2/gnu/inc/tx_port.h +++ b/ports/rxv2/gnu/inc/tx_port.h @@ -271,7 +271,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/GNURX Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/GNURX Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/iar/inc/tx_port.h b/ports/rxv2/iar/inc/tx_port.h index 8d4d34af..df3c9472 100644 --- a/ports/rxv2/iar/inc/tx_port.h +++ b/ports/rxv2/iar/inc/tx_port.h @@ -271,7 +271,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/iar/src/tx_thread_context_restore.s b/ports/rxv2/iar/src/tx_thread_context_restore.s index 125fbae0..0e72a823 100644 --- a/ports/rxv2/iar/src/tx_thread_context_restore.s +++ b/ports/rxv2/iar/src/tx_thread_context_restore.s @@ -123,7 +123,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports/rxv3/ccrx/inc/tx_port.h b/ports/rxv3/ccrx/inc/tx_port.h index d34371e8..cef3082a 100644 --- a/ports/rxv3/ccrx/inc/tx_port.h +++ b/ports/rxv3/ccrx/inc/tx_port.h @@ -279,7 +279,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv3/CCRX Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv3/CCRX Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/ccrx/src/tx_thread_context_restore.src b/ports/rxv3/ccrx/src/tx_thread_context_restore.src index 0585bb1e..2e22d478 100644 --- a/ports/rxv3/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv3/ccrx/src/tx_thread_context_restore.src @@ -123,7 +123,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports/rxv3/gnu/inc/tx_port.h b/ports/rxv3/gnu/inc/tx_port.h index 66c11aef..b539d025 100644 --- a/ports/rxv3/gnu/inc/tx_port.h +++ b/ports/rxv3/gnu/inc/tx_port.h @@ -275,7 +275,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv3/GNURX Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv3/GNURX Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/iar/inc/tx_port.h b/ports/rxv3/iar/inc/tx_port.h index 70808968..cef1a286 100644 --- a/ports/rxv3/iar/inc/tx_port.h +++ b/ports/rxv3/iar/inc/tx_port.h @@ -276,7 +276,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv3/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv3/IAR Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/iar/src/tx_thread_context_restore.s b/ports/rxv3/iar/src/tx_thread_context_restore.s index 1409749e..84aa1be0 100644 --- a/ports/rxv3/iar/src/tx_thread_context_restore.s +++ b/ports/rxv3/iar/src/tx_thread_context_restore.s @@ -122,7 +122,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports/win32/vs_2019/inc/tx_port.h b/ports/win32/vs_2019/inc/tx_port.h index 672f9b63..d43742f1 100644 --- a/ports/win32/vs_2019/inc/tx_port.h +++ b/ports/win32/vs_2019/inc/tx_port.h @@ -419,7 +419,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Win32/Visual Studio Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Win32/Visual Studio Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif @@ -434,7 +434,7 @@ extern ULONG _tx_win32_global_int_disabled_fl extern LARGE_INTEGER _tx_win32_time_stamp; extern ULONG _tx_win32_system_error; extern HANDLE _tx_win32_timer_handle; -extern DWORD _tx_win32_timer_id; +extern UINT _tx_win32_timer_id; extern LARGE_INTEGER _tx_win32_time_stamp; @@ -443,7 +443,7 @@ extern LARGE_INTEGER _tx_win32_time_stamp; #endif #ifndef TX_TIMER_PERIODIC -#define TX_TIMER_PERIODIC 18 +#define TX_TIMER_PERIODIC 10 #endif #endif diff --git a/ports/win32/vs_2019/src/tx_initialize_low_level.c b/ports/win32/vs_2019/src/tx_initialize_low_level.c index 71cacd10..b4df4521 100644 --- a/ports/win32/vs_2019/src/tx_initialize_low_level.c +++ b/ports/win32/vs_2019/src/tx_initialize_low_level.c @@ -30,7 +30,7 @@ #include #include #include - +#pragma comment (lib, "Winmm.lib") /* Define various Win32 objects used by the ThreadX port. */ @@ -47,9 +47,8 @@ extern TX_THREAD *_tx_thread_current_ptr; how other interrupts may be defined as well. See code below for an example. */ -HANDLE _tx_win32_timer_handle; -DWORD _tx_win32_timer_id; -DWORD WINAPI _tx_win32_timer_interrupt(LPVOID p); +UINT _tx_win32_timer_id; +VOID CALLBACK _tx_win32_timer_interrupt(UINT wTimerID, UINT msg, DWORD dwUser, DWORD dw1, DWORD dw2); #ifdef TX_WIN32_DEBUG_ENABLE @@ -243,26 +242,6 @@ VOID _tx_initialize_low_level(VOID) /* Initialize the global interrupt disabled flag. */ _tx_win32_global_int_disabled_flag = TX_FALSE; - - /* Setup periodic timer interrupt. */ - _tx_win32_timer_handle = - CreateThread(NULL, 0, _tx_win32_timer_interrupt, (LPVOID) &_tx_win32_timer_handle,CREATE_SUSPENDED, &_tx_win32_timer_id); - - /* Check for a good thread create. */ - if (!_tx_win32_timer_handle) - { - - /* Error creating the timer interrupt. */ - printf("ThreadX Win32 error creating timer interrupt thread!\n"); - while(1) - { - } - } - - /* Otherwise, we have a good thread create. Now set the priority to - a level lower than the system thread but higher than the application - threads. */ - SetThreadPriority(_tx_win32_timer_handle, THREAD_PRIORITY_BELOW_NORMAL); /* Done, return to caller. */ } @@ -272,36 +251,39 @@ VOID _tx_initialize_low_level(VOID) all interrupt threads. Interrupt threads in addition to the timer may be added to this routine as well. */ -void _tx_initialize_start_interrupts(void) +void _tx_initialize_start_interrupts(void) { + TIMECAPS tc; + UINT wTimerRes; - /* Kick the timer thread off to generate the ThreadX periodic interrupt - source. */ - ResumeThread(_tx_win32_timer_handle); + /* Queries the timer device to determine its resolution. */ + if (timeGetDevCaps(&tc, sizeof(TIMECAPS)) != TIMERR_NOERROR) + { + /* Error; application can't continue. */ + printf("Query timer device error."); + while (1) + { + } + } + + wTimerRes = min(max(tc.wPeriodMin, TX_TIMER_PERIODIC), tc.wPeriodMax); + + /* Start a specified timer event. The timer runs in its own thread. + It calls the specified callback function when the event is activated. */ + _tx_win32_timer_id = timeSetEvent(TX_TIMER_PERIODIC, wTimerRes, _tx_win32_timer_interrupt, 0, TIME_PERIODIC); } - /* Define the ThreadX system timer interrupt. Other interrupts may be simulated in a similar way. */ - -DWORD WINAPI _tx_win32_timer_interrupt(LPVOID p) +VOID CALLBACK _tx_win32_timer_interrupt(UINT wTimerID, UINT msg, DWORD dwUser, DWORD dw1, DWORD dw2) { + /* Call ThreadX context save for interrupt preparation. */ + _tx_thread_context_save(); - while(1) - { + /* Call the ThreadX system timer interrupt processing. */ + _tx_timer_interrupt(); - /* Sleep for the desired time. */ - Sleep(TX_TIMER_PERIODIC); - - /* Call ThreadX context save for interrupt preparation. */ - _tx_thread_context_save(); - - - /* Call the ThreadX system timer interrupt processing. */ - _tx_timer_interrupt(); - - /* Call ThreadX context restore for interrupt completion. */ - _tx_thread_context_restore(); - } -} + /* Call ThreadX context restore for interrupt completion. */ + _tx_thread_context_restore(); +} \ No newline at end of file diff --git a/ports/xtensa/xcc/inc/tx_port.h b/ports/xtensa/xcc/inc/tx_port.h index 82ee5f97..835d9cf3 100644 --- a/ports/xtensa/xcc/inc/tx_port.h +++ b/ports/xtensa/xcc/inc/tx_port.h @@ -471,7 +471,7 @@ extern int xt_timer_intnum; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * Azure RTOS Xtensa Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * Azure RTOS Xtensa Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h index f772c52c..5b526fe6 100644 --- a/ports_module/cortex_a35/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35/ac6/inc/tx_port.h @@ -387,7 +387,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/ac6/inc/txm_module_port.h b/ports_module/cortex_a35/ac6/inc/txm_module_port.h index e74c9c3f..235d44b5 100644 --- a/ports_module/cortex_a35/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35/ac6/inc/txm_module_port.h @@ -279,6 +279,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S index 9e552c94..5578d8eb 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S @@ -126,7 +126,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) // || (_tx_thread_preempt_disable)) // { diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h index 0a25293e..cd799721 100644 --- a/ports_module/cortex_a35/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35/gnu/inc/tx_port.h @@ -387,7 +387,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/gnu/inc/txm_module_port.h b/ports_module/cortex_a35/gnu/inc/txm_module_port.h index c594439c..bd87ad1d 100644 --- a/ports_module/cortex_a35/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35/gnu/inc/txm_module_port.h @@ -279,6 +279,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S index 6707597d..ff59efa7 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S @@ -127,7 +127,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + // else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) // || (_tx_thread_preempt_disable)) // { diff --git a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h index f8714841..7d374f65 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h @@ -444,7 +444,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h index 234510b8..df67dd7a 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h @@ -274,6 +274,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/AC6 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h index 33c403d2..94674cca 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h @@ -444,7 +444,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h index ee279ca1..92642b31 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h @@ -274,6 +274,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A35/GNU Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_a7/ac5/inc/tx_port.h b/ports_module/cortex_a7/ac5/inc/tx_port.h index 38cb7a87..2a7709a8 100644 --- a/ports_module/cortex_a7/ac5/inc/tx_port.h +++ b/ports_module/cortex_a7/ac5/inc/tx_port.h @@ -345,7 +345,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/ac5/inc/txm_module_port.h b/ports_module/cortex_a7/ac5/inc/txm_module_port.h index bc1aac48..4a9030db 100644 --- a/ports_module/cortex_a7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_a7/ac5/inc/txm_module_port.h @@ -407,7 +407,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s index 65e74ba0..4996da07 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s @@ -142,7 +142,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s index 9fba762b..320ba56d 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s @@ -132,7 +132,7 @@ _tx_thread_fiq_context_restore __tx_thread_fiq_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..0e094b38 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx.bat @@ -0,0 +1,290 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_alignment_adjust.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_external_memory_enable.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_mm_initialize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_mm_register_setup.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/txm_module_manager_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT ../module_manager/src/txm_module_manager_user_mode_entry.S + +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o + +arm-none-eabi-ar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o +arm-none-eabi-ar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o txm_module_manager_mm_initialize.o +arm-none-eabi-ar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o +arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o +arm-none-eabi-ar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o +arm-none-eabi-ar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o +arm-none-eabi-ar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o +arm-none-eabi-ar -r tx.a txm_module_manager_user_mode_entry.o +arm-none-eabi-ar -r tx.a txm_module_manager_internal_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_allocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_deallocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pointer_get_extended.o +arm-none-eabi-ar -r tx.a txm_module_manager_properties_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_util.o diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx_demo.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx_demo.bat new file mode 100644 index 00000000..032a2195 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc sample_threadx.c +armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x80000000 --first tx_initialize_low_level.o(VECTORS) --remove --map --symbols --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..39df5df9 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_library.bat @@ -0,0 +1,118 @@ +del txm.a + +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_release.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_release.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_lib/src/txm_module_thread_shell_entry.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_send.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_time_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_time_set.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_change.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_create.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c + +armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o +armar -r txm.a txm_block_pool_prioritize.o txm_block_release.o +armar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o +armar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o +armar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o +armar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o +armar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o +armar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o +armar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o +armar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o +armar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o +armar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o +armar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o +armar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o +armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o +armar -r txm.a txm_time_get.o txm_time_set.o +armar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o +armar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_manager_sample.bat new file mode 100644 index 00000000..f92b4ff5 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_manager_sample.bat @@ -0,0 +1,8 @@ +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module_manager.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT module_code.c +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT reset.S +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT crt0.S +rem arm-none-eabi-gcc -g --elf --ro 0x80000000 --first tx_initialize_low_level.o(VECTORS) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o module_code.o tx.a +rem arm-none-eabi-ld -A cortex-a7 -ereset_handler -T sample_threadx.ld tx_initialize_low_level.o module_code.o sample_threadx_module_manager.o tx.a libc.a -o sample_threadx_module_manager.axf -M > sample_threadx_module_manager.map +arm-none-eabi-gcc -g -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -T sample_threadx.ld --specs=nosys.specs -o sample_threadx_module_manager.out -Wl,-Map=sample_threadx_module_manager.map module_code.o tx_initialize_low_level.o sample_threadx_module_manager.o tx.a \ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat new file mode 100644 index 00000000..8e6f8286 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base txm_module_preamble.S +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module.c +rem arm-none-eabi-gcc -g --elf --ro 0 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a +rem arm-none-eabi-gcc -g -mcpu=cortex-a7 -T sample_threadx_module.ld -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork --specs=nosys.specs -e _txm_module_thread_shell_entry -o sample_threadx_module.out -Wl,-Map=sample_threadx_module.map gcc_setup.o txm_module_preamble.o sample_threadx_module.o txm.a +arm-none-eabi-ld -A cortex-a7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map \ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/crt0.S b/ports_module/cortex_a7/gnu/example_build/crt0.S new file mode 100644 index 00000000..56b6c958 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S new file mode 100644 index 00000000..d7c61892 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S @@ -0,0 +1,127 @@ + + .text + .align 4 + .syntax unified + + .global _gcc_setup + .thumb_func +_gcc_setup: + + STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + + ldr r3, =__FLASH_segment_start__ + ldr r4, =__RAM_segment_start__ + mov r5,r0 + + /* Copy GOT table. */ + + ldr r0, =__got_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__new_got_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__new_got_end__ + sub r2,r2,r4 + add r2,r2,r9 + +new_got_setup: + cmp r1, r2 // See if there are more GOT entries + beq got_setup_done // No, done with GOT setup + ldr r6, [r0] // Pickup current GOT entry + cmp r6, #0 // Is it 0? + beq address_built // Yes, just skip the adjustment + cmp r6, r4 // Is it in the code or data area? + blt flash_area // If less than, it is a code address + sub r6, r6, r4 // Compute offset of data area + add r6, r6, r9 // Build address based on the loaded data address + b address_built // Finished building address +flash_area: + sub r6, r6, r3 // Compute offset of code area + add r6, r6, r5 // Build address based on the loaded code address +address_built: + str r6, [r1] // Store in new GOT table + add r0, r0, #4 // Move to next entry + add r1, r1, #4 // + b new_got_setup // Continue at the top of the loop +got_setup_done: + + + /* Copy initialised sections into RAM if required. */ + + ldr r0, =__data_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__data_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__data_end__ + sub r2,r2,r4 + add r2,r2,r9 + bl crt0_memory_copy + + /* Zero bss. */ + + ldr r0, =__bss_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__bss_end__ + sub r1,r1,r4 + add r1,r1,r9 + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + + ldr r0, =__heap_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__heap_end__ + sub r1,r1,r4 + add r1,r1,r9 + sub r1,r1,r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + bx lr // Return to caller + + .align 4 + + /* Startup helper functions. */ + + .thumb_func +crt0_memory_copy: + + cmp r0, r1 + beq memory_copy_done + cmp r2, r1 + beq memory_copy_done + sub r2, r2, r1 +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + cmp r2, #0 + bne memory_copy_loop +memory_copy_done: + bx lr + + .thumb_func +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + /* Setup attibutes of heap section so it doesn't take up room in the elf file */ + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/reset.S b/ports_module/cortex_a7/gnu/example_build/reset.S new file mode 100644 index 00000000..597e9d9a --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/reset.S @@ -0,0 +1,64 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + + .global _start + .global __tx_undefined + .global __tx_swi_interrupt + .global __tx_prefetch_handler + .global __tx_abort_handler + .global __tx_reserved_handler + .global __tx_irq_handler + .global __tx_fiq_handler + +/* Define the vector area. This should be located or copied to 0. */ + + .text + .global __vectors +__vectors: + + LDR pc, STARTUP // Reset goes to startup function + LDR pc, UNDEFINED // Undefined handler + LDR pc, SWI // Software interrupt handler + LDR pc, PREFETCH // Prefetch exception handler + LDR pc, ABORT // Abort exception handler + LDR pc, RESERVED // Reserved exception handler + LDR pc, IRQ // IRQ interrupt handler + LDR pc, FIQ // FIQ interrupt handler + +STARTUP: + .word _start // Reset goes to C startup function +UNDEFINED: + .word __tx_undefined // Undefined handler +SWI: + .word __tx_swi_interrupt // Software interrupt handler +PREFETCH: + .word __tx_prefetch_handler // Prefetch exception handler +ABORT: + .word __tx_abort_handler // Abort exception handler +RESERVED: + .word __tx_reserved_handler // Reserved exception handler +IRQ: + .word __tx_irq_handler // IRQ interrupt handler +FIQ: + .word __tx_fiq_handler // FIQ interrupt handler diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld b/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..3dea4e1c --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld @@ -0,0 +1,239 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", + "elf32-littlearm") +OUTPUT_ARCH(arm) +/* ENTRY(_start) */ +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + . = 0x00000000; + + .vectors : {reset.o(.text) } + + /* Read-only sections, merged into text segment: */ + . = 0x00001000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.sdata : + { + *(.rel.sdata) + *(.rel.sdata.*) + *(.rel.gnu.linkonce.s*) + } + .rela.sdata : + { + *(.rela.sdata) + *(.rela.sdata.*) + *(.rela.gnu.linkonce.s*) + } + .rel.sbss : { *(.rel.sbss) } + .rela.sbss : { *(.rela.sbss) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.text.*) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + *(.glue_7t) *(.glue_7) + } =0 + .init : + { + KEEP (*(.init)) + } =0 + _etext = .; + PROVIDE (etext = .); + .fini : + { + KEEP (*(.fini)) + } =0 + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) } + .rodata1 : { *(.rodata1) } + .eh_frame_hdr : { *(.eh_frame_hdr) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(256) + (. & (256 - 1)); + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + .eh_frame : { KEEP (*(.eh_frame)) } + .gcc_except_table : { *(.gcc_except_table) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .jcr : { KEEP (*(.jcr)) } + .got : { *(.got.plt) *(.got) } + .dynamic : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + __bss_start__ = .; + .sbss : + { + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.scommon) + } + .bss : + { + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + } + . = ALIGN(32 / 8); + + _bss_end__ = . ; __bss_end__ = . ; + PROVIDE (end = .); + + .stack : + { + + _stack_bottom = ABSOLUTE(.) ; + + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + SYS stack if nested interrupts are enabled. */ + . = ALIGN(8) ; + . += 4096 ; + _sp = . - 16 ; + _stack_top = ABSOLUTE(.) ; + } + + _end = .; __end__ = . ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* These must appear regardless of . */ +} diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c new file mode 100644 index 00000000..fce2a3fa --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c @@ -0,0 +1,427 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void *) &semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void *) &mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* Test external/shared memory. */ + *(ULONG *) 0x90000000 = 0xdeadbeef; + *(ULONG *) 0x90000FFC = 0xfeed0add; + *(ULONG *) 0x90001000 = 0xfedcba01; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld new file mode 100644 index 00000000..30c66655 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld @@ -0,0 +1,210 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00030000, LENGTH = 0x00010000 + RAM (wx) : ORIGIN = 0, LENGTH = 0x00100000 +} + + +SECTIONS +{ + __FLASH_segment_start__ = 0x00030000; + __FLASH_segment_end__ = 0x00040000; + __RAM_segment_start__ = 0x10000000; + __RAM_segment_end__ = 0x10008000; + + __HEAPSIZE__ = 128; + + __preamble_load_start__ = __FLASH_segment_start__; + .preamble __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __preamble_start__ = .; + *(.preamble .preamble.*) + } + __preamble_end__ = __preamble_start__ + SIZEOF(.preamble); + + __dynsym_load_start__ = ALIGN(__preamble_end__ , 4); + .dynsym ALIGN(__dynsym_load_start__ , 4) : AT(ALIGN(__dynsym_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.dynsym)) + KEEP (*(.dynsym*)) + . = ALIGN(4); + } + __dynsym_end__ = __dynsym_load_start__ + SIZEOF(.dynsym); + + __dynstr_load_start__ = ALIGN(__dynsym_end__ , 4); + .dynstr ALIGN(__dynstr_load_start__ , 4) : AT(ALIGN(__dynstr_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.dynstr)) + KEEP (*(.dynstr*)) + . = ALIGN(4); + } + __dynstr_end__ = __dynstr_load_start__ + SIZEOF(.dynstr); + + __reldyn_load_start__ = ALIGN(__dynstr_end__ , 4); + .rel.dyn ALIGN(__reldyn_load_start__ , 4) : AT(ALIGN(__reldyn_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.dyn)) + KEEP (*(.rel.dyn*)) + . = ALIGN(4); + } + __reldyn_end__ = __reldyn_load_start__ + SIZEOF(.rel.dyn); + + __relplt_load_start__ = ALIGN(__reldyn_end__ , 4); + .rel.plt ALIGN(__relplt_load_start__ , 4) : AT(ALIGN(__relplt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.plt)) + KEEP (*(.rel.plt*)) + . = ALIGN(4); + } + __relplt_end__ = __relplt_load_start__ + SIZEOF(.rel.plt); + + __plt_load_start__ = ALIGN(__relplt_end__ , 4); + .plt ALIGN(__plt_load_start__ , 4) : AT(ALIGN(__plt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.plt)) + KEEP (*(.plt*)) + . = ALIGN(4); + } + __plt_end__ = __plt_load_start__ + SIZEOF(.plt); + + __interp_load_start__ = ALIGN(__plt_end__ , 4); + .interp ALIGN(__interp_load_start__ , 4) : AT(ALIGN(__interp_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.interp)) + KEEP (*(.interp*)) + . = ALIGN(4); + } + __interp_end__ = __interp_load_start__ + SIZEOF(.interp); + + __hash_load_start__ = ALIGN(__interp_end__ , 4); + .hash ALIGN(__hash_load_start__ , 4) : AT(ALIGN(__hash_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.hash)) + KEEP (*(.hash*)) + . = ALIGN(4); + } + __hash_end__ = __hash_load_start__ + SIZEOF(.hash); + + __text_load_start__ = ALIGN(__hash_end__ , 4); + .text ALIGN(__text_load_start__ , 4) : AT(ALIGN(__text_load_start__, 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table ) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + __got_load_start__ = ALIGN(__ctors_end__ , 4); + .got ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + . = ALIGN(4); + _sgot = .; + KEEP (*(.got)) + KEEP (*(.got*)) + . = ALIGN(4); + _egot = .; + } + __got_end__ = __got_load_start__ + SIZEOF(.got); + + __rodata_load_start__ = ALIGN(__got_end__ , 4); + .rodata ALIGN(__got_end__ , 4) : AT(ALIGN(__got_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + __new_got_start__ = ALIGN(__RAM_segment_start__ , 4); + + __new_got_end__ = __new_got_start__ + SIZEOF(.got); + + .fast ALIGN(__new_got_end__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + .fast_run ALIGN(__fast_end__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + __data_size__ = __heap_end__ - __RAM_segment_start__; + +} + diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..8b17e34a --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c @@ -0,0 +1,132 @@ +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program + manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for + use. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + +/* Define the module object pool area. */ +UCHAR object_memory[16384]; + +/* Define the module data pool area. */ +#define MODULE_DATA_SIZE 65536 +unsigned char module_data_area[MODULE_DATA_SIZE]; + +/* Define a module instance. */ +TXM_MODULE_INSTANCE my_module1; +TXM_MODULE_INSTANCE my_module2; + +/* Module code is in an array created by module_to_c_array utility. */ +extern unsigned char module_code[]; + +/* Define the count of memory faults. */ +ULONG memory_faults; + +/* Define fault handler. */ +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + + /* Create the module manager thread. */ + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + first_unused_memory, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); + + /* Create a pool for module objects. */ + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Initialize MMU. */ + txm_module_manager_mm_initialize(); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); + + /* Load a second instance of the module. */ + //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); + + /* Enable shared memory regions for one module. */ + //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the modules. */ + txm_module_manager_start(&my_module1); + //txm_module_manager_start(&my_module2); + + /* Sleep for a while and let the modules run.... */ + tx_thread_sleep(50); + + /* Thread 0 in module1 should be terminated due to violating the MMU. */ + + /* Stop the modules. */ + txm_module_manager_stop(&my_module1); + txm_module_manager_stop(&my_module2); + + /* Unload the modules. */ + txm_module_manager_unload(&my_module1); + txm_module_manager_unload(&my_module2); + + /* Reload the modules. */ + txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); + + /* Give both modules shared memory. */ + txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the module again. */ + txm_module_manager_start(&my_module2); + txm_module_manager_start(&my_module1); + + /* Now just spin... */ + while(1) + { + tx_thread_sleep(100); + /* Thread 0 and 5 in module1 should not exist because they violate the maximum priority. */ + } +} + + + + diff --git a/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..2c923371 --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s @@ -0,0 +1,428 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + +SVC_MODE = 0xD3 // Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 // Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 // Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF // Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 // FIQ stack size +IRQ_STACK_SIZE = 1024 // IRQ stack size +SYS_STACK_SIZE = 1024 // System stack size +THUMB_MASK = 0x20 // THUMB mode bit + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + .global _end + .global _sp + .global _stack_bottom + + +/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_initialize_low_level // Call _tx_initialize_low_level function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: + + /* We must be in SVC mode at this point! */ + + /* Setup various stack pointers. */ + + LDR r1, =_sp // Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING + + /* Setup the system mode stack for nested interrupt support */ + + LDR r2, =SYS_STACK_SIZE // Pickup stack size + MOV r3, #SYS_MODE // Build SYS mode CPSR + MSR CPSR_c, r3 // Enter SYS mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup SYS stack pointer + SUB r1, r1, r2 // Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE // Pickup stack size + MOV r0, #FIQ_MODE // Build FIQ mode CPSR + MSR CPSR, r0 // Enter FIQ mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup FIQ stack pointer + SUB r1, r1, r2 // Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE // Pickup IRQ stack size + MOV r0, #IRQ_MODE // Build IRQ mode CPSR + MSR CPSR, r0 // Enter IRQ mode + SUB r1, r1, #1 // Backup 1 byte + BIC r1, r1, #7 // Ensure 8-byte alignment + MOV sp, r1 // Setup IRQ stack pointer + SUB r3, r1, r2 // Calculate end of IRQ stack + MOV r0, #SVC_MODE // Build SVC mode CPSR + MSR CPSR, r0 // Enter SVC mode + LDR r2, =_stack_bottom // Pickup stack bottom + CMP r3, r2 // Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop // If the IRQ stack exceeds the stack bottom, just sit here! + + LDR r2, =_tx_thread_system_stack_ptr // Pickup stack pointer + STR r1, [r2] // Save the system stack + + LDR r1, =_end // Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + ADD r1, r1, #8 // Increment to next free word + STR r1, [r2] // Save first free memory address + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif + +/* Define shells for each of the interrupt vectors. */ + + .global __tx_undefined +__tx_undefined: + B __tx_undefined // Undefined handler + + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler // Reserved exception handler + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +// + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + + BL _tx_timer_interrupt // Timer interrupt handler + + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + /* This is an example of a vectored IRQ handler. */ + + + + /* Save initial context and call context save to prepare for + vectored ISR execution. */ + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ + + + +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +asdf + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler // FIQ interrupt handler +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles MMU exceptions and fills the */ +/* _txm_module_manager_memory_fault_info struct. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_memory_fault_handler */ +/* _tx_execution_thread_exit */ +/* _tx_thread_schedule */ +/* */ +/* CALLED BY */ +/* */ +/* MMU exceptions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ + +// ******************************************************************* +// MMU Exception Handling +// ******************************************************************* + // EXTERN _tx_thread_system_state + // EXTERN _txm_module_manager_memory_fault_info + // EXTERN _tx_thread_current_ptr + // EXTERN _txm_module_manager_memory_fault_handler + // EXTERN _tx_execution_thread_exit + // EXTERN _tx_thread_schedule + + .global __tx_prefetch_handler + .global __tx_abort_handler +__tx_prefetch_handler: +__tx_abort_handler: + STMDB sp!, {r0-r3} // Save some working registers + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3, #0] // Pickup system state + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + SUB lr, lr, #4 // Adjust point of exception + + /* Now pickup and store all the fault related information. */ + + // Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r3, #0] // Save current thread pointer + STR lr, [r3, #4] // Save point of fault + MRC p15, 0, r0, c6, c0, 0 // Read DFAR + STR r0, [r3, #8] // Save DFAR + MRC p15, 0, r0, c5, c0, 0 // Read DFSR + STR r0, [r3, #12] // Save DFSR + MRC p15, 0, r0, c6, c0, 2 // Read IFAR + STR r0, [r3, #16] // Save IFAR + MRC p15, 0, r0, c5, c0, 1 // Read IFSR + STR r0, [r3, #20] // Save IFSR + + // Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] // Save r0 + STR r1, [r3, #32] // Save r1 + STR r2, [r3, #36] // Save r2 + POP {r0} + STR r0, [r3, #40] // Save r3 + STR r4, [r3, #44] // Save r4 + STR r5, [r3, #48] // Save r5 + STR r6, [r3, #52] // Save r6 + STR r7, [r3, #56] // Save r7 + STR r8, [r3, #60] // Save r8 + STR r9, [r3, #64] // Save r9 + STR r10,[r3, #68] // Save r10 + STR r11,[r3, #72] // Save r11 + STR r12,[r3, #76] // Save r12 + + CPSID if, #0x1F // Enter SYS mode + MOV r0, lr // Pickup lr + MOV r1, sp // Pickup sp + CPSID if, #0x17 // Back to ABT mode + STR r0, [r3, #80] // Save lr + STR r1, [r3, #24] // Save sp + MRS r0, SPSR // Pickup SPSR + STR r0, [r3, #84] // Save SPSR + ORR r0, r0, #SYS_MODE // Return into SYS mode + BIC r0, r0, #THUMB_MASK // Clear THUMB mode + MSR SPSR_c, r0 // Save SPSR + + // Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit // Call the thread exit function +#endif + + LDR r0, =_tx_thread_system_state // Pickup address of system state + LDR r1, [r0] // Pickup system state + SUB r1, r1, #1 // Decrement + STR r1, [r0] // Store new system state + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from exception + LDR lr, =_tx_thread_schedule // Load scheduler address + MOVS pc, lr // Return to scheduler +// ******************************************************************* +// End of MMU exception handling. +// ******************************************************************* + + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .word _tx_build_options // Reference to bring in +VERSION_ID: + .word _tx_version_id // Reference to bring in diff --git a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s new file mode 100644 index 00000000..663c448f --- /dev/null +++ b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s @@ -0,0 +1,50 @@ + .section .txm_module_preamble + .align 4 + +/* Define common external references. */ + + .global _txm_module_thread_shell_entry + .global demo_module_start + .global _txm_module_callback_request_thread_entry + + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x01000001 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> RVDS + // 2 -> GNU + // Bits 23-1: Reserved + // Bit 0: 0 -> Privileged mode execution (no MMU protection) + // 1 -> User mode execution (MMU protection) + .dc.l _txm_module_thread_shell_entry // Module Shell Entry Point + .dc.l demo_module_start // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 2046 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 2046 // Module Callback Thread Stack Size + .dc.l __code_size__ // Module Code Size + .dc.l __data_size__ // Module Data Size - default to 16K (need to make sure this is large enough for module's data needs!) + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex_a7/gnu/inc/tx_port.h b/ports_module/cortex_a7/gnu/inc/tx_port.h new file mode 100644 index 00000000..df474130 --- /dev/null +++ b/ports_module/cortex_a7/gnu/inc/tx_port.h @@ -0,0 +1,349 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARMv7-A */ +/* 6.1.12 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the ARMv7-A. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-A Version 6.2.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports_module/cortex_a7/gnu/inc/txm_module_port.h b/ports_module/cortex_a7/gnu/inc/txm_module_port.h new file mode 100644 index 00000000..a3330e34 --- /dev/null +++ b/ports_module/cortex_a7/gnu/inc/txm_module_port.h @@ -0,0 +1,413 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* Defined, this option enables the MMU hardware and requires memory protected + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load + functions will return a TXM_MODULE_INVALID_PROPERTIES error). + Default setting for this value is defined. */ +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_MEMORY_PROTECTION 0x00000001 +#else +#define TXM_MODULE_MEMORY_PROTECTION 0x00000000 +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ +#define INLINE_DECLARE + +#define TXM_MAXIMUM_MODULES 16 +#define TXM_MODULE_LEVEL1_PAGE_TABLE_SIZE 32 +#define TXM_ASID_TABLE_LENGTH 256 + +#define TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 0) +#define TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 1) +#define TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 2) +#define TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 3) + +#define TXM_MASTER_PAGE_TABLE_INDEX 0 + +/* 1 entry per 1MB, so this covers 4G address space */ +#define TXM_MASTER_PAGE_TABLE_ENTRIES 4096 + +/* Smallest MMU page size is 4kB. */ +#define TXM_MODULE_MEMORY_ALIGNMENT 4096 +#define TXM_MMU_LEVEL1_PAGE_SHIFT 20 +#define TXM_MMU_LEVEL2_PAGE_SHIFT 12 +#define TXM_LEVEL_2_PAGE_TABLE_ENTRIES 256 + +/* Level 1 section base address mask. */ +#define TXM_MMU_LEVEL1_MASK 0xFFF00000 + +/* Level 2 section base address mask. */ +#define TXM_MMU_LEVEL2_MASK 0xFFFFF000 + +/* Non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL1_CODE_ATTRIBUTES 0x000219EE +/* Non-global, outer & inner write-back, write-allocate, user read, write, no-execute. */ +#define TXM_MMU_LEVEL1_DATA_ATTRIBUTES 0x00021DFE + +/* Level 1 "level 2 descriptor base address" mask. */ +#define TXM_MMU_LEVEL1_SECOND_MASK 0xFFFFFC00 + +/* Level 1 "level 2 descriptor" attributes. */ +#define TXM_MMU_LEVEL1_SECOND_ATTRIBUTES 0x0000001E1 + +/* Kernel level 2 attributes: global, outer & inner write-back, write-allocate, user read/write */ +#define TXM_MMU_KERNEL_LEVEL2_CODE_ATTRIBUTES 0x0000006E +#define TXM_MMU_KERNEL_LEVEL2_DATA_ATTRIBUTES 0x0000005E + +/* Module level 2 attributes: non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL2_CODE_ATTRIBUTES 0x0000086E +#define TXM_MMU_LEVEL2_DATA_ATTRIBUTES 0x0000087F + + +/* Settings the user can use to set up shared memory attributes. */ +#define TXM_MMU_ATTRIBUTE_XN 0x00000001 +#define TXM_MMU_ATTRIBUTE_B 0x00000002 +#define TXM_MMU_ATTRIBUTE_C 0x00000004 +#define TXM_MMU_ATTRIBUTE_AP 0x00000018 +#define TXM_MMU_ATTRIBUTE_TEX 0x000000E0 + +/* Masks for each attribute. */ +#define TXM_MMU_ATTRIBUTE_XN_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_B_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_C_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_AP_MASK 0x00000003 +#define TXM_MMU_ATTRIBUTE_TEX_MASK 0x00000007 + +/* Shift amounts for bitfields above to correct register locations. */ +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE 0x000201E2 + +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE 0x00000802 + +/* Shift amounts from bit 0 position. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT 10 +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT 12 + +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT 4 +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT 6 + +/* Masks for L1 page attributes. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) + +/* Masks for L2 page attributes. */ +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) + +#define TXM_ADDRESS_TRANSLATION_FAULT_BIT 1 + +#define TXM_ASID_RESERVED 0xFFFFFFFF + +#define TXM_MODULE_ASID_ERROR 0xF6 +#define TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR 0xF7 + +/* Number of L2 pages each module can have. */ +#define TXM_MODULE_LEVEL2_EXTERNAL_PAGES 16 +/* Size, in pages, of the L2 page pool. */ +#define TXM_LEVEL2_EXTERNAL_POOL_PAGES (TXM_MODULE_LEVEL2_EXTERNAL_PAGES * TXM_MAXIMUM_MODULES) + + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_asid; \ + ULONG *txm_external_page_table[TXM_MODULE_LEVEL2_EXTERNAL_PAGES]; + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_dfar; + ULONG txm_module_manager_memory_fault_info_dfsr; + ULONG txm_module_manager_memory_fault_info_ifar; + ULONG txm_module_manager_memory_fault_info_ifsr; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_cpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (TXM_MODULE_MEMORY_ALIGNMENT - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. */ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MMU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) \ + _txm_level2_page_clear(module_instance); \ + _txm_module_manager_remove_asid(module_instance); + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data or shared memory. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check((ULONG) obj_ptr) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#define txm_module_manager_mm_initialize _txm_module_manager_mm_initialize +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +UINT _txm_module_manager_mm_initialize(VOID); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(ULONG pointer); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/GNU Version 6.2.1 *"; + +#endif + diff --git a/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..e8b74476 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,181 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" + + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +TX_INTERRUPT_SAVE_AREA + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_STARTED_EXTENSION(thread_ptr) + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the C library */ + extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); + _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..fae7e72d --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,222 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 // Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 // Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 // Disable IRQ, SVC mode +IRQ_MODE = 0x92 // Disable IRQ, IRQ mode +#endif + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + SUB r2, r2, #1 // Decrement the counter + STR r2, [r3] // Store the counter + CMP r2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup actual current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR r2, [r3] // Pickup actual preempt disable flag + CMP r2, #0 // Is it set? + BNE __tx_thread_no_preempt_restore // Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR r2, [r3] // Pickup actual execute thread pointer + CMP r0, r2 // Is the same thread highest priority? + BNE __tx_thread_preempt_restore // No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Recover the saved context and return to the point of interrupt. */ + + /* Pickup the saved stack pointer. */ + + /* Recover the saved context and return to the point of interrupt. */ + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + MOV r1, lr // Save lr (point of interrupt) + MOV r2, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r2 // Enter SVC mode + STR r1, [sp, #-4]! // Save point of interrupt + STMDB sp!, {r4-r12, lr} // Save upper half of registers + MOV r4, r3 // Save SPSR in r4 + MOV r2, #IRQ_MODE // Build IRQ mode CPSR + MSR CPSR_c, r2 // Enter IRQ mode + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOV r5, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r5 // Enter SVC mode + STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save // No, skip VFP IRQ save + VMRS r2, FPSCR // Pickup the FPSCR + STR r2, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D16-D31} // Save D16-D31 + VSTMDB sp!, {D0-D15} // Save D0-D15 + +_tx_skip_irq_vfp_save: + +#endif + + MOV r3, #1 // Build interrupt stack type + STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + STR sp, [r0, #8] // Save stack pointer in thread control + // block + + /* Save the remaining time-slice and disable it. */ + LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + STR r2, [r0, #24] // Save thread's time-slice + MOV r2, #0 // Clear value + STR r2, [r3] // Disable global time-slice flag + +__tx_thread_dont_save_ts: + + /* Clear the current task pointer. */ + MOV r0, #0 // NULL value + STR r0, [r1] // Clear current thread pointer + + /* Return to the scheduler. */ + B _tx_thread_schedule // Return to scheduler + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + MOV r0, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r0 // Enter SVC mode + B _tx_thread_schedule // Return to scheduler diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..7ac48c2e --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + + STMDB sp!, {r0-r3} // Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other registers + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_irq_processing_return // Continue IRQ processing + +__tx_thread_not_nested_save: + + /* Otherwise, not nested, check to see if a thread was running. */ + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} // Store other registers + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_irq_processing_return // Continue IRQ processing + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + ADD sp, sp, #16 // Recover saved registers + B __tx_irq_processing_return // Continue IRQ processing diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..006be973 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,223 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +SVC_MODE = 0xD3 // SVC mode +FIQ_MODE = 0xD1 // FIQ mode +MODE_MASK = 0x1F // Mode mask +THUMB_MASK = 0x20 // Thumb bit mask +IRQ_MODE_BITS = 0x12 // IRQ mode bits + + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + + CPSID if // Disable IRQ and FIQ interrupts + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + SUB r2, r2, #1 // Decrement the counter + STR r2, [r3] // Store the counter + CMP r2, #0 // Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + + LDR r1, [sp] // Pickup the saved SPSR + MOV r2, #MODE_MASK // Build mask to isolate the interrupted mode + AND r1, r1, r2 // Isolate mode bits + CMP r1, #IRQ_MODE_BITS // Was an interrupt taken in IRQ mode before we + // got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore // Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup actual current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore // Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR r2, [r3] // Pickup actual preempt disable flag + CMP r2, #0 // Is it set? + BNE __tx_thread_fiq_no_preempt_restore // Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR r2, [r3] // Pickup actual execute thread pointer + CMP r0, r2 // Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore // No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOVS pc, lr // Return to point of interrupt + +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} // Recover temporarily saved registers + MOV r1, lr // Save lr (point of interrupt) + MOV r2, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r2 // Enter SVC mode + STR r1, [sp, #-4]! // Save point of interrupt + STMDB sp!, {r4-r12, lr} // Save upper half of registers + MOV r4, r3 // Save SPSR in r4 + MOV r2, #FIQ_MODE // Build FIQ mode CPSR + MSR CPSR_c, r2 // Reenter FIQ mode + LDMIA sp!, {r0-r3} // Recover r0-r3 + MOV r5, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r5 // Enter SVC mode + STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save // No, skip VFP IRQ save + VMRS r2, FPSCR // Pickup the FPSCR + STR r2, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D16-D31} // Save D16-D31 + VSTMDB sp!, {D0-D15} // Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 // Build interrupt stack type + STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + STR sp, [r0, #8] // Save stack pointer in thread control + // block */ + LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it active? + BEQ __tx_thread_fiq_dont_save_ts // No, don't save it + + STR r2, [r0, #24] // Save thread's time-slice + MOV r2, #0 // Clear value + STR r2, [r3] // Disable global time-slice flag + +__tx_thread_fiq_dont_save_ts: + + /* Clear the current task pointer. */ + + MOV r0, #0 // NULL value + STR r0, [r1] // Clear current thread pointer + + /* Return to the scheduler. */ + + B _tx_thread_schedule // Return to scheduler + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, #24 // Recover FIQ stack space + MOV r3, #SVC_MODE // Build SVC mode CPSR + MSR CPSR_c, r3 // Lockout interrupts + B _tx_thread_schedule // Return to scheduler + diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..7db6a4c2 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s @@ -0,0 +1,178 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + + STMDB sp!, {r0-r3} // Save some working registers + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other registers + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_fiq_processing_return // Continue FIQ processing +// +__tx_thread_fiq_not_nested_save: + + /* Otherwise, not nested, check to see if a thread was running. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_fiq_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r2, lr} // Store other registers, Note that we don't + // need to save sl and ip since FIQ has + // copies of these registers. Nested + // interrupt processing does need to save + // these registers. + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_fiq_processing_return // Continue FIQ processing + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, lr} // Store other registers that will get used + // or stripped off the stack in context + // restore + B __tx_fiq_processing_return // Continue FIQ processing diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..b34d881e --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 // Disable IRQ interrupts +#endif +MODE_MASK = 0x1F // Mode mask +FIQ_MODE_BITS = 0x11 // FIQ mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + ORR r0, r0, #DISABLE_INTS // Build disable interrupt value + MSR CPSR_c, r0 // Disable interrupts + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for + // 8-byte alignment logic) + BIC r0, r0, #MODE_MASK // Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR + MSR CPSR_c, r0 // Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..c9cd5a06 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +FIQ_DISABLE = 0x40 // FIQ disable bit +MODE_MASK = 0x1F // Mode mask +SYS_MODE_BITS = 0x1F // System mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + BIC r0, r0, #MODE_MASK // Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS // Build system mode CPSR + MSR CPSR_c, r0 // Enter system mode + STMDB sp!, {r1, lr} // Push the system mode lr on the system mode stack + // and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR + MSR CPSR_c, r0 // Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..63b1609a --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +INT_MASK = 0x03F + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR // Pickup current CPSR + MOV r2, #INT_MASK // Build interrupt mask + AND r1, r3, r2 // Clear interrupt lockout bits + ORR r1, r1, r0 // Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 // Setup new CPSR + BIC r0, r3, r2 // Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..13258808 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR // Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ +#else + CPSID i // Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..2d582511 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 // Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..ec7e63c6 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 // Disable IRQ interrupts +#endif +MODE_MASK = 0x1F // Mode mask +IRQ_MODE_BITS = 0x12 // IRQ mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + ORR r0, r0, #DISABLE_INTS // Build disable interrupt value + MSR CPSR_c, r0 // Disable interrupts + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for + // 8-byte alignment logic) + BIC r0, r0, #MODE_MASK // Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR + MSR CPSR_c, r0 // Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..c69976ed --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +IRQ_DISABLE = 0x80 // IRQ disable bit +MODE_MASK = 0x1F // Mode mask +SYS_MODE_BITS = 0x1F // System mode bits + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr // Save ISR return address + MRS r0, CPSR // Pickup the CPSR + BIC r0, r0, #MODE_MASK // Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS // Build system mode CPSR + MSR CPSR_c, r0 // Enter system mode + STMDB sp!, {r1, lr} // Push the system mode lr on the system mode stack + // and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR + MSR CPSR_c, r0 // Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 // Return to caller +#else + MOV pc, r3 // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..d8dd5ddd --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,446 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter +#endif + +#define IRQ_MODE 0xD2 // IRQ mode +#define USR_MODE 0x10 // USR mode +#define SVC_MODE 0x13 // SVC mode +#define SYS_MODE 0x1F // SYS mode + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define ENABLE_INTS 0xC0 // IRQ & FIQ Interrupts enabled mask +#else +#define ENABLE_INTS 0x80 // IRQ Interrupts enabled mask +#endif + +#define MODE_MASK 0x1F // Mode mask +#define THUMB_MASK 0x20 // Thumb bit mask + + .global _txm_system_mode_enter + .global _txm_system_mode_exit + .global _txm_ttbr1_page_table + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: + + // Enter the scheduler. + SVC 0 + + // We should never get here - ever! +_tx_scheduler_fault__: + B _tx_scheduler_fault__ +// } + + +///////////////////////////////////////////////////////////////////// +// SWI_Handler +///////////////////////////////////////////////////////////////////// + + .global __tx_swi_interrupt // Software interrupt handler +__tx_swi_interrupt: + + STMFD sp!, {r0-r3, r12, lr} // Store the registers + MOV r1, sp // Set pointer to parameters + MRS r0, spsr // Get spsr + STMFD sp!, {r0, r3} // Store spsr onto stack and another + // register to maintain 8-byte-aligned stack + TST r0, #THUMB_MASK // Occurred in Thumb state? + LDRNEH r0, [lr,#-2] // Yes: Load halfword and... + BICNE r0, r0, #0xFF00 // ...extract comment field + LDREQ r0, [lr,#-4] // No: Load word and... + BICEQ r0, r0, #0xFF000000 // ...extract comment field + + // r0 now contains SVC number + // r1 now contains pointer to stacked registers + + // The service call is handled here + + CMP r0, #0 // Is it a schedule request? + BEQ _tx_handler_svc_schedule // Yes, go there + + CMP r0, #1 // Is it a system mode enter request? + BEQ _tx_handler_svc_super_enter // Yes, go there + + CMP r0, #2 // Is it a system mode exit request? + BEQ _tx_handler_svc_super_exit // Yes, go there + + LDR r2, =0x123456 + CMP r0, r2 // Is it an ARM request? + BEQ _tx_handler_svc_arm // Yes, go there + +///////////////////////////////////////////////////////////////////// +// Unknown SVC argument +///////////////////////////////////////////////////////////////////// + // Unrecognized service call +_tx_handler_svc_unrecognized: + +_tx_handler_svc_unrecognized_loop: // We should never get here + B _tx_handler_svc_unrecognized_loop + +///////////////////////////////////////////////////////////////////// +// SVC 1 +///////////////////////////////////////////////////////////////////// + // At this point we have an SVC 1, which means we are entering the system mode to service a kernel call +_tx_handler_svc_super_enter: + // Make sure that we have been called from the system mode enter location (security) + LDR r2, =_txm_system_mode_enter // Load the address of the known call point + SUB r1, lr, #4 // Calculate the address of the actual call + CMP r1, r2 // Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized // Return to where we came + + // Clear the user mode flag in the thread structure + LDR r1, =_tx_thread_current_ptr // Load the current thread pointer address + LDR r2, [r1] // Load current thread location from the pointer (pointer indirection) + MOV r1, #0 // Load the new user mode flag value (user mode flag clear -> not user mode -> system) + STR r1, [r2, #0x9C] // Clear tx_thread_module_current_user_mode for thread + + // Now we enter the system mode and return + LDMFD sp!, {r0, r3} // Get spsr from the stack + BIC r0, r0, #MODE_MASK // clear mode field + ORR r0, r0, #SYS_MODE // system mode code + MSR SPSR_cxsf, r0 // Restore the spsr + + LDR r1, [r2, #0xA8] // Load the module kernel stack pointer + CPS #SYS_MODE // Switch to SYS mode + MOV r3, sp // Grab thread stack pointer + MOV sp, r1 // Set SP to kernel stack pointer + CPS #SVC_MODE // Switch back to SVC mode + STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + // do nothing +#else + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r3, [r2, #20] // Set stack size + LDRD r0, r1, [r2, #0xA4] // Load the module kernel stack start and end + STRD r0, r1, [r2, #0x0C] // Set stack start and end +#endif + + LDMFD sp!, {r0-r3, r12, pc}^ // Restore the registers and return + +///////////////////////////////////////////////////////////////////// +// SVC 2 +///////////////////////////////////////////////////////////////////// + // At this point we have an SVC 2, which means we are exiting the system mode after servicing a kernel call +_tx_handler_svc_super_exit: + // Make sure that we have been called from the system mode exit location (security) + LDR r2, =_txm_system_mode_exit // Load the address of the known call point + SUB r1, lr, #4 // Calculate the address of the actual call + CMP r1, r2 // Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized // Return to where we came + + // Set the user mode flag into the thread structure + LDR r1, =_tx_thread_current_ptr // Load the current thread pointer address + LDR r2, [r1] // Load the current thread location from the pointer (pointer indirection) + MOV r1, #1 // Load the new user mode flag value (user mode enabled -> not system anymore) + STR r1, [r2, #0x9C] // Set tx_thread_module_current_user_mode for thread + + // Now we enter user mode (exit the system mode) and return + LDMFD sp!, {r0, r3} // Get spsr from the stack + BIC r0, r0, #MODE_MASK // clear mode field + ORR r0, r0, #USR_MODE // user mode code + MSR SPSR_cxsf, r0 // Restore the spsr + + LDR r1, [r2, #0xB0] // Load the module thread stack pointer + CPS #SYS_MODE // Switch to SYS mode + MOV r3, sp // Grab kernel stack pointer + MOV sp, r1 // Set SP back to thread stack pointer + CPS #SVC_MODE // Switch back to SVC mode +#ifdef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + // do nothing +#else + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r3, [r2, #20] // Set stack size + LDRD r0, r1, [r2, #0xB4] // Load the module thread stack start and end + STRD r0, r1, [r2, #0x0C] // Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ // Restore the registers and return + +///////////////////////////////////////////////////////////////////// +// ARM Semihosting +///////////////////////////////////////////////////////////////////// +_tx_handler_svc_arm: + + // *** TODO: handle semihosting requests or ARM angel requests *** + + // just return + LDMFD sp!, {r0, r3} // Get spsr from the stack + MSR SPSR_cxsf, r0 // Restore the spsr + LDMFD sp!, {r0-r3, r12, pc}^ // Restore the registers and return + +///////////////////////////////////////////////////////////////////// +// SVC 0 +///////////////////////////////////////////////////////////////////// + // At this point we have an SVC 0: enter the scheduler. +_tx_handler_svc_schedule: + + LDMFD sp!, {r0, r3} // Get spsr from stack + MSR SPSR_cxsf, r0 // Restore spsr + LDMFD sp!, {r0-r3, r12, lr} // Restore the registers + + // This code waits for a thread control block pointer to appear in + // the _tx_thread_execute_ptr variable. Once a thread pointer appears + // in the variable, the corresponding thread is resumed. + + /* Enable interrupts. */ + + MRS r2, CPSR // Pickup CPSR + BIC r0, r2, #ENABLE_INTS // Clear the disable bit(s) + MSR CPSR_cxsf, r0 // Enable interrupts + + + /* Wait for a thread to execute. */ + // do + // { + LDR r1, =_tx_thread_execute_ptr // Address of thread execute ptr +__tx_thread_schedule_loop: + LDR r0, [r1] // Pickup next thread to execute + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_schedule_loop // If so, keep looking for a thread + // } + // while(_tx_thread_execute_ptr == TX_NULL); + + // Yes! We have a thread to execute. Lockout interrupts and transfer control to it. +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + + /* Setup the current thread pointer. */ + // _tx_thread_current_ptr = _tx_thread_execute_ptr; + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread + STR r0, [r1] // Setup current thread pointer + + /* Increment the run count for this thread. */ + // _tx_thread_current_ptr -> tx_thread_run_count++; + + LDR r2, [r0, #4] // Pickup run counter + LDR r3, [r0, #24] // Pickup time-slice for this thread + ADD r2, r2, #1 // Increment thread run-counter + STR r2, [r0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + // _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; + + LDR r2, =_tx_timer_time_slice // Pickup address of time-slice variable + STR r3, [r2, #0] // Setup time-slice + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 // Save r0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV r0, r5 // Restore r0 +#endif + + // Determine if an interrupt frame or a synchronous task suspension frame is present. + CPS #SYS_MODE // Enter SYS mode + LDR sp, [r0, #8] // Switch to thread stack pointer + LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + CPS #SVC_MODE // Enter SVC mode + + ///////////////////////////////////////////////////////////////////// + // Set up MMU for module. + LDR r2, [r0, #0x94] // Pickup the module pointer + CMP r2, #0 // Valid module pointer? + LDRNE r2, [r2, #0x64] // Load ASID + // Otherwise, ASID 0 & master table will be loaded. + // Is ASID already loaded? + MRC p15, 0, r1, c13, c0, 1 // Read CONTEXTIDR into r1 + CMP r1, r2 + // If so, skip MMU setup. + BEQ _tx_skip_mmu_update + // New ASID & TTBR values to load + DSB + ISB + // Load new ASID and TTBR + LDR r1, =_txm_ttbr1_page_table // Load master TTBR + ORR r1, r1, #0x48 // OR it with #TTBR0_ATTRIBUTES + MCR p15, 0, r1, c2, c0, 0 // Change TTBR to master + ISB + DSB + MCR p15, 0, r2, c13, c0, 1 // Change ASID to new value + ISB + // Change TTBR to new value + MOV r3, #14 + ADD r1, r1, r2, LSL r3 + MCR p15, 0, r1, c2, c0, 0 // Change TTBR to new value + + // refresh TLB + MOV r2, #0 + DSB + MCR p15, 0, r2, c8, c7, 0 // Invalidate entire unified TLB + MCR p15, 0, r2, c7, c5, 0 // Invalidate all instruction caches to PoU + MCR p15, 0, r2, c7, c5, 6 // Invalidate branch predictor + DSB + ISB + + // test address translation + //mcr p15, 0, r0, c7, c8, 0 + +_tx_skip_mmu_update: + ///////////////////////////////////////////////////////////////////// + + CMP r4, #0 // Check for synchronous context switch + BEQ _tx_solicited_return + + MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SYS_MODE // Enter SYS mode + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} // Recover D0-D15 + VLDMIA sp!, {D16-D31} // Recover D16-D31 + LDR r4, [sp], #4 // Pickup FPSCR + VMSR FPSCR, r4 // Restore FPSCR + CPS #SVC_MODE // Enter SVC mode + LDR lr, [r1, #0x144] // Get thread PC + CPS #SYS_MODE // Enter SYS mode +_tx_skip_interrupt_vfp_restore: +#endif + + LDMIA sp!, {r0-r12, lr} // Restore registers + ADD sp, sp, #4 // Fix stack pointer + CPS #SVC_MODE // Enter SVC mode + SUBS pc, lr, #0 // Return to point of thread interrupt + +_tx_solicited_return: + MOV r2, r5 // Move CPSR to scratch register + CPS #SYS_MODE // Enter SYS mode + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] // Pickup the VFP enabled flag + CMP r1, #0 // Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore // No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} // Recover D8-D15 + VLDMIA sp!, {D16-D31} // Recover D16-D31 + LDR r4, [sp], #4 // Pickup FPSCR + VMSR FPSCR, r4 // Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + + LDMIA sp!, {r4-r11, lr} // Restore registers + MOV r1, lr // Copy lr to r1 to preserve across mode change + CPS #SVC_MODE // Enter SVC mode + MSR SPSR_cxsf, r2 // Recover CPSR + MOV lr, r1 // Deprecated return via r1, so copy r1 to lr and return via lr + SUBS pc, lr, #0 // Return to thread synchronously + +///////////////////////////////////////////////////////////////////// +// End __tx_handler_swi +///////////////////////////////////////////////////////////////////// + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR // Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Enable IRQ and FIQ interrupts +#else + CPSID i // Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup current thread pointer + CMP r1, #0 // Check for NULL thread pointer + BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable + MOV r0, #1 // Build enable value + STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 // Recover CPSR + BX LR // Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR // Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Enable IRQ and FIQ interrupts +#else + CPSID i // Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup current thread pointer + CMP r1, #0 // Check for NULL thread pointer + BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable + MOV r0, #0 // Build disable value + STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 // Recover CPSR + BX LR // Return to caller diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..f413e673 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .arm + +SVC_MODE = 0x13 // SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled +#endif + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_stack_build // Call _tx_thread_stack_build function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the ARMv7-A should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + a1 (r0) Initial value for a1 + a2 (r1) Initial value for a2 + a3 (r2) Initial value for a3 + a4 (r3) Initial value for a4 + v1 (r4) Initial value for v1 + v2 (r5) Initial value for v2 + v3 (r6) Initial value for v3 + v4 (r7) Initial value for v4 + v5 (r8) Initial value for v5 + sb (r9) Initial value for sb + sl (r10) Initial value for sl + fp (r11) Initial value for fp + ip (r12) Initial value for ip + lr (r14) Initial value for lr + pc (r15) Initial value for + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #7 // Ensure 8-byte alignment + SUB r2, r2, #76 // Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, #1 // Build interrupt stack type + STR r3, [r2, #0] // Store stack type + MOV r3, #0 // Build initial register value + STR r3, [r2, #8] // Store initial r0 + STR r3, [r2, #12] // Store initial r1 + STR r3, [r2, #16] // Store initial r2 + STR r3, [r2, #20] // Store initial r3 + STR r3, [r2, #24] // Store initial r4 + STR r3, [r2, #28] // Store initial r5 + STR r3, [r2, #32] // Store initial r6 + STR r3, [r2, #36] // Store initial r7 + STR r3, [r2, #40] // Store initial r8 + STR r3, [r2, #44] // Store initial r9 + LDR r3, [r0, #12] // Pickup stack starting address + STR r3, [r2, #48] // Store initial r10 (sl) + LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] // Store initial r14 (lr) + MOV r3, #0 // Build initial register value + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r1, [r2, #64] // Store initial pc + STR r3, [r2, #68] // 0 for back-trace + MRS r1, CPSR // Pickup CPSR + BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] // Store initial CPSR + + /* Setup stack pointer. */ + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..cb7d62ce --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,162 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + + + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + + + +/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_thread_system_return // Call _tx_thread_system_return function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + STMDB sp!, {r4-r11, lr} // Save minimal context + + LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr + LDR r5, [r4] // Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] // Pickup the VFP enabled flag + CMP r1, #0 // Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save // No, skip VFP solicited save + VMRS r1, FPSCR // Pickup the FPSCR + STR r1, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D16-D31} // Save D16-D31 + VSTMDB sp!, {D8-D15} // Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 // Build a solicited stack type + MRS r1, CPSR // Pickup the CPSR + STMDB sp!, {r0-r1} // Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit // Call the thread exit function +#endif + MOV r3, r4 // Pickup address of current ptr + MOV r0, r5 // Pickup current thread pointer + LDR r2, =_tx_timer_time_slice // Pickup address of time slice + LDR r1, [r2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + + STR sp, [r0, #8] // Save thread stack pointer + + /* Determine if the time-slice is active. */ + + MOV r4, #0 // Build clear value + CMP r1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + + STR r4, [r2] // Clear time-slice + STR r1, [r0, #24] // Save current time-slice + +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + + STR r4, [r3] // Clear current thread pointer + B _tx_thread_schedule // Jump to scheduler! diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..d846223f --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter + + + +/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save + since it will never be called 16-bit mode. */ + + .arm + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 10-15-2021 William E. Lamie Modified comment(s), added */ +/* execution profile support, */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state // Pickup address of system state variable + LDR r2, [r3, #0] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + MOV pc, lr // Return to caller + +__tx_thread_not_nested_save: + + /* Otherwise, not nested, check to see if a thread was running. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1, #0] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + MOV pc, lr // Return to caller + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, #0 // Clear stack limit + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + ADD sp, sp, #32 // Recover saved registers + MOV pc, lr // Return to caller diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..7337ed0c --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .arm + + +/* Define Assembly language external references... */ + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + + + +/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for + applications calling this function from to 16-bit Thumb mode. */ + + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc // Switch to 32-bit mode + NOP // + .arm + STMFD sp!, {lr} // Save return address + BL _tx_timer_interrupt // Call _tx_timer_interrupt function + LDMFD sp!, {lr} // Recover saved return address + BX lr // Return to 16-bit caller + + + .text + .align 2 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt ARMv7-A */ +/* 6.1.11 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-25-2022 Zhen Kong Updated comments, */ +/* resulting in version 6.1.11 */ +/* */ +/**************************************************************************/ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1] // Store new system clock + + /* Test for time-slice expiration. */ + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it non-active? + BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3] // Store new time-slice value + + /* Check for expiration. */ + + CMP r2, #0 // Has it expired? + BNE __tx_timer_no_time_slice // No, skip expiration processing + + /* Set the time-slice expired flag. */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3] // Set time-slice expiration flag + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1] // Pickup current timer + LDR r2, [r0] // Pickup timer list entry + CMP r2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3] // Set expired flag + B __tx_timer_done // Finished timer processing + +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + ADD r0, r0, #4 // Move to next timer + + /* Check for wraparound. */ + + LDR r3, =_tx_timer_list_end // Pickup address of timer list end + LDR r2, [r3] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wraparound logic + + /* Wrap to beginning of list. */ + + LDR r3, =_tx_timer_list_start // Pickup address of timer list start + LDR r0, [r3] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] // Store new current timer pointer + +__tx_timer_done: + + /* See if anything has expired. */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + LDR r2, [r3] // Pickup time-slice expired flag + CMP r2, #0 // Did a time-slice expire? + BNE __tx_something_expired // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup address of other expired flag + LDR r0, [r1] // Pickup timer expired flag + CMP r0, #0 // Did a timer expire? + BEQ __tx_timer_nothing_expired // No, nothing expired + +__tx_something_expired: + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + + LDR r1, =_tx_timer_expired // Pickup address of expired flag + LDR r0, [r1] // Pickup timer expired flag + CMP r0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + BL _tx_timer_expiration_process // Call the timer expiration handling routine + +__tx_timer_dont_activate: + + /* Did time slice expire? */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of time-slice expired + LDR r2, [r3] // Pickup the actual flag + CMP r2, #0 // See if the flag is set + BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing + + /* Time slice interrupted thread. */ + + BL _tx_thread_time_slice // Call time-slice processing + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + +__tx_timer_nothing_expired: + +#ifdef __THUMB_INTERWORK + BX lr // Return to caller +#else + MOV pc, lr // Return to caller +#endif diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..beeeb9f6 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; + + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + local_data_size = *data_size; + local_data_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + + /* Return all the information to the caller. */ + *code_size = ((local_code_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *code_alignment = local_code_alignment; + *data_size = ((local_data_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..bb37b9e3 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,483 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +/* External page tables. */ +extern ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_get Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets an available L2 page table and places it in the */ +/* module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* page_addr Address of L2 page */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_external_memory_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) +{ + +UINT i; +UINT status; +UINT table_index; +UINT pool_index; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Find first free table slot in module control block. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i] == TX_NULL) + { + table_index = i; + break; + } + } + + if(i >= TXM_MODULE_LEVEL2_EXTERNAL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + + else + { + /* Find first free table in pool. */ + for(i = 0; i < TXM_LEVEL2_EXTERNAL_POOL_PAGES; i++) + { + if(_txm_level2_external_page_pool[i][0] == (ULONG) TX_NULL) + { + pool_index = i; + break; + } + } + + if(i >= TXM_LEVEL2_EXTERNAL_POOL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + } + + + if(status == TX_SUCCESS) + { + /* Place page address in table slot. Return page address. */ + module_instance->txm_external_page_table[table_index] = _txm_level2_external_page_pool[pool_index]; + *page_addr = (ULONG)_txm_level2_external_page_pool[pool_index]; + } + + return(status); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_clear Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function clears the first entry in a L2 page table and clears */ +/* the table entry from the module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i; + + /* Clear table slots and zero out L2 entry. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i]) + { + *(ULONG *)module_instance->txm_external_page_table[i] = (ULONG)TX_NULL; + module_instance->txm_external_page_table[i] = TX_NULL; + } + } +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MMU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* TX_MEMSET Fill memory with constant */ +/* _txm_level2_page_get Get L2 page table */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable( TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG start_addr = (ULONG) start_address; +ULONG end_addr; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_addr; +ULONG page_addr; +ULONG asid; +ULONG level1_attributes; +ULONG level2_attributes; +UINT status; +UINT i; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if the module instance is memory protected. */ + if (module_instance -> txm_module_instance_asid == 0) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not protected. */ + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Start address must be aligned to MMU block size (4 kB). + Length will be rounded up to 4 kB alignment. */ + if(start_addr & ~TXM_MMU_LEVEL2_MASK) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /**************************************************************************/ + /* At this point, we have a valid address. Set up MMU. */ + /**************************************************************************/ + + /* Round length up to 4 kB alignment. */ + if(length & ~TXM_MMU_LEVEL2_MASK) + { + length = ((length + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + } + + /* Get end address. */ + end_addr = start_addr + length - 1; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_addr++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Get module ASID. */ + asid = module_instance -> txm_module_instance_asid; + + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* Build L2 attributes. */ + level2_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* If start_addr is not aligned, we need a L2 page. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][level1_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_addr = ((start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_addr - start_addr) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + ((ULONG *) page_addr)[level2_index] = (start_addr & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_addr & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][temp_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + ((ULONG *) page_addr)[i] = (end_addr & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Build L1 attributes. */ + level1_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE; + + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | level1_attributes; + } + + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..1157bcf2 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..d795091a --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c new file mode 100644 index 00000000..024caeef --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c @@ -0,0 +1,301 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +#define CACHE_DISABLED 0x12 +#define SDRAM_START 0x00000000 +#define SDRAM_END 0x1fffffff +#define CACHE_WRITEBACK 0x1e + +#define SECTION_DESCRIPTOR 0x00000002 +#define DACR_CLIENT_MODE 0x55555555 + + +/*** Page table attributes TTBR0 *********************************************** +* IRGN = 01 - Normal memory, Inner Write-Back Write-Allocate Cacheable +* S - non-shareable +* RGN = 01 - Normal memory, Outer Write-Back Write-Allocate Cacheable +* NOS - outer-shareable +*******************************************************************************/ +#define TTBR0_ATTRIBUTES 0x48 + + + +/* ASID table, index is ASID number and contents hold pointer to module. */ +TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; + +/* Master page table, 2^14 (16kB) alignment. + * First table is the master level 1 table, the rest are for each module. */ +__attribute__ ((aligned (16384))) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + +/* Module start and end level 2 page tables, 2^10 (1kB) alignment. + * First set of 4 tables are the master level 2 tables, the rest are for each module. + * Each module needs two L2 tables for code and two L2 tables for data. */ +__attribute__ ((aligned (1024))) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ +__attribute__ ((aligned (1024))) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_mm_initialize(VOID) +{ + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + UINT i; + ULONG cp15reg; + UINT user_mode_index; + UINT counter_limit; + + /* Clear ASID table. */ + for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) + { + _txm_asid_table[i] = 0; + } + _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; + + + /********************************************************************************/ + /* This is an example showing how to set up the cache attributes. */ + /********************************************************************************/ + +/******************************************************************************* +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| +* |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| +* +* Bits[31:20] - Top 12 bits of VA is pointer into table +* nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +* S[16]=0 - Indicates normal memory is shared when set. +* AP2[15]=0 +* TEX[14:12]=000 +* AP[11:10]=11 - Configure for full read/write access in all modes +* IMPP[9]=0 - Ignored +* Domain[5:8]=1111 - Set all pages to use domain 15 +* XN[4]=0 - Execute never disabled +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section +*******************************************************************************/ + +/* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ +/* setting for Strongly-ordered memory + B-00000000000000000000010111100010 */ +#define TTB_PARA_STRGLY 0x05E2 + +/* setting for Outer and inner not cache normal memory + B-00000000000000000001010111100010 */ +#define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 + +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) + B-00000000000000000001010111101110 */ +#define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE + +/* In this chip (RZA1) there are the following 12 sections with the defined memory size (MB) */ +#define M_SIZE_NOR 128 /* [Area00] CS0, CS1 area (for NOR flash) */ +#define M_SIZE_SDRAM 128 /* [Area01] CS2, CS3 area (for SDRAM) */ +#define M_SIZE_CS45 128 /* [Area02] CS4, CS5 area */ +#define M_SIZE_SPI 128 /* [Area03] SPI, SP2 area (for Serial flash) */ +#define M_SIZE_RAM 10 /* [Area04] Internal RAM */ +#define M_SIZE_IO_1 502 /* [Area05] I/O area 1 */ +#define M_SIZE_NOR_M 128 /* [Area06] CS0, CS1 area (for NOR flash) (mirror) */ +#define M_SIZE_SDRAM_M 128 /* [Area07] CS2, CS3 area (for SDRAM) (mirror) */ +#define M_SIZE_CS45_M 128 /* [Area08] CS4, CS5 area (mirror) */ +#define M_SIZE_SPI_M 128 /* [Area09] SPI, SP2 area (for Serial flash) (mirror) */ +#define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ +#define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ +/* Should add to: 4096 */ + + counter_limit = M_SIZE_NOR; + for (i = 0; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_SDRAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_CS45; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_RAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_IO_1; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_NOR_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_SDRAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_CS45_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_RAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_IO_2; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + /********************************************************************************/ + /* This is the end of the example showing how to set up the cache attributes. */ + /********************************************************************************/ + + + /* Clear ASID. */ + cp15reg = 0; + __asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); + __asm("isb"); + + /* Put the page table address in TTBR. */ + cp15reg = (int)(VOID*)_txm_ttbr1_page_table; + cp15reg |= TTBR0_ATTRIBUTES; + __asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); + + /* Set the domain to client mode. */ + cp15reg = DACR_CLIENT_MODE; + __asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); + + +/* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ +#define TTB_LEVEL2_NORMAL_CACHE 0x05E + +/* Level 2 clear AP attributes mask. */ +#define TTB_LEVEL2_AP_CLEAR_MASK 0xFFFFFFCF + +/* Attributes for user mode table entry in level 2 table. */ +#define TTB_LEVEL2_USER_MODE_ENTRY 0x06E + + /* Set up Level 2 table for user to kernel mode entry trampoline. */ + /* Find which table entry _txm_module_manager_user_mode_entry is in. */ + user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; + /* Fill table. */ + for (i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; + } + + /* Enter Level 2 table in to master table. */ + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ + user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + + /* Set attribute bits for the user mode entry page. */ + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; + + /* Enable the MMU. */ + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); + cp15reg |= 0x1; + __asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); + + return(TX_SUCCESS); + +#else + return(TX_FEATURE_NOT_ENABLED); +#endif +} diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..5614bf11 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,589 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +extern TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; +extern ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function determines if pointer is within the module's data or */ +/* shared memory. */ +/* */ +/* INPUT */ +/* */ +/* pointer Data pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(ULONG pointer) +{ + +ULONG translation; + + /* ATS1CUR operation on address supplied in pointer, Stage 1 unprivileged read. */ + __asm volatile ("MCR p15, 0, %0, c7, c8, 2" : : "r"(pointer) : ); + __asm volatile ("ISB"); /* Ensure completion of the MCR write to CP15. */ + __asm volatile ("MRC p15, 0, %0, c7, c4, 0" : "=r"(translation) : : ); /* Read result from 32-bit PAR into translation. */ + + if (translation & TXM_ADDRESS_TRANSLATION_FAULT_BIT) + { + return(TX_FALSE); + } + + return(TX_TRUE); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_assign_asid Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function assigns an Application Specific ID (ASID) to a */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_assign_asid(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i = 1; + + /* Find first non-zero ASID, starting at index 1. */ + while(i < TXM_ASID_TABLE_LENGTH) + { + if(_txm_asid_table[i] != 0) + { + i++; + } + else + { + module_instance -> txm_module_instance_asid = i; + _txm_asid_table[i] = module_instance; + return(TX_SUCCESS); + } + } + + return(TXM_MODULE_ASID_ERROR); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_remove_asid Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes a module from the ASID list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance) +{ + if(module_instance -> txm_module_instance_asid) + { + _txm_asid_table[module_instance -> txm_module_instance_asid] = 0; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-A7 MMU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_assign_asid */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_SETUP */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + +ULONG start_address; +ULONG end_address; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_address; +ULONG l2_address; +ULONG attributes = 0; +ULONG asid; +UINT i; + + + /* Assign an ASID to this module. */ + _txm_module_manager_assign_asid(module_instance); + + asid = module_instance -> txm_module_instance_asid; + + /* Copy master level 1 page table to module's page table. */ + for(i = 0; i < TXM_MASTER_PAGE_TABLE_ENTRIES; i++) + { + _txm_ttbr1_page_table[asid][i] = _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i]; + } + + /* Clear level 2 tables. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = 0; + } + + /* Get code start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_code_start; + /* Extend end address to end of page (TXM_MODULE_MEMORY_ALIGNMENT-1). */ + end_address = ((((ULONG)module_instance -> txm_module_instance_code_end) + TXM_MODULE_MEMORY_ALIGNMENT-1) & ~((ULONG)TXM_MODULE_MEMORY_ALIGNMENT-1)) - 1; + + /* How many level 1 table entries does code span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does code need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module code range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_CODE_ATTRIBUTES; + } + + /**************************************************************************/ + /* At this point, code protection is set up. */ + /* Data protection is set up below. */ + /**************************************************************************/ + + /* Get data start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_data_start; + end_address = (ULONG)module_instance -> txm_module_instance_data_end; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_DATA_ATTRIBUTES; + } + +#endif +} diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..951b9629 --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,149 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define THUMB_MASK 0x20 // THUMB bit +#define USR_MODE 0x10 // USR mode +#define SYS_MODE 0x1F // SYS mode +#ifdef TX_ENABLE_FIQ_SUPPORT +#define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled +#else +#define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .text + .global _txm_module_manager_thread_stack_build + .type _txm_module_manager_thread_stack_build, "function" +_txm_module_manager_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A7 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 Initial value for r0 + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r12 Initial value for r12 + lr Initial value for lr (r14) + pc Initial value for pc (r15) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #7 // Ensure 8-byte alignment + SUB r2, r2, #76 // Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, #1 // Build interrupt stack type + STR r3, [r2, #0] // Store stack type + STR r0, [r2, #8] // Store initial r0 (thread pointer) + LDR r3, [r0, #8] // Pickup thread info pointer (it's in the stack pointer location right now) + STR r3, [r2, #12] // Store initial r1 + LDR r3, [r3, #8] // Pickup data base register + STR r3, [r2, #44] // Store initial r9 + MOV r3, #0 // Build initial register value + STR r3, [r2, #16] // Store initial r2 + STR r3, [r2, #20] // Store initial r3 + STR r3, [r2, #24] // Store initial r4 + STR r3, [r2, #28] // Store initial r5 + STR r3, [r2, #32] // Store initial r6 + STR r3, [r2, #36] // Store initial r7 + STR r3, [r2, #40] // Store initial r8 + LDR r3, [r0, #12] // Pickup stack starting address + STR r3, [r2, #48] // Store initial r10 (sl) + MOV r3, #0 // Build initial register value + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #60] // Store initial lr + STR r1, [r2, #64] // Store initial pc + STR r3, [r2, #68] // 0 for back-trace + MRS r3, CPSR // Pickup CPSR + BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR + TST r1, #1 // Test if THUMB bit set in initial PC + ORRNE r3, r3, #THUMB_MASK // Set T bit if set + LDR r1, [r0, #156] // Load tx_thread_module_current_user_mode + TST r1, #1 // Test if the flag is set + ORREQ r3, r3, #SYS_MODE // Flag not set: Build CPSR, SYS mode, IRQ enabled + ORRNE r3, r3, #USR_MODE // Flag set: Build CPSR, USR mode, IRQ enabled + STR r3, [r2, #4] // Store initial CPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s new file mode 100644 index 00000000..e3d7269a --- /dev/null +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _txm_module_manager_kernel_dispatch + .global _txm_system_mode_enter + .global _txm_system_mode_exit +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allows modules to enter kernel mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 Enter kernel mode */ +/* SVC 2 Exit kernel mode */ +/* */ +/* CALLED BY */ +/* */ +/* Modules in user mode */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ + .text + .align 12 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _txm_module_manager_user_mode_entry + .type _txm_module_manager_user_mode_entry, "function" +_txm_module_manager_user_mode_entry: +_txm_system_mode_enter: + SVC 1 // Get out of user mode +_txm_module_priv: + // At this point, we are in system mode. + // Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function. + PUSH {r3, lr} + BL _txm_module_manager_kernel_dispatch + POP {r3, lr} + + .global _txm_system_mode_exit +_txm_system_mode_exit: + // Trap to restore user mode while inside of ThreadX + SVC 2 + + BX lr // Return to the caller + NOP + NOP + + // Fill up 4kB page. + .align 12 +_txm_module_manager_user_mode_end: diff --git a/ports_module/cortex_a7/iar/example_build/azure_rtos.eww b/ports_module/cortex_a7/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..a8dd1c9e --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/azure_rtos.eww @@ -0,0 +1,19 @@ + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\sample_threadx_module.ewp + + + $WS_DIR$\sample_threadx_module_manager.ewp + + + $WS_DIR$\tx.ewp + + + $WS_DIR$\txm.ewp + + + diff --git a/ports_module/cortex_a7/iar/example_build/cstartup.s b/ports_module/cortex_a7/iar/example_build/cstartup.s new file mode 100644 index 00000000..329decce --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN SWI_Handler + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx.c b/ports_module/cortex_a7/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..983109cc --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx.c @@ -0,0 +1,376 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx.ewd b/ports_module/cortex_a7/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..579e4443 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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__ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0802FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_DRAM_start__ = 0x80000000; +define symbol __region_DRAM_end__ = 0x807FFFFF; +define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; +place in DRAM_region { section DRAM }; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..d81c0c6d --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void *) &semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void *) &mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* Test external/shared memory. */ + *(ULONG *) 0x90000000 = 0xdeadbeef; + *(ULONG *) 0x90000FFC = 0xfeed0add; + *(ULONG *) 0x90001000 = 0xfedcba01; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewd b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewd new file mode 100644 index 00000000..e785027c --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0800FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0; +define symbol __ICFEDIT_size_svcstack__ = 0; +define symbol __ICFEDIT_size_irqstack__ = 0; +define symbol __ICFEDIT_size_fiqstack__ = 0; +define symbol __ICFEDIT_size_undstack__ = 0; +define symbol __ICFEDIT_size_abtstack__ = 0; +define symbol __ICFEDIT_size_heap__ = 0x100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..9aa08e2f --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,133 @@ +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program + manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for + use. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + +/* Define the module object pool area. */ +UCHAR object_memory[16384]; + +UCHAR manager_thread_stack[DEMO_STACK_SIZE]; + +/* Define the module data pool area. */ +#define MODULE_DATA_SIZE 65536/2 +unsigned char module_data_area[MODULE_DATA_SIZE]; + +/* Define a module instance. */ +TXM_MODULE_INSTANCE my_module1; +TXM_MODULE_INSTANCE my_module2; + +/* Module code is in an array created by module_to_c_array utility. */ +//extern unsigned char module_code[]; + +/* Define the count of memory faults. */ +ULONG memory_faults; + +/* Define fault handler. */ +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + + /* Create the module manager thread. */ + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_thread_stack, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); + + /* Create a pool for module objects. */ + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Initialize MMU. */ + txm_module_manager_mm_initialize(); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); + + /* Load a second instance of the module. */ + //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); + + /* Enable shared memory regions for one module. */ + //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the modules. */ + txm_module_manager_start(&my_module1); + //txm_module_manager_start(&my_module2); + + /* Sleep for a while and let the modules run.... */ + tx_thread_sleep(50); + + /* Thread 0 in module1 should be terminated due to violating the MMU. */ + + /* Stop the modules. */ + txm_module_manager_stop(&my_module1); + txm_module_manager_stop(&my_module2); + + /* Unload the modules. */ + txm_module_manager_unload(&my_module1); + txm_module_manager_unload(&my_module2); + + /* Reload the modules. */ + txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) 0x00100000); + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); + + /* Give both modules shared memory. */ + txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the module again. */ + txm_module_manager_start(&my_module2); + txm_module_manager_start(&my_module1); + + /* Now just spin... */ + while(1) + { + tx_thread_sleep(100); + /* Thread 0 and 5 in module1 should not exist because they violate the maximum priority. */ + } +} + + + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewd b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.ewd new file mode 100644 index 00000000..bffc6509 --- /dev/null +++ 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$PROJ_DIR$\sample_threadx_module_manager.c + + + $PROJ_DIR$\Debug\Exe\tx.a + + + $PROJ_DIR$\tx_initialize_low_level.s + + diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf new file mode 100644 index 00000000..f076b002 --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; //Module in 0x00100000-0x0013FFFF +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x081FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_DRAM_start__ = 0x80000000; +define symbol __region_DRAM_end__ = 0x807FFFFF; +define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block PAGE_ALIGN with alignment = 4096 { section page_align }; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly, + block PAGE_ALIGN }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; +place in DRAM_region { section DRAM }; + +place in RAM_region { last section FREE_MEM}; \ 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100644 index 00000000..f592c1ed --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,456 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0x1F ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + +; ******************************************************************* +; MMU Exception Handling +; ******************************************************************* +THUMB_MASK DEFINE 0x20 ; Thumb bit (5) of CPSR/SPSR +ABT_MODE DEFINE 0x17 ; ABORT mode + + EXTERN _tx_thread_system_state + EXTERN _txm_module_manager_memory_fault_info + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_schedule + RSEG .text:CODE:NOROOT(2) + ARM + PUBLIC __tx_prefetch_handler + PUBLIC __tx_abort_handler +__tx_prefetch_handler +__tx_abort_handler + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + SUB lr, lr, #4 ; Adjust point of exception +; +; /* Now pickup and store all the fault related information. */ +; + ; Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r3, #0] ; Save current thread pointer + STR lr, [r3, #4] ; Save point of fault + MRC p15, 0, r0, c6, c0, 0 ; Read DFAR + STR r0, [r3, #8] ; Save DFAR + MRC p15, 0, r0, c5, c0, 0 ; Read DFSR + STR r0, [r3, #12] ; Save DFSR + MRC p15, 0, r0, c6, c0, 2 ; Read IFAR + STR r0, [r3, #16] ; Save IFAR + MRC p15, 0, r0, c5, c0, 1 ; Read IFSR + STR r0, [r3, #20] ; Save IFSR + + ; Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] ; Save r0 + STR r1, [r3, #32] ; Save r1 + STR r2, [r3, #36] ; Save r2 + POP {r0} + STR r0, [r3, #40] ; Save r3 + STR r4, [r3, #44] ; Save r4 + STR r5, [r3, #48] ; Save r5 + STR r6, [r3, #52] ; Save r6 + STR r7, [r3, #56] ; Save r7 + STR r8, [r3, #60] ; Save r8 + STR r9, [r3, #64] ; Save r9 + STR r10,[r3, #68] ; Save r10 + STR r11,[r3, #72] ; Save r11 + STR r12,[r3, #76] ; Save r12 + + CPS #SYS_MODE ; Enter SYS mode + MOV r0, lr ; Pickup lr + MOV r1, sp ; Pickup sp + CPS #ABT_MODE ; Back to ABT mode + STR r0, [r3, #80] ; Save lr + STR r1, [r3, #24] ; Save sp + MRS r0, SPSR ; Pickup SPSR + STR r0, [r3, #84] ; Save SPSR + ORR r0, r0, #SYS_MODE ; Return into SYS mode + BIC r0, r0, #THUMB_MASK ; Clear THUMB mode + MSR SPSR_c, r0 ; Save SPSR + + ; Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r0, =_tx_thread_system_state ; Pickup address of system state + LDR r1, [r0] ; Pickup system state + SUB r1, r1, #1 ; Decrement + STR r1, [r0] ; Store new system state + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from exception + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; ******************************************************************* +; End of MMU exception handling. +; ******************************************************************* + + +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + + END diff --git a/ports_module/cortex_a7/iar/example_build/txm.ewd b/ports_module/cortex_a7/iar/example_build/txm.ewd new file mode 100644 index 00000000..42ecf5fe --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/txm.ewd @@ -0,0 +1,3088 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_time_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_time_set.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + + + diff --git a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..31ccca5b --- /dev/null +++ b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s @@ -0,0 +1,67 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 ; Module ID + DC32 0x6 ; Module Major Version + DC32 0x1 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000001 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-1: Reserved + ; Bit 0: 0 -> Privileged mode execution (no MPU protection) + ; 1 -> User mode execution (MPU protection) + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1022 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex_a7/iar/inc/tx_port.h b/ports_module/cortex_a7/iar/inc/tx_port.h new file mode 100644 index 00000000..3780666b --- /dev/null +++ b/ports_module/cortex_a7/iar/inc/tx_port.h @@ -0,0 +1,424 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/IAR */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; +#endif + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif +#endif + +/* Define VFP extension for the Cortex-A7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.2.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif + diff --git a/ports_module/cortex_a7/iar/inc/txm_module_port.h b/ports_module/cortex_a7/iar/inc/txm_module_port.h new file mode 100644 index 00000000..1b31c6f7 --- /dev/null +++ b/ports_module/cortex_a7/iar/inc/txm_module_port.h @@ -0,0 +1,424 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* Defined, this option enables the MMU hardware and requires memory protected + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load + functions will return a TXM_MODULE_INVALID_PROPERTIES error). + Default setting for this value is defined. */ +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_MEMORY_PROTECTION 0x00000001 +#else +#define TXM_MODULE_MEMORY_PROTECTION 0x00000000 +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ +#define INLINE_DECLARE + +#define TXM_MAXIMUM_MODULES 16 +#define TXM_MODULE_LEVEL1_PAGE_TABLE_SIZE 32 +#define TXM_ASID_TABLE_LENGTH 256 + +#define TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 0) +#define TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 1) +#define TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 2) +#define TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 3) + +#define TXM_MASTER_PAGE_TABLE_INDEX 0 + +/* 1 entry per 1MB, so this covers 4G address space */ +#define TXM_MASTER_PAGE_TABLE_ENTRIES 4096 + +/* Smallest MMU page size is 4kB. */ +#define TXM_MODULE_MEMORY_ALIGNMENT 4096 +#define TXM_MMU_LEVEL1_PAGE_SHIFT 20 +#define TXM_MMU_LEVEL2_PAGE_SHIFT 12 +#define TXM_LEVEL_2_PAGE_TABLE_ENTRIES 256 + +/* Level 1 section base address mask. */ +#define TXM_MMU_LEVEL1_MASK 0xFFF00000 + +/* Level 2 section base address mask. */ +#define TXM_MMU_LEVEL2_MASK 0xFFFFF000 + +/* Non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL1_CODE_ATTRIBUTES 0x000219EE +/* Non-global, outer & inner write-back, write-allocate, user read, write, no-execute. */ +#define TXM_MMU_LEVEL1_DATA_ATTRIBUTES 0x00021DFE + +/* Level 1 "level 2 descriptor base address" mask. */ +#define TXM_MMU_LEVEL1_SECOND_MASK 0xFFFFFC00 + +/* Level 1 "level 2 descriptor" attributes. */ +#define TXM_MMU_LEVEL1_SECOND_ATTRIBUTES 0x0000001E1 + +/* Kernel level 2 attributes: global, outer & inner write-back, write-allocate, user read/write */ +#define TXM_MMU_KERNEL_LEVEL2_CODE_ATTRIBUTES 0x0000006E +#define TXM_MMU_KERNEL_LEVEL2_DATA_ATTRIBUTES 0x0000005E + +/* Module level 2 attributes: non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL2_CODE_ATTRIBUTES 0x0000086E +#define TXM_MMU_LEVEL2_DATA_ATTRIBUTES 0x0000087F + + +/* Settings the user can use to set up shared memory attributes. */ +#define TXM_MMU_ATTRIBUTE_XN 0x00000001 +#define TXM_MMU_ATTRIBUTE_B 0x00000002 +#define TXM_MMU_ATTRIBUTE_C 0x00000004 +#define TXM_MMU_ATTRIBUTE_AP 0x00000018 +#define TXM_MMU_ATTRIBUTE_TEX 0x000000E0 + +/* Masks for each attribute. */ +#define TXM_MMU_ATTRIBUTE_XN_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_B_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_C_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_AP_MASK 0x00000003 +#define TXM_MMU_ATTRIBUTE_TEX_MASK 0x00000007 + +/* Shift amounts for bitfields above to correct register locations. */ +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE 0x000201E2 + +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE 0x00000802 + +/* Shift amounts from bit 0 position. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT 10 +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT 12 + +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT 4 +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT 6 + +/* Masks for L1 page attributes. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) + +/* Masks for L2 page attributes. */ +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) + +#define TXM_ADDRESS_TRANSLATION_FAULT_BIT 1 + +#define TXM_ASID_RESERVED 0xFFFFFFFF + +#define TXM_MODULE_ASID_ERROR 0xF6 +#define TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR 0xF7 + +/* Number of L2 pages each module can have. */ +#define TXM_MODULE_LEVEL2_EXTERNAL_PAGES 16 +/* Size, in pages, of the L2 page pool. */ +#define TXM_LEVEL2_EXTERNAL_POOL_PAGES (TXM_MODULE_LEVEL2_EXTERNAL_PAGES * TXM_MAXIMUM_MODULES) + + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_asid; \ + ULONG *txm_external_page_table[TXM_MODULE_LEVEL2_EXTERNAL_PAGES]; + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_dfar; + ULONG txm_module_manager_memory_fault_info_dfsr; + ULONG txm_module_manager_memory_fault_info_ifar; + ULONG txm_module_manager_memory_fault_info_ifsr; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_cpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (TXM_MODULE_MEMORY_ALIGNMENT - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. */ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MMU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) \ + _txm_level2_page_clear(module_instance); \ + _txm_module_manager_remove_asid(module_instance); + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data or shared memory. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check((ULONG) obj_ptr) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#define txm_module_manager_mm_initialize _txm_module_manager_mm_initialize +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +UINT _txm_module_manager_mm_initialize(VOID); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(ULONG pointer); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/iar Version 6.2.1 *"; + +#endif + diff --git a/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..d28c17b7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..a332a862 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,252 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + + +IRQ_MODE EQU 0x12 ; IRQ mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +THUMB_MASK EQU 0x20 ; Thumb bit mask + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +#endif +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_exit +#endif +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + ARM +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + CPS #SYS_MODE ; Enter SYS mode + STR r1, [sp, #-4]! ; Save point of interrupt on thread's stack + STMDB sp!, {r4-r12, lr} ; Save upper half of registers on thread's stack + MOV r4, r3 ; Save SPSR in r4 + CPS #IRQ_MODE ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + CPS #SYS_MODE ; Enter SYS mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + CPS #IRQ_MODE ; Enter IRQ mode + MRS r1, SPSR ; Get SPSR + ORR r1, r1, #SYS_MODE ; Change to SYS Mode + BIC r1, r1, #THUMB_MASK ; Clear thumb bit + MSR SPSR_cxsf, r1 ; Put SYS Mode in SPSR + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..8daa4306 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,192 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + ARM +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..96844809 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,246 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_exit +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + ARM +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __TARGET_FPU_VFP + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..4f0b6cf7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s @@ -0,0 +1,192 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + ARM +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..7f4cd145 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + ARM +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode +#ifdef INTER + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..7b8beef2 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + EXPORT _tx_thread_fiq_nesting_start + ARM +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode +#ifdef INTER + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..f237cc35 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,92 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask +#else +INT_MASK EQU 0x80 ; Interrupt bit mask +#endif +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + ARM +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + BX lr ; Return to caller +; +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..360764e0 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + ARM +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ +#else + CPSID i ; Disable IRQ +#endif + + BX lr ; Return to caller + +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..bbd940e3 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,81 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + ARM +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..fcfd3796 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + + + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + ARM +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + BX r3 ; Return to caller +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..471fa268 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + + +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + ARM +_tx_thread_irq_nesting_start + MOV r3, lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + BX r3 ; Return to caller + +;} +; + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..378a5336 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,452 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_thread_enter +#endif + +IRQ_MODE EQU 0xD2 ; IRQ mode +USR_MODE EQU 0x10 ; USR mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode + +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask +#endif + +MODE_MASK EQU 0x1F ; Mode mask +THUMB_MASK EQU 0x20 ; Thumb bit mask + + EXTERN _txm_system_mode_enter + EXTERN _txm_system_mode_exit + EXTERN _txm_ttbr1_page_table + + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + ARM +_tx_thread_schedule + + ; Enter the scheduler. + SVC 0 + + ; We should never get here - ever! +_tx_scheduler_fault__ + B _tx_scheduler_fault__ +;} +; **************************************************************************** + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RSEG .text:CODE:NOROOT(2) + PUBLIC SWI_Handler + ARM +SWI_Handler + + STMFD sp!, {r0-r3, r12, lr} ; Store the registers + MOV r1, sp ; Set pointer to parameters + MRS r0, spsr ; Get spsr + STMFD sp!, {r0, r3} ; Store spsr onto stack and another + ; register to maintain 8-byte-aligned stack + TST r0, #THUMB_MASK ; Occurred in Thumb state? + LDRNEH r0, [lr,#-2] ; Yes: Load halfword and... + BICNE r0, r0, #0xFF00 ; ...extract comment field + LDREQ r0, [lr,#-4] ; No: Load word and... + BICEQ r0, r0, #0xFF000000 ; ...extract comment field + + ; r0 now contains SVC number + ; r1 now contains pointer to stacked registers + + ; + ; The service call is handled here + ; + + CMP r0, #0 ; Is it a schedule request? + BEQ _tx_handler_svc_schedule ; Yes, go there + + CMP r0, #1 ; Is it a system mode enter request? + BEQ _tx_handler_svc_super_enter ; Yes, go there + + CMP r0, #2 ; Is it a system mode exit request? + BEQ _tx_handler_svc_super_exit ; Yes, go there + + LDR r2, =0x123456 + CMP r0, r2 ; Is it an ARM request? + BEQ _tx_handler_svc_arm ; Yes, go there + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Unknown SVC argument +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Unrecognized service call +_tx_handler_svc_unrecognized + +_tx_handler_svc_unrecognized_loop ; We should never get here + B _tx_handler_svc_unrecognized_loop + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 1, which means we are entering + ; supervisor mode to service a kernel call. +_tx_handler_svc_super_enter + ; Make sure that we have been called from the system mode enter location (security) + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Clear the user mode flag in the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) + MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) + STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread + + ; Now we enter the system mode and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #SYS_MODE ; system mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV r3, sp ; Grab thread stack pointer + MOV sp, r1 ; Set SP to kernel stack pointer + CPS #SVC_MODE ; Switch back to SVC mode + STR r3, [r2, #0xB0] ; Save thread stack pointer +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 2, which means we are exiting + ; supervisor mode after servicing a kernel call. +_tx_handler_svc_super_exit + ; Make sure that we have been called from the system mode exit location (security) + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Set the user mode flag into the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load the current thread location from the pointer (pointer indirection) + MOV r1, #1 ; Load the new user mode flag value (user mode enabled -> not system anymore) + STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread + + ; Now we enter user mode (exit the system mode) and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #USR_MODE ; user mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xB0] ; Load the module thread stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV sp, r1 ; Set SP back to thread stack pointer + CPS #SVC_MODE ; Switch back to SVC mode +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; ARM Semihosting +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +_tx_handler_svc_arm + + ; *** TODO: handle semihosting requests or ARM angel requests *** + + ; just return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + MSR SPSR_cxsf, r0 ; Restore the spsr + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 0 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 0: enter the scheduler. +_tx_handler_svc_schedule + + LDMFD sp!, {r0, r3} ; Get spsr from stack + MSR SPSR_cxsf, r0 ; Restore spsr + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; in the variable, the corresponding thread is resumed. +; +; /* Enable interrupts. */ +; + CPSIE i ; Enable IRQ interrupts + +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + CPSID i ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice variable + STR r3, [r2, #0] ; Setup time-slice +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif + + ; Determine if an interrupt frame or a synchronous task suspension frame is present. + CPS #SYS_MODE ; Enter SYS mode + LDR sp, [r0, #8] ; Switch to thread stack pointer + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CPS #SVC_MODE ; Enter SVC mode + + ; ************************************************************************** + ; Set up MMU for module. + LDR r2, [r0, #0x94] ; Pickup the module pointer + CMP r2, #0 ; Valid module pointer? + LDRNE r2, [r2, #0x64] ; Load ASID + ; Otherwise, ASID 0 & master table will be loaded. + ; Is ASID already loaded? + MRC p15, 0, r1, c13, c0, 1 ; Read CONTEXTIDR into r1 + CMP r1, r2 + ; If so, skip MMU setup. + BEQ _tx_skip_mmu_update + ; New ASID & TTBR values to load + DSB + ISB + ; Load new ASID and TTBR + LDR r1, =_txm_ttbr1_page_table ; Load master TTBR + ORR r1, r1, #0x48 ; OR it with #TTBR0_ATTRIBUTES + MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to master + ISB + DSB + MCR p15, 0, r2, c13, c0, 1 ; Change ASID to new value + ISB + ; Change TTBR to new value + MOV r3, #14 + ADD r1, r1, r2, LSL r3 + MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to new value + + ; refresh TLB + MOV r2, #0 + DSB + MCR p15, 0, r2, c8, c7, 0 ; Invalidate entire unified TLB + MCR p15, 0, r2, c7, c5, 0 ; Invalidate all instruction caches to PoU + MCR p15, 0, r2, c7, c5, 6 ; Invalidate branch predictor + DSB + ISB + + ;test address translation + ;mcr p15, 0, r0, c7, c8, 0 + +_tx_skip_mmu_update + ; ************************************************************************** + + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + + MSR SPSR_cxsf, r5 ; Setup SPSR for return + LDR r1, [r0, #8] ; Get thread SP + LDR lr, [r1, #0x40] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR + CPS #SVC_MODE ; Enter SVC mode + LDR lr, [r1, #0x144] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode +_tx_skip_interrupt_vfp_restore +#endif + + LDMIA sp!, {r0-r12, lr} ; Restore registers + ADD sp, sp, #4 ; Fix stack pointer + CPS #SVC_MODE ; Enter SVC mode + SUBS pc, lr, #0 ; Return to point of thread interrupt + +_tx_solicited_return + MOV r2, r5 ; Move CPSR to scratch register + CPS #SYS_MODE ; Enter SYS mode + +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore +#endif + + LDMIA sp!, {r4-r11, lr} ; Restore registers + MOV r1, lr ; Copy lr to r1 to preserve across mode change + CPS #SVC_MODE ; Enter SVC mode + MSR SPSR_cxsf, r2 ; Recover CPSR + SUBS pc, r1, #0 ; Return to thread synchronously + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; End SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + ARM +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + ARM +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..dcde4147 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,153 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif + +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + ARM +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SYS_MODE ; Build CPSR, SYS mode, interrupts enabled + BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb bit set? + ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller + + +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..b52a15b1 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,148 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_thread_exit +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + ARM +_tx_thread_system_return + +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save +#endif + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..202ab5d4 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -0,0 +1,173 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + ARM +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + BX lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + BX lr ; Return to caller + +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + BX lr ; Return to caller + +; } +;} + + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..29e1c9be --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,245 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + ARM +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + BX lr ; Return to caller +; +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..cdbfc2c7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; + + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + local_data_size = *data_size; + local_data_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + + /* Return all the information to the caller. */ + *code_size = ((local_code_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *code_alignment = local_code_alignment; + *data_size = ((local_data_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..1fa2f9db --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,483 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +/* External page tables. */ +extern ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_get Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets an available L2 page table and places it in the */ +/* module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* page_addr Address of L2 page */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_external_memory_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) +{ + +UINT i; +UINT status; +UINT table_index; +UINT pool_index; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Find first free table slot in module control block. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i] == TX_NULL) + { + table_index = i; + break; + } + } + + if(i >= TXM_MODULE_LEVEL2_EXTERNAL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + + else + { + /* Find first free table in pool. */ + for(i = 0; i < TXM_LEVEL2_EXTERNAL_POOL_PAGES; i++) + { + if(_txm_level2_external_page_pool[i][0] == (ULONG) TX_NULL) + { + pool_index = i; + break; + } + } + + if(i >= TXM_LEVEL2_EXTERNAL_POOL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + } + + + if(status == TX_SUCCESS) + { + /* Place page address in table slot. Return page address. */ + module_instance->txm_external_page_table[table_index] = _txm_level2_external_page_pool[pool_index]; + *page_addr = (ULONG)_txm_level2_external_page_pool[pool_index]; + } + + return(status); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_clear Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function clears the first entry in a L2 page table and clears */ +/* the table entry from the module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i; + + /* Clear table slots and zero out L2 entry. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i]) + { + *(ULONG *)module_instance->txm_external_page_table[i] = (ULONG)TX_NULL; + module_instance->txm_external_page_table[i] = TX_NULL; + } + } +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MMU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* TX_MEMSET Fill memory with constant */ +/* _txm_level2_page_get Get L2 page table */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable( TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG start_addr = (ULONG) start_address; +ULONG end_addr; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_addr; +ULONG page_addr; +ULONG asid; +ULONG level1_attributes; +ULONG level2_attributes; +UINT status; +UINT i; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if the module instance is memory protected. */ + if (module_instance -> txm_module_instance_asid == 0) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not protected. */ + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Start address must be aligned to MMU block size (4 kB). + Length will be rounded up to 4 kB alignment. */ + if(start_addr & ~TXM_MMU_LEVEL2_MASK) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /**************************************************************************/ + /* At this point, we have a valid address. Set up MMU. */ + /**************************************************************************/ + + /* Round length up to 4 kB alignment. */ + if(length & ~TXM_MMU_LEVEL2_MASK) + { + length = ((length + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + } + + /* Get end address. */ + end_addr = start_addr + length - 1; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_addr++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Get module ASID. */ + asid = module_instance -> txm_module_instance_asid; + + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* Build L2 attributes. */ + level2_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* If start_addr is not aligned, we need a L2 page. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][level1_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_addr = ((start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_addr - start_addr) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + ((ULONG *) page_addr)[level2_index] = (start_addr & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_addr & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][temp_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + ((ULONG *) page_addr)[i] = (end_addr & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Build L1 attributes. */ + level1_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE; + + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | level1_attributes; + } + + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..d63dedf0 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..7cbd22fc --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c new file mode 100644 index 00000000..18b20506 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c @@ -0,0 +1,304 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +#define CACHE_DISABLED 0x12 +#define SDRAM_START 0x00000000 +#define SDRAM_END 0x1fffffff +#define CACHE_WRITEBACK 0x1e + +#define SECTION_DESCRIPTOR 0x00000002 +#define DACR_CLIENT_MODE 0x55555555 + + +/*** Page table attributes TTBR0 *********************************************** +* IRGN = 01 - Normal memory, Inner Write-Back Write-Allocate Cacheable +* S - non-shareable +* RGN = 01 - Normal memory, Outer Write-Back Write-Allocate Cacheable +* NOS - outer-shareable +*******************************************************************************/ +#define TTBR0_ATTRIBUTES 0x48 + + + +/* ASID table, index is ASID number and contents hold pointer to module. */ +TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; + +/* Master page table, 2^14 (16kB) alignment. + * First table is the master level 1 table, the rest are for each module. */ +#pragma data_alignment=16384 +ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + +/* Module start and end level 2 page tables, 2^10 (1kB) alignment. + * First set of 4 tables are the master level 2 tables, the rest are for each module. + * Each module needs two L2 tables for code and two L2 tables for data. */ +#pragma data_alignment=1024 +ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ +#pragma data_alignment=1024 +ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_mm_initialize(VOID) +{ + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + UINT i; + ULONG cp15reg; + UINT user_mode_index; + UINT counter_limit; + + /* Clear ASID table. */ + for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) + { + _txm_asid_table[i] = 0; + } + _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; + + + /********************************************************************************/ + /* This is an example showing how to set up the cache attributes. */ + /********************************************************************************/ + +/******************************************************************************* +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| +* |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| +* +* Bits[31:20] - Top 12 bits of VA is pointer into table +* nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +* S[16]=0 - Indicates normal memory is shared when set. +* AP2[15]=0 +* TEX[14:12]=000 +* AP[11:10]=11 - Configure for full read/write access in all modes +* IMPP[9]=0 - Ignored +* Domain[5:8]=1111 - Set all pages to use domain 15 +* XN[4]=0 - Execute never disabled +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section +*******************************************************************************/ + +/* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ +/* setting for Strongly-ordered memory + B-00000000000000000000010111100010 */ +#define TTB_PARA_STRGLY 0x05E2 + +/* setting for Outer and inner not cache normal memory + B-00000000000000000001010111100010 */ +#define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 + +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) + B-00000000000000000001010111101110 */ +#define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE + +/* In this chip (RZA1) there are the following 12 sections with the defined memory size (MB) */ +#define M_SIZE_NOR 128 /* [Area00] CS0, CS1 area (for NOR flash) */ +#define M_SIZE_SDRAM 128 /* [Area01] CS2, CS3 area (for SDRAM) */ +#define M_SIZE_CS45 128 /* [Area02] CS4, CS5 area */ +#define M_SIZE_SPI 128 /* [Area03] SPI, SP2 area (for Serial flash) */ +#define M_SIZE_RAM 10 /* [Area04] Internal RAM */ +#define M_SIZE_IO_1 502 /* [Area05] I/O area 1 */ +#define M_SIZE_NOR_M 128 /* [Area06] CS0, CS1 area (for NOR flash) (mirror) */ +#define M_SIZE_SDRAM_M 128 /* [Area07] CS2, CS3 area (for SDRAM) (mirror) */ +#define M_SIZE_CS45_M 128 /* [Area08] CS4, CS5 area (mirror) */ +#define M_SIZE_SPI_M 128 /* [Area09] SPI, SP2 area (for Serial flash) (mirror) */ +#define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ +#define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ +/* Should add to: 4096 */ + + counter_limit = M_SIZE_NOR; + for (i = 0; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_SDRAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_CS45; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_RAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_IO_1; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_NOR_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_SDRAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_CS45_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_RAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_IO_2; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + /********************************************************************************/ + /* This is the end of the example showing how to set up the cache attributes. */ + /********************************************************************************/ + + + /* Clear ASID. */ + cp15reg = 0; + asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); + asm("isb"); + + /* Put the page table address in TTBR. */ + cp15reg = (int)(VOID*)_txm_ttbr1_page_table; + cp15reg |= TTBR0_ATTRIBUTES; + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); + + /* Set the domain to client mode. */ + cp15reg = DACR_CLIENT_MODE; + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); + + +/* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ +#define TTB_LEVEL2_NORMAL_CACHE 0x05E + +/* Level 2 clear AP attributes mask. */ +#define TTB_LEVEL2_AP_CLEAR_MASK 0xFFFFFFCF + +/* Attributes for user mode table entry in level 2 table. */ +#define TTB_LEVEL2_USER_MODE_ENTRY 0x06E + + /* Set up Level 2 table for user to kernel mode entry trampoline. */ + /* Find which table entry _txm_module_manager_user_mode_entry is in. */ + user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; + /* Fill table. */ + for (i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; + } + + /* Enter Level 2 table in to master table. */ + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ + user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + + /* Set attribute bits for the user mode entry page. */ + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; + + /* Enable the MMU. */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); + cp15reg |= 0x1; + asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); + + return(TX_SUCCESS); + +#else + return(TX_FEATURE_NOT_ENABLED); +#endif +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..2dd195bf --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,589 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +extern TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; +extern ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function determines if pointer is within the module's data or */ +/* shared memory. */ +/* */ +/* INPUT */ +/* */ +/* pointer Data pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(ULONG pointer) +{ + +ULONG translation; + + /* ATS1CUR operation on address supplied in pointer, Stage 1 unprivileged read. */ + asm("MCR p15, 0, %0, c7, c8, 2" : : "r"(pointer) : ); + asm("ISB"); /* Ensure completion of the MCR write to CP15. */ + asm("MRC p15, 0, %0, c7, c4, 0" : "=r"(translation) : : ); /* Read result from 32-bit PAR into translation. */ + + if (translation & TXM_ADDRESS_TRANSLATION_FAULT_BIT) + { + return(TX_FALSE); + } + + return(TX_TRUE); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_assign_asid Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function assigns an Application Specific ID (ASID) to a */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_assign_asid(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i = 1; + + /* Find first non-zero ASID, starting at index 1. */ + while(i < TXM_ASID_TABLE_LENGTH) + { + if(_txm_asid_table[i] != 0) + { + i++; + } + else + { + module_instance -> txm_module_instance_asid = i; + _txm_asid_table[i] = module_instance; + return(TX_SUCCESS); + } + } + + return(TXM_MODULE_ASID_ERROR); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_remove_asid Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes a module from the ASID list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance) +{ + if(module_instance -> txm_module_instance_asid) + { + _txm_asid_table[module_instance -> txm_module_instance_asid] = 0; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-A7/MMU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-A7 MMU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_assign_asid */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_SETUP */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + +ULONG start_address; +ULONG end_address; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_address; +ULONG l2_address; +ULONG attributes = 0; +ULONG asid; +UINT i; + + + /* Assign an ASID to this module. */ + _txm_module_manager_assign_asid(module_instance); + + asid = module_instance -> txm_module_instance_asid; + + /* Copy master level 1 page table to module's page table. */ + for(i = 0; i < TXM_MASTER_PAGE_TABLE_ENTRIES; i++) + { + _txm_ttbr1_page_table[asid][i] = _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i]; + } + + /* Clear level 2 tables. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = 0; + } + + /* Get code start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_code_start; + /* Extend end address to end of page (TXM_MODULE_MEMORY_ALIGNMENT-1). */ + end_address = ((((ULONG)module_instance -> txm_module_instance_code_end) + TXM_MODULE_MEMORY_ALIGNMENT-1) & ~((ULONG)TXM_MODULE_MEMORY_ALIGNMENT-1)) - 1; + + /* How many level 1 table entries does code span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does code need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module code range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_CODE_ATTRIBUTES; + } + + /**************************************************************************/ + /* At this point, code protection is set up. */ + /* Data protection is set up below. */ + /**************************************************************************/ + + /* Get data start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_data_start; + end_address = (ULONG)module_instance -> txm_module_instance_data_end; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_DATA_ATTRIBUTES; + } + +#endif +} diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..46ff4ec7 --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,151 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + +; +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR +USR_MODE EQU 0x10 ; USR mode +SYS_MODE EQU 0x1F ; SYS mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _txm_module_manager_thread_stack_build + ARM +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; r0 Initial value for r0 +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r12 Initial value for r12 +; lr Initial value for lr (r14) +; pc Initial value for pc (r15) +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + STR r0, [r2, #8] ; Store initial r0 (thread pointer) + LDR r3, [r0, #8] ; Pickup thread info pointer (it's in the stack pointer location right now) + STR r3, [r2, #12] ; Store initial r1 + LDR r3, [r3, #8] ; Pickup data base register + STR r3, [r2, #44] ; Store initial r9 + MOV r3, #0 ; Build initial register value + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + TST r1, #1 ; Test if THUMB bit set in initial PC + ORRNE r3, r3, #THUMB_MASK ; Set T bit if set + LDR r1, [r0, #156] ; Load tx_thread_module_current_user_mode + TST r1, #1 ; Test if the flag is set + ORREQ r3, r3, #SYS_MODE ; Flag not set: Build CPSR, SYS mode, IRQ enabled + ORRNE r3, r3, #USR_MODE ; Flag set: Build CPSR, USR mode, IRQ enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s new file mode 100644 index 00000000..501c79bb --- /dev/null +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -0,0 +1,96 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_kernel_dispatch + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* tx Cortex-A7/MMU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + RSEG .text:CODE:NOROOT(2) + PUBLIC _txm_module_manager_user_mode_entry + ARM +_txm_module_manager_user_mode_entry + + PUBLIC _txm_system_mode_enter + ARM +_txm_system_mode_enter + SVC 1 ; Get out of user mode +_txm_module_priv + ; At this point, we are in system mode. + ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function. + PUSH {r3, lr} + BL _txm_module_manager_kernel_dispatch + POP {r3, lr} + + PUBLIC _txm_system_mode_exit + ARM +_txm_system_mode_exit + ; Trap to restore user mode while inside of ThreadX + SVC 2 + + BX lr ; Return to the caller + NOP + NOP + + ; Fill up 4kB page. + SECTION page_align:CONST:ROOT(2) + +_txm_module_manager_user_mode_end + + END diff --git a/ports_module/cortex_m0+/ac6/inc/tx_port.h b/ports_module/cortex_m0+/ac6/inc/tx_port.h index 200367a3..7ff0e3c0 100644 --- a/ports_module/cortex_m0+/ac6/inc/tx_port.h +++ b/ports_module/cortex_m0+/ac6/inc/tx_port.h @@ -518,7 +518,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0+/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0+/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h index 155880c7..3f3665d9 100644 --- a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h @@ -376,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M0+/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M0+/AC6 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m0+/gnu/inc/tx_port.h b/ports_module/cortex_m0+/gnu/inc/tx_port.h index 286fb913..ff946eed 100644 --- a/ports_module/cortex_m0+/gnu/inc/tx_port.h +++ b/ports_module/cortex_m0+/gnu/inc/tx_port.h @@ -532,7 +532,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0+/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0+/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h index 54956a1e..14321057 100644 --- a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h @@ -376,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M0+/GNU Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M0+/GNU Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m0+/iar/inc/tx_port.h b/ports_module/cortex_m0+/iar/inc/tx_port.h index 41f06ec5..2f362165 100644 --- a/ports_module/cortex_m0+/iar/inc/tx_port.h +++ b/ports_module/cortex_m0+/iar/inc/tx_port.h @@ -568,7 +568,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0+/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0+/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m0+/iar/inc/txm_module_port.h b/ports_module/cortex_m0+/iar/inc/txm_module_port.h index 51253ef0..a000557d 100644 --- a/ports_module/cortex_m0+/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/iar/inc/txm_module_port.h @@ -376,6 +376,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M0+/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M0+/IAR Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index ae6e2c50..aadb0e2f 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -577,7 +577,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/ac6/inc/txm_module_port.h b/ports_module/cortex_m23/ac6/inc/txm_module_port.h index 72bc525b..e72c9d4e 100644 --- a/ports_module/cortex_m23/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m23/ac6/inc/txm_module_port.h @@ -357,6 +357,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h index 330d08e2..03673ae9 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_port.h +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -488,7 +488,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/gnu/inc/txm_module_port.h b/ports_module/cortex_m23/gnu/inc/txm_module_port.h index 9017e38a..e25ab9f5 100644 --- a/ports_module/cortex_m23/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m23/gnu/inc/txm_module_port.h @@ -347,6 +347,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h index 36016ea5..ecde4de8 100644 --- a/ports_module/cortex_m23/iar/inc/tx_port.h +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -708,7 +708,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/iar/inc/txm_module_port.h b/ports_module/cortex_m23/iar/inc/txm_module_port.h index 088efd4b..6c4534dc 100644 --- a/ports_module/cortex_m23/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m23/iar/inc/txm_module_port.h @@ -350,6 +350,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m3/ac5/inc/tx_port.h b/ports_module/cortex_m3/ac5/inc/tx_port.h index 79177b2b..e3a738a9 100644 --- a/ports_module/cortex_m3/ac5/inc/tx_port.h +++ b/ports_module/cortex_m3/ac5/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac5/inc/txm_module_port.h b/ports_module/cortex_m3/ac5/inc/txm_module_port.h index ba34ddc8..a306699a 100644 --- a/ports_module/cortex_m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac5/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/AC5 */ -/* 6.2.0 */ +/* txm_module_port.h Cortex-M3 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,11 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ /* 10-31-2022 Scott Larson Configure heap size, */ /* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -67,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -80,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -122,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -140,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -225,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -250,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -440,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index cb13e4a6..132fa40b 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 4a00404f..f10f77bd 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m3/ac6/inc/tx_port.h b/ports_module/cortex_m3/ac6/inc/tx_port.h index 79177b2b..e3a738a9 100644 --- a/ports_module/cortex_m3/ac6/inc/tx_port.h +++ b/ports_module/cortex_m3/ac6/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 235aca2c..a306699a 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/AC6 */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M3 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -47,6 +47,12 @@ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -68,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -81,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -123,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -141,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -226,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -251,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -441,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S index 9dbe0204..6240faef 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S index 5061b512..4238df92 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -31,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S index 1f6a3f11..fb6a0379 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S index 93159485..aa3c2f06 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S index c060ec5f..40d707d9 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S index 70aec7a7..17d50ac2 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S index 3a24f007..a83abf4f 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M3/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S index 1e61de61..9059d0d0 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M3/AC6 */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index cb13e4a6..132fa40b 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 4a00404f..f10f77bd 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S index e2df9b29..590991a6 100644 --- a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m3/gnu/inc/tx_port.h b/ports_module/cortex_m3/gnu/inc/tx_port.h index 79177b2b..e3a738a9 100644 --- a/ports_module/cortex_m3/gnu/inc/tx_port.h +++ b/ports_module/cortex_m3/gnu/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h index c77eb2f0..a306699a 100644 --- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/GNU */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M3 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,9 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -65,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -78,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -94,6 +120,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ +/* Users can define the module heap size. */ +#ifndef TXM_MODULE_HEAP_SIZE +#define TXM_MODULE_HEAP_SIZE 512 +#endif + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -115,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -133,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -218,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for GNU compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -243,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -433,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S index 4b62c21c..efcde926 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S index 13283881..156a8523 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S index 309053a8..eecce756 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S index 7da1fe8a..e35aaf65 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S index 136b56b7..f45801f8 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S index e6a1da3f..fd0718f4 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S index 8a1f4a29..e0fa4951 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M3/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S index 5c3d6a2e..99cab68b 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M3/GNU */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index cb13e4a6..132fa40b 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 4a00404f..f10f77bd 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m3/iar/inc/tx_port.h b/ports_module/cortex_m3/iar/inc/tx_port.h index 79177b2b..e3a738a9 100644 --- a/ports_module/cortex_m3/iar/inc/tx_port.h +++ b/ports_module/cortex_m3/iar/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/iar/inc/txm_module_port.h b/ports_module/cortex_m3/iar/inc/txm_module_port.h index 5c8aa17e..a306699a 100644 --- a/ports_module/cortex_m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m3/iar/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M3/IAR */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M3 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,9 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -65,6 +74,7 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -79,6 +89,21 @@ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; \ VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -95,6 +120,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ +/* Users can define the module heap size. */ +#ifndef TXM_MODULE_HEAP_SIZE +#define TXM_MODULE_HEAP_SIZE 512 +#endif + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -116,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -134,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -219,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for IAR compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -244,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -434,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c index cb13e4a6..132fa40b 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 4a00404f..f10f77bd 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M3 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index 0b44956c..1291399b 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -706,7 +706,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/inc/txm_module_port.h b/ports_module/cortex_m33/ac6/inc/txm_module_port.h index b3b114b1..af48abb0 100644 --- a/ports_module/cortex_m33/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m33/ac6/inc/txm_module_port.h @@ -357,6 +357,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/AC6 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index 2a6e81f2..bccc6322 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -77,8 +77,8 @@ /* resulting in version 6.1.12 */ /* 10-31-2022 Scott Larson Added low power support, */ /* resulting in version 6.2.0 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index 0b44956c..1291399b 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -706,7 +706,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/gnu/inc/txm_module_port.h b/ports_module/cortex_m33/gnu/inc/txm_module_port.h index 1c49473b..66686daf 100644 --- a/ports_module/cortex_m33/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m33/gnu/inc/txm_module_port.h @@ -351,6 +351,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/GNU Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/GNU Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index 0b44956c..1291399b 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -706,7 +706,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/iar/inc/txm_module_port.h b/ports_module/cortex_m33/iar/inc/txm_module_port.h index 2f0f9a6b..c5a93a45 100644 --- a/ports_module/cortex_m33/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m33/iar/inc/txm_module_port.h @@ -352,6 +352,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M33/IAR Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index 38cc3302..e5067e16 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/IAR */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -89,8 +89,8 @@ /* resulting in version 6.1.12 */ /* 10-31-2022 Scott Larson Added low power support, */ /* resulting in version 6.2.0 */ -/* xx-xx-xxxx Scott Larson Added preproc FPU option, */ -/* resulting in version 6.x */ +/* 03-08-2023 Scott Larson Added preproc FPU option, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports_module/cortex_m4/ac5/inc/tx_port.h b/ports_module/cortex_m4/ac5/inc/tx_port.h index 73cb0069..65b98d36 100644 --- a/ports_module/cortex_m4/ac5/inc/tx_port.h +++ b/ports_module/cortex_m4/ac5/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index bddabbe3..66a426f9 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/AC5 */ -/* 6.2.0 */ +/* txm_module_port.h Cortex-M4 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,11 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ /* 10-31-2022 Scott Larson Configure heap size, */ /* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -67,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -80,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -122,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -140,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -225,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -250,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -440,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 79af7655..71fe4041 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 36127034..4c1ed15f 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m4/ac6/inc/tx_port.h b/ports_module/cortex_m4/ac6/inc/tx_port.h index 73cb0069..65b98d36 100644 --- a/ports_module/cortex_m4/ac6/inc/tx_port.h +++ b/ports_module/cortex_m4/ac6/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac6/inc/txm_module_port.h b/ports_module/cortex_m4/ac6/inc/txm_module_port.h index 27488cda..66a426f9 100644 --- a/ports_module/cortex_m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac6/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/AC6 */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M4 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -47,6 +47,12 @@ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -68,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -81,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -123,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -141,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -226,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -251,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -441,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S index 6e1fe7cf..b28d5cf0 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S index 15ad1292..df3406fc 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -31,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S index b79a59c1..83fa1216 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S index 2adec1d8..d7c8208f 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S index a920cdbf..0541495b 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S index 5e4eddb2..a55ed875 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S index a8b6dc97..237dd5e0 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M4/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S index 9385e1cb..9f22f66b 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M4/AC6 */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 79af7655..71fe4041 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 36127034..4c1ed15f 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S index a9413251..41ea3d71 100644 --- a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m4/gnu/inc/tx_port.h b/ports_module/cortex_m4/gnu/inc/tx_port.h index 73cb0069..65b98d36 100644 --- a/ports_module/cortex_m4/gnu/inc/tx_port.h +++ b/ports_module/cortex_m4/gnu/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/gnu/inc/txm_module_port.h b/ports_module/cortex_m4/gnu/inc/txm_module_port.h index 3cb14d4f..66a426f9 100644 --- a/ports_module/cortex_m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m4/gnu/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/GNU */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M4 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,9 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -65,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -78,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -94,6 +120,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ +/* Users can define the module heap size. */ +#ifndef TXM_MODULE_HEAP_SIZE +#define TXM_MODULE_HEAP_SIZE 512 +#endif + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -115,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -133,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -218,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for GNU compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -243,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -433,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S index 852d8302..3fc8ed13 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S index 1c8a2ebf..d5ee5323 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S index 30960b56..14fdc57d 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S index d2945f08..e10c91b5 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S index a2efd882..5f6198d5 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S index 536d815b..32ae964b 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S index 3783ccd7..6bddf428 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M4/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S index 043921be..1343fce5 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M4/GNU */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 79af7655..71fe4041 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 36127034..4c1ed15f 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m4/iar/inc/tx_port.h b/ports_module/cortex_m4/iar/inc/tx_port.h index 73cb0069..65b98d36 100644 --- a/ports_module/cortex_m4/iar/inc/tx_port.h +++ b/ports_module/cortex_m4/iar/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/iar/inc/txm_module_port.h b/ports_module/cortex_m4/iar/inc/txm_module_port.h index e92cfc0f..66a426f9 100644 --- a/ports_module/cortex_m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m4/iar/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M4/IAR */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M4 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,9 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -65,6 +74,7 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -79,6 +89,21 @@ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; \ VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -95,6 +120,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ +/* Users can define the module heap size. */ +#ifndef TXM_MODULE_HEAP_SIZE +#define TXM_MODULE_HEAP_SIZE 512 +#endif + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -116,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -134,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -219,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for IAR compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -244,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -434,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 79af7655..71fe4041 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 36127034..4c1ed15f 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M4 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m7/ac5/inc/tx_port.h b/ports_module/cortex_m7/ac5/inc/tx_port.h index 1b6fa4fb..e736707e 100644 --- a/ports_module/cortex_m7/ac5/inc/tx_port.h +++ b/ports_module/cortex_m7/ac5/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac5/inc/txm_module_port.h b/ports_module/cortex_m7/ac5/inc/txm_module_port.h index ae4bdf24..d0b1f693 100644 --- a/ports_module/cortex_m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac5/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/AC5 */ -/* 6.2.0 */ +/* txm_module_port.h Cortex-M7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,11 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ /* 10-31-2022 Scott Larson Configure heap size, */ /* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -67,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -80,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -122,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -140,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -225,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -250,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -440,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 138a4463..41617a60 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 55369436..1a1fe747 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h index 1b6fa4fb..e736707e 100644 --- a/ports_module/cortex_m7/ac6/inc/tx_port.h +++ b/ports_module/cortex_m7/ac6/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac6/inc/txm_module_port.h b/ports_module/cortex_m7/ac6/inc/txm_module_port.h index e1cce9ca..d0b1f693 100644 --- a/ports_module/cortex_m7/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac6/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/AC6 */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -47,6 +47,12 @@ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -68,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -81,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -123,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -141,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -226,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -251,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -441,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC6 Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S index 341e8a16..d68f5340 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S index 62d8b329..4aa6d7d9 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -31,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S index 0843f69e..88299092 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S index 3f36a36a..5225ad5c 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S index 924fa21d..6f3f3f67 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S index 52c2c207..3b8cca0e 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S index c1b3b9e8..97d20aaa 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M7/AC6 */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S index bde18d04..84f73e25 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M7/AC6 */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 138a4463..41617a60 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 55369436..1a1fe747 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S index a9413251..41ea3d71 100644 --- a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m7/gnu/inc/tx_port.h b/ports_module/cortex_m7/gnu/inc/tx_port.h index 1b6fa4fb..e736707e 100644 --- a/ports_module/cortex_m7/gnu/inc/tx_port.h +++ b/ports_module/cortex_m7/gnu/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/gnu/inc/txm_module_port.h b/ports_module/cortex_m7/gnu/inc/txm_module_port.h index ba3b3ec0..d0b1f693 100644 --- a/ports_module/cortex_m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m7/gnu/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/GNU */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,9 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -65,6 +74,22 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -78,6 +103,7 @@ VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -94,6 +120,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ +/* Users can define the module heap size. */ +#ifndef TXM_MODULE_HEAP_SIZE +#define TXM_MODULE_HEAP_SIZE 512 +#endif + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -115,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -133,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -218,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for GNU compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -243,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -433,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/GNU Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S index 888d5442..9f091168 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @@ -32,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S index 6111ffee..be97f725 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S index 2ea849dc..9c9c9552 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S index 16935d55..2904b56e 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S index 27f8c5bd..a6a6ab9b 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S index 7c2cb83a..b55b9afd 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S index 307af29e..e71dfd73 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .text 32 .align 4 .syntax unified @@ -28,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M7/GNU */ -/* 6.1.7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S index d0fc6929..853f09e6 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S @@ -20,6 +20,8 @@ /**************************************************************************/ /**************************************************************************/ +#include "tx_user.h" + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -38,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M7/GNU */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +77,8 @@ /* 01-31-2022 Scott Larson Modified comment(s), added */ /* TX_NO_TIMER support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Scott Larson Include tx_user.h, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 138a4463..41617a60 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 55369436..1a1fe747 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h index 1b6fa4fb..e736707e 100644 --- a/ports_module/cortex_m7/iar/inc/tx_port.h +++ b/ports_module/cortex_m7/iar/inc/tx_port.h @@ -720,7 +720,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7 Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/iar/inc/txm_module_port.h b/ports_module/cortex_m7/iar/inc/txm_module_port.h index 32103d56..d0b1f693 100644 --- a/ports_module/cortex_m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m7/iar/inc/txm_module_port.h @@ -25,8 +25,8 @@ /* */ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ -/* txm_module_port.h Cortex-M7/IAR */ -/* 6.1.12 */ +/* txm_module_port.h Cortex-M7 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,9 +41,18 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 01-31-2022 Scott Larson Modified comments and made */ +/* heap user-configurable, */ +/* resulting in version 6.1.10 */ /* 07-29-2022 Scott Larson Enabled user-defined and */ /* default MPU settings, */ /* resulting in version 6.1.12 */ +/* 10-31-2022 Scott Larson Configure heap size, */ +/* resulting in version 6.2.0 */ +/* 03-08-2023 Scott Larson Set default values for RBAR, */ +/* unify this file for all */ +/* compilers, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ @@ -65,6 +74,7 @@ following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -79,6 +89,21 @@ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; \ VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif The following extensions must also be defined in tx_port.h: @@ -95,6 +120,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ +/* Users can define the module heap size. */ +#ifndef TXM_MODULE_HEAP_SIZE +#define TXM_MODULE_HEAP_SIZE 512 +#endif + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -116,14 +146,15 @@ The following extensions must also be defined in tx_port.h: #endif /* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) - are not used by ThreadX. These may be defined by the user. */ -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 + are not used by ThreadX. These may be defined by the user. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0x1C #define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0x1D #define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0x1E #define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 -#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0x1F #define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 @@ -134,38 +165,39 @@ The following extensions must also be defined in tx_port.h: and the defines below are not used. If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the - below values when a thread that is not owned by a module is running. */ -#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 + below values when a thread that is not owned by a module is running. + RBAR needs the valid bit and region number set, as MPU alias registers are used. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0x10 #define TXM_MODULE_MPU_DEFAULT_RASR_0 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0x11 #define TXM_MODULE_MPU_DEFAULT_RASR_1 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0x12 #define TXM_MODULE_MPU_DEFAULT_RASR_2 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0x13 #define TXM_MODULE_MPU_DEFAULT_RASR_3 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0x14 #define TXM_MODULE_MPU_DEFAULT_RASR_4 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0x15 #define TXM_MODULE_MPU_DEFAULT_RASR_5 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0x16 #define TXM_MODULE_MPU_DEFAULT_RASR_6 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0x17 #define TXM_MODULE_MPU_DEFAULT_RASR_7 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0x18 #define TXM_MODULE_MPU_DEFAULT_RASR_8 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0x19 #define TXM_MODULE_MPU_DEFAULT_RASR_9 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0x1A #define TXM_MODULE_MPU_DEFAULT_RASR_10 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0x1B #define TXM_MODULE_MPU_DEFAULT_RASR_11 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0x1C #define TXM_MODULE_MPU_DEFAULT_RASR_12 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0x1D #define TXM_MODULE_MPU_DEFAULT_RASR_13 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0x1E #define TXM_MODULE_MPU_DEFAULT_RASR_14 0 -#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0x1F #define TXM_MODULE_MPU_DEFAULT_RASR_15 0 @@ -219,24 +251,16 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for IAR compiler. */ - +/* Define INLINE_DECLARE to inline for this compiler. */ #define INLINE_DECLARE inline -#ifdef TXM_MODULE_MANAGER_16_MPU +#define TXM_MPU_VALID_BIT 0x10 +#define TXM_ENABLE_REGION 0x01 +#define TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX 0 -/* Define the number of MPU entries assigned to the code and data sections. - On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access - to the kernel entry function, thus 15 remain for code and data protection. */ -#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 -#define TXM_MODULE_MPU_CODE_ENTRIES 4 -#define TXM_MODULE_MPU_DATA_ENTRIES 4 -#define TXM_MODULE_MPU_SHARED_ENTRIES 3 - -#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 -#define TXM_MODULE_MPU_SHARED_INDEX 9 - -#define TXM_ENABLE_REGION 0x01 +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 /* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ typedef struct TXM_MODULE_MPU_INFO_STRUCT @@ -244,44 +268,50 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT ULONG txm_module_mpu_region_address; ULONG txm_module_mpu_region_attribute_size; } TXM_MODULE_MPU_INFO; -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + + +#ifdef TXM_MODULE_MANAGER_16_MPU + +/* Define the number of MPU entries assigned to the code and data sections. + On some Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MANAGER_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES 3 +#define TXM_MODULE_MANAGER_MPU_SHARED_INDEX 9 +#define TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX 12 + /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_count; \ - ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ - ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES]; #else /* TXM_MODULE_MANAGER_16_MPU is not defined */ /* Define the number of MPU entries assigned to the code and data sections. On Cortex-M3, M4, and some M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ -#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 -#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 -#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 -#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 - -/* Shared memory region attributes. */ -#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 -#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 +#define TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 /* Define the port-extensions to the module manager instance structure. */ -#define TXM_MODULE_MANAGER_PORT_EXTENSION \ - ULONG txm_module_instance_mpu_registers[16]; \ - ULONG txm_module_instance_shared_memory_address; \ - ULONG txm_module_instance_shared_memory_length; +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; #endif /* TXM_MODULE_MANAGER_16_MPU */ + /* Define the memory fault information structure that is populated when a memory fault occurs. */ - - typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; @@ -434,6 +464,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/IAR Version 6.1.12 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7 Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 138a4463..41617a60 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_external_memory_enable Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Update defines, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, @@ -125,7 +127,7 @@ ULONG attributes_check = 0; } /* Determine if there are shared memory entries available. */ - if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -152,19 +154,19 @@ ULONG attributes_check = 0; Set up MPU registers. */ /* Pick up index into shared memory entries. */ - shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; /* Save address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); /* Generate SRD, size, and enable attributes. */ - size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) @@ -262,10 +264,10 @@ TXM_MODULE_PREAMBLE *module_preamble; /* At this point, we have a valid address and block size. Set up MPU registers. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; /* Calculate the region size. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); + region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); @@ -276,7 +278,7 @@ TXM_MODULE_PREAMBLE *module_preamble; } /* Build register with attributes. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 55369436..1a1fe747 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -68,7 +68,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_region_size_get Cortex-M7 */ -/* 6.1.9 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,6 +81,7 @@ const ULONG txm_module_default_mpu_registers[32] = /* INPUT */ /* */ /* block_size Size of the block in bytes */ +/* Must be a power of two */ /* */ /* OUTPUT */ /* */ @@ -99,86 +100,32 @@ const ULONG txm_module_default_mpu_registers[32] = /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 03-08-2023 Scott Larson Changed from lookup table to */ +/* calculation and check for */ +/* minumum block size, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { -ULONG return_value; +ULONG return_value = 5; /* 5 is the region size for 64 byte block. */ - /* Process relative to the input block size. */ - if (block_size == 32) + /* Check if at or below minumum block size. */ + if (block_size <= 32) { - return_value = 0x04; + /* Return minimum region size. */ + return 0x04; } - else if (block_size == 64) + + /* Remove some trailing zeros from block_size. */ + block_size = block_size >> 6; + + /* Increment return_value until block_size lsb is set. */ + while((block_size & 1) == 0) { - return_value = 0x05; - } - else if (block_size == 128) - { - return_value = 0x06; - } - else if (block_size == 256) - { - return_value = 0x07; - } - else if (block_size == 512) - { - return_value = 0x08; - } - else if (block_size == 1024) - { - return_value = 0x09; - } - else if (block_size == 2048) - { - return_value = 0x0A; - } - else if (block_size == 4096) - { - return_value = 0x0B; - } - else if (block_size == 8192) - { - return_value = 0x0C; - } - else if (block_size == 16384) - { - return_value = 0x0D; - } - else if (block_size == 32768) - { - return_value = 0x0E; - } - else if (block_size == 65536) - { - return_value = 0x0F; - } - else if (block_size == 131072) - { - return_value = 0x10; - } - else if (block_size == 262144) - { - return_value = 0x11; - } - else if (block_size == 524288) - { - return_value = 0x12; - } - else if (block_size == 1048576) - { - return_value = 0x13; - } - else if (block_size == 2097152) - { - return_value = 0x14; - } - else - { - /* Max 4MB MPU pages for modules. */ - return_value = 0x15; + block_size = block_size >> 1; + return_value++; } return(return_value); @@ -235,10 +182,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -250,7 +197,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -258,7 +205,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -268,7 +215,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.12 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -284,7 +231,7 @@ UINT srd_bit_index; /* 1 Module code region */ /* 2 Module code region */ /* 3 Module code region */ -/* 4 Module code region */ +/* 4 Module code region [optional shared memory region] */ /* 5 Module data region */ /* 6 Module data region */ /* 7 Module data region */ @@ -333,6 +280,10 @@ UINT srd_bit_index; /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ /* 07-29-2022 Scott Larson Enable user defined regions, */ /* resulting in version 6.1.12 */ +/* 03-08-2023 Scott Larson Initialize unused MPU region, */ +/* fix MPU settings for region */ +/* size less than 32 bytes, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -348,27 +299,24 @@ ULONG callback_stack_size; ULONG block_size; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; /* Setup the first MPU region for kernel mode entry. */ /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; - /* Set the attributes, size (32 bytes) and enable bit. */ - module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - - /* Initialize the MPU table index. */ - mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -376,67 +324,100 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ - for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_CODE_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the code address. */ - code_address = code_address + block_size; - /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -445,7 +426,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -453,45 +434,89 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the data area. */ - for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + for (i = 0; i < TXM_MODULE_MANAGER_MPU_DATA_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to data size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(data_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(data_size - block_size > data_size) + { + /* Case 2 covered the remaining data size. This region will not be used. */ + block_size = 0; + } + else + { + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from data_size to calculate remaining space. */ - data_size = data_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(data_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - data_size = data_size - block_size; - block_size = _txm_power_of_two_block_size(data_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; - /* Build the attribute-size register with permissions, SRD, size, enable. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; - /* Adjust the data address. */ - data_address = data_address + block_size; - + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of data protection. */ + + /* Setup MPU for the shared regions. */ + while (mpu_table_index < TXM_MODULE_MANAGER_MPU_USER_REGION_INDEX) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | TXM_MPU_VALID_BIT; + /* Increment MPU table index. */ mpu_table_index++; } @@ -515,39 +540,30 @@ ULONG data_size; ULONG start_stop_stack_size; ULONG callback_stack_size; ULONG block_size; -ULONG base_address_register; ULONG base_attribute_register; ULONG region_size; ULONG srd_bits = 0; -UINT mpu_register = 0; -UINT mpu_table_index; +UINT mpu_table_index = 1; UINT i; - /* Setup the first region for the ThreadX trampoline code. */ - /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ - base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - - /* Mask address to proper range, region 0, set Valid bit. */ - base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; - module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - - /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ - module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MPU_VALID_BIT; + /* Set the attributes, region size (32 bytes), and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | 0x08 | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ - /* Initialize the MPU register. */ - mpu_register = 1; + /* Setup code protection. */ - /* Initialize the MPU table index. */ - mpu_table_index = 2; - - /* Setup values for code area. */ + /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ - if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address == 0) { /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size @@ -556,99 +572,120 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { - /* First two MPU blocks are 1/4 of the largest power of two - that is greater than or equal to code size. */ - if (i < 2) + switch(i) { - block_size = _txm_power_of_two_block_size(code_size) >> 2; + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + case 0: + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + break; + } + case 2: + { + /* Third MPU block is the largest power of 2 that fits within the remaining space. */ + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size); + + /* Minimum block size is 32. */ + if(block_size > 32) + { + /* POW2 function result is divided by two to fit in the remaining space. */ + block_size = block_size >> 1; + } + break; + } + case 3: + { + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + /* Calculate remaining space. */ + if(code_size - block_size > code_size) + { + /* Case 2 covered the remaining code size. This region will not be used. */ + block_size = 0; + } + else + { + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + break; + } + default: + { + /* Case 1 is the same as 0 - the block size was already calculated. */ + break; + } } - - /* Third MPU block is the largest power of 2 that fits in the remaining space. */ - else if (i == 2) + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + + /* Only configure attribute register if the block is valid. */ + if(block_size) { - /* Subtract (block_size*2) from code_size to calculate remaining space. */ - code_size = code_size - (block_size << 1); - block_size = _txm_power_of_two_block_size(code_size) >> 1; + /* Calculate the region size information. */ + region_size = _txm_module_manager_region_size_get(block_size); + + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | (region_size << 1) | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; } - - /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ else { - /* Calculate remaining space. */ - code_size = code_size - block_size; - block_size = _txm_power_of_two_block_size(code_size); - srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = 0; } - - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070001; - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - - /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - /* Adjust the code address. */ - code_address = code_address + block_size; - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + /* Increment MPU table index. */ + mpu_table_index++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ - base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x06070000; - + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + /* Is there still some code? If so set the region enable bit. */ if (code_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -658,34 +695,27 @@ UINT i; { code_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } - - /* Adjust indeces to pass over the shared memory entry. */ - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Data protection is already set up so we can simply return here. */ + return; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -694,46 +724,43 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - - /* Calculate the region size information. */ - region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + + /* Calculate the region size and pre-shift it so we don't need to shift it multiple times in the for loop. */ + region_size = _txm_module_manager_region_size_get(block_size) << 1; + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ - base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | TXM_MPU_VALID_BIT; + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - - /* Build the base attribute register. */ - base_attribute_register = region_size | srd_bits | 0x13070000; - + + /* Build the attribute-size register with permissions, SRD, size. */ + base_attribute_register = region_size | srd_bits | TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ - base_attribute_register = base_attribute_register | 0x1; + base_attribute_register |= TXM_ENABLE_REGION; } - - /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -743,12 +770,9 @@ UINT i; { data_size = 0; } - - /* Move MPU table index. */ - mpu_table_index = mpu_table_index + 2; - - /* Increment the MPU register index. */ - mpu_register++; + + /* Increment MPU table index. */ + mpu_table_index++; } #endif @@ -808,7 +832,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_r4/ac6/inc/tx_port.h b/ports_module/cortex_r4/ac6/inc/tx_port.h index 3fba0f78..5b244681 100644 --- a/ports_module/cortex_r4/ac6/inc/tx_port.h +++ b/ports_module/cortex_r4/ac6/inc/tx_port.h @@ -346,7 +346,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_r4/ac6/inc/txm_module_port.h b/ports_module/cortex_r4/ac6/inc/txm_module_port.h index 3f64b4f0..d4aea6fd 100644 --- a/ports_module/cortex_r4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_r4/ac6/inc/txm_module_port.h @@ -360,7 +360,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/ARM Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/ARM Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S index c480e844..5d21f062 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S @@ -139,7 +139,7 @@ _tx_thread_fiq_context_restore: __tx_thread_fiq_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr))*/ /* (_tx_thread_preempt_disable)) */ /* { */ diff --git a/ports_module/cortex_r4/iar/inc/tx_port.h b/ports_module/cortex_r4/iar/inc/tx_port.h index dc72590a..f2c0a271 100644 --- a/ports_module/cortex_r4/iar/inc/tx_port.h +++ b/ports_module/cortex_r4/iar/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.2.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_r4/iar/inc/txm_module_port.h b/ports_module/cortex_r4/iar/inc/txm_module_port.h index 10a00ed7..d5ebb0da 100644 --- a/ports_module/cortex_r4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_r4/iar/inc/txm_module_port.h @@ -341,7 +341,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/IAR Version 6.2.1 *"; #endif diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s index 69e9c979..84592785 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s @@ -122,7 +122,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { ; diff --git a/ports_module/rxv2/iar/inc/tx_port.h b/ports_module/rxv2/iar/inc/tx_port.h index f6741c57..f5242f2c 100644 --- a/ports_module/rxv2/iar/inc/tx_port.h +++ b/ports_module/rxv2/iar/inc/tx_port.h @@ -288,7 +288,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/rxv2/iar/inc/txm_module_port.h b/ports_module/rxv2/iar/inc/txm_module_port.h index 11274096..79199dae 100644 --- a/ports_module/rxv2/iar/inc/txm_module_port.h +++ b/ports_module/rxv2/iar/inc/txm_module_port.h @@ -396,6 +396,6 @@ VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instan #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module RXv2/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module RXv2/IAR Version 6.2.1 *"; #endif diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s index f629f065..99af7d46 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s @@ -119,7 +119,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { diff --git a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h index 08b14a9a..dfb1a7fe 100644 --- a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h +++ b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h @@ -404,7 +404,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h index d689942c..261a285d 100644 --- a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h @@ -397,7 +397,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h index 152af0ad..9b1de969 100644 --- a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h @@ -400,7 +400,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h index 3e891802..843802ed 100644 --- a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h @@ -424,7 +424,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.1.9 *"; + "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h index 2e95d211..0b7d8112 100644 --- a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h @@ -421,7 +421,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h index 7839b37a..77cd0543 100644 --- a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h @@ -444,7 +444,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GHS Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GHS Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h b/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h index 1beca312..982e8441 100644 --- a/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h @@ -447,7 +447,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/IAR Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/IAR Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S index 35a8fc96..8246e24f 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule ARMv8-A-SMP */ -/* 6.1.10 */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,8 +63,11 @@ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ +/* added ARMv8.2-A support, */ /* resulting in version 6.1.10 */ +/* 03-08-2023 Cindy Deng Updated comment(s), */ +/* added memory barrier, */ +/* resulting in version 6.2.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -165,7 +168,7 @@ _tx_thread_ready_for_execution: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x2, x20, LSL #3] // Setup current thread pointer - + DMB ISH LDR x1, [x1, x20, LSL #3] // Reload the execute pointer CMP w0, w1 // Did it change? BEQ _execute_pointer_did_not_change // If not, skip handling diff --git a/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h index fcac1485..019db6eb 100644 --- a/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h @@ -420,7 +420,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h index 9175e1f4..bb2d7a87 100644 --- a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h @@ -397,7 +397,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h index a1451a98..3aff8831 100644 --- a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h index 512efb55..f740e50a 100644 --- a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h @@ -402,7 +402,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h index 8aa41416..11b9a895 100644 --- a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h @@ -395,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/GNU Version Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/GNU Version Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h b/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h index 1de09e88..33a10e32 100644 --- a/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h @@ -399,7 +399,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-R SMP Version 6.2.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv7-R SMP Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/linux/gnu/inc/tx_port.h b/ports_smp/linux/gnu/inc/tx_port.h index 1b235a4b..f1cf2075 100644 --- a/ports_smp/linux/gnu/inc/tx_port.h +++ b/ports_smp/linux/gnu/inc/tx_port.h @@ -634,7 +634,7 @@ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG su #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Linux/gcc Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Linux/gcc Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h b/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h index 7b7c7d1f..f10994e0 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h +++ b/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial release version 6.x */ +/* 03-08-2023 Scott Larson Initial release version 6.2.1 */ /* */ /**************************************************************************/ @@ -425,7 +425,7 @@ THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.x *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt b/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt index 4e83ef31..20ac0134 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt +++ b/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt @@ -254,7 +254,7 @@ file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -xx-xx-xxxx Initial ThreadX version 6.x of MIPS32_interAptiv VPE/GNU port. +03-08-2023 Initial ThreadX version 6.2.1 of MIPS32_interAptiv VPE/GNU port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S index db595bad..c26a03a5 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S index efecb643..24c997b9 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S index 926e1f37..a202a3dc 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S index b2ab32d5..c4d20177 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S @@ -32,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S index cd601aa5..b9da17f6 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S index e0b6bf35..9727e37f 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_get MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_core_get diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S index 4dcc23b4..d3432815 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_preempt MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_core_preempt diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S index c64880cf..17bc4535 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_state_get MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_current_state_get diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S index 33cf34c6..feaf00b6 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_thread_get MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_current_thread_get diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S index c2c872b5..7fbee9a8 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_initialize_wait MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_initialize_wait diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S index bb75b728..83b3921f 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_low_level_initialize MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_low_level_initialize diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S index 61e397c0..6e0cfb18 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_protect MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_protect diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S index 04176026..848fd11f 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_time_get MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_time_get diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S index af145e62..76929705 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_unprotect MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_unprotect diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S index f4354578..97b02b05 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S index 53aae75e..71c631d4 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S index b3b9a620..d6e235af 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt MIPS32_interAptiv/GNU */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h b/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h index e0a1b12c..cbe0fe52 100644 --- a/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h +++ b/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_el.h PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h b/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h index 92326b44..0cbf582a 100644 --- a/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h +++ b/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial release version 6.x */ +/* 03-08-2023 Scott Larson Initial release version 6.2.1 */ /* */ /**************************************************************************/ @@ -515,7 +515,7 @@ THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP MIPS32_interAptiv/Green Hills Version 6.x *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP MIPS32_interAptiv/Green Hills Version 6.2.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt b/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt index 5d56465f..20365485 100644 --- a/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt +++ b/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt @@ -295,7 +295,7 @@ file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -xx-xx-xxxx Initial ThreadX version 6.x of MIPS32_interAptiv VPE/Green Hills port. +03-08-2023 Initial ThreadX version 6.2.1 of MIPS32_interAptiv VPE/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c b/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c index 01f2eb43..8c18ab5c 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c @@ -56,7 +56,7 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* FUNCTION RELEASE */ /* */ /* _tx_el_initialize PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) @@ -223,7 +223,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _tx_el_thread_register PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -254,7 +254,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ UINT _tx_el_thread_register(TX_THREAD *thread_ptr) @@ -328,7 +328,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _tx_el_thread_unregister PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -359,7 +359,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr) @@ -442,7 +442,7 @@ UINT i, j; /* FUNCTION RELEASE */ /* */ /* _tx_el_user_event_insert PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -476,7 +476,7 @@ UINT i, j; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, @@ -565,7 +565,7 @@ UCHAR *entry_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_el_thread_running PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -597,7 +597,7 @@ UCHAR *entry_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_thread_running(TX_THREAD *thread_ptr) @@ -665,7 +665,7 @@ UCHAR *entry_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_el_thread_preempted PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -699,7 +699,7 @@ UCHAR *entry_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr) @@ -768,7 +768,7 @@ UCHAR *entry_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_el_interrupt PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -799,7 +799,7 @@ UCHAR *entry_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_interrupt(UINT interrupt_number) @@ -872,7 +872,7 @@ UCHAR *entry_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_el_interrupt_end PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -903,7 +903,7 @@ UCHAR *entry_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_interrupt_end(UINT interrupt_number) @@ -976,7 +976,7 @@ UCHAR *entry_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_el_interrupt_control PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -1006,7 +1006,7 @@ UCHAR *entry_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ UINT _tx_el_interrupt_control(UINT new_posture) @@ -1034,7 +1034,7 @@ UINT old_posture; /* FUNCTION RELEASE */ /* */ /* _tx_el_event_log_on PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -1063,7 +1063,7 @@ UINT old_posture; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_event_log_on(void) @@ -1079,7 +1079,7 @@ VOID _tx_el_event_log_on(void) /* FUNCTION RELEASE */ /* */ /* _tx_el_event_log_off PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -1109,7 +1109,7 @@ VOID _tx_el_event_log_on(void) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_event_log_off(void) @@ -1125,7 +1125,7 @@ VOID _tx_el_event_log_off(void) /* FUNCTION RELEASE */ /* */ /* _tx_el_event_log_set PORTABLE SMP */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -1154,7 +1154,7 @@ VOID _tx_el_event_log_off(void) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx William E. Lamie Initial Version 6.x */ +/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ /* */ /**************************************************************************/ VOID _tx_el_event_filter_set(UINT filter) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip index ca9ddf69..0e6ef331 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip index fd3bfe99..0a4d5cef 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip index 9f091336..34b99fa2 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip index b8e022f6..90533cca 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip @@ -32,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip index 90feae33..b6a2aca7 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip index 2b83325d..c7d75f42 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_get MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_core_get diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip index 8ae1941c..b775d04a 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_preempt MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_core_preempt diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip index 5c6f419b..b1aad2b4 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_state_get MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_current_state_get diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip index 956c5523..60a09e11 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_thread_get MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_current_thread_get diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip index 7c68f441..9ff72eeb 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_initialize_wait MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_initialize_wait diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip index 153830cd..ee37dcde 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_low_level_initialize MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_low_level_initialize diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip index 3bf04743..c52ea21c 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_protect MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_protect diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip index 43b34696..03339736 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_time_get MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_time_get diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip index 132c7dd0..182fa59f 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_unprotect MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ .globl _tx_thread_smp_unprotect diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip index d6e37477..b1cb7216 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip index 2889ba5d..a2833709 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip index 25b783ac..a670c564 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt MIPS32_interAptiv/Green Hills */ -/* 6.x */ +/* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* xx-xx-xxxx Scott Larson Initial Version 6.x */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID)