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apply 6.0.2 patch

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This commit is contained in:
Scott Larson 2020-08-14 09:10:48 -07:00
parent 6a018a4cfd
commit 40a402b827
227 changed files with 2232 additions and 3212 deletions
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7
common/inc/tx_api.h
View File

@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE C */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@ -47,6 +47,9 @@
/* 06-30-2020 William E. Lamie Modified comment(s), and */
/* updated product constants, */
/* resulting in version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), and */
/* updated product constants, */
/* resulting in version 6.0.2 */
/* */
/**************************************************************************/
@ -79,7 +82,7 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 0
#define THREADX_PATCH_VERSION 1
#define THREADX_PATCH_VERSION 2
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX

13
common_smp/inc/tx_api.h
View File

@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE SMP */
/* 6.0.1 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@ -44,6 +44,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
/* 08-14-2020 William E. Lamie Modified comment(s), and */
/* updated product constants, */
/* resulting in version 6.0.2 */
/* */
/**************************************************************************/
@ -80,9 +83,13 @@ extern "C" {
/* Define the major/minor version information that can be used by the application
and the ThreadX source as well. */
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 0
#define THREADX_PATCH_VERSION 2
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
#define THREADX_MAJOR_VERSION 5
#define THREADX_MINOR_VERSION 9
/* API input parameters and general constants. */

61
ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
@ -87,7 +77,7 @@ __tx_vectors
DCD __tx_IntHandler ; Int 0
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
@ -96,13 +86,13 @@ Reset_Handler
CPSID i
LDR R0, =__main
BX R0
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -136,29 +126,32 @@ Reset_Handler
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
EXPORT _tx_initialize_low_level
_tx_initialize_low_level
;
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADDS r1, r1, #4 ;
ADDS r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
LDR r0, =0xE000ED08 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
STR r1, [r0] ; Set vector table address
;
; /* Enable the cycle count register. */
;
@ -166,15 +159,15 @@ _tx_initialize_low_level
; LDR r1, [r0] ; Pickup the current value
; MOVS r2, #1
; ORRS r1, r1, r2 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD08 ; Offset to vector base register
ADD r0, r0, r2 ; Build vector base register
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
STR r1, [r0] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@ -195,30 +188,30 @@ _tx_initialize_low_level
;
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers
; Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
@ -239,14 +232,14 @@ __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
__tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
@ -269,7 +262,7 @@ SysTick_Handler
BX lr
; }
EXPORT __tx_NMIHandler
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler
@ -280,5 +273,3 @@ __tx_DBGHandler
ALIGN
LTORG
END

5
ports/cortex_m0/ac5/readme_threadx.txt
View File

@ -133,6 +133,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M0/AC5 port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools.

18
ports/cortex_m0/ac5/src/tx_thread_context_restore.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
@ -42,13 +32,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@ -98,4 +93,3 @@ _tx_thread_context_restore
ALIGN
LTORG
END

20
ports/cortex_m0/ac5/src/tx_thread_context_save.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
@ -43,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@ -92,10 +87,9 @@ _tx_thread_context_save
ENDIF
;
; /* Return to interrupt processing. */
;
;
BX lr ; Return to interrupt processing caller
;}
ALIGN
LTORG
END

14
ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s
View File

@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@ -84,4 +79,3 @@ _tx_thread_interrupt_control
ALIGN
LTORG
END

13
ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s
View File

@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

13
ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s
View File

@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

78
ports/cortex_m0/ac5/src/tx_thread_schedule.s
View File

@ -21,15 +21,6 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
@ -37,7 +28,7 @@
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
IMPORT _tx_execution_thread_exit
ENDIF
;
;
@ -48,7 +39,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -82,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@ -94,7 +88,7 @@ _tx_thread_schedule
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOVS r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@ -102,7 +96,7 @@ _tx_thread_schedule
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
@ -112,22 +106,22 @@ _tx_thread_schedule
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switch-out switch-in handler... Note that this handler is
; /* Generic context switch-out switch-in handler... Note that this handler is
; common for both PendSV and SVCall. */
;
;
EXPORT PendSV_Handler
EXPORT __tx_PendSVHandler
PendSV_Handler
__tx_PendSVHandler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@ -137,7 +131,7 @@ __tx_ts_handler
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
MOV lr, r1 ;
CPSIE i ; Enable interrupts
ENDIF
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
@ -146,9 +140,9 @@ __tx_ts_handler
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CMP r1,#0 ; If NULL, skip preservation
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Recover PSP and preserve current thread context. */
;
@ -156,15 +150,15 @@ __tx_ts_handler
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
@ -172,7 +166,7 @@ __tx_ts_handler
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CMP r5, #0 ; If not active, skip processing
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
@ -183,7 +177,6 @@ __tx_ts_handler
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
@ -192,7 +185,7 @@ __tx_ts_new
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CMP r1, #0 ;
CMP r1, #0 ;
BEQ __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
@ -229,26 +222,26 @@ __tx_ts_restore
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11)
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
@ -259,20 +252,19 @@ __tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build base NVIC address
STR r7, [r5] ; Clear any PendSV
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
ALIGN
LTORG
END

23
ports/cortex_m0/ac5/src/tx_thread_stack_build.s
View File

@ -20,15 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -36,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -69,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -76,11 +70,11 @@
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M0 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r8 Initial value for r8
; r9 Initial value for r9
@ -102,7 +96,7 @@ _tx_thread_stack_build
; Stack Bottom: (higher memory address) */
;
LDR r2, [r0, #16] ; Pickup end of stack area
MOVS r3, #0x7 ;
MOVS r3, #0x7 ;
BICS r2, r2, r3 ; Align frame for 8-byte alignment
SUBS r2, r2, #68 ; Subtract frame size
LDR r3, =0xFFFFFFFD ; Build initial LR value
@ -143,4 +137,3 @@ _tx_thread_stack_build
ALIGN
LTORG
END

24
ports/cortex_m0/ac5/src/tx_thread_system_return.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -37,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -70,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@ -77,9 +70,9 @@
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
@ -90,8 +83,7 @@ _tx_thread_system_return
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
BX lr ; Return to caller
NOP
;}
END
END

25
ports/cortex_m0/ac5/src/tx_timer_interrupt.s
View File

@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
@ -53,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -88,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@ -111,7 +103,7 @@ _tx_timer_interrupt
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CMP r2, #0 ; Is it non-active?
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
@ -229,18 +221,18 @@ __tx_timer_dont_activate
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CMP r2, #0 ; See if the flag is set
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
;
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag
LDR r1, [r0] ; Is the preempt disable flag set?
CMP r1, #0 ;
CMP r1, #0 ;
BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r1, [r0] ; Pickup the current thread pointer
@ -271,4 +263,3 @@ __tx_timer_nothing_expired
ALIGN
LTORG
END

53
ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
@ -48,8 +38,8 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* */
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M0/GNU */
@/* 6.0.1 */
@/* _tx_initialize_low_level Cortex-M0/AC6 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -83,6 +73,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), and */
@/* commented out code for */
@/* enabling DWT, */
@/* resulting in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@ -96,27 +90,27 @@ _tx_initialize_low_level:
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address
ADDS r1, r1, #4 @
ADDS r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Enable the cycle count register. */
@
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
MOVS r2, #1
ORRS r1, r1, r2 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
@ /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
@ LDR r0, =0xE0001000 @ Build address of DWT register
@ LDR r1, [r0] @ Pickup the current value
@ MOVS r2, #1
@ ORRS r1, r1, r2 @ Set the CYCCNTENA bit
@ STR r1, [r0] @ Enable the cycle count register
@
@ /* Setup Vector Table Offset Register. */
@
@
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD08 @ Offset to vector base register
ADD r0, r0, r2 @ Build vector base register
LDR r1, =vector_table @ Pickup address of vector table
STR r1, [r0] @ Set vector table address
STR r1, [r0] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
@ -138,25 +132,24 @@ _tx_initialize_low_level:
LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD18 @
ADD r0, r0, r2 @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD1C @
ADD r0, r0, r2 @
LDR r2, =0xD1C @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 8-11 Priority Registers
@ Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 @ Build address of NVIC registers
LDR r2, =0xD20 @
ADD r0, r0, r2 @
LDR r2, =0xD20 @
ADD r0, r0, r2 @
STR r1, [r0] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@
BX lr
@}
@
@ /* System Tick timer interrupt handler */

6
ports/cortex_m0/ac6/readme_threadx.txt
View File

@ -148,6 +148,12 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M0/AC6 port. The following files were
changed/added for port specific version 6.0.2:
tx_initialize_low_level.S Comment out DWT code.
*.S Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC6 tools.

18
ports/cortex_m0/ac6/src/tx_thread_context_restore.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -48,13 +38,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -81,6 +73,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@ -92,4 +87,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

20
ports/cortex_m0/ac6/src/tx_thread_context_save.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -43,13 +33,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@ -75,6 +67,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)
@ -84,6 +79,5 @@
_tx_thread_context_save:
@
@ /* Not needed for this port - just return! */
BX lr
BX lr
@}

16
ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -38,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -69,6 +61,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@ -89,6 +84,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

16
ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -38,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_disable Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -68,6 +60,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_disable(VOID)
@ -83,6 +78,3 @@ _tx_thread_interrupt_disable:
BX lr
@/* } */

16
ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -38,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_restore Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -69,6 +61,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_interrupt_restore(UINT old_posture)
@ -81,6 +76,3 @@ _tx_thread_interrupt_restore:
BX lr
@/* } */

83
ports/cortex_m0/ac6/src/tx_thread_schedule.S
View File

@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@ -44,7 +35,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -78,6 +69,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@ -91,7 +85,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOVS r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@ -99,7 +93,7 @@ _tx_thread_schedule:
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
LDR r0, =0x10000000 @ Load PENDSVSET bit
@ -109,29 +103,29 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
.global PendSV_Handler
@
.global PendSV_Handler
.thumb_func
.thumb_func
PendSV_Handler:
.global __tx_PendSVHandler
.global __tx_SVCallHandler
.thumb_func
__tx_PendSVHandler:
__tx_PendSVHandler:
.thumb_func
__tx_SVCallHandler:
@
@ /* Get current thread value and new thread pointer. */
@
@
.thumb_func
__tx_ts_handler:
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ -141,7 +135,7 @@ __tx_ts_handler:
PUSH {r0, lr} @ Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit @ Call the thread exit function
POP {r0, r1} @ Recover LR
MOV lr, r1 @
MOV lr, r1 @
CPSIE i @ Enable interrupts
#endif
LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
@ -150,9 +144,9 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CMP r1,#0 @ If NULL, skip preservation
BEQ __tx_ts_new @
BEQ __tx_ts_new @
@
@ /* Recover PSP and preserve current thread context. */
@
@ -160,12 +154,12 @@ __tx_ts_handler:
MRS r3, PSP @ Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 @ Allocate stack space
STM r3!, {r4-r7} @ Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 @
MOV r5,r9 @
MOV r6,r10 @
MOV r7,r11 @
MOV r4,r8 @
MOV r5,r9 @
MOV r6,r10 @
MOV r7,r11 @
SUBS r3, r3, #32 @ Allocate stack space
STM r3!,{r4-r7} @
STM r3!,{r4-r7} @
SUBS r3, r3, #20 @ Allocate stack space
MOV r5, lr @ Move LR into R4
STR r5, [r3] @ Save LR
@ -176,7 +170,7 @@ __tx_ts_handler:
LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
LDR r5, [r4] @ Pickup current time-slice
CMP r5, #0 @ If not active, skip processing
BEQ __tx_ts_new @
BEQ __tx_ts_new @
@
@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
@
@ -186,16 +180,16 @@ __tx_ts_handler:
@
MOVS r5, #0 @ Build clear value
STR r5, [r4] @ Clear time-slice
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
__tx_ts_new:
@
@ /* Now we are looking for a new thread to execute! */
@
CPSID i @ Disable interrupts
LDR r1, [r2] @ Is there another thread ready to execute?
CMP r1, #0 @
CMP r1, #0 @
BEQ __tx_ts_wait @ No, skip to the wait processing
@
@ /* Yes, another thread is ready for else, make the current thread the new thread. */
@ -205,7 +199,7 @@ __tx_ts_new:
@
@ /* Increment the thread run count. */
@
__tx_ts_restore:
__tx_ts_restore:
LDR r7, [r1, #4] @ Pickup the current thread run count
LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
LDR r5, [r1, #24] @ Pickup thread's current time-slice
@ -232,26 +226,26 @@ __tx_ts_restore:
ADDS r3, r3, #4 @ Position past LR
MOV lr, r5 @ Restore LR
LDM r3!,{r4-r7} @ Recover thread's registers (r4-r11)
MOV r11,r7 @
MOV r10,r6 @
MOV r9,r5 @
MOV r11,r7 @
MOV r10,r6 @
MOV r9,r5 @
MOV r8,r4 @
LDM r3!,{r4-r7} @
LDM r3!,{r4-r7} @
MSR PSP, r3 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
__tx_ts_wait:
CPSID i @ Disable interrupts
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
@ -261,16 +255,15 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
__tx_ts_ready:
LDR r7, =0x08000000 @ Build clear PendSV value
LDR r5, =0xE000ED04 @ Build base NVIC address
STR r7, [r5] @ Clear any PendSV
STR r7, [r5] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread

24
ports/cortex_m0/ac6/src/tx_thread_stack_build.S
View File

@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -79,11 +73,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M0 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r8 Initial value for r8
@ r9 Initial value for r9
@ -105,7 +99,7 @@ _tx_thread_stack_build:
@ Stack Bottom: (higher memory address) */
@
LDR r2, [r0, #16] @ Pickup end of stack area
MOVS r3, #0x7 @
MOVS r3, #0x7 @
BICS r2, r2, r3 @ Align frame for 8-byte alignment
SUBS r2, r2, #68 @ Subtract frame size
LDR r3, =0xFFFFFFFD @ Build initial LR value
@ -143,5 +137,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

23
ports/cortex_m0/ac6/src/tx_thread_system_return.S
View File

@ -11,7 +11,7 @@
@
@
@/**************************************************************************/
@@/**************************************************************************/
@/**************************************************************************/
@/** */
@/** ThreadX Component */
@/** */
@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@ -79,9 +73,9 @@
.thumb_func
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
LDR r0, =0x10000000 @ Load PENDSVSET bit
LDR r1, =0xE000ED04 @ Load NVIC base
STR r0, [r1] @ Set PENDSVBIT in ICSR
@ -92,6 +86,5 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

26
ports/cortex_m0/ac6/src/tx_timer_interrupt.S
View File

@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M0/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@ -228,18 +220,18 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
LDR r1, [r0] @ Is the preempt disable flag set?
CMP r1, #0 @
CMP r1, #0 @
BNE __tx_timer_skip_time_slice @ Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
LDR r1, [r0] @ Pickup the current thread pointer
@ -267,5 +259,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}

18
ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S
View File

@ -51,7 +51,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -85,6 +85,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), and */
@/* commented out code for */
@/* enabling DWT, */
@/* resulting in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@ -105,12 +109,12 @@ _tx_initialize_low_level:
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Enable the cycle count register. */
@
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
MOVS r2, #1
ORRS r1, r1, r2 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
@ /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
@ LDR r0, =0xE0001000 @ Build address of DWT register
@ LDR r1, [r0] @ Pickup the current value
@ MOVS r2, #1
@ ORRS r1, r1, r2 @ Set the CYCCNTENA bit
@ STR r1, [r0] @ Enable the cycle count register
@
@ /* Setup Vector Table Offset Register. */
@

6
ports/cortex_m0/gnu/readme_threadx.txt
View File

@ -145,6 +145,12 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M0/GNU port. The following files were
changed/added for port specific version 6.0.2:
tx_initialize_low_level.S Comment out DWT code.
*.S Modified comments and whitespace.
05/19/2020 Initial ThreadX 6.0 version for Cortex-M0 using GNU tools.

18
ports/cortex_m0/gnu/src/tx_thread_context_restore.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -49,13 +39,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -82,6 +74,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@ -93,4 +88,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

20
ports/cortex_m0/gnu/src/tx_thread_context_save.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -44,13 +34,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@ -76,6 +68,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)
@ -85,6 +80,5 @@
_tx_thread_context_save:
@
@ /* Not needed for this port - just return! */
BX lr
BX lr
@}

16
ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -38,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -69,6 +61,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@ -89,6 +84,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

16
ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -38,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_disable Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -68,6 +60,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_disable(VOID)
@ -83,6 +78,3 @@ _tx_thread_interrupt_disable:
BX lr
@/* } */

16
ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -38,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_restore Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -69,6 +61,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_interrupt_restore(UINT old_posture)
@ -81,6 +76,3 @@ _tx_thread_interrupt_restore:
BX lr
@/* } */

83
ports/cortex_m0/gnu/src/tx_thread_schedule.S
View File

@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@ -46,7 +37,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -80,6 +71,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@ -93,7 +87,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOVS r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@ -101,7 +95,7 @@ _tx_thread_schedule:
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
LDR r0, =#0x10000000 @ Load PENDSVSET bit
@ -111,29 +105,29 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
.global PendSV_Handler
@
.global PendSV_Handler
.thumb_func
.thumb_func
PendSV_Handler:
.global __tx_PendSVHandler
.global __tx_SVCallHandler
.thumb_func
__tx_PendSVHandler:
__tx_PendSVHandler:
.thumb_func
__tx_SVCallHandler:
@
@ /* Get current thread value and new thread pointer. */
@
@
.thumb_func
__tx_ts_handler:
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ -143,7 +137,7 @@ __tx_ts_handler:
PUSH {r0, lr} @ Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit @ Call the thread exit function
POP {r0, r1} @ Recover LR
MOV lr, r1 @
MOV lr, r1 @
CPSIE i @ Enable interrupts
#endif
LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
@ -152,9 +146,9 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CMP r1,#0 @ If NULL, skip preservation
BEQ __tx_ts_new @
BEQ __tx_ts_new @
@
@ /* Recover PSP and preserve current thread context. */
@
@ -162,12 +156,12 @@ __tx_ts_handler:
MRS r3, PSP @ Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 @ Allocate stack space
STM r3!, {r4-r7} @ Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 @
MOV r5,r9 @
MOV r6,r10 @
MOV r7,r11 @
MOV r4,r8 @
MOV r5,r9 @
MOV r6,r10 @
MOV r7,r11 @
SUBS r3, r3, #32 @ Allocate stack space
STM r3!,{r4-r7} @
STM r3!,{r4-r7} @
SUBS r3, r3, #20 @ Allocate stack space
MOV r5, lr @ Move LR into R4
STR r5, [r3] @ Save LR
@ -178,7 +172,7 @@ __tx_ts_handler:
LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
LDR r5, [r4] @ Pickup current time-slice
CMP r5, #0 @ If not active, skip processing
BEQ __tx_ts_new @
BEQ __tx_ts_new @
@
@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
@
@ -188,16 +182,16 @@ __tx_ts_handler:
@
MOVS r5, #0 @ Build clear value
STR r5, [r4] @ Clear time-slice
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
__tx_ts_new:
@
@ /* Now we are looking for a new thread to execute! */
@
CPSID i @ Disable interrupts
LDR r1, [r2] @ Is there another thread ready to execute?
CMP r1, #0 @
CMP r1, #0 @
BEQ __tx_ts_wait @ No, skip to the wait processing
@
@ /* Yes, another thread is ready for else, make the current thread the new thread. */
@ -207,7 +201,7 @@ __tx_ts_new:
@
@ /* Increment the thread run count. */
@
__tx_ts_restore:
__tx_ts_restore:
LDR r7, [r1, #4] @ Pickup the current thread run count
LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable
LDR r5, [r1, #24] @ Pickup thread's current time-slice
@ -234,26 +228,26 @@ __tx_ts_restore:
ADDS r3, r3, #4 @ Position past LR
MOV lr, r5 @ Restore LR
LDM r3!,{r4-r7} @ Recover thread's registers (r4-r11)
MOV r11,r7 @
MOV r10,r6 @
MOV r9,r5 @
MOV r11,r7 @
MOV r10,r6 @
MOV r9,r5 @
MOV r8,r4 @
LDM r3!,{r4-r7} @
LDM r3!,{r4-r7} @
MSR PSP, r3 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
__tx_ts_wait:
CPSID i @ Disable interrupts
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
@ -263,16 +257,15 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
__tx_ts_ready:
LDR r7, =0x08000000 @ Build clear PendSV value
LDR r5, =0xE000ED04 @ Build base NVIC address
STR r7, [r5] @ Clear any PendSV
STR r7, [r5] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread

24
ports/cortex_m0/gnu/src/tx_thread_stack_build.S
View File

@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -76,6 +67,9 @@
@/* needed. Removed references */
@/* to stack frame, resulting */
@/* in version 6.0.1 */
@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -84,11 +78,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M0 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r8 Initial value for r8
@ r9 Initial value for r9
@ -110,7 +104,7 @@ _tx_thread_stack_build:
@ Stack Bottom: (higher memory address) */
@
LDR r2, [r0, #16] @ Pickup end of stack area
MOVS r3, #0x7 @
MOVS r3, #0x7 @
BICS r2, r2, r3 @ Align frame for 8-byte alignment
SUBS r2, r2, #68 @ Subtract frame size
LDR r3, =0xFFFFFFFD @ Build initial LR value
@ -148,5 +142,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

23
ports/cortex_m0/gnu/src/tx_thread_system_return.S
View File

@ -11,7 +11,7 @@
@
@
@/**************************************************************************/
@@/**************************************************************************/
@/**************************************************************************/
@/** */
@/** ThreadX Component */
@/** */
@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text 32
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@ -79,9 +73,9 @@
.global _tx_thread_system_return
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
LDR r0, =0x10000000 @ Load PENDSVSET bit
LDR r1, =0xE000ED04 @ Load NVIC base
STR r0, [r1] @ Set PENDSVBIT in ICSR
@ -92,6 +86,5 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

26
ports/cortex_m0/gnu/src/tx_timer_interrupt.S
View File

@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M0/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@ -228,18 +220,18 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
LDR r1, [r0] @ Is the preempt disable flag set?
CMP r1, #0 @
CMP r1, #0 @
BNE __tx_timer_skip_time_slice @ Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address
LDR r1, [r0] @ Pickup the current thread pointer
@ -267,5 +259,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}

72
ports/cortex_m0/iar/example_build/tx_initialize_low_level.s
View File

@ -20,43 +20,33 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
;
;
SYSTEM_CLOCK EQU 50000000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
RSEG FREE_MEM:DATA
PUBLIC __tx_free_memory_start
__tx_free_memory_start
DS32 4
DS32 4
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -90,6 +80,10 @@ __tx_free_memory_start
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), and */
;/* commented out code for */
;/* enabling DWT, */
;/* resulting in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@ -97,33 +91,33 @@ __tx_free_memory_start
PUBLIC _tx_initialize_low_level
_tx_initialize_low_level:
;
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
STR r0, [r2, #0] ; Save first free memory address
;
; /* Enable the cycle count register. */
;
LDR r0, =0xE0001000 ; Build address of DWT register
LDR r1, [r0] ; Pickup the current value
MOVS r2, #1
ORRS r1, r1, r2 ; Set the CYCCNTENA bit
STR r1, [r0] ; Enable the cycle count register
; /* Not all M0 have DWT, uncomment if you have a DWT and want to use it. */
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; MOVS r2, #1
; ORRS r1, r1, r2 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD08 ; Offset to vector base register
ADD r0, r0, r2 ; Build vector base register
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
STR r1, [r0] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@ -144,26 +138,26 @@ _tx_initialize_low_level:
;
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers
; Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
;
BX lr
;}
;

6
ports/cortex_m0/iar/readme_threadx.txt
View File

@ -148,6 +148,12 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M0/IAR port. The following files were
changed/added for port specific version 6.0.2:
tx_initialize_low_level.s Comment out DWT code.
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M0 using IAR's ARM tools.

38
ports/cortex_m0/iar/src/tx_thread_context_restore.s
View File

@ -21,40 +21,32 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_schedule
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_isr_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_schedule
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -81,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@ -103,4 +98,3 @@ _tx_thread_context_restore:
;
;}
END

31
ports/cortex_m0/iar/src/tx_thread_context_save.s
View File

@ -21,35 +21,27 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_execution_isr_enter
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_state
EXTERN _tx_thread_current_ptr
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@ -84,11 +79,11 @@ _tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, r1} ; Recover return address
MOV lr, r1 ;
MOV lr, r1 ;
#endif
;
; /* Context is already saved - just return! */

18
ports/cortex_m0/iar/src/tx_thread_interrupt_control.s
View File

@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@ -83,4 +78,3 @@ _tx_thread_interrupt_control:
;
;}
END

17
ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s
View File

@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

17
ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s
View File

@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

93
ports/cortex_m0/iar/src/tx_thread_schedule.s
View File

@ -21,32 +21,23 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -80,6 +71,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@ -92,7 +86,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOVS r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@ -100,7 +94,7 @@ _tx_thread_schedule:
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
@ -110,21 +104,21 @@ _tx_thread_schedule:
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switch-out switch-in handler... */
;
;
PUBLIC PendSV_Handler
PUBLIC __tx_PendSVHandler
PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@ -134,7 +128,7 @@ __tx_ts_handler:
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
MOV lr, r1 ;
CPSIE i ; Enable interrupts
#endif
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
@ -143,9 +137,9 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CMP r1,#0 ; If NULL, skip preservation
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Recover PSP and preserve current thread context. */
;
@ -153,15 +147,15 @@ __tx_ts_handler:
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
@ -169,7 +163,7 @@ __tx_ts_handler:
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CMP r5, #0 ; If not active, skip processing
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
@ -180,7 +174,7 @@ __tx_ts_handler:
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
@ -189,7 +183,7 @@ __tx_ts_new:
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CMP r1, #0 ;
CMP r1, #0 ;
BEQ __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
@ -226,26 +220,26 @@ __tx_ts_restore:
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11)
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
@ -255,18 +249,17 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build base NVIC address
STR r7, [r5] ; Clear any PendSV
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
END

27
ports/cortex_m0/iar/src/tx_thread_stack_build.s
View File

@ -21,23 +21,14 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -70,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -77,11 +71,11 @@
PUBLIC _tx_thread_stack_build
_tx_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M0 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r8 Initial value for r8
; r9 Initial value for r9
@ -103,7 +97,7 @@ _tx_thread_stack_build:
; Stack Bottom: (higher memory address) */
;
LDR r2, [r0, #16] ; Pickup end of stack area
MOVS r3, #0x7 ;
MOVS r3, #0x7 ;
BICS r2, r2, r3 ; Align frame for 8-byte alignment
SUBS r2, r2, #68 ; Subtract frame size
LDR r3, =0xFFFFFFFD ; Build initial LR value
@ -142,4 +136,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

28
ports/cortex_m0/iar/src/tx_thread_system_return.s
View File

@ -20,25 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -71,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@ -79,9 +72,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
@ -92,7 +85,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

29
ports/cortex_m0/iar/src/tx_timer_interrupt.s
View File

@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
EXTERN _tx_timer_time_slice
EXTERN _tx_timer_system_clock
@ -46,14 +35,14 @@
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M0/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -88,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@ -110,7 +102,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CMP r2, #0 ; Is it non-active?
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
@ -228,18 +220,18 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CMP r2, #0 ; See if the flag is set
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag
LDR r1, [r0] ; Is the preempt disable flag set?
CMP r1, #0 ;
CMP r1, #0 ;
BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r1, [r0] ; Pickup the current thread pointer
@ -268,4 +260,3 @@ __tx_timer_nothing_expired:
;
;}
END

60
ports/cortex_m0/keil/example_build/tx_initialize_low_level.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
@ -87,7 +77,7 @@ __tx_vectors
DCD __tx_IntHandler ; Int 0
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
@ -96,13 +86,13 @@ Reset_Handler
CPSID i
LDR R0, =__main
BX R0
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -136,29 +126,32 @@ Reset_Handler
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
EXPORT _tx_initialize_low_level
_tx_initialize_low_level
;
;
; /* Ensure that interrupts are disabled. */
;
CPSID i ; Disable interrupts
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADDS r1, r1, #4 ;
ADDS r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
LDR r0, =0xE000ED08 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
STR r1, [r0] ; Set vector table address
;
; /* Enable the cycle count register. */
;
@ -166,15 +159,15 @@ _tx_initialize_low_level
; LDR r1, [r0] ; Pickup the current value
; MOVS r2, #1
; ORRS r1, r1, r2 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD08 ; Offset to vector base register
ADD r0, r0, r2 ; Build vector base register
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0] ; Set vector table address
STR r1, [r0] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@ -195,30 +188,30 @@ _tx_initialize_low_level
;
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
LDR r2, =0xD18 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
LDR r2, =0xD1C ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers
; Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
LDR r0, =0xE000E000 ; Build address of NVIC registers
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
LDR r2, =0xD20 ;
ADD r0, r0, r2 ;
STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
@ -239,14 +232,14 @@ __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
__tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
@ -269,7 +262,7 @@ SysTick_Handler
BX lr
; }
EXPORT __tx_NMIHandler
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler
@ -280,5 +273,4 @@ __tx_DBGHandler
ALIGN
LTORG
END

7
ports/cortex_m0/keil/readme_threadx.txt
View File

@ -139,7 +139,12 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools.
08-14-2020 ThreadX update of Cortex-M0/Keil port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using Keil tools.
Copyright(c) 1996-2020 Microsoft Corporation

19
ports/cortex_m0/keil/src/tx_thread_context_restore.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
@ -42,13 +32,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@ -98,4 +93,4 @@ _tx_thread_context_restore
ALIGN
LTORG
END

21
ports/cortex_m0/keil/src/tx_thread_context_save.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
@ -43,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@ -75,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@ -92,10 +87,10 @@ _tx_thread_context_save
ENDIF
;
; /* Return to interrupt processing. */
;
;
BX lr ; Return to interrupt processing caller
;}
ALIGN
LTORG
END

15
ports/cortex_m0/keil/src/tx_thread_interrupt_control.s
View File

@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@ -84,4 +79,4 @@ _tx_thread_interrupt_control
ALIGN
LTORG
END

13
ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s
View File

@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

13
ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s
View File

@ -20,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -35,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -66,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

79
ports/cortex_m0/keil/src/tx_thread_schedule.s
View File

@ -21,15 +21,6 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
@ -37,7 +28,7 @@
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
IMPORT _tx_execution_thread_exit
ENDIF
;
;
@ -48,7 +39,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -82,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@ -94,7 +88,7 @@ _tx_thread_schedule
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOVS r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@ -102,7 +96,7 @@ _tx_thread_schedule
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
@ -112,22 +106,22 @@ _tx_thread_schedule
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switch-out switch-in handler... Note that this handler is
; /* Generic context switch-out switch-in handler... Note that this handler is
; common for both PendSV and SVCall. */
;
;
EXPORT PendSV_Handler
EXPORT __tx_PendSVHandler
PendSV_Handler
__tx_PendSVHandler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@ -137,7 +131,7 @@ __tx_ts_handler
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit ; Call the thread exit function
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
MOV lr, r1 ;
CPSIE i ; Enable interrupts
ENDIF
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
@ -146,9 +140,9 @@ __tx_ts_handler
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CMP r1,#0 ; If NULL, skip preservation
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Recover PSP and preserve current thread context. */
;
@ -156,15 +150,15 @@ __tx_ts_handler
MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer)
SUBS r3, r3, #16 ; Allocate stack space
STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11})
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
MOV r4,r8 ;
MOV r5,r9 ;
MOV r6,r10 ;
MOV r7,r11 ;
SUBS r3, r3, #32 ; Allocate stack space
STM r3!, {r4-r7} ;
STM r3!, {r4-r7} ;
SUBS r3, r3, #20 ; Allocate stack space
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
MOV r5, LR ;
STR r5, [r3] ; Save LR on the stack
STR r3, [r1, #8] ; Save its stack pointer
;
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
@ -172,7 +166,7 @@ __tx_ts_handler
LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r4] ; Pickup current time-slice
CMP r5, #0 ; If not active, skip processing
BEQ __tx_ts_new ;
BEQ __tx_ts_new ;
;
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
;
@ -183,7 +177,7 @@ __tx_ts_handler
MOVS r5, #0 ; Build clear value
STR r5, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
@ -192,7 +186,7 @@ __tx_ts_new
;
CPSID i ; Disable interrupts
LDR r1, [r2] ; Is there another thread ready to execute?
CMP r1, #0 ;
CMP r1, #0 ;
BEQ __tx_ts_wait ; No, skip to the wait processing
;
; /* Yes, another thread is ready for else, make the current thread the new thread. */
@ -229,26 +223,26 @@ __tx_ts_restore
ADDS r3, r3, #4 ; Position past LR
MOV lr, r5 ; Restore LR
LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11)
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MOV r11,r7 ;
MOV r10,r6 ;
MOV r9,r5 ;
MOV r8,r4 ;
LDM r3!,{r4-r7} ;
MSR PSP, r3 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
@ -259,20 +253,19 @@ __tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
LDR r7, =0x08000000 ; Build clear PendSV value
LDR r5, =0xE000ED04 ; Build base NVIC address
STR r7, [r5] ; Clear any PendSV
STR r7, [r5] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
ALIGN
LTORG
END

23
ports/cortex_m0/keil/src/tx_thread_stack_build.s
View File

@ -20,15 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -36,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -69,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -76,11 +70,11 @@
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M0 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r8 Initial value for r8
; r9 Initial value for r9
@ -102,7 +96,7 @@ _tx_thread_stack_build
; Stack Bottom: (higher memory address) */
;
LDR r2, [r0, #16] ; Pickup end of stack area
MOVS r3, #0x7 ;
MOVS r3, #0x7 ;
BICS r2, r2, r3 ; Align frame for 8-byte alignment
SUBS r2, r2, #68 ; Subtract frame size
LDR r3, =0xFFFFFFFD ; Build initial LR value
@ -143,4 +137,3 @@ _tx_thread_stack_build
ALIGN
LTORG
END

25
ports/cortex_m0/keil/src/tx_thread_system_return.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -37,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -70,6 +60,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@ -77,9 +70,9 @@
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
LDR r0, =0x10000000 ; Load PENDSVSET bit
LDR r1, =0xE000ED04 ; Load NVIC base
STR r0, [r1] ; Set PENDSVBIT in ICSR
@ -90,8 +83,8 @@ _tx_thread_system_return
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
BX lr ; Return to caller
NOP
;}
END
END

25
ports/cortex_m0/keil/src/tx_timer_interrupt.s
View File

@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
@ -53,7 +42,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M0/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -88,6 +77,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@ -111,7 +103,7 @@ _tx_timer_interrupt
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CMP r2, #0 ; Is it non-active?
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
@ -229,18 +221,18 @@ __tx_timer_dont_activate
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CMP r2, #0 ; See if the flag is set
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
;
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag
LDR r1, [r0] ; Is the preempt disable flag set?
CMP r1, #0 ;
CMP r1, #0 ;
BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r1, [r0] ; Pickup the current thread pointer
@ -271,4 +263,3 @@ __tx_timer_nothing_expired
ALIGN
LTORG
END

46
ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -15,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
@ -83,7 +78,7 @@ __tx_vectors
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
@ -99,7 +94,7 @@ Reset_Handler
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -133,6 +128,9 @@ Reset_Handler
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@ -145,24 +143,24 @@ _tx_initialize_low_level
CPSID i
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADD r1, r1, #4 ;
ADD r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Enable the cycle count register. */
;
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Set system stack pointer from vector value. */
;
@ -193,11 +191,11 @@ _tx_initialize_low_level
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
@ -213,13 +211,13 @@ __user_initial_stackheap
;/* Define shells for each of the unused vectors. */
;
EXPORT __tx_BadHandler
__tx_BadHandler
__tx_BadHandler
B __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
@ -227,7 +225,7 @@ __tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
@ -246,7 +244,7 @@ __tx_SysTickHandler
BX LR
; }
EXPORT __tx_NMIHandler
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler

5
ports/cortex_m3/ac5/readme_threadx.txt
View File

@ -135,6 +135,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M3/AC5 port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC5 tools.

22
ports/cortex_m3/ac5/src/tx_thread_context_restore.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -15,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_exit
@ -38,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -71,6 +68,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)

24
ports/cortex_m3/ac5/src/tx_thread_context_save.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -15,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_isr_enter
@ -38,13 +33,15 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@ -70,6 +67,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@ -86,7 +86,7 @@ _tx_thread_context_save
ENDIF
;
; /* Return to interrupt processing. */
;
;
BX lr ; Return to interrupt processing caller
;}
ALIGN

19
ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -15,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -30,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -61,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@ -77,4 +77,3 @@ _tx_thread_interrupt_control
;
;}
END

18
ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -15,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -30,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -61,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

18
ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -15,14 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -30,7 +27,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -61,6 +58,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

60
ports/cortex_m3/ac5/src/tx_thread_schedule.s
View File

@ -2,6 +2,11 @@
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
@ -16,15 +21,6 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
IMPORT _tx_thread_current_ptr
IMPORT _tx_thread_execute_ptr
IMPORT _tx_timer_time_slice
@ -32,7 +28,7 @@
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
IMPORT _tx_execution_thread_exit
ENDIF
;
;
@ -43,7 +39,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -77,6 +73,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@ -89,7 +88,7 @@ _tx_thread_schedule
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@ -97,7 +96,7 @@ _tx_thread_schedule
; /* Enable the interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
@ -107,21 +106,21 @@ _tx_thread_schedule
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context switching PendSV handler. */
;
;
EXPORT __tx_PendSVHandler
EXPORT PendSV_Handler
__tx_PendSVHandler
__tx_PendSVHandler
PendSV_Handler
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@ -139,7 +138,7 @@ __tx_ts_handler
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@ -163,10 +162,10 @@ __tx_ts_handler
; /* Clear the global time-slice. */
;
STR r3, [r4] ; Clear time-slice
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new
__tx_ts_new
;
; /* Now we are looking for a new thread to execute! */
;
@ -181,7 +180,7 @@ __tx_ts_new
;
; /* Increment the thread run count. */
;
__tx_ts_restore
__tx_ts_restore
LDR r7, [r1, #4] ; Pickup the current thread run count
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
LDR r5, [r1, #24] ; Pickup thread's current time-slice
@ -209,14 +208,14 @@ __tx_ts_restore
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
BX lr ; Return to thread!
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait
__tx_ts_wait
CPSID i ; Disable interrupts
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
@ -229,20 +228,19 @@ __tx_ts_wait
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready
__tx_ts_ready
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
ALIGN
LTORG
END

12
ports/cortex_m3/ac5/src/tx_thread_stack_build.s
View File

@ -31,7 +31,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -64,6 +64,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -71,11 +74,11 @@
EXPORT _tx_thread_stack_build
_tx_thread_stack_build
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M3 should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@ -135,4 +138,3 @@ _tx_thread_stack_build
BX lr ; Return to caller
;}
END

24
ports/cortex_m3/ac5/src/tx_thread_system_return.s
View File

@ -15,16 +15,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
AREA ||.text||, CODE, READONLY
;/**************************************************************************/
@ -32,7 +22,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -65,6 +55,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@ -72,9 +65,9 @@
EXPORT _tx_thread_system_return
_tx_thread_system_return
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@ -85,7 +78,6 @@ _tx_thread_system_return
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

23
ports/cortex_m3/ac5/src/tx_timer_interrupt.s
View File

@ -15,17 +15,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
IMPORT _tx_timer_time_slice
IMPORT _tx_timer_system_clock
@ -48,7 +37,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M3/AC5 */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -83,6 +72,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@ -106,7 +98,7 @@ _tx_timer_interrupt
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@ -223,13 +215,13 @@ __tx_timer_dont_activate
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@ -263,4 +255,3 @@ __tx_timer_nothing_expired
ALIGN
LTORG
END

40
ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
@ -57,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -91,6 +81,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@ -104,17 +97,17 @@ _tx_initialize_low_level:
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address
ADD r1, r1, #4 @
ADD r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Setup Vector Table Offset Register. */
@
@
MOV r0, #0xE000E000 @ Build address of NVIC registers
LDR r1, =vector_table @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
STR r1, [r0, #0xD08] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
@ -128,7 +121,7 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
ORR r1, r1, #1 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
STR r1, [r0] @ Enable the cycle count register
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
@ -150,11 +143,11 @@ _tx_initialize_low_level:
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@
BX lr
@}
@
@ -190,7 +183,7 @@ __tx_IntHandler:
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter @ Call the ISR enter function
#endif
#endif
@ /* Do interrupt handler work here */
@ /* BL <your C Function>.... */
@ -226,7 +219,7 @@ SysTick_Handler:
@ /* NMI, DBG handlers */
.global __tx_NMIHandler
.global __tx_NMIHandler
.thumb_func
__tx_NMIHandler:
B __tx_NMIHandler
@ -235,8 +228,3 @@ __tx_NMIHandler:
.thumb_func
__tx_DBGHandler:
B __tx_DBGHandler

5
ports/cortex_m3/ac6/readme_threadx.txt
View File

@ -146,6 +146,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M3/AC6 port. The following files were
changed/added for port specific version 6.0.2:
*.S Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC6 tools.

18
ports/cortex_m3/ac6/src/tx_thread_context_restore.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -48,13 +38,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -81,6 +73,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@ -92,4 +87,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

17
ports/cortex_m3/ac6/src/tx_thread_context_save.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -43,13 +33,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@ -75,6 +67,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

16
ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -37,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -68,6 +60,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@ -87,6 +82,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

44
ports/cortex_m3/ac6/src/tx_thread_schedule.S
View File

@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@ -44,7 +35,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -78,6 +69,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@ -91,7 +85,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOV r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@ -99,7 +93,7 @@ _tx_thread_schedule:
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
@ -109,14 +103,14 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
@
.global PendSV_Handler
.global __tx_PendSVHandler
.thumb_func
@ -125,8 +119,8 @@ PendSV_Handler:
__tx_PendSVHandler:
@
@ /* Get current thread value and new thread pointer. */
@
__tx_ts_handler:
@
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ -144,7 +138,7 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CBZ r1, __tx_ts_new @ If NULL, skip preservation
@
@ /* Recover PSP and preserve current thread context. */
@ -169,7 +163,7 @@ __tx_ts_handler:
@
STR r3, [r4] @ Clear time-slice
@
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
@ -215,11 +209,11 @@ __tx_ts_restore:
MSR PSP, r12 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
@ -235,16 +229,16 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
MOV r7, #0x08000000 @ Build clear PendSV value
MOV r8, #0xE000E000 @ Build base NVIC address
STR r7, [r8, #0xD04] @ Clear any PendSV
STR r7, [r8, #0xD04] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread

22
ports/cortex_m3/ac6/src/tx_thread_stack_build.S
View File

@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -79,11 +73,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M3 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r4 Initial value for r4
@ r5 Initial value for r5
@ -142,5 +136,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

21
ports/cortex_m3/ac6/src/tx_thread_system_return.S
View File

@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text 32
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@ -79,9 +73,9 @@
.global _tx_thread_system_return
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
MOV r1, #0xE000E000 @ Load NVIC base
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
@ -92,7 +86,6 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

24
ports/cortex_m3/ac6/src/tx_timer_interrupt.S
View File

@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M3/AC6 */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@ -228,13 +220,13 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
@
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
@ -266,5 +258,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}

43
ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_initialize.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_stack_ptr
.global _tx_initialize_unused_memory
@ -59,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* FUNCTION RELEASE */
@/* */
@/* _tx_initialize_low_level Cortex-M3/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -96,6 +86,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */
@/* GNU assembly comment, */
@/* resulting in version 6.0.1 */
@/* 08-14-2020 William E. Lamie Modified Comment(s), clean */
@/* up whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_initialize_low_level(VOID)
@ -109,17 +102,17 @@ _tx_initialize_low_level:
CPSID i
@
@ /* Set base of available memory to end of non-initialised RAM area. */
@
@
LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADD r1, r1, #4 @
LDR r1, =__RAM_segment_used_end__ @ Build first free address
ADD r1, r1, #4 @
STR r1, [r0] @ Setup first unused memory pointer
@
@ /* Setup Vector Table Offset Register. */
@
@
MOV r0, #0xE000E000 @ Build address of NVIC registers
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
LDR r1, =_vectors @ Pickup address of vector table
STR r1, [r0, #0xD08] @ Set vector table address
@
@ /* Set system stack pointer from vector value. */
@
@ -133,7 +126,7 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 @ Build address of DWT register
LDR r1, [r0] @ Pickup the current value
ORR r1, r1, #1 @ Set the CYCCNTENA bit
STR r1, [r0] @ Enable the cycle count register
STR r1, [r0] @ Enable the cycle count register
@
@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@
@ -155,11 +148,10 @@ _tx_initialize_low_level:
LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers
@ Note: PnSV must be lowest priority, which is 0xFF
@
@ /* Return to caller. */
@
BX lr
@
BX lr
@}
@
@ -195,7 +187,7 @@ __tx_IntHandler:
PUSH {r0, lr}
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
BL _tx_execution_isr_enter @ Call the ISR enter function
#endif
#endif
@ /* Do interrupt handler work here */
@ /* BL <your C Function>.... */
@ -231,7 +223,7 @@ SysTick_Handler:
@ /* NMI, DBG handlers */
.global __tx_NMIHandler
.global __tx_NMIHandler
.thumb_func
__tx_NMIHandler:
B __tx_NMIHandler
@ -240,8 +232,3 @@ __tx_NMIHandler:
.thumb_func
__tx_DBGHandler:
B __tx_DBGHandler

5
ports/cortex_m3/gnu/readme_threadx.txt
View File

@ -143,6 +143,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M3/GNU port. The following files were
changed/added for port specific version 6.0.2:
*.S Modified comments and whitespace.
05/19/2020 Initial ThreadX 6.0 version for Cortex-M3 using GNU tools.

18
ports/cortex_m3/gnu/src/tx_thread_context_restore.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -49,13 +39,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M3/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function restores the interrupt context if it is processing a */
@/* nested interrupt. If not, it returns to the interrupt thread if no */
@/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -82,6 +74,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)
@ -93,4 +88,3 @@ _tx_thread_context_restore:
@ /* Not needed for this port - just return! */
BX lr
@}

17
ports/cortex_m3/gnu/src/tx_thread_context_save.S
View File

@ -20,16 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -44,13 +34,15 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M3/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function is only needed for legacy applications and it should */
@/* not be called in any new development on a Cortex-M. */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@ -76,6 +68,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

16
ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S
View File

@ -20,14 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@/* #define TX_SOURCE_CODE */
@/* Include necessary system files. */
@/* #include "tx_api.h"
#include "tx_thread.h" */
.text 32
.align 4
@ -37,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M3/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -68,6 +60,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)
@ -87,6 +82,3 @@ _tx_thread_interrupt_control:
BX lr @ Return to caller
@/* } */

43
ports/cortex_m3/gnu/src/tx_thread_schedule.S
View File

@ -21,15 +21,6 @@
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@#include "tx_timer.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
@ -46,7 +37,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -80,6 +71,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@ -93,7 +87,7 @@ _tx_thread_schedule:
@ from the PendSV handling routines below. */
@
@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
@
@
MOV r0, #0 @ Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag
STR r0, [r2, #0] @ Clear preempt disable flag
@ -101,7 +95,7 @@ _tx_thread_schedule:
@ /* Enable interrupts */
@
CPSIE i
@
@
@ /* Enter the scheduler for the first time. */
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
@ -111,14 +105,14 @@ _tx_thread_schedule:
ISB @ Flush pipeline
@
@ /* Wait here for the PendSV to take place. */
@
@
__tx_wait_here:
B __tx_wait_here @ Wait for the PendSV to happen
@}
@
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ /* Generic context switch-out switch-in handler... Note that this handler is
@ common for both PendSV and SVCall. */
@
@
.global PendSV_Handler
.global __tx_PendSVHandler
.thumb_func
@ -127,8 +121,8 @@ PendSV_Handler:
__tx_PendSVHandler:
@
@ /* Get current thread value and new thread pointer. */
@
__tx_ts_handler:
@
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ -146,7 +140,7 @@ __tx_ts_handler:
LDR r1, [r0] @ Pickup current thread pointer
@
@ /* Determine if there is a current thread to finish preserving. */
@
@
CBZ r1, __tx_ts_new @ If NULL, skip preservation
@
@ /* Recover PSP and preserve current thread context. */
@ -171,7 +165,7 @@ __tx_ts_handler:
@
STR r3, [r4] @ Clear time-slice
@
@
@
@ /* Executing thread is now completely preserved!!! */
@
__tx_ts_new:
@ -217,11 +211,11 @@ __tx_ts_restore:
MSR PSP, r12 @ Setup the thread's stack pointer
@
@ /* Return to thread. */
@
@
BX lr @ Return to thread!
@
@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
@ are disabled to allow use of WFI for waiting for a thread to arrive. */
@
__tx_ts_wait:
@ -237,16 +231,15 @@ __tx_ts_wait:
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
@ already in the handler! */
@
__tx_ts_ready:
MOV r7, #0x08000000 @ Build clear PendSV value
MOV r8, #0xE000E000 @ Build base NVIC address
STR r7, [r8, #0xD04] @ Clear any PendSV
STR r7, [r8, #0xD04] @ Clear any PendSV
@
@ /* Re-enable interrupts and restore new thread. */
@
@
CPSIE i @ Enable interrupts
B __tx_ts_restore @ Restore the thread

22
ports/cortex_m3/gnu/src/tx_thread_stack_build.S
View File

@ -20,15 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.text
.align 4
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M3/GNU */
@/* 6.0.1 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -76,6 +67,9 @@
@/* needed. Removed references */
@/* to stack frame, resulting */
@/* in version 6.0.1 */
@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -84,11 +78,11 @@
.thumb_func
_tx_thread_stack_build:
@
@
@
@ /* Build a fake interrupt frame. The form of the fake interrupt stack
@ on the Cortex-M3 should look like the following after it is built:
@
@ Stack Top:
@
@ Stack Top:
@ LR Interrupted LR (LR at time of PENDSV)
@ r4 Initial value for r4
@ r5 Initial value for r5
@ -147,5 +141,3 @@ _tx_thread_stack_build:
@ control block
BX lr @ Return to caller
@}

21
ports/cortex_m3/gnu/src/tx_thread_system_return.S
View File

@ -19,15 +19,6 @@
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@/* #define TX_SOURCE_CODE */
@
@
@/* Include necessary system files. */
@
@/* #include "tx_api.h"
@ #include "tx_thread.h"
@ #include "tx_timer.h" */
.text 32
@ -38,7 +29,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M3/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +62,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)
@ -79,9 +73,9 @@
.global _tx_thread_system_return
_tx_thread_system_return:
@
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ /* Return to real scheduler via PendSV. Note that this routine is often
@ replaced with in-line assembly in tx_port.h to improved performance. */
@
@
MOV r0, #0x10000000 @ Load PENDSVSET bit
MOV r1, #0xE000E000 @ Load NVIC base
STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR
@ -92,7 +86,6 @@ _tx_thread_system_return:
CPSIE i @ Enable interrupts
MSR PRIMASK, r1 @ Restore original interrupt posture
_isr_context:
BX lr @ Return to caller
BX lr @ Return to caller
@/* } */

24
ports/cortex_m3/gnu/src/tx_timer_interrupt.S
View File

@ -20,17 +20,6 @@
@/**************************************************************************/
@/**************************************************************************/
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_timer.h"
@#include "tx_thread.h"
@
@
@Define Assembly language external references...
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@ -51,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M3/GNU */
@/* 6.0 */
@/* 6.0.2 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -86,6 +75,9 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 08-14-2020 Scott Larson Modified comment(s), clean up */
@/* whitespace, resulting */
@/* in version 6.0.2 */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)
@ -110,7 +102,7 @@ _tx_timer_interrupt:
@ if (_tx_timer_time_slice)
@ {
@
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice
LDR r2, [r3, #0] @ Pickup time-slice
CMP r2, #0 @ Is it non-active?
BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing
@ -228,13 +220,13 @@ __tx_timer_dont_activate:
@ if (_tx_timer_expired_time_slice)
@ {
@
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired
LDR r2, [r3, #0] @ Pickup the actual flag
CMP r2, #0 @ See if the flag is set
BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing
@
@ /* Time slice interrupted thread. */
@ _tx_thread_time_slice();
@ _tx_thread_time_slice();
@
BL _tx_thread_time_slice @ Call time-slice processing
LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag
@ -266,5 +258,3 @@ __tx_timer_nothing_expired:
BX lr @ Return to caller
@
@}

51
ports/cortex_m3/iar/example_build/tx_initialize_low_level.s
View File

@ -20,42 +20,32 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_initialize_unused_memory
EXTERN _tx_timer_interrupt
EXTERN __vector_table
EXTERN _tx_execution_isr_enter
EXTERN _tx_execution_isr_exit
;
;
SYSTEM_CLOCK EQU 7200000
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
RSEG FREE_MEM:DATA
PUBLIC __tx_free_memory_start
__tx_free_memory_start
DS32 4
DS32 4
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -89,6 +79,9 @@ __tx_free_memory_start
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@ -102,7 +95,7 @@ _tx_initialize_low_level:
;
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area
LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer
STR r0, [r2, #0] ; Save first free memory address
@ -112,13 +105,13 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 ; Build address of DWT register
LDR r1, [r0] ; Pickup the current value
ORR r1, r1, #1 ; Set the CYCCNTENA bit
STR r1, [r0] ; Enable the cycle count register
STR r1, [r0] ; Enable the cycle count register
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__vector_table ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Set system stack pointer from vector value. */
;
@ -149,8 +142,8 @@ _tx_initialize_low_level:
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
@ -175,7 +168,5 @@ __tx_SysTickHandler:
POP {r0, lr}
BX LR
; }
END
END

5
ports/cortex_m3/iar/readme_threadx.txt
View File

@ -148,6 +148,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M3/IAR port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M3 using IAR's ARM tools.

25
ports/cortex_m3/iar/src/tx_thread_context_restore.s
View File

@ -21,33 +21,25 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_execution_isr_exit
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_execution_isr_exit
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
@ -74,6 +66,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
@ -94,4 +89,4 @@ _tx_thread_context_restore:
BX lr
;
;}
END
END

26
ports/cortex_m3/iar/src/tx_thread_context_save.s
View File

@ -21,33 +21,25 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_execution_isr_enter
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
EXTERN _tx_execution_isr_enter
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is only needed for legacy applications and it should */
;/* not be called in any new development on a Cortex-M. */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
@ -73,6 +65,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
@ -82,7 +77,7 @@ _tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
;
PUSH {r0, lr} ; Save return address
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, lr} ; Recover return address
@ -93,4 +88,3 @@ _tx_thread_context_save:
BX lr
;}
END

18
ports/cortex_m3/iar/src/tx_thread_interrupt_control.s
View File

@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
@ -83,4 +78,3 @@ _tx_thread_interrupt_control:
;
;}
END

17
ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s
View File

@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_disable(UINT new_posture)

17
ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s
View File

@ -20,23 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_restore Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -67,6 +59,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_interrupt_restore(UINT new_posture)

59
ports/cortex_m3/iar/src/tx_thread_schedule.s
View File

@ -21,32 +21,23 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
EXTERN _tx_thread_current_ptr
EXTERN _tx_thread_execute_ptr
EXTERN _tx_timer_time_slice
EXTERN _tx_thread_system_stack_ptr
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -80,6 +71,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@ -92,7 +86,7 @@ _tx_thread_schedule:
; from the PendSV handling routines below. */
;
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
;
;
MOV r0, #0 ; Build value for TX_FALSE
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
STR r0, [r2, #0] ; Clear preempt disable flag
@ -100,7 +94,7 @@ _tx_thread_schedule:
; /* Enable interrupts */
;
CPSIE i
;
;
; /* Enter the scheduler for the first time. */
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
@ -110,21 +104,21 @@ _tx_thread_schedule:
ISB ; Flush pipeline
;
; /* Wait here for the PendSV to take place. */
;
;
__tx_wait_here:
B __tx_wait_here ; Wait for the PendSV to happen
;}
;
; /* Generic context PendSV handler. */
;
;
PUBLIC PendSV_Handler
PUBLIC __tx_PendSVHandler
PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@ -142,7 +136,7 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@ -167,7 +161,7 @@ __tx_ts_handler:
;
STR r3, [r4] ; Clear time-slice
;
;
;
; /* Executing thread is now completely preserved!!! */
;
__tx_ts_new:
@ -213,11 +207,11 @@ __tx_ts_restore:
MSR PSP, r12 ; Setup the thread's stack pointer
;
; /* Return to thread. */
;
;
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
@ -233,18 +227,17 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
;
CPSIE i ; Enable interrupts
B __tx_ts_restore ; Restore the thread
;}
END

25
ports/cortex_m3/iar/src/tx_thread_stack_build.s
View File

@ -21,23 +21,14 @@
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -70,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@ -77,11 +71,11 @@
PUBLIC _tx_thread_stack_build
_tx_thread_stack_build:
;
;
;
; /* Build a fake interrupt frame. The form of the fake interrupt stack
; on the Cortex-M should look like the following after it is built:
;
; Stack Top:
;
; Stack Top:
; LR Interrupted LR (LR at time of PENDSV)
; r4 Initial value for r4
; r5 Initial value for r5
@ -141,4 +135,3 @@ _tx_thread_stack_build:
BX lr ; Return to caller
;}
END

28
ports/cortex_m3/iar/src/tx_thread_system_return.s
View File

@ -20,25 +20,15 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -71,6 +61,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
@ -79,9 +72,9 @@
_tx_thread_system_return??rA:
_tx_thread_system_return:
;
; /* Return to real scheduler via PendSV. Note that this routine is often
; /* Return to real scheduler via PendSV. Note that this routine is often
; replaced with in-line assembly in tx_port.h to improved performance. */
;
;
MOV r0, #0x10000000 ; Load PENDSVSET bit
MOV r1, #0xE000E000 ; Load NVIC base
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
@ -92,7 +85,6 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
END
END

27
ports/cortex_m3/iar/src/tx_timer_interrupt.s
View File

@ -20,17 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
EXTERN _tx_timer_time_slice
EXTERN _tx_timer_system_clock
@ -46,14 +35,14 @@
EXTERN _tx_thread_preempt_disable
;
;
SECTION `.text`:CODE:NOROOT(2)
THUMB
SECTION `.text`:CODE:NOROOT(2)
THUMB
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt Cortex-M3/IAR */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -87,6 +76,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@ -109,7 +101,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@ -226,13 +218,13 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
@ -265,4 +257,3 @@ __tx_timer_nothing_expired:
;
;}
END

2
ports/cortex_m3/keil/example_build/sample_threadx.c
View File

@ -43,7 +43,7 @@ UCHAR thread_5_stack[DEMO_STACK_SIZE];
/* Define the queue area. */
UCHAR queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)];
UCHAR queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)];
/* Define thread prototypes. */

42
ports/cortex_m3/keil/example_build/tx_initialize_low_level.s
View File

@ -20,16 +20,6 @@
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_initialize.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_initialize_unused_memory
@ -88,7 +78,6 @@ __tx_vectors
DCD __tx_IntHandler ; Int 1
DCD __tx_IntHandler ; Int 2
DCD __tx_IntHandler ; Int 3
;
;
AREA ||.text||, CODE, READONLY
@ -104,7 +93,7 @@ Reset_Handler
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level Cortex-M3/RVDS */
;/* 6.0.1 */
;/* 6.0.2 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@ -138,6 +127,9 @@ Reset_Handler
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* 08-14-2020 Scott Larson Modified comment(s), clean up */
;/* whitespace, resulting */
;/* in version 6.0.2 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
@ -150,24 +142,24 @@ _tx_initialize_low_level
CPSID i
;
; /* Set base of available memory to end of non-initialised RAM area. */
;
;
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
ADD r1, r1, #4 ;
ADD r1, r1, #4 ;
STR r1, [r0] ; Setup first unused memory pointer
;
; /* Setup Vector Table Offset Register. */
;
;
MOV r0, #0xE000E000 ; Build address of NVIC registers
LDR r1, =__tx_vectors ; Pickup address of vector table
STR r1, [r0, #0xD08] ; Set vector table address
STR r1, [r0, #0xD08] ; Set vector table address
;
; /* Enable the cycle count register. */
;
; LDR r0, =0xE0001000 ; Build address of DWT register
; LDR r1, [r0] ; Pickup the current value
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
; STR r1, [r0] ; Enable the cycle count register
; STR r1, [r0] ; Enable the cycle count register
;
; /* Set system stack pointer from vector value. */
;
@ -198,11 +190,11 @@ _tx_initialize_low_level
; Note: PnSV must be lowest priority, which is 0xFF
;
; /* Return to caller. */
;
BX lr
;
BX lr
;}
;
;
;
;/* Define initial heap/stack routine for the ARM RVCT startup code.
; This routine will set the initial stack and heap locations */
;
@ -218,13 +210,13 @@ __user_initial_stackheap
;/* Define shells for each of the unused vectors. */
;
EXPORT __tx_BadHandler
__tx_BadHandler
__tx_BadHandler
B __tx_BadHandler
EXPORT __tx_SVCallHandler
__tx_SVCallHandler
B __tx_SVCallHandler
B __tx_SVCallHandler
EXPORT __tx_IntHandler
@ -232,7 +224,7 @@ __tx_IntHandler
; VOID InterruptHandler (VOID)
; {
PUSH {r0, lr}
; /* Do interrupt handler work here */
; /* .... */
@ -251,7 +243,7 @@ __tx_SysTickHandler
BX LR
; }
EXPORT __tx_NMIHandler
EXPORT __tx_NMIHandler
__tx_NMIHandler
B __tx_NMIHandler
@ -262,5 +254,3 @@ __tx_DBGHandler
ALIGN
LTORG
END

5
ports/cortex_m3/keil/readme_threadx.txt
View File

@ -142,6 +142,11 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
08-14-2020 ThreadX update of Cortex-M3/Keil port. The following files were
changed/added for port specific version 6.0.2:
*.s Modified comments and whitespace.
06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using Keil tools.

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