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Update on 16 Dec 2022. Expand to see details.

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b5d5df511 #include tx_user.h in assembly files for cortex-m ports
33e04e3d5 initial port of MIPS SMP for GHS and GNU
2eda2c17d capitalize extensions for M23 asm files
21c354ccb Fix armv7-m MPU settings for corner case, unify txm_module_port.h files
4a1ff93f9 remove uneeded include for ac6
c823e91ff update riscv iar example for latest iar tools
5559d185d check module stack for overlap (not kernel stack)
efa9ce7b7 apply patch from mobileye to fix time slice processing
75fdcb722 Updated copy_armv7_cm.yml
de04b9904 initialize unused MPU settings so that aliasing will work
79b317b60 add config directory to IAR RISC-V port in order to use simulator
This commit is contained in:
Scott Larson 2022-12-16 08:16:32 +00:00
parent b42c5acd8b
commit 4e62226eea
148 changed files with 21660 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
common_modules/module_manager/src/txm_module_manager_thread_create.c
View File

@ -39,7 +39,7 @@
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_create PORTABLE C */
/* 6.1.3 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -91,6 +91,9 @@
/* added 64-bit support, */
/* added SMP support, */
/* resulting in version 6.1.3 */
/* xx-xx-xxxx Scott Larson Check module stack for */
/* overlap, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
@ -158,8 +161,8 @@ ULONG i;
}
/* Check the stack pointer to see if it overlaps with this thread's stack. */
if ((((UCHAR *) ((VOID *) stack_start)) <= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end))) &&
(((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start))))
if ((((UCHAR *) ((VOID *) stack_start)) <= ((UCHAR *) ((VOID *) next_thread -> tx_thread_module_stack_end))) &&
(((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_module_stack_start))))
{
/* Stacks overlap, clear the stack pointer to force a stack error below. */
stack_start = TX_NULL;

5
ports/cortex_m0/ac6/src/tx_thread_context_restore.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
@ -41,7 +42,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -76,6 +77,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)

5
ports/cortex_m0/ac6/src/tx_thread_context_save.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
@ -36,7 +37,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -70,6 +71,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

5
ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -61,6 +62,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)

5
ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_disable Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -60,6 +61,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_disable(VOID)

5
ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_restore Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -61,6 +62,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_interrupt_restore(UINT old_posture)

5
ports/cortex_m0/ac6/src/tx_thread_schedule.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
@ -43,7 +44,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/AC6 */
@/* 6.1.5 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -80,6 +81,8 @@
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)

5
ports/cortex_m0/ac6/src/tx_thread_stack_build.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.text
.align 4
@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -62,6 +63,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

5
ports/cortex_m0/ac6/src/tx_thread_system_return.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text
.align 4
@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -62,6 +63,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)

5
ports/cortex_m0/ac6/src/tx_timer_interrupt.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@ -40,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -75,6 +76,8 @@
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)

5
ports/cortex_m0/gnu/src/tx_thread_context_restore.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -42,7 +43,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_restore Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -80,6 +81,8 @@
@/* 09-30-2020 Scott Larson Modified comment(s), and */
@/* cleaned up whitespace, */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_restore(VOID)

5
ports/cortex_m0/gnu/src/tx_thread_context_save.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@ -34,7 +35,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_context_save Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -71,6 +72,8 @@
@/* 09-30-2020 Scott Larson Modified comment(s), and */
@/* cleaned up whitespace, */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_context_save(VOID)

7
ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_control Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -62,7 +63,9 @@
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_control(UINT new_posture)

5
ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_disable Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -62,6 +63,8 @@
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* UINT _tx_thread_interrupt_disable(VOID)

7
ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -30,7 +31,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_interrupt_restore Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -62,7 +63,9 @@
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_interrupt_restore(UINT old_posture)

5
ports/cortex_m0/gnu/src/tx_thread_schedule.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_thread_current_ptr
.global _tx_thread_execute_ptr
@ -41,7 +42,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/GNU */
@/* 6.1.5 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -80,6 +81,8 @@
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)

5
ports/cortex_m0/gnu/src/tx_thread_stack_build.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.text
.align 4
@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_stack_build Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -68,6 +69,8 @@
@/* to stack frame, clean up */
@/* whitespace, resulting */
@/* in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

5
ports/cortex_m0/gnu/src/tx_thread_system_return.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
#include "tx_user.h"
.text 32
.align 4
@ -29,7 +30,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_system_return Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -64,6 +65,8 @@
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@/* VOID _tx_thread_system_return(VOID)

7
ports/cortex_m0/gnu/src/tx_timer_interrupt.S
View File

@ -20,6 +20,7 @@
@/**************************************************************************/
@/**************************************************************************/
@
#include "tx_user.h"
@
.global _tx_timer_time_slice
.global _tx_timer_system_clock
@ -40,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_timer_interrupt Cortex-M0/GNU */
@/* 6.1 */
@/* 6.x */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@ -76,7 +77,9 @@
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* resulting in version 6.1 */
@/* xx-xx-xxxx Scott Larson Include tx_user.h, */
@/* resulting in version 6.x */
@/* */
@/**************************************************************************/
@VOID _tx_timer_interrupt(VOID)

5
ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S
View File

@ -20,6 +20,7 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
SYSTEM_CLOCK = 6000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@ -34,7 +35,7 @@ HEAP_SIZE = 0x00000000
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -68,6 +69,8 @@ HEAP_SIZE = 0x00000000
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)

2
ports/cortex_m23/ac6/src/tx_misra.S
View File

@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#define SHT_PROGBITS 0x1
.global __aeabi_memset

6
ports/cortex_m23/ac6/src/tx_thread_context_restore.s → ports/cortex_m23/ac6/src/tx_thread_context_restore.S
View File

@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports/cortex_m23/ac6/src/tx_thread_context_save.s → ports/cortex_m23/ac6/src/tx_thread_context_save.S
View File

@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

5
ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s → ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

5
ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s → ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

5
ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s → ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

5
ports/cortex_m23/ac6/src/tx_thread_schedule.s → ports/cortex_m23/ac6/src/tx_thread_schedule.S
View File

@ -20,6 +20,7 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_thread_enter
@ -30,7 +31,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M23/AC6 */
/* 6.1.6 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -69,6 +70,8 @@
/* 06-02-2021 Scott Larson Added secure stack initialize */
/* in SVC handler, */
/* resulting in version 6.1.7 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)

5
ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s → ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_allocate Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -58,6 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)

5
ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s → ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_free Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -56,6 +57,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)

5
ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */
/* 6.1.12 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -60,6 +61,8 @@
/* secure stack initialization */
/* macro to port-specific, */
/* resulting in version 6.1.12 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)

5
ports/cortex_m23/ac6/src/tx_thread_stack_build.s → ports/cortex_m23/ac6/src/tx_thread_stack_build.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

5
ports/cortex_m23/ac6/src/tx_thread_system_return.s → ports/cortex_m23/ac6/src/tx_thread_system_return.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

5
ports/cortex_m23/ac6/src/tx_timer_interrupt.s → ports/cortex_m23/ac6/src/tx_timer_interrupt.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-M23/AC6 */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -60,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

5
ports/cortex_m23/gnu/src/tx_initialize_low_level.S
View File

@ -20,6 +20,7 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
SYSTEM_CLOCK = 6000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
@ -34,7 +35,7 @@ HEAP_SIZE = 0x00000000
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -68,6 +69,8 @@ HEAP_SIZE = 0x00000000
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)

2
ports/cortex_m23/gnu/src/tx_misra.S
View File

@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#define SHT_PROGBITS 0x1
.global __aeabi_memset

6
ports/cortex_m23/gnu/src/tx_thread_context_restore.s → ports/cortex_m23/gnu/src/tx_thread_context_restore.S
View File

@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)

6
ports/cortex_m23/gnu/src/tx_thread_context_save.s → ports/cortex_m23/gnu/src/tx_thread_context_save.S
View File

@ -20,6 +20,8 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
@ -28,7 +30,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -58,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)

5
ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s → ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)

5
ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s → ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(VOID)

5
ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s → ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -57,6 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_interrupt_restore(UINT previous_posture)

5
ports/cortex_m23/gnu/src/tx_thread_schedule.s → ports/cortex_m23/gnu/src/tx_thread_schedule.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-M23/GNU */
/* 6.1.6 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -65,6 +66,8 @@
/* 06-02-2021 Scott Larson Added secure stack initialize */
/* in SVC handler, */
/* resulting in version 6.1.7 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)

5
ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s → ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_allocate Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -58,6 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size)

5
ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s → ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_free Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -56,6 +57,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr)

5
ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */
/* 6.1.12 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -60,6 +61,8 @@
/* secure stack initialization */
/* macro to port-specific, */
/* resulting in version 6.1.12 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_secure_stack_initialize(VOID)

5
ports/cortex_m23/gnu/src/tx_thread_stack_build.s → ports/cortex_m23/gnu/src/tx_thread_stack_build.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

5
ports/cortex_m23/gnu/src/tx_thread_system_return.s → ports/cortex_m23/gnu/src/tx_thread_system_return.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -59,6 +60,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)

5
ports/cortex_m23/gnu/src/tx_timer_interrupt.s → ports/cortex_m23/gnu/src/tx_timer_interrupt.S
View File

@ -20,13 +20,14 @@
/**************************************************************************/
/**************************************************************************/
#include "tx_user.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-M23/GNU */
/* 6.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@ -60,6 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* xx-xx-xxxx Scott Larson Include tx_user.h, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)

2
ports/xtensa/xcc/inc/xtensa_context.h
View File

@ -427,9 +427,11 @@ XSTRUCT_END(XtExcFrame)
addi a10, a1, -XT_STK_FRMSZ
s32i a10, a11, tx_thread_stack_ptr // save outgoing thread stack pointer
l32i a10, a12, 0 // a10 <- _tx_timer_time_slice
beqz a10, .Ldont_save_ts
s32i a10, a11, tx_thread_time_slice // save outgoing time slice value
movi a10, 0
s32i a10, a12, 0 // disable time slice
.Ldont_save_ts:
s32i a10, a11, tx_thread_solicited // mark as preempted
s32i a10, a8, 0 // Clear _tx_thread_current_ptr
#if XCHAL_CP_NUM > 0

99
ports_smp/mips32_interaptiv_smp/gnu/example_build/boot.h Normal file
View File

@ -0,0 +1,99 @@
/*
* boot.h
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define END(name)\
.##size name,.-name;\
.##end name
#define GCR_CONFIG_ADDR 0xbfbf8000 // KSEG0 address of the GCR registers
#define GIC_P_BASE_ADDR 0x1bdc0000 // physical address of the GIC
#define GIC_BASE_ADDR 0xbbdc0000 // KSEG0 address address of the GIC
#define CPC_P_BASE_ADDR 0x1bde0001 // physical address of the CPC
#define CPC_BASE_ADDR 0xbbde0000 // KSEG0 address address of the CPC
#define DENALI_CTL_SECTION 0xbbc00000
#define MALTA_DISP_ADDR 0xbf000410
#define STACK_BASE_ADDR 0x82000000 /* Change: Base on memory size. */
#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
/**************************************************************************************
Register use while executing in this file: ("GLOBAL" denotes a common value.)
**************************************************************************************/
#define r1_all_ones $1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
// $2 - $7 (v0, v1 a0 - a3) reserved for program use
#define r8_core_num $8 /* t0 Core number. Only core 0 is active after reset. */
#define r9_vpe_num $9 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */
#define r10_has_mt_ase $10 /* t2 Core implements the MT ASE. */
#define r11_is_cps $11 /* t3 Core is part of a Coherent Processing System. */
// $12 - $15 (t4 - t7) are free to use
// $16, $17 (s0 and s1) reserved for program use
#define r18_tc_num $18 /* s2 MT ASE TC number (0 if non-MT.) */
#define r19_more_cores $19 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */
#define r20_more_vpes $20 /* s4 Number of vpes in this core in addition to vpe 0. */
#define r21_more_tcs $21 /* s5 Number of tcs in vpe in addition to the first. */
#define r22_gcr_addr $22 /* s6 Uncached (kseg1) base address of the Global Config Registers. */
#define r23_cpu_num $23 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
#define r24_malta_word $24 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
#define r25_coreid $25 /* t9 Copy of cp0 PRiD GLOBAL! */
#define r26_int_addr $26 /* k0 Interrupt handler scratch address. */
#define r27_int_data $27 /* k1 Interrupt handler scratch data. */
// $28 gp and $29 sp
#define r30_cpc_addr $30 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */
// $31 ra

247
ports_smp/mips32_interaptiv_smp/gnu/example_build/build_threadx.bat Normal file
View File

@ -0,0 +1,247 @@
del tx.a
mips-sde-elf-gcc -c -g -mmt -EL tx_initialize_low_level.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_stack_build.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_schedule.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_system_return.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_context_save.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_context_restore.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_interrupt_control.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_core_get.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_core_preempt.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_current_state_get.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_current_thread_get.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_initialize_wait.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_low_level_initialize.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_protect.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_time_get.S
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_unprotect.S
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_interrupt.S
mips-sde-elf-gcc -c -g -mmt -EL tx_block_allocate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_cleanup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_pool_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_block_release.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_allocate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_cleanup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_pool_search.c
mips-sde-elf-gcc -c -g -mmt -EL tx_byte_release.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_cleanup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_set.c
mips-sde-elf-gcc -c -g -mmt -EL tx_event_flags_set_notify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_initialize_high_level.c
mips-sde-elf-gcc -c -g -mmt -EL tx_initialize_kernel_enter.c
mips-sde-elf-gcc -c -g -mmt -EL tx_initialize_kernel_setup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_cleanup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_priority_change.c
mips-sde-elf-gcc -c -g -mmt -EL tx_mutex_put.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_cleanup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_flush.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_front_send.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_receive.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_send.c
mips-sde-elf-gcc -c -g -mmt -EL tx_queue_send_notify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_ceiling_put.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_cleanup.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_put.c
mips-sde-elf-gcc -c -g -mmt -EL tx_semaphore_put_notify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_entry_exit_notify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_identify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_preemption_change.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_priority_change.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_relinquish.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_reset.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_resume.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_shell_entry.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_sleep.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_core_exclude.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_core_exclude_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_current_state_set.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_debug_entry_insert.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_high_level_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_rebalance_execute_list.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_smp_utilities.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_stack_analyze.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_stack_error_handler.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_stack_error_notify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_suspend.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_system_preempt_check.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_system_resume.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_system_suspend.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_terminate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_time_slice.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_time_slice_change.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_timeout.c
mips-sde-elf-gcc -c -g -mmt -EL tx_thread_wait_abort.c
mips-sde-elf-gcc -c -g -mmt -EL tx_time_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_time_set.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_activate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_change.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_create.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_deactivate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_delete.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_expiration_process.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_performance_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_performance_system_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_system_activate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_system_deactivate.c
mips-sde-elf-gcc -c -g -mmt -EL tx_timer_thread_entry.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_enable.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_disable.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_initialize.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_interrupt_control.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_isr_enter_insert.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_isr_exit_insert.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_object_register.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_object_unregister.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_user_event_insert.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_buffer_full_notify.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_event_filter.c
mips-sde-elf-gcc -c -g -mmt -EL tx_trace_event_unfilter.c
mips-sde-elf-gcc -c -g -mmt -EL txe_block_allocate.c
mips-sde-elf-gcc -c -g -mmt -EL txe_block_pool_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_block_pool_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_block_pool_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_block_pool_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL txe_block_release.c
mips-sde-elf-gcc -c -g -mmt -EL txe_byte_allocate.c
mips-sde-elf-gcc -c -g -mmt -EL txe_byte_pool_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_byte_pool_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_byte_pool_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_byte_pool_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL txe_byte_release.c
mips-sde-elf-gcc -c -g -mmt -EL txe_event_flags_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_event_flags_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_event_flags_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_event_flags_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_event_flags_set.c
mips-sde-elf-gcc -c -g -mmt -EL txe_event_flags_set_notify.c
mips-sde-elf-gcc -c -g -mmt -EL txe_mutex_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_mutex_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_mutex_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_mutex_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_mutex_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL txe_mutex_put.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_flush.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_front_send.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_receive.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_send.c
mips-sde-elf-gcc -c -g -mmt -EL txe_queue_send_notify.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_ceiling_put.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_prioritize.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_put.c
mips-sde-elf-gcc -c -g -mmt -EL txe_semaphore_put_notify.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_entry_exit_notify.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_info_get.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_preemption_change.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_priority_change.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_relinquish.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_reset.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_resume.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_suspend.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_terminate.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_time_slice_change.c
mips-sde-elf-gcc -c -g -mmt -EL txe_thread_wait_abort.c
mips-sde-elf-gcc -c -g -mmt -EL txe_timer_activate.c
mips-sde-elf-gcc -c -g -mmt -EL txe_timer_change.c
mips-sde-elf-gcc -c -g -mmt -EL txe_timer_create.c
mips-sde-elf-gcc -c -g -mmt -EL txe_timer_deactivate.c
mips-sde-elf-gcc -c -g -mmt -EL txe_timer_delete.c
mips-sde-elf-gcc -c -g -mmt -EL txe_timer_info_get.c
mips-sde-elf-ar -r tx.a tx_initialize_low_level.o tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
mips-sde-elf-ar -r tx.a tx_thread_smp_core_get.o tx_thread_smp_core_preempt.o tx_thread_smp_current_state_get.o tx_thread_smp_current_thread_get.o tx_thread_smp_initialize_wait.o
mips-sde-elf-ar -r tx.a tx_thread_smp_low_level_initialize.o tx_thread_smp_protect.o tx_thread_smp_time_get.o tx_thread_smp_unprotect.o
mips-sde-elf-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
mips-sde-elf-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
mips-sde-elf-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
mips-sde-elf-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
mips-sde-elf-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
mips-sde-elf-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
mips-sde-elf-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
mips-sde-elf-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
mips-sde-elf-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
mips-sde-elf-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o
mips-sde-elf-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
mips-sde-elf-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
mips-sde-elf-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
mips-sde-elf-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
mips-sde-elf-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
mips-sde-elf-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
mips-sde-elf-ar -r tx.a tx_thread_smp_core_exclude.o tx_thread_smp_core_exclude_get.o tx_thread_smp_current_state_set.o tx_thread_smp_debug_entry_insert.o
mips-sde-elf-ar -r tx.a tx_thread_smp_high_level_initialize.o tx_thread_smp_rebalance_execute_list.o tx_thread_smp_utilities.o
mips-sde-elf-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
mips-sde-elf-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
mips-sde-elf-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
mips-sde-elf-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
mips-sde-elf-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o
mips-sde-elf-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
mips-sde-elf-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
mips-sde-elf-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o
mips-sde-elf-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o
mips-sde-elf-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o
mips-sde-elf-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
mips-sde-elf-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
mips-sde-elf-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
mips-sde-elf-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
mips-sde-elf-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o
mips-sde-elf-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
mips-sde-elf-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o

20
ports_smp/mips32_interaptiv_smp/gnu/example_build/build_threadx_demo.bat Normal file
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mips-sde-elf-gcc -c -g -mmt -EL -I. copy_c2_ram.S
mips-sde-elf-gcc -c -g -mmt -EL -I. demo_threadx.c
mips-sde-elf-gcc -c -g -mmt -EL -I. start.S
mips-sde-elf-gcc -c -g -mmt -EL -I. set_gpr_boot_values.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_gpr.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_tlb.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_itc.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_caches2.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_cp0.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_cm.S
mips-sde-elf-gcc -c -g -mmt -EL -I. release_mp.S
mips-sde-elf-gcc -c -g -mmt -EL -I. join_domain.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_gic.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_cpc.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_vpe1.S
mips-sde-elf-gcc -c -g -mmt -EL -I. init_CoreFPGA6_mem.S
mips-sde-elf-ld -EL copy_c2_ram.o start.o set_gpr_boot_values.o init_gpr.o init_tlb.o init_itc.o init_caches2.o init_cp0.o init_cm.o release_mp.o join_domain.o init_gic.o init_cpc.o init_vpe1.o demo_threadx.o libc.a tx.a -T demo_threadx.ld -o demo_threadx.out -M > demo_threadx.map
mips-sde-elf-objcopy -O srec demo_threadx.out demo_threadx.srec

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/*
* copy_c2_ram.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Copy code and data to ram then clear BSS
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <regdef.h>
#include <boot.h>
#define s1_all_ones s1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. */
#define a0_temp_data a0 /* a0 data to be moved */
#define a1_temp_addr a1 /* from address */
#define a2_temp_dest a2 /* to address */
#define a3_temp_mark a3 /* ending address */
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(copy_c2_ram)
li s1_all_ones, 0xffffffff
/* RAMHACK: Link addr == load addr. No copy of code from ROM to RAM required.
// Copy code and read-only/initialized data from FLASH to (uncached) RAM.
la a1_temp_addr, _zap1
ins a1_temp_addr, s1_all_ones, 29, 1
la a2_temp_dest, _ftext_ram
ins a2_temp_dest, s1_all_ones, 29, 1
la a3_temp_mark, _edata_ram
ins a3_temp_mark, s1_all_ones, 29, 1
beq a2_temp_dest, a3_temp_mark, zero_bss
nop
next_ram_word:
lw a0_temp_data, 0(a1_temp_addr)
sw a0_temp_data, 0(a2_temp_dest)
addiu a2_temp_dest, 4
bne a3_temp_mark, a2_temp_dest, next_ram_word
addiu a1_temp_addr, 4
*/
// RAMHACK: Zero sbss in addition to bss.
zero_sbss:
la a1_temp_addr, _start_sbss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_sbss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, zero_bss
nop
next_sbss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_sbss_word
nop
zero_bss:
la a1_temp_addr, _start_bss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_bss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, copy_c2_ram_done
nop
next_bss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_bss_word
nop
copy_c2_ram_done:
jr ra
nop
END(copy_c2_ram)

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/*
* cps.h
*
* Created on: May 1, 2012
* Author: MIPS TECHNOLOGIES, INC
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
/*
* This include file contains #defines for the memory mapped registers in a coherent Processing system
* of both single cores and multi threaded cores. It contains registers offset for all the registers,
* defines for the fields with in the registers and encodings for some of the fields.
*
* The fields in the registers are defined by a pair of #defines, one define is the starting bit position of
* the field and another, (with a "_S" appended to the name), is the size of the field. Here is an example of
* how you would use these #defines in the the extraction of a filed:
*
* li $5, GIC_BASE_ADDR # load GIC KSEG0 Address
* lw $4, GIC_SH_CONFIG($5) # Read the GIC_SH_CONFIG Register
* ext $4, NUMINTERRUPTS, NUMINTERRUPTS_S # Extract NUMINTERRUPTS
*
* The names for the registers and fields are usually the same as used in the Software Users Manual
* (SUM). The exceptions occur when the names would conflict with each other in that case the name
* is appended with something to make it unique.
*/
#ifndef CPS_H_
#define CPS_H_
// GCR Offset for GCR_CONFIG, field positions and field size
#define GCR_CONFIG 0x0000
#define NUM_ADDR_REGIONS 16
#define NUM_ADDR_REGIONS_S 4
#define NUMIOCU 8
#define NUMIOCU_S 4
#define PCORES 0
#define PCORES_S 8
// GCR Offset for GCR_BASE, field positions and field size
#define GCR_BASE 0x0008
#define GCR_BASE_ADDR 15
#define GCR_BASE_ADDR_S 17
#define CCA_DEFAULT_OVERRIDE_VALUE 5
#define CCA_DEFAULT_OVERRIDE_VALUE_S 3
#define CCA_DEFAULT_OVERRIDE_ENABLE 4
#define CCA_DEFAULT_OVERRIDE_ENABLE_S 1
#define CM_DEFAULT_TARGET 0
#define CM_DEFAULT_TARGET_S 2
// GCR Offset for GCR_CONTROL, field positions and field size
#define GCR_CONTROL 0x0010
#define SYNCCTL 16
#define SYNCCTL_S 1
#define CM_SYNC_TX_DISABLE 5
#define CM_SYNC_TX_DISABLE_S 1
#define CM_AUTO_CLR_IVU_EN 4
#define CM_AUTO_CLR_IVU_EN_S 1
#define CM_COHST_SH_ALWAYS_EN 3
#define CM_COHST_SH_ALWAYS_EN_S 1
#define CM_PARK_EN 2
#define CM_PARK_EN_S 1
#define CM_DISABLE_MMIO_LIMIT 1
#define CM_DISABLE_MMIO_LIMIT_S 1
#define CM_SPEC_READ_EN 0
#define CM_SPEC_READ_EN_S 1
// GCR Offset for GCR_CONTROL_2, field positions and field size
#define GCR_CONTROL2 0x0018
#define L2_CACHEOP_LIMIT 16
#define L2_CACHEOP_LIMIT_S 4
#define L1_CACHEOP_LIMIT 3
#define L1_CACHEOP_LIMIT_S 4
// GCR Offset for GCR_ACCESS, field positions and field size
#define GCR_ACCESS 0x0020
#define CM_ACCESS_EN 0
#define CM_ACCESS_EN_S 8
// GCR Offset for GCR_REV, field positions and field size
#define GCR_REV 0x0030
#define MAJOR_REV_GCR 8
#define MAJOR_REV_GCR_S 8
#define MINOR_REV_GCR 7
#define MINOR_REV_GCR_S 8
// GCR Offset for GCR_ERROR_MASK
#define GCR_ERROR_MASK 0x0040
// error type encoding
#define GC_WR_ERR 1
#define GC_RD_ERR 2
#define COH_WR_ERR 3
#define COH_RD_ERR 4
#define MMIO_WR_ERR 5
#define MMIO_RD_ERR 6
#define INTVN_WR_ERR 17
#define INTVN_RD_ERR 18
// GCR Offset for GCR_ERROR_CAUSE, field positions and field size
#define GCR_ERROR_CAUSE 0x0048
#define CM_ERROR_TYPE 27
#define CM_ERROR_TYPE_S 5
#define CM_ERROR_INFO 0
#define CM_ERROR_INFO_S 27
// Fields and sizes for Error Types 1 - 5
#define CCA 15
#define CCA_S 3
#define TARGET_REGION 12
#define TARGET_REGION_S 3
#define OCP_MCMD_ERROR 7
#define OCP MCMD_ERROR_S 5
#define SOURCE_TAGID 3
#define SOURCE_TAGID_S 4
#define SOURCE_PORT 0
#define SOURCE_PORT_S 3
// Fields for Error Types 16 - 17
#define COHERENT_STATE_CORE_3 19
#define COHERENT_STATE_CORE_3_S 2
#define INTERVENTION_SRESP_CORE3 18
#define INTERVENTION_SRESP_CORE3_S 1
#define COHERENT_STATE_CORE_2 16
#define COHERENT_STATE_CORE_2_S 2
#define INTERVENTION_SRESP_CORE2 15
#define INTERVENTION_SRESP_CORE2_S 1
#define COHERENT_STATE_CORE_1 13
#define COHERENT_STATE_CORE_1_S 2
#define INTERVENTION_SRESP_CORE1 12
#define INTERVENTION_SRESP_CORE1_S 1
#define COHERENT_STATE_CORE_0 10
#define COHERENT_STATE_CORE_0_S 2
#define INTERVENTION_SRESP_CORE0 9
#define INTERVENTION_SRESP_CORE0_S 1
#define FROM_STORE_CONDITIONAL 8
#define FROM_STORE_CONDITIONAL_S 1
#define OCP_MCMD 3
#define OCP_MCMD_S 5
#define SOURCE_PORT 0
#define SOURCE_PORT_S 3
// Coherent state encoding
#define CS_INVALID 0
#define CS_SHARED 1
#define CS_MODIFID 2
#define CS_EXCLUSIVE
// Intervention Response encoding
#define IR_OK 0
#define IR_DATA 1
// MCmd Encodings for CM_ERROR_INFO
#define LEGACY_WRITE 0x01
#define LEGACY_READ 0x02
#define COHERENT_READ_OWN 0x08
#define COHERENT_READ_SHARE 0x09
#define COHERENT_READ_DISCARD 0x0A
#define COHERENT_READ_SHARE_ALWAYS 0x0B
#define COHERENT_UPGRADE 0x0C
#define COHERENT_WRITEBACK 0x0D
#define COHERENT_COPYBACK 0x10
#define COHERENT_COPYBACK_INVALIADATE 0x11
#define COHERENT_INVALIADATE 0x12
#define COHERENT_WRITE_INVALIADATE 0x13
#define COHERENT_COMPLETION_SYNC 0x14
// GCR Offset for GCR_ERROR_ADDR
#define GCR_ERROR_ADDR 0x0050
// GCR Offset for GCR_ERROR_MULT
#define GCR_ERROR_MULT 0x0058
#define CM_ERROR_2ND 0
#define CM_ERROR_2ND_S 5
// GCR Offset for GCR_GIC_BASE, fields and sizes
#define GCR_GIC_BASE 0x0080
#define GIC_BASEADDRESS 17
#define GIC_BASEADDRESS_S 15
#define GIC_EN 0
#define GIC_EN_S 1
// GCR Offset for GCR_CPC_BAS, fields and sizes
#define GCR_CPC_BASE 0x0088
#define CPC_BASEADDRESS 15
#define CPC_BASEADDRESS_S 17
#define CPC_EN 0
#define CPC_EN_S 1
// GCR Offset for GCR_REGn_BASE, fields and sizes
#define GCR_REG0_BASE 0x0090
#define GCR_REG1_BASE 0x00A0
#define GCR_REG2_BASE 0x00B0
#define GCR_REG3_BASE 0x00C0
#define GCR_REG4_BASE 0x0190
#define GCR_REG5_BASE 0x01A0
#define CM_REGION_BASEADDRESS 16
#define CM_REGION_BASEADDRESS_S 16
// GCR Offset for GCR_REGn_MASK, fields, sizes and encodings
#define GCR_REG0_MASK 0x0098
#define GCR_REG1_MASK 0x00A8
#define GCR_REG2_MASK 0x00B8
#define GCR_REG3_MASK 0x00C8
#define GCR_REG4_MASK 0x0198
#define GCR_REG5_MASK 0x01A8
#define CM_REGION_ADDRESS_MASK 16
#define CM_REGION_ADDRESS_MASK_S 16
#define CCA_OVERRIDE_VALUE 5
#define CCA_OVERRIDE_VALUE_S 3
#define CCA_OVERRIDE_ENABLE 4
#define CCA_OVERRIDE_ENABLE_S 1
#define CM_REGION_TARGET 0
#define CM_REGION_TARGET_S 2
// CM_REGION_TARGET encoding
#define CM_REGION_TARGET_DISABLE 0x0
#define CM_REGION_TARGET_MEMORY 0x1
#define CM_REGION_TARGET_IOCU 0x2
// GCR Offset for GCR_GIC_STATUS, fields and sizes
#define GCR_GIC_STATUS 0x00D0
#define GIC_EX 0
#define GIC_EX_S 1
// GCR Offset for GCR_CACHE_REV, fields and sizes
#define GCR_CACHE_REV 0x00E0
#define MAJOR_REV_CACHE 8
#define MAJOR_REV_CACHE_S 8
#define MINOR_REV_CACHE 7
#define MINOR_REV_CACHE_S 8
// GCR Offset for GCR_CPC_STATUS, fields and sizes
#define GCR_CPC_STATUS 0x00F0
#define CPC_EX 0
#define CPC_EX_S 1
// GCR Offset for GCR_IOCU1_REV, fields and sizes
#define GCR_IOCU1_REV 0x0200
#define MAJOR_REV_IOCU 8
#define MAJOR_REV_IOCU_S 8
#define MINOR_REV_IOCU 7
#define MINOR_REV_IOCU_S 8
// GCR Core Local and Core other offsets
#define CORE_LOCAL_CONTROL_BLOCK 0x2000
#define CORE_OTHER_CONTROL_BLOCK 0x4000
// GCR Core Local and Other COHERENCE, fields and sizes
#define GCR_CL_COHERENCE 0x0008
#define GCR_CO_COHERENCE 0x0008
#define COH_DOMAIN_EN 0
#define COH_DOMAIN_EN_S 8
// GCR Core Local and Other CONFIG , fields and sizes
#define GCR_CL_CONFIG 0x0010
#define GCR_CO_CONFIG 0x0010
#define IOCU_TYPE 10
#define IOCU_TYPE_S 2
#define PVPE 0
#define PVPE_S 10
// GCR Core Local and Other OTHER, fields and sizes
#define GCR_CL_OTHER 0x0018
#define GCR_CO_OTHER 0x0018
#define OTHER_CORE_NUM 16
#define OTHER_CORE_NUM_S 16
// GCR Core Local and Other RESET_BASE, fields and sizes
#define GCR_CL_RESET_BASE 0x0020
#define GCR_CO_RESET_BASE 0x0020
#define BEV_EXCEPTION_BASE 12
#define BEV_EXCEPTION_BASE_S 20
// GCR Core Local and Other ID
#define GCR_CL_ID 0x0028
#define GCR_CO_ID 0x0028
// GCR Global Debug Block Offsets
#define Global_Debug_Block 0x6000
// GCR Global Debug GCR_DB_TCBCONTROLB, fields and sizes
#define GCR_DB_TCBCONTROLB 0x0008
#define WE_DB_TCBCONTROLB 31
#define WE_DB_TCBCONTROLB_S 1
#define TWSRC_WIDTH 26
#define TWSRC_WIDTH_S 2
#define TRPAD 18
#define TRPAD_S 1
#define RM 16
#define RM_S 1
#define TR 15
#define TR_S 1
#define BF 14
#define BF_S 1
#define TM 12
#define TM_S 2
#define CR 8
#define CR_S 3
#define CAL 7
#define CAL_S 1
#define OFC 1
#define OFC_S 1
#define FUNNEL_TRACE_ENABLE 0
#define FUNNEL_TRACE_ENABLE_S 1
// GCR Global Debug GCR_DB_TCBCONTROLD, fields and sizes
#define GCR_DB_TCBCONTROLD 0x0010
#define P4_CTL 24
#define P4_CTL_S 2
#define P3_CTL 22
#define P3_CTL_S 2
#define P2_CTL 20
#define P2_CTL_S 2
#define P1_CTL 18
#define P1_CTL_S 2
#define P0_CTL 16
#define P0_CTL_S 2
#define TW_SRC_VAL 8
#define TW_SRC_VAL_S 3
#define TRACE_WB 7
#define TRACE_WB_S 1
#define CM_INHIBIT_OVERFLOW 5
#define CM_INHIBIT_OVERFLOW_S 1
#define TLEV 3
#define TLEV_S 2
#define AE_PER_PORT 2
#define AE_PER_PORT_S 1
#define GLOBAL_CM_EN 1
#define GLOBAL_CM_EN_S 1
#define CM_EN 0
#define CM_EN_S 1
// GCR Global Debug GCR_DB_TCBCONTROLE, fields and sizes
#define GCR_DB_TCBCONTROLE 0x0020
#define TrIdle 8
#define TrIdle_S 1
#define PeC 0
#define PeC_S 1
// GCR Global Debug GCR_DB_TCBConfig, fields and sizes
#define GCR_DB_TCBCONFIG 0x0028
#define CF1 31
#define CF1_S 1
#define SZ 17
#define SZ_S 4
#define CRMAX 14
#define CRMAX_S 3
#define CRMIN 11
#define CRMIN_S 3
#define PW 9
#define PW_S 2
#define ONT 5
#define ONT_S 1
#define OFT 4
#define OFT_S 1
#define TCB_REV 0
#define TCB_REV_S 4
// GCR Global Debug GCR_DB_PC_CTL, fields and sizes
#define GCR_DB_PC_CTL 0x0100
#define PERF_INT_EN 30
#define PERF_INT_EN_S 1
#define PERF_OVF_STOP 29
#define PERF_OVF_STOP_S 1
#define P1_RESET 9
#define P1_RESET_S 1
#define P1_COUNT_ON 8
#define P1_COUNT_ON_S 1
#define P0_RESET 7
#define P0_RESET_S 1
#define P0_COUNT_ON 6
#define P0_COUNT_ON_S 1
#define CYCL_CNT_RESET 5
#define CYCL_CNT_RESET_S 1
#define CYCL_CNT__ON 4
#define CYCL_CNT__ON_S 1
#define PERF_NUM_CNT 0
#define PERF_NUM_CNT_S 4
// GCR Global Debug Read Pointer GCR_DB_TCBRDP
#define GCR_DB_TCBRDP 0x0108
// GCR Global Debug Write Pointer GCR_DB_TCBWDP
#define GCR_DB_TCBWRP 0x0110
// GCR Global Debug Start Pointer GCR_DB_TCBSTP
#define GCR_DB_TCBSTP 0x0118
// GCR_DB_PC_OV, fields and sizes
#define GCR_DB_PC_OV 0x0120
#define P1_OVERFLOW 2
#define P1_OVERFLOW_S 1
#define P0_OVERFLOW 1
#define P0_OVERFLOW_S 1_S 1
#define CYCL_CNT_OVERFLOW 0
#define CYCL_CNT_OVERFLOW_S 1
// GCR Global Debug GCR_DB_PC_EVENT, fields and sizes
#define GCR_DB_PC_EVENT 0x0130
#define P1_EVENT 8
#define P1_EVENT_S 8
#define P0_EVENT 0
#define P0_EVENT_S 8
// GCR Global Debug GCR_DB_PC_CYCLE
#define GCR_DB_PC_CYCLE 0x0180
// GCR Global Debug Qualifier and count registers
#define GCR_DB_PC_QUAL0 0x0190
#define GCR_DB_PC_CNT0 0x0198
#define GCR_DB_PC_QUAL1 0x01a0
#define GCR_DB_PC_CNT1 0x01a8
// GCR Global Debug Trace word access registers
#define GCR_DB_TCBTW_LO 0x0200
#define GCR_DB_TCBTW_HI 0x0208
// GIC Offsets within the Global interrupt controller
#define GIC_SH_CONFIG 0x0000
#define COUNTSTOP 28
#define COUNTSTOP_S 1
#define COUNTBITS 24
#define COUNTBITS_S 4
#define NUMINTERRUPTS 16
#define NUMINTERRUPTS_S 8
#define PVPES 0
#define PVPES_S 9
#define GIC_SH_CounterLo 0x0010
#define GIC_SH_CounterHi 0x0014
#define GIC_RevisionID 0x0020
#define GIC_SH_POL31_0 0x0100
#define GIC_SH_POL63_32 0x0104
#define GIC_SH_POL95_64 0x0108
#define GIC_SH_POL127_96 0x010c
#define GIC_SH_POL159_128 0x0110
#define GIC_SH_POL191_160 0x0114
#define GIC_SH_POL223_192 0x0118
#define GIC_SH_POL255_224 0x011c
#define GIC_SH_TRIG31_0 0x0180
#define GIC_SH_TRIG63_32 0x0184
#define GIC_SH_TRIG95_64 0x0188
#define GIC_SH_TRIG127_96 0x018c
#define GIC_SH_TRIG159_128 0x0190
#define GIC_SH_TRIG191_160 0x0194
#define GIC_SH_TRIG223_192 0x0198
#define GIC_SH_TRIG255_224 0x019c
#define GIC_SH_DUAL31_0 0x0200
#define GIC_SH_DUAL63_32 0x0204
#define GIC_SH_DUAL95_64 0x0208
#define GIC_SH_DUAL127_96 0x020c
#define GIC_SH_DUAL159_128 0x0210
#define GIC_SH_DUAL159_128 0x0210
#define GIC_SH_DUAL191_160 0x0214
#define GIC_SH_DUAL223_192 0x0218
#define GIC_SH_DUAL255_224 0x021c
#define GIC_SH_WEDGE 0x0280
#define GIC_SH_RMASK31_0 0x0300
#define GIC_SH_RMASK63_32 0x0304
#define GIC_SH_RMASK95_64 0x0308
#define GIC_SH_RMASK127_96 0x030c
#define GIC_SH_RMASK159_128 0x0310
#define GIC_SH_RMASK191_160 0x0314
#define GIC_SH_RMASK223_192 0x0318
#define GIC_SH_RMASK255_224 0x031c
#define GIC_SH_SMASK31_00 0x0380
#define GIC_SH_SMASK63_32 0x0384
#define GIC_SH_SMASK95_64 0x0388
#define GIC_SH_SMASK127_96 0x038c
#define GIC_SH_SMASK159_128 0x0390
#define GIC_SH_SMASK191_160 0x0394
#define GIC_SH_SMASK223_192 0x0398
#define GIC_SH_SMASK255_224 0x039c
#define GIC_SH_MASK31_00 0x0400
#define GIC_SH_MASK63_32 0x0404
#define GIC_SH_MASK95_64 0x0408
#define GIC_SH_MASK127_96 0x040c
#define GIC_SH_MASK159_128 0x0410
#define GIC_SH_MASK191_160 0x0414
#define GIC_SH_MASK223_192 0x0418
#define GIC_SH_MASK255_224 0x041c
#define GIC_SH_PEND31_00 0x0480
#define GIC_SH_PEND63_32 0x0484
#define GIC_SH_PEND95_64 0x0488
#define GIC_SH_PEND127_96 0x048c
#define GIC_SH_PEND159_128 0x0490
#define GIC_SH_PEND191_160 0x0494
#define GIC_SH_PEND223_192 0x0498
#define GIC_SH_PEND255_224 0x049c
// Global MAP to Pin GIC_SH_MAP_PIN + (4 x interrupt_source)
#define GIC_SH_MAP_PIN 0x0500
#define GIC_SH_MAP_SPACER 0x20
// Map source to VPEs 31 - 0 GIC_SH_MAP0_VPE31_0 + (0x20 x interrupt source)
#define GIC_SH_MAP0_VPE31_0 0x2000
// Map source to VPEs 63 - 32 GIC_SH_MAP0_VPE63_32 + (0x20 x interrupt source)
#define GIC_SH_MAP0_VPE63_32 0x2004
// Map source to core 31 - 0 GIC_SH_MAP0_CORE31_0 + (0x20 x interrupt source)
#define GIC_SH_MAP0_CORE31_0 0x2000
// Map source to core 63 - 32 GIC_SH_MAP0_CORE63_32 + (0x20 x interrupt source)
#define GIC_SH_MAP0_CORE63_32 0x2004
#define GIC_VB_DINT_SEND 0x6000
// GIC VPE Local offsets (note the VPEL)
#define GIC_VPE_LOCAL_SECTION_OFFSET 0x8000
#define GIC_VPEL_CTL 0x0000
#define GIC_VPEL_PEND 0x0004
#define GIC_VPEL_MASK 0x0008
#define GIC_VPEL_RMASK 0x000c
#define GIC_VPEL_SMASK 0x0010
#define GIC_VPEL_WD_MAP 0x0040
#define GIC_VPEL_COMPARE_MAP 0x0044
#define GIC_VPEL_TIMER_MAP (0x0048 )
#define GIC_VPEL_FDC_MAP 0x004c
#define GIC_VPEL_PERFCTR_MAP 0x0050
#define GIC_VPEL_SWInt0_MAP 0x0054
#define GIC_VPEL_SWInt1_MAP 0x0058
#define GIC_VPEL_OTHER_ADDR 0x0080
#define GIC_VPEL_IDENT 0x0088
#define GIC_VPEL_WD_CONFIG0 0x0090
#define GIC_VPEL_WD_COUNT0 0x0094
#define GIC_VPEL_WD_INITIAL0 0x0098
#define GIC_VPEL_CompareLo 0x00A0
#define GIC_VPEL_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_VPEL_EICSS + (4 x interrupt number)
#define GIC_VPEL_EICSS 0x0100
#define GIC_VL_DINT_PART 0x3000
#define GIC_VL_BRK_GROUP 0x3080
// GIC VPE Other offsets (note the VPEO)
#define GIC_VPE_OTHER_SECTION_OFFSET 0xc000
#define GIC_VPEO_CTL 0x0000
#define GIC_VPEO_PEND 0x0004
#define GIC_VPEO_MASK 0x0008
#define GIC_VPEO_RMASK 0x000c
#define GIC_VPEO_SMASK 0x0010
#define GIC_VPEO_WD_MAP 0x0040
#define GIC_VPEO_COMPARE_MAP 0x0044
#define GIC_VPEO_TIMER_MAP 0x0048
#define GIC_VPEO_FDC_MAP 0x004c
#define GIC_VPEO_PERFCTR_MAP 0x0050
#define GIC_VPEO_SWInt0_MAP 0x0054
#define GIC_VPEO_SWInt1_MAP 0x0058
#define GIC_VPEO_OTHER_ADDR 0x0080
#define GIC_VPEO_IDENT 0x0088
#define GIC_VPEO_WD_CONFIG0 0x0090
#define GIC_VPEO_WD_COUNT0 0x0094
#define GIC_VPEO_WD_INITIAL0 0x0098
#define GIC_VPEO_CompareLo 0x00A0
#define GIC_VPEO_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_VPEO_EICSS + (4 x interrupt number)
#define GIC_VPEO_EICSS 0x0100
#define GIC_VO_DINT_PART 0x3000
#define GIC_VO_BRK_GROUP 0x3080
// GIC CORE Local offsets (note the COREL)
#define GIC_CORE_LOCAL_SECTION_OFFSET 0x8000
#define GIC_COREL_CTL 0x0000
#define GIC_COREL_PEND 0x0004
#define GIC_COREL_MASK 0x0008
#define GIC_COREL_RMASK 0x000c
#define GIC_COREL_SMASK 0x0010
#define GIC_COREL_WD_MAP 0x0040
#define GIC_COREL_COMPARE_MAP 0x0044
#define GIC_COREL_TIMER_MAP 0x0048
#define GIC_COREL_FDC_MAP 0x004c
#define GIC_COREL_PERFCTR_MAP 0x0050
#define GIC_COREL_SWInt0_MAP 0x0054
#define GIC_COREL_SWInt1_MAP 0x0058
#define GIC_COREL_OTHER_ADDR 0x0080
#define GIC_COREL_IDENT 0x0088
#define GIC_COREL_WD_CONFIG0 0x0090
#define GIC_COREL_WD_COUNT0 0x0094
#define GIC_COREL_WD_INITIAL0 0x0098
#define GIC_COREL_CompareLo 0x00A0
#define GIC_COREL_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_COREL_EICSS + (4 x interrupt number)
#define GIC_COREL_EICSS 0x0100
#define GIC_COREL_DINT_PART 0x3000
#define GIC_COREL_BRK_GROUP 0x3080
// GIC CORE Other offsets (note the COREO)
#define GIC_CORE_OTHER_SECTION_OFFSET 0xc000
#define GIC_COREO_CTL 0x0000
#define GIC_COREO_PEND 0x0004
#define GIC_COREO_MASK 0x0008
#define GIC_COREO_RMASK 0x000c
#define GIC_COREO_SMASK 0x0010
#define GIC_COREO_WD_MAP 0x0040
#define GIC_COREO_COMPARE_MAP 0x0044
#define GIC_COREO_TIMER_MAP 0x0048
#define GIC_COREO_FDC_MAP 0x004c
#define GIC_COREO_PERFCTR_MAP 0x0050
#define GIC_COREO_SWInt0_MAP 0x0054
#define GIC_COREO_SWInt1_MAP 0x0058
#define GIC_COREO_OTHER_ADDR 0x0080
#define GIC_COREO_IDENT 0x0088
#define GIC_COREO_WD_CONFIG0 0x0090
#define GIC_COREO_WD_COUNT0 0x0094
#define GIC_COREO_WD_INITIAL0 0x0098
#define GIC_COREO_CompareLo 0x00A0
#define GIC_COREO_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_COREO_EICSS + (4 x interrupt number)
#define GIC_COREO_EICSS 0x0100
#define GIC_COREO_DINT_PART 0x3000
#define GIC_COREO_BRK_GROUP 0x3080
// Bit fields for Local Interrupt Control Register (GIC_COREi_CTL) or for MT (GIC_VPEi_CTL) or
#define FDC_ROUTABLE 4
#define FDC_ROUTABLE_S 1
#define SWINT_ROUTABLE 3
#define SWINT_ROUTABLE_S 1
#define PERFCOUNT_ROUTABLE 2
#define PERFCOUNT_ROUTABLE_S 1
#define TIMER_ROUTABLE 1
#define TIMER_ROUTABLE_S 1
#define EIC_MODE 0
#define EIC_MODE_S 1
// Bit fields for Local Interrupt Pending Registers (GIC_COREi_PEND) or for MT (GIC_VPEi_PEND)
#define FDC_PEND 6
#define FDC_PEND_S 1
#define SWINT1_PEND 5
#define SWINT1_PEND_S 1
#define SWINT0_PEND 4
#define SWINT0_PEND_S 1
#define PERFCOUNT_PEND 3
#define PERFCOUNT_PEND_S 1
#define TIMER_PEND 2
#define TIMER_PEND_S 1
#define COMPARE_PEND 1
#define COMPARE_PEND_S 1
#define WD_PEND 0
#define WD_PEND_S 1
// Bit fields for Local Interrupt Mask Registers (GIC_COREi_MASK) or for MT (GIC_VPEi_MASK)
#define FDC_MASK 6
#define FDC_MASK_S 1
#define SWINT1_MASK 5
#define SWINT1_MASK_S 1
#define SWINT0_MASK 4
#define SWINT0_MASK_S 1
#define PERFCOUNT_MASK 3
#define PERFCOUNT_MASK_S 1
#define TIMER_MASK 2
#define TIMER_MASK_S 1
#define COMPARE_MASK 1
#define COMPARE_MASK_S 1
#define WD_MASK 0
#define WD_MASK_S 1
// Bit fields for Local Interrupt Reset Mask Registers (GIC_COREi_RMASK) or for MT (GIC_VPEi_RMASK)
#define FDC_MASK_RESET 6
#define FDC_MASK_RESET_S 1
#define SWINT1_MASK_RESET 5
#define SWINT1_MASK_RESET_S 1
#define SWINT0_MASK_RESET 4
#define SWINT0_MASK_RESET_S 1
#define PERFCOUNT_MASK_RESET 3
#define PERFCOUNT_MASK_RESET_S 1
#define TIMER_MASK_RESET 2
#define TIMER_MASK_RESET_S 1
#define COMPARE_MASK_RESET 1
#define COMPARE_MASK_RESET_S 1
#define WD_MASK_RESET 0
#define WD_MASK_RESET_S 1
// Bit fields for Local Interrupt Set Mask Registers (GIC_COREi_SMASK) or for MT (GIC_VPEi_SMASK)
#define FDC_MASK_SET 6
#define FDC_MASK_SET_S 1
#define SWINT1_MASK_SET 5
#define SWINT1_MASK_SET_S 1
#define SWINT0_MASK_SET 4
#define SWINT0_MASK_SET_S 1
#define PERFCOUNT_MASK_SET 3
#define PERFCOUNT_MASK_SET_S 1
#define TIMER_MASK_SET 2
#define TIMER_MASK_SET_S 1
#define COMPARE_MASK_SET 1
#define COMPARE_MASK_SET_S 1
#define WD_MASK_SET 0
#define WD_MASK_SET_S 1
// Bit fields for CORE-Other or for MT VPE-Other Addressing Register
#define VPENum 0
#define VPENum_S 16
#define CORENum 0
#define CORENum_S 16
// Bit fields for Core-Local Identification Register (GIC_COREi_IDENT) or for MT (GIC_VPEi_IDENT)
#define VPENumIDENT 0
#define VPENumIDENT_S 32
#define CORENumIDENT 0
#define CORENumIDENT_S 32
// Bit fields for Local EIC Shadow Set Registers (GIC_COREi_EICSSj) or for MT (GIC_VPEi_EICSSj)
#define EIC_SS 0
#define EIC_SS_S 4
// Bit fields for Local WatchDog/Compare/PerfCount/SWIntx Map to Pin Registers
#define MAP_TO_PIN 31
#define MAP_TO_PIN_S 1
#define MAP_TO_NMI 30
#define MAP_TO_NMI_S 1
#define MAP_TO_YQ 29
#define MAP_TO_YQ_S 1
#define MAP 0
#define MAP_S 6
// Bit fields for Watchdog Timer Config Register (GIC_COREi_WD_CONFIGk) or for MT (GIC_VPEi_WD_CONFIGk)
#define WDRESET 7
#define WDRESET_S 1
#define WDINTR 6
#define WDINTR_S 1
#define WAITMODE_CNTRL 5
#define WAITMODE_CNTRL_S 1
#define DEBUGMODE_CNTRL 5
#define DEBUGMODE_CNTRL_S 1
#define TYPE 1
#define TYPE_S 3
// TYPE Filed encoding:
#define WD_One_Trip_Mode 0
#define WD_Second_Countdown_Mode 1
#define PIT_Mode 2
// Bit fields for Local DINT Group Participate Register (GIC_Cx_DINT_PART) or for MT (GIC_Vx_DINT_PART)
#define DINT_Group_Particpate 0
#define DINT_Group_Particpate_S 1
// GIC, GIC User Mode Visible Section Offsets
#define USER_MODE_VISIBLE_SECTION_OFFSET 0x10000
#define GIC_SH_COUNTERLO 0x0000
#define GIC_SH_COUNTERHI 0x0004
// Cluster Power Controller Global Section
// CPC Block CPC_ACCESS_REG, fields and sizes
#define CPC_ACCESS_REG 0x000
#define CM_ACCESS_EN 0
#define CM_ACCESS_EN_S 8
// CPC Block CPC_SEQDEL_REG, fields and sizes
#define CPC_SEQDEL_REG 0x008
#define MICROSTEP 0
#define MICROSTEP_S 10
// CPC Block CPC_RAIL_REG, fields and sizes
#define CPC_RAIL_REG 0x010
#define RAILDELAY 0
#define RAILDELAY_S 10
// CPC Block CPC_RESETLEN_REG, fields and sizes
#define CPC_RESETLEN_REG 0x018
#define RESETLEN 0
#define RESETLEN_S 10
// CPC Block CPC_REVISION_REG, fields and sizes
#define CPC_REVISION_REG 0x020
#define MAJOR_REV_CPC 8
#define MAJOR_REV_CPC_S 8
#define MINOR_REV_CPC 0
#define MINOR_REV_CPC_S 8
// Cluster Power Controller Local and Other section
#define CPS_CORE_LOCAL_CONTROL_BLOCK 0x2000
#define CPS_CORE_OTHER_CONTROL_BLOCK 0x4000
// CPC Local and Other CPC_CMD_REG, command encoding
#define CPC_CMDL_REG 0x000
#define CPC_CMDO_REG 0x000
#define CLOCK_OFF 1
#define PWR_DOWN 2
#define PWR_UP 3
#define CPC_RESET 4
// CPC Local and Other CPC_STAT_CONF, fields, sizes and encodings
#define CPC_STATL_CONF_REG 0x008
#define CPC_STATO_CONF_REG 0x008
#define PWRUP_EVENT 23
#define PWRUP_EVENT_S 1
#define SEQ_STATE 19
#define SEQ_STATE_S 4
// sequencer state encodings
#define PWR_DOWN_STATE 0x0
#define VDD_OK_STATE 0x1
#define UP_DELAY_STATE 0x2
#define UCLK_OFF_STATE 0x3
#define CPC_RESET_STATE 0x4
#define CPC_RESET_DLY_STATE 0x5
#define NON_COHERENT_EXECUTION_STATE 0x6
#define COHERENT_EXECUTION_STATE 0x7
#define ISOLATE_STATE 0x8
#define CLR_BUS_STATE 0x8
#define DCLK_OFF_STATE 0xA
#define CLKGAT_IMPL 17
#define CLKGAT_IMPL_S 1
#define PWRDN_IMPL 16
#define PWRDN_IMPL_S 1
#define EJTAG_PROBE 15
#define EJTAG_PROBE_S 1
#define PWUP_POLICY 8
#define PWUP_POLICY_S 2
// Power up state encodings
#define POLICY_PWR_DOWN 0
#define POLICY_GO_CLOCK_OFF 1
#define PLOICY_PWR_UP 2
#define IO_TRFFC_EN 4
#define IO_TRFFC_EN_S 1
#define CPC_CMD_STATE 0
#define CPC_CMD_STATE_S 4
// CPC Local and Other Addressing Register CPC_OTHER_REG, field and size
#define CPC_OTHERL_REG 0x010
#define CPC_OTHERO_REG 0x010
#define CPC_CORENUM 16
#define CPC_CORENUM_S 8
#endif /* CPS_H_ */

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/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 4096
#define DEMO_BYTE_POOL_SIZE 40000
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define MALTA constants for accessing the display. */
#define MALTA_ASCIIWORD 0xBF000410 /* ASCIIWORD bit 32:0 */
#define MALTA_ASCIIPOS0 0xBF000418 /* ASCIIPOS0 bit 7:0 */
#define MALTA_ASCIIPOS1 0xBF000420 /* ASCIIPOS1 bit 7:0 */
#define MALTA_ASCIIPOS2 0xBF000428 /* ASCIIPOS2 bit 7:0 */
#define MALTA_ASCIIPOS3 0xBF000430 /* ASCIIPOS3 bit 7:0 */
#define MALTA_ASCIIPOS4 0xBF000438 /* ASCIIPOS4 bit 7:0 */
#define MALTA_ASCIIPOS5 0xBF000440 /* ASCIIPOS5 bit 7:0 */
#define MALTA_ASCIIPOS6 0xBF000448 /* ASCIIPOS6 bit 7:0 */
#define MALTA_ASCIIPOS7 0xBF000450 /* ASCIIPOS7 bit 7:0 */
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_THREAD lcd_thread;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
ULONG lcd_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
void lcd_thread_entry(ULONG thread_input);
#ifdef TX_ENABLE_EVENT_TRACE
UCHAR event_buffer[64000];
#endif
/* Define main entry point. */
int main()
{
/* Indicate ThreadX is being entered. */
*((ULONG *) MALTA_ASCIIPOS0) = 'T';
*((ULONG *) MALTA_ASCIIPOS1) = 'X';
*((ULONG *) MALTA_ASCIIPOS2) = ' ';
*((ULONG *) MALTA_ASCIIPOS3) = 'E';
*((ULONG *) MALTA_ASCIIPOS4) = 'N';
*((ULONG *) MALTA_ASCIIPOS5) = 'T';
*((ULONG *) MALTA_ASCIIPOS6) = 'E';
*((ULONG *) MALTA_ASCIIPOS7) = 'R';
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer;
#ifdef TX_ENABLE_EVENT_TRACE
tx_trace_enable(event_buffer, sizeof(event_buffer), 32);
#endif
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for LCD thread. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the lcd thread. */
tx_thread_create(&lcd_thread, "lcd thread", lcd_thread_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
/* Indicate that we are ready to start scheduling, which will happen after
this rountine returns. */
*((ULONG *) MALTA_ASCIIPOS0) = 'T';
*((ULONG *) MALTA_ASCIIPOS1) = 'X';
*((ULONG *) MALTA_ASCIIPOS2) = ' ';
*((ULONG *) MALTA_ASCIIPOS3) = 'G';
*((ULONG *) MALTA_ASCIIPOS4) = 'O';
*((ULONG *) MALTA_ASCIIPOS5) = '!';
*((ULONG *) MALTA_ASCIIPOS6) = ' ';
*((ULONG *) MALTA_ASCIIPOS7) = ' ';
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void lcd_thread_entry(ULONG thread_input)
{
UINT state = 0;
/* Loop to continue displaying info on the LCD. */
while(1)
{
/* Sleep for a bit... */
tx_thread_sleep(100);
lcd_counter++;
switch (state)
{
case 0:
*((ULONG *) MALTA_ASCIIPOS0) = 'T';
*((ULONG *) MALTA_ASCIIPOS1) = 'H';
*((ULONG *) MALTA_ASCIIPOS2) = 'R';
*((ULONG *) MALTA_ASCIIPOS3) = 'E';
*((ULONG *) MALTA_ASCIIPOS4) = 'A';
*((ULONG *) MALTA_ASCIIPOS5) = 'D';
*((ULONG *) MALTA_ASCIIPOS6) = 'X';
*((ULONG *) MALTA_ASCIIPOS7) = ' ';
break;
case 1:
*((ULONG *) MALTA_ASCIIPOS0) = 'D';
*((ULONG *) MALTA_ASCIIPOS1) = 'e';
*((ULONG *) MALTA_ASCIIPOS2) = 'm';
*((ULONG *) MALTA_ASCIIPOS3) = 'o';
*((ULONG *) MALTA_ASCIIPOS4) = ' ';
*((ULONG *) MALTA_ASCIIPOS5) = 'F';
*((ULONG *) MALTA_ASCIIPOS6) = 'o';
*((ULONG *) MALTA_ASCIIPOS7) = 'r';
break;
case 2:
*((ULONG *) MALTA_ASCIIPOS0) = 'M';
*((ULONG *) MALTA_ASCIIPOS1) = 'I';
*((ULONG *) MALTA_ASCIIPOS2) = 'P';
*((ULONG *) MALTA_ASCIIPOS3) = 'S';
*((ULONG *) MALTA_ASCIIPOS4) = ' ';
*((ULONG *) MALTA_ASCIIPOS5) = 'G';
*((ULONG *) MALTA_ASCIIPOS6) = 'N';
*((ULONG *) MALTA_ASCIIPOS7) = 'U';
break;
case 3:
*((ULONG *) MALTA_ASCIIPOS0) = 'i';
*((ULONG *) MALTA_ASCIIPOS1) = 'n';
*((ULONG *) MALTA_ASCIIPOS2) = 't';
*((ULONG *) MALTA_ASCIIPOS3) = 'A';
*((ULONG *) MALTA_ASCIIPOS4) = 'p';
*((ULONG *) MALTA_ASCIIPOS5) = 't';
*((ULONG *) MALTA_ASCIIPOS6) = 'i';
*((ULONG *) MALTA_ASCIIPOS7) = 'v';
break;
case 7:
*((ULONG *) MALTA_ASCIIPOS0) = 'E';
*((ULONG *) MALTA_ASCIIPOS1) = 'R';
*((ULONG *) MALTA_ASCIIPOS2) = 'R';
*((ULONG *) MALTA_ASCIIPOS3) = 'O';
*((ULONG *) MALTA_ASCIIPOS4) = 'R';
*((ULONG *) MALTA_ASCIIPOS5) = ' ';
*((ULONG *) MALTA_ASCIIPOS6) = ' ';
*((ULONG *) MALTA_ASCIIPOS7) = ' ';
break;
default:
break;
}
/* Change state for new print! */
state++;
if (state > 3)
state = 0;
}
}

109
ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.ld Normal file
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OUTPUT_ARCH(mips)
/**** Start point ****/
ENTRY(_start) /* Entry point of application */
SECTIONS
{
/**** Code and read-only data ****/
.vector_0x000 0x80000000 :
{
}
.vector_0x100 0x80000100 :
{
}
.vector_0x180 0x80000180 :
{
}
.vector_0x200 0x80000200 :
{
}
.vector_0x280 0x80000280 :
{
}
.vector_0x300 0x80000300 :
{
}
.text 0x80100000 :
{
_ftext = ABSOLUTE(.) ; /* Start of code and read-only data */
start.o(.text) /* Reset entry point */
*(.text*)
_ecode = ABSOLUTE(.) ; /* End of code */
*(.rodata*)
. = ALIGN(8);
_etext = ABSOLUTE(.) ; /* End of code and read-only data */
} = 0
/**** Initialised data ****/
.data :
{
_fdata = ABSOLUTE(.); /* Start of initialised data */
*(.data*)
. = ALIGN(8);
_gp = ABSOLUTE(. + 0x7ff0); /* Base of small data */
LC8 = ABSOLUTE(. + 0x7ff0); /* Base of small data */
*(.lit8)
*(.lit4)
*(.sdata*)
. = ALIGN(8);
_edata = ABSOLUTE(.) ; /* End of initialised data */
}
/**** Uninitialised data ****/
.sbss :
{
_start_sbss = .;
*(.sbss*)
*(.scommon)
_end_sbss = .;
}
.bss :
{
_start_bss = .;
*(.bss*)
*(COMMON)
_ebss = ABSOLUTE(.) ;
_end_bss = .;
}
.stack _ebss :
{
/* Allocate room for stack */
. = ALIGN(8) ;
. += 4096 ;
_sp = . - 16 ;
_stack_top = ABSOLUTE(.) ;
}
_free_memory = _stack_top + 4 ;
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
/DISCARD/ :
{
*(.reginfo)
}
PROVIDE(etext = _etext);
PROVIDE (end = _stack_top);
}

69
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_CoreFPGA6_mem.S Normal file
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/*
* init_CoreFPGA5mem.S
*
* Created on: Jun 4, 2012
* Author: chrisr
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <regdef.h>
#include <boot.h>
.set noreorder # Don't allow the assembler to reorder instructions.
/**************************************************************************************
Wait for the controller to startup. Then its good to go!
**************************************************************************************/
LEAF(init_CoreFPGA6_mem)
/* Wait for MIG to init */
la a0, 0xbbc00004
1:
/* RAMHACK: The read of Xilinx DRAM controller reg while executig from DRAM causing bad fetch?
lw a2, 0(a0)
andi a2, 0x1
beqz a2, 1b
nop
*/
jr ra
nop
END(init_CoreFPGA6_mem)

215
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_L23caches.S Normal file
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/*
* init_L23caches.S
*
* Created on: Jun 8, 2012
* Author: chrisr
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <mips/regdef.h>
#include <mips/m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
/**************************************************************************************
* Initialize the L2 and L3 caches Uncached version no CPS
**************************************************************************************/
LEAF(init_l23u)
// Use CCA Override disable the L2 cache or initialize the L2
// and L3 caches if CCA override is not available.
// NOTE: If you have a L3 cache you must add code here
// to disable it or initialize it if it can't be disabled.
// First check to see if this is a CPS, if not
// the l2 CCA override is not present and the L2 will have to be initialized
// from uncached code.
beqz r11_is_cps, init_l23
nop
// Diaable the L2 cache using CCA override by writting a 0x50 to
// the GCR Base register. 0x50 enables the CCA override bit and sets
// the CCA to uncached.
lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
li a3, 0x50 // Enable CCA and set to uncached
ins a0, a3, 0, 8 // Insert bits
sw a0, 0x0008(r22_gcr_addr) // Write GCR_BASE
// Read the GCR_BASE register back to see if the enabling
// of the CCA override took. If it did skip the L2 and L3
// initialization. (It will be called later once the L1 cache has
// been initialized, for better performance.)
lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
ext a0, a0, 4, 1 // Extract CCA_Override_Enable
bnez a0, done_l23 // Skip uncached execution if CCA
// Override is implemented.
nop
// If the code gets here the CCA override is not available so
// the L2 cache can't be disabled and must be initialized now
// instead of later.
b init_l23
nop
END(init_l23u)
/**************************************************************************************
* Initialize the L2 and L3 caches cached version is CPS
**************************************************************************************/
LEAF(init_l23c)
// Skip cached execution if CCA Override is not implemented.
// If CCA override is not implemented the L2 and L3 caches
// would have already been initialized when init_l23u was called.
beqz r11_is_cps, done_l23
nop
lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
bnez r8_core_num, done_l23 // Check it for Core0.
ext a0, a0, 4, 1 // Extract CCA_Override_Enable bit
// If CCA override is not set it means that the setting failed in
// init_l23u and the L2 and L3 caches were initialized at that time
// If it is set then the code will fall through and initialize the L2/L3 caches
beqz a0, done_l23
nop
END(init_l23c)
LEAF(init_l23)
// L2 Cache initialization routine
// Check L2 cache size
mfc0 v0, C0_CONFIG2 // C0_Config2
// Isolate L2$ Line Size
ext v1, v0, 4, 4 // extract SL
// Skip ahead if No L2$
beq v1, zero, done_l2cache
nop
li a2, 2
sllv v1, a2, v1 // Now have true L2$ line size in bytes
// Isolate L2$ Sets per Way
ext a0, v0, 8, 4 // extract SS
li a2, 64
sllv a0, a2, a0 // L2$ Sets per way
// Isolate L2$ Associativity
// L2$ Assoc (-1)
ext a1, v0, 0, 4 // extract SA
add a1, 1
mul a0, a0, a1 // Get total number of sets
lui a2, 0x8000 // Get a KSeg0 address for cacheops
// Clear L23TagLo/L23TagHi registers
mtc0 zero, C0_TAGLO, 4
move a3, a0
// L2$ Index Store Tag Cache Op
// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
next_L2cache_tag:
cache 0xB, 0(a2) // Write Tag using index store tag
add a3, -1 // Decrement set counter
bne a3, zero, next_L2cache_tag // Done yet?
add a2, v1 // Get next line address
done_l2cache:
// Isolate L3$ Line Size
ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
// Skip ahead if No L3$
beq v1, zero, done_l3cache
nop
li a2, 2
sllv v1, a2, v1 // Decode L3$ line size in bytes
// Isolate L3$ Sets per Way
ext a0, v0, CFG2_TSSHIFT, 4 // Extract L3 sets per way TDS encoding
li a2, 64
sllv a0, a2, a0 // Decode L3 Sets per way
// Isolate L3$ Associativity
// L3$ Assoc (-1)
ext a1, v0, CFG2_TASHIFT, 4 // Extrace L3 associativity 2TA encoding
add a1, 1 // Decode L3 associativity (number of sets)
mul a0, a0, a1 // Compute total number of sets
lui a2, 0x8000 // Get a KSeg0 address for cacheops
// Clear L23Tag register
mtc0 zero, C0_TAGLO, 4
move a3, a0
// L3$ Index Store Tag Cache Op
// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
next_L3cache_tag:
cache 0xA, 0(a2) // TCIndexStTag
add a3, -1 // Decrement set counter
bne a3, zero, next_L3cache_tag
add a2, v1 // Get next line address
done_l3cache:
// disable CCA Override
beqz r11_is_cps, done_l23
nop
lw a0, 0x0008(r22_gcr_addr) // GCR_BASE
ins a0, zero, 0, 8 // CCA Override disabled
sw a0, 0x0008(r22_gcr_addr) // GCR_BASE
done_l23:
jr ra
nop
END(init_l23)

252
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_caches2.S Normal file
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/*
* init_caches2.S
*
* Created on: March 30, 2012
* Author: MIPS TECHNOLOGIES, INC
* Common Cache initialization for a coherent processing system
*
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
* init_icache invalidates all Instruction cache entries
**************************************************************************************/
LEAF(init_icache)
// For this Core there is always a I cache
// The IS field determines how may set there are
// IS = 2 there are 256 sets per way 1024 total
// IS = 3 there are 512 sets per way 2048 total
// v1 set to line size, will be used to increment through the cache tags
li v1, 32 // Line size is always 32 bytes.
mfc0 v0, C0_CONFIG1 // Read C0_Config1
ext a3, v0, CFG1_ILSHIFT, 3 // Extract IS
li a2, 2 // Used to test against
beq a2, a3, Isets_done // if IS = 2
li a3, 1024 // sets = 256
li a3, 2048 // else sets = 512 Skipped if branch taken
Isets_done:
lui a2, 0x8000 // Get a KSeg0 address for cacheops
// clear the lock bit, valid bit, and the LRF bit
mtc0 zero, C0_TAGLO // Clear C0_ITagLo to invalidate entry
next_icache_tag:
cache 0x8, 0(a2) // Index Store tag Cache opt
add a3, -1 // Decrement set counter
bne a3, zero, next_icache_tag // Done yet?
add a2, v1 // Increment line address by line size
done_icache:
jr ra
nop
END(init_icache)
/**************************************************************************************
* init_dcache invalidates all data cache entries
**************************************************************************************/
LEAF(init_dcache)
// For this Core there is always a D cache
// The DS field determines how may set there are
// DS = 2 there are 256 sets per way 1024 total
// DS = 3 there are 512 sets per way 2048 total
// v1 set to line size, will be used to increment through the cache tags
li v1, 32 // Line size is always 32 bytes.
mfc0 v0, C0_CONFIG1 // Read C0_Config1
ext a3, v0, CFG1_DSSHIFT, 3 // Extract DS
li a2, 2 // Used to test against
beq a2, a3, Dsets_done // if DS = 2
li a3, 1024 // sets = 256
li a3, 2048 // else sets = 512 Skipped if branch taken
Dsets_done:
lui a2, 0x8000 // Get a KSeg0 address for cacheops
// clear the lock bit, valid bit, and the LRF bit
mtc0 zero, C0_TAGLO, 2 // Clear C0_DTagLo to invalidate entry
next_dcache_tag:
cache 0x9, 0(a2) // Index Store tag Cache opt
add a3, -1 // Decrement set counter
bne a3, zero, next_dcache_tag // Done yet?
add a2, v1 // Increment line address by line size
done_dcache:
jr ra
nop
END(init_dcache)
/**************************************************************************************
**************************************************************************************/
LEAF(disable_L23)
bnez r8_core_num, done_disable_L23 # Only done from core 0.
// Use CCA Override disable the L2 cache
// NOTE: If you have a L3 cache you must add code here
// to disable it or initialize it if it can't be disabled.
// Disable the L2 cache using CCA override by writing a 0x50 to
// the GCR Base register. 0x50 enables the CCA override bit and sets
// the CCA to uncached.
lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
li a3, 0x50 // Enable CCA and set to uncached
ins a0, a3, 0, 8 // Insert bits
sw a0, 0x0008(r22_gcr_addr) // Write GCR_BASE
done_disable_L23:
jr ra
nop
END(disable_L23)
/**************************************************************************************
* Initialize the L2 and L3 caches
**************************************************************************************/
LEAF(init_L23)
bnez r8_core_num, done_cach_init # Only done from core 0.
// L2 Cache initialization routine
// Check L2 cache size
mfc0 v0, C0_CONFIG2 // Read C0_Config2
// Isolate L2$ Line Size
ext v1, v0, 4, 4 // extract L2 line size
li a2, 2
sllv v1, a2, v1 // Now have true L2$ line size in bytes
// Isolate L2 Sets per Way (cache lines per way)
ext a3, v0, 8, 4 // extrace sets per way encoding
li a2, 64
sllv a3, a2, a3 // L2$ Sets per way
// Isolate L2 Associativity (number of ways)
// L2$ Assoc (-1)
ext a1, v0, 0, 4 // extract ways encoding
add a1, 1 // Decode L2 number of ways
mul a3, a3, a1 // Get total number of sets (sets per way * number of ways)
lui a2, 0x8000 // Get a KSeg0 address for cacheops
// Clear L23TagLo/L23TagHi registers these are used to set the cache tag
mtc0 zero, C0_TAGLO, 4
mtc0 zero, C0_TAGHI, 4
// L2$ Index Store Tag Cache Op
// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
next_L2cache_tag:
cache 0xB, 0(a2) // Write Tag using index store tag
add a3, -1 // Decrement set counter
bne a3, zero, next_L2cache_tag // Done yet?
add a2, v1 // Get next line address (each tag covers one line)
// Start of L3 cache initialization
// Isolate L3$ Line Size
ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
// Skip ahead if No L3$
beq v1, zero, done_l3cache
nop
li a2, 2
sllv v1, a2, v1 // Decode L3$ line size in bytes
// Isolate L3$ Sets per Way (cache lines per way)
ext a3, v0, CFG2_TSSHIFT, 4 // Extract L3 sets per way TDS encoding
li a2, 64
sllv a3, a2, a3 // Decode L3 Sets per way
// Isolate L3$ Associativity (number of ways)
// L3$ Assoc (-1)
ext a1, v0, CFG2_TASHIFT, 4 // Extrace L3 associativity 2TA encoding
add a1, 1 // Decode L3 associativity (number of sets)
mul a3, a3, a1 // Compute total number of sets
lui a2, 0x8000 // Get a KSeg0 address for cacheops
// Clear L23TagLo/L23TagHi registers
mtc0 zero, C0_TAGLO, 4
mtc0 zero, C0_TAGHI, 4
// L3 Index Store Tag Cache Op
// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
next_L3cache_tag:
cache 0xA, 0(a2) // TCIndexStTag
add a3, -1 // Decrement set counter
bne a3, zero, next_L3cache_tag
add a2, v1 // Get next line address
done_l3cache:
// disable CCA Override to enable L2 cache
lw a0, 0x0008(r22_gcr_addr) // GCR_BASE
ins a0, zero, 0, 8 // CCA Override disabled
sw a0, 0x0008(r22_gcr_addr) // GCR_BASE
done_cach_init:
jr ra
nop
END(init_L23)
LEAF(change_k0_cca)
// NOTE! This code must be executed in KSEG1 (not KSGE0 uncached)
// Set CCA for kseg0 to cacheable
mfc0 v0, C0_CONFIG // read C0_Config
beqz r11_is_cps, set_kseg0_cca
li v1, 3 // CCA for non coherent core
li v1, 5 // CCA for coherent cores
set_kseg0_cca:
ins v0, v1, 0, 3 // instert K0
mtc0 v0, C0_CONFIG // write C0_Config
jr.hb ra
nop
END(change_k0_cca)

86
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/*
* init_cm.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* initializatoin of the Coherency Manager
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_cm)
beqz r11_is_cps, done_cm_init // skip if not a CPS or CM register verification failed.
nop
// Allow each core access to the CM registers (they should only access their local registers.)
li a0, 2 // Start building mask for cores in this cps.
sll a0, a0, r19_more_cores
addiu a0, -1 // Complete mask.
sw a0, GCR_ACCESS(r22_gcr_addr) // GCR_ACCESS
// Check to see if this CPS implements an IOCU.
lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
ext a0, a0, NUMIOCU, NUMIOCU_S // Extract NUMIOCU.
beqz a0, done_cm_init
lui a0, 0xffff
// Disable the CM regions if there is an IOCU.
sw a0, GCR_REG0_BASE(r22_gcr_addr) // GCR_REG0_BASE
sw a0, GCR_REG0_MASK(r22_gcr_addr) // GCR_REG0_MASK
sw a0, GCR_REG1_BASE(r22_gcr_addr) // GCR_REG1_BASE
sw a0, GCR_REG1_MASK(r22_gcr_addr) // GCR_REG1_MASK
sw a0, GCR_REG2_BASE(r22_gcr_addr) // GCR_REG2_BASE
sw a0, GCR_REG2_MASK(r22_gcr_addr) // GCR_REG2_MASK
sw a0, GCR_REG3_BASE(r22_gcr_addr) // GCR_REG3_BASE
sw a0, GCR_REG3_MASK(r22_gcr_addr) // GCR_REG3_MASK
done_cm_init:
jr ra
nop
END(init_cm)

119
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/*
* initcp0.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Common CP0 register initializations
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_cp0)
// Initialize Status
// RAMHACK: Use RAM (Status.BEV == 0) exception vectors.
// li v1, 0x00400404 // (M_StatusIM | M_StatusERL | M_StatusBEV)
li v1, 0x00000404 // (M_StatusIM | M_StatusERL)
mtc0 v1, C0_STATUS // write C0_Status
// Initialize Watch registers if implemented.
mfc0 v0, C0_CONFIG1 // read C0_Config1
ext v1, v0, 3, 1 // extract bit 3 WR (Watch registers implemented)
beq v1, zero, done_wr
li v1, 0x7 // (M_WatchHiI | M_WatchHiR | M_WatchHiW)
// Clear Watch Status bits and disable watch exceptions
mtc0 v1, C0_WATCHHI // write C0_WatchHi0
mfc0 v0, C0_WATCHHI // read C0_WatchHi0
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO // write C0_WatchLo0
mtc0 v1, C0_WATCHHI, 1 // write C0_WatchHi1
mfc0 v0, C0_WATCHHI, 1 // read C0_WatchHi1
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 1 // write C0_WatchLo1
mtc0 v1, C0_WATCHHI, 2 // write C0_WatchHi2
mfc0 v0, C0_WATCHHI, 2 // read C0_WatchHi2
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 2 // write C0_WatchLo2
mtc0 v1, C0_WATCHHI, 3 // write C0_WatchHi3
mfc0 v0, C0_WATCHHI, 3 // read C0_WatchHi3
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 3 // write C0_WatchLo3
mtc0 v1, C0_WATCHHI, 4 // write C0_WatchHi4
mfc0 v0, C0_WATCHHI, 4 // read C0_WatchHi4
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 4 // write C0_WatchLo4
mtc0 v1, C0_WATCHHI, 5 // write C0_WatchHi5
mfc0 v0, C0_WATCHHI, 5 // read C0_WatchHi5
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 5 // write C0_WatchLo5
mtc0 v1, C0_WATCHHI, 6 // write C0_WatchHi6
mfc0 v0, C0_WATCHHI, 6 // read C0_WatchHi6
bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
mtc0 zero, C0_WATCHLO, 6 // write C0_WatchLo6
mtc0 v1, C0_WATCHHI, 7 // write C0_WatchHi7
mtc0 zero, C0_WATCHLO, 7 // write C0_WatchLo7
done_wr:
// Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
// RAMHACK: Use vectored interrupts (Cause.IV) to isolate them from other exceptions.
lui v1, 0x0080 // Cause.IV = 1
mtc0 v1, C0_CAUSE // write C0_Cause: Init AFTER init of CP0 WatchHi/Lo registers.
// Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
mtc0 zero, C0_COMPARE // write C0_Compare
jr ra
nop
END(init_cp0)

73
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/*
* init_cpc.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* initializatoin of the Cluster Power Controler
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_cpc)
beqz r11_is_cps, done_init_cpc // Skip if non-CPS.
nop
lw a0, GCR_CPC_STATUS(r22_gcr_addr) // Read GCR_CPC_STATUS
andi a0, 1 // CPC_EX is bit 0
beqz a0, done_init_cpc // Skip if CPC is not implemented (CPC_EX not set)
move r30_cpc_addr, zero
li a0, CPC_P_BASE_ADDR // Locate CPC at same location YAMON does.
sw a0, GCR_CPC_BASE(r22_gcr_addr) // Write CPC_BASE address to GCR
li r30_cpc_addr, CPC_BASE_ADDR // Maintain address of CPC register block.
done_init_cpc:
jr ra
nop
END(init_cpc)

155
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/*
* init_gic.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Initialization of the Global Interrupt Conrtoller
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_gic)
beqz r11_is_cps, done_gic // Skip if non-CPS.
nop
la a1, GCR_GIC_STATUS + GCR_CONFIG_ADDR // Read GCR_GIC_STATUS
lw a0, 0(a1)
ext a0, a0, GIC_EX, GIC_EX_S // Isolate GCR_GIC_STATUS[GIC_EX].
beqz a0, done_gic // If no gic then skip.
nop
bnez r23_cpu_num, init_vpe_gic // Only core0 vpe0 inits shared portion.
nop
li a1, GCR_CONFIG_ADDR + GCR_GIC_BASE // Locate and enable GIC
li a0, GIC_P_BASE_ADDR | 1 // Physical address + enable bit
sw a0, 0(a1)
// Verify gic is 5 "slices" of 8 interrupts giving 40 interrupts.
li a1, GIC_BASE_ADDR // load GIC KSEG0 Address
lw a0, GIC_SH_CONFIG(a1) // GIC_SH_CONFIG
ext a0, a0, NUMINTERRUPTS, NUMINTERRUPTS_S // NUMINTERRUPTS (actually slices - 1)
li a3, 4
beq a0, a3, configure_slices
nop
sdbbp // Failed assertion that gic implements 40 external interrupts.
configure_slices:
// Hardcoded to set up the last 16 of 40 external interrupts (24..39) for IPI.
// First interrupts 24... 31 (top 8 bits of 31_0 registers)
li a0, 0xff000000
sw a0, GIC_SH_RMASK31_0(a1) // (disable 0..31)
sw a0, GIC_SH_POL31_0(a1) // (high/rise 24..31)
sw a0, GIC_SH_TRIG31_0(a1) // (edge 24..31)
sw a0, GIC_SH_SMASK31_00(a1) // (enable 24..31)
// Then interrupts 32...40 (lower 8 bits of 63_32 registers)
li a0, 0xff
sw a0, GIC_SH_RMASK63_32(a1) // (disable 32..63)
sw a0, GIC_SH_POL63_32(a1) // (high/rise 32..39)
sw a0, GIC_SH_TRIG63_32(a1) // (edge 32..39)
sw a0, GIC_SH_SMASK63_32(a1) // (enable 32..39)
// Initialize configuration of shared interrupts
// Direct GIC_int24..39 to vpe 0..7
// MIPS Linux convention that last 16 interrupts implemented be set aside for IPI signaling.
// (The actual interrupts are tied low and software sends interrupts via GIC_SH_WEDGE writes.)
li a0, 1 // set bit 0 for CORE0 or for MT vpe0
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 24) (a1) // Source 24 to VPE 0
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 32) (a1) // Source 32 to VPE 0
sll a0, a0, 1 // set bit 1 for CORE1 or for MT vpe1
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 25) (a1) // Source 25 to VPE 1
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 33) (a1) // Source 33 to VPE 1
sll a0, a0, 1 // set bit 2 for CORE2 or for MT vpe2
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 26) (a1) // Source 26 to VPE 2
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 34) (a1) // Source 34 to VPE 2
sll a0, a0, 1 // set bit 3 for CORE3 or for MT vpe3
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 27) (a1) // Source 27 to VPE 3
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 35) (a1) // Source 35 to VPE 3
sll a0, a0, 1 // set bit 4 for CORE4 or for MT vpe4
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 28) (a1) // Source 28 to VPE 4
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 36) (a1) // Source 36 to VPE 4
sll a0, a0, 1 // set bit 5 for CORE5 or for MT vpe5
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 29) (a1) // Source 29 to VPE 5
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 37) (a1) // Source 37 to VPE 5
sll a0, a0, 1 // set bit 6 for CORE6 or for MT vpe6
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 30) (a1) // Source 30 to VPE 6
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 38) (a1) // Source 38 to VPE 6
sll a0, a0, 1 // set bit 7 for CORE7 or for MT vpe7
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 31) (a1) // Source 31 to VPE 7
sw a0, GIC_SH_MAP0_VPE31_0 + (GIC_SH_MAP_SPACER * 39) (a1) // Source 39 to VPE 7
init_vpe_gic:
// Initialize configuration of per Core or for MT vpe interrupts
li a1, (GIC_BASE_ADDR | GIC_CORE_LOCAL_SECTION_OFFSET)
lw a3, GIC_COREL_CTL(a1)
map_timer_int:
ext a0, a3, TIMER_ROUTABLE, TIMER_ROUTABLE_S
beqz a0, map_perfcount_int
nop
li a0, 0x80000005 // Int5 is selected for timer routing
sw a0, GIC_COREL_TIMER_MAP(a1)
map_perfcount_int:
ext a0, a3, PERFCOUNT_ROUTABLE, PERFCOUNT_ROUTABLE_S
beqz a0, done_gic
nop
li a0, 0x80000004 // Int4 is selected for performance routing
sw a0, GIC_COREL_PERFCTR_MAP(a1)
done_gic:
jr ra
nop
END(init_gic)

118
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/*
* init_gpr.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Start of boot code for 24K Family of Cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_gpr)
// Initialize the general purpose registers and any shadow register sets.
// Although not necessary, register initialization may be useful during boot,
// debug, and simulation when certain ways of initializing registers may not work
// (xor rN, rN, rN for example.)
// Initialize register sets
li $1, 0xdeadbeef // (0xdeadbeef stands out, kseg2 mapped, odd.)
// Determine how many shadow sets are implemented (in addition to the base register set.)
// the first time thru the loop it will initialize using $1 set above.
// At the bottom og the loop, 1 is subtract from $30
// and loop back to next_shadow_set to start the next loop and the next lowest set number.
mfc0 $29, C0_SRSCTL // read C0_SRSCtl
ext $30, $29, 26, 4 // extract HSS
next_shadow_set:
// set PSS to shadow set to be initialized
ins $29, $30, 6, 4 // insert PSS
mtc0 $29, C0_SRSCTL // write C0_SRSCtl
wrpgpr $1, $1
wrpgpr $2, $1
wrpgpr $3, $1
wrpgpr $4, $1
wrpgpr $5, $1
wrpgpr $6, $1
wrpgpr $7, $1
wrpgpr $8, $1
wrpgpr $9, $1
wrpgpr $10, $1
wrpgpr $11, $1
wrpgpr $12, $1
wrpgpr $13, $1
wrpgpr $14, $1
wrpgpr $15, $1
wrpgpr $16, $1
wrpgpr $17, $1
wrpgpr $18, $1
wrpgpr $19, $1
wrpgpr $20, $1
wrpgpr $21, $1
wrpgpr $22, $1
wrpgpr $23, $1
wrpgpr $24, $1
wrpgpr $25, $1
wrpgpr $26, $1
wrpgpr $27, $1
wrpgpr $28, $1
wrpgpr $29, $1
beqz $30, done_init_gpr // early exit when we get to set 0 so we don't clobber return in $31
nop
wrpgpr $30, $1
wrpgpr $31, $1
b next_shadow_set
add $30, -1 // Since the code started with the highest set number this decrements to the next lower number
done_init_gpr:
jr ra
nop
END(init_gpr)

62
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/*
* init_itc.S
*
* Created on: Jan 13, 2011
* Author: MIPS TECHNOLOGIES, INC
* Common Inter Thread Communicaton initialization
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_itc)
nop
// enhanceme: Add ITC init.
done_init_itc:
jr ra
nop
END(init_itc)

254
ports_smp/mips32_interaptiv_smp/gnu/example_build/init_mc_denali.S Normal file
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/*
* init_mc_denali.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
Initialization code for Denali memory controller needed for CoreFPGA5
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#ifndef SDR_SDRAM_DIMM
#define SDR_SDRAM_DIMM 0 /* Set to 0 if you have a DDR SDRAM DIMM. */
#endif
#include <boot.h>
#include <mips/regdef.h>
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
Hardcoded Denali Databahn DRAM controller initialization.
**************************************************************************************/
LEAF(init_mc_denali)
li a1, DENALI_CTL_SECTION
lw a0, 0x0c(a1)
ins a0, zero, 16, 1 # Clear Start bit
sw a0, 0x0c(a1)
//# (Use YAMON to dump register settings for your target.)
#if (SDR_SDRAM_DIMM) /* defined in c command line in make file */
li a0, 0x00000100
sw a0, 0x04(a1)
li a0, 0x00000001
sw a0, 0x0c(a1)
li a0, 0x01000101
sw a0, 0x10(a1)
li a0, 0x02020200
sw a0, 0x14(a1)
li a0, 0x00000302
sw a0, 0x18(a1)
li a0, 0x02020000
sw a0, 0x1c(a1)
li a0, 0x00080A01
sw a0, 0x20(a1)
li a0, 0x02040000
sw a0, 0x24(a1)
li a0, 0x000F0404
sw a0, 0x28(a1)
li a0, 0x00090602
sw a0, 0x2c(a1)
li a0, 0x0A0A001E
sw a0, 0x30(a1)
li a0, 0x00000A0A
sw a0, 0x34(a1)
li a0, 0x04040000
sw a0, 0x38(a1)
li a0, 0x00000404
sw a0, 0x3c(a1)
li a0, 0x01010000
sw a0, 0x40(a1)
li a0, 0x02040101
sw a0, 0x44(a1)
li a0, 0x000C2D06
sw a0, 0x48(a1)
li a0, 0x00062706
sw a0, 0x50(a1)
li a0, 0x00000006
sw a0, 0x54(a1)
li a0, 0x00000014
sw a0, 0x58(a1)
li a0, 0x01010101
sw a0, 0x60(a1)
li a0, 0x01010000
sw a0, 0x64(a1)
li a0, 0x00010100
sw a0, 0x68(a1)
li a0, 0x0F0F0002
sw a0, 0x6c(a1)
lw a0, 0x0c(a1)
ins a0, r1_all_ones, 16, 1 # Set Start bit
sw a0, 0x0c(a1)
#else
//# Sequence of accesses recorded from YAMON 2.21 booting w/ supplied DDR DIMM...
//# Hardcoded initial values.
li a0, 0x01000000
sw a0, 0x00(a1)
li a0, 0x01000100
sw a0, 0x04(a1)
li a0, 0x00000001
sw a0, 0x08(a1)
li a0, 0x01000000
sw a0, 0x0c(a1)
li a0, 0x03000101
sw a0, 0x10(a1)
li a0, 0x02020000
sw a0, 0x14(a1)
li a0, 0x00000302
sw a0, 0x18(a1)
li a0, 0x02010000
sw a0, 0x1c(a1)
li a0, 0x00020A01
sw a0, 0x20(a1)
li a0, 0x02040000
sw a0, 0x24(a1)
li a0, 0x00000606
sw a0, 0x28(a1)
li a0, 0x00090602
sw a0, 0x2c(a1)
li a0, 0x2020001E
sw a0, 0x30(a1)
li a0, 0x00002020
sw a0, 0x34(a1)
li a0, 0x0b0b0000
sw a0, 0x38(a1)
li a0, 0x00000b0b
sw a0, 0x3c(a1)
li a0, 0x01010000
sw a0, 0x40(a1)
li a0, 0x02040101
sw a0, 0x44(a1)
li a0, 0x00030507
sw a0, 0x48(a1)
li a0, 0x00c80000
sw a0, 0x4c(a1)
li a0, 0x00c80618
sw a0, 0x50(a1)
li a0, 0x000000c8
sw a0, 0x54(a1)
li a0, 0x00000014
sw a0, 0x58(a1)
li a0, 0x00000000
sw a0, 0x5c(a1)
li a0, 0x01010101
sw a0, 0x60(a1)
li a0, 0x01010000
sw a0, 0x64(a1)
li a0, 0x00010100
sw a0, 0x68(a1)
li a0, 0x0F0F0002
sw a0, 0x6c(a1)
li a0, 0x00000000
sw a0, 0x70(a1)
li a0, 0x00000000
sw a0, 0x74(a1)
li a0, 0x00000000
sw a0, 0x78(a1)
li a0, 0x00020000
sw a0, 0x7c(a1)
li a0, 0x000f0606
sw a0, 0x28(a1)
li a0, 0x00000001
sw a0, 0x08(a1)
li a0, 0x01020000
sw a0, 0x14(a1)
li a0, 0x00000303
sw a0, 0x18(a1)
li a0, 0x01000101
sw a0, 0x10(a1)
li a0, 0x00000302
sw a0, 0x18(a1)
li a0, 0x000f0604
sw a0, 0x28(a1)
li a0, 0x000f0404
sw a0, 0x28(a1)
li a0, 0x00008207
sw a0, 0x48(a1)
li a0, 0x01000101
sw a0, 0x10(a1)
lw a0, 0x0c(a1)
ins a0, r1_all_ones, 16, 1 # Set Start bit
sw a0, 0x0c(a1)
wait_init_ddr:
lw a0, 0x28(a1)
ext a0, a0, 26, 1 # Extract init status
beq a0, zero, wait_init_ddr
nop
li a0, 0x0F020A01
sw a0, 0x20(a1)
li a0, 0x00000404
sw a0, 0x28(a1)
li a0, 0x00010000
sw a0, 0x70(a1)
li a0, 0x01010101
sw a0, 0x10(a1)
li a0, 0x00000402
sw a0, 0x28(a1)
li a0, 0x00000202
sw a0, 0x28(a1)
li a0, 0x00000203
sw a0, 0x28(a1)
li a0, 0x00000303
sw a0, 0x28(a1)
li a0, 0x00000304
sw a0, 0x28(a1)
li a0, 0x00000404
sw a0, 0x28(a1)
li a0, 0x00000405
sw a0, 0x28(a1)
li a0, 0x00000505
sw a0, 0x28(a1)
#endif
jr ra
nop
END(init_mc_denali)

88
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/*
* init_tlb.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Common TLB initialization for MIPS cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_tlb)
check_for_tlb:
// Determine if we have a TLB
mfc0 v1, C0_CONFIG // read C0_Config
ext v1, v1, 7, 3 // extract MT field
li a3, 0x1 // load a 1 to check against
bne v1, a3, done_init_tlb
mfc0 v0, C0_CONFIG1 // C0_Config1
nop
start_init_tlb:
// Config1MMUSize == Number of TLB entries - 1
ext v1, v0, CFG1_MMUSSHIFT, 6 // extract MMU Size
mtc0 zero, C0_ENTRYLO0 // write C0_EntryLo0
mtc0 zero, C0_ENTRYLO1 // write C0_EntryLo1
mtc0 zero, C0_PAGEMASK // write C0_PageMask
mtc0 zero, C0_WIRED // write C0_Wired
li a0, 0x80000000
next_tlb_entry_pair:
mtc0 v1, C0_INDEX // write C0_Index
mtc0 a0, C0_ENTRYHI // write C0_EntryHi
ehb
tlbwi
add a0, (2<<13) // Add 8K to the address to avoid TLB conflict with previous entry
bne v1, zero, next_tlb_entry_pair
add v1, -1
done_init_tlb:
jr ra
nop
END(init_tlb)

262
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/*
* init_vpe1.S
*
* Created on: Jan 13, 2011
* Author: MIPS TECHNOLOGIES, INC
* Initialize the second vpe and additional TCs
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <m32c0.h>
// defines not yet in m32c0.h
#define C0_MVPCTL $0, 1
#define C0_MVPCONF0 $0, 2
#define C0_VPECTL $1, 1
#define C0_VPECONF0 $1, 2
#define C0_TCSTATUS $2, 1
#define C0_TCBIND $2, 2
#define C0_TCRESTART $2, 3
#define C0_TCHALT $2, 4
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(init_vpe1)
// Each vpe will need to set up additional TC bound to it. (No rebinding.)
beqz r21_more_tcs, done_init_vpe1 // If there is no .
nop
beqz r20_more_vpes, done_init_vpe1 // If there is no vpe1 then skip init_vpe1.
nop
// This is executing on TC0 bound to VPE0. Therefore VPEConf0.MVP is set.
// Enter config mode
mfc0 v0, C0_MVPCTL // read C0_MVPCtl
or v0, (1 << 1) // set VPC
mtc0 v0, C0_MVPCTL // write C0_MVPCtl
ehb
#define a0_NTCS a0
#define a2_NVPES a2
#define a3_TC a3
// Get number of a3_TC's and VPE's
mfc0 v0, C0_MVPCONF0 // read C0_MVPCONF0
ext a0_NTCS, v0, 0, 8 // extract PTC
ext a2_NVPES, v0, 10, 4 // extract PVPE
// Initialise a3_TC's/VPE's
move a3_TC, zero
nexttc:
// Select TCn
mfc0 v0, C0_VPECTL // read C0_VPECTL
ins v0, a3_TC, 0, 8 // insert TargTC
mtc0 v0, C0_VPECTL // write C0_VPECTL
ehb
// Bind a3_TC to next VPE
beqz a3_TC, nextvpe // Don't rebind TC0
nop
// Halt a3_TC being configured
li v0, 1 // set Halt bit
mttc0 v0, C0_TCHALT // write C0_TCHALT
ehb
move v1, a3_TC
// Bind TC to a VPE
mftc0 v0, C0_TCBIND // Read C0_TCBind
ins v0, v1, 0, 4 // change S_TCBindCurVPE
mttc0 v0, C0_TCBIND // write C0_TCBind
// This code checks to see if the a3_TC mumber is
// less than the VPE number. This ensures
// in a system with more than 1 VPE and TCs each
// VPE will have at least one a3_TC bound to it
// and any TCs left over will be bound to the last a3_TC
slt v1, a2_NVPES, a3_TC
bnez v1, 2f // Bind spare a3_TC's to VPElast
move v1, a2_NVPES
// Set XTC for active a3_TC's
mftc0 v0, C0_VPECONF0 // read C0_VPECONF0
ins v0, a3_TC, 21, 8 // insert XTC
mttc0 v0, C0_VPECONF0 // write C0_VPECONF0
move v1, a3_TC
2:
// Bind a3_TC to a VPE
mftc0 v0, C0_TCBIND // read C0_TCBIND
ins v0, v1, 0, 4 // insert VPE
mttc0 v0, C0_TCBIND // write C0_TCBIND
// Set up TCStatus register:
// Disable Coprocessor Usable bits
// Disable MDMX/DSP ASE
// Clear Dirty a3_TC
// not dynamically allocatable
// not allocated
// Kernel mode
// interrupt exempt
// ASID 0
li v0, (1 << 10) // set IXMT
mttc0 v0, C0_TCSTATUS // write C0_TCSTATUS
// Initialize the a3_TC's register file
li v0, 0xdeadbeef
mttgpr v0, $1
mttgpr v0, $2
mttgpr v0, $3
mttgpr v0, $4
mttgpr v0, $5
mttgpr v0, $6
mttgpr v0, $7
mttgpr v0, $8
mttgpr v0, $9
mttgpr v0, $10
mttgpr v0, $11
mttgpr v0, $12
mttgpr v0, $13
mttgpr v0, $14
mttgpr v0, $15
mttgpr v0, $16
mttgpr v0, $17
mttgpr v0, $18
mttgpr v0, $19
mttgpr v0, $20
mttgpr v0, $21
mttgpr v0, $22
mttgpr v0, $23
mttgpr v0, $24
mttgpr v0, $25
mttgpr v0, $26
mttgpr v0, $27
mttgpr v0, $28
mttgpr v0, $29
mttgpr v0, $30
mttgpr v0, $31
nextvpe:
slt v1, a2_NVPES, a3_TC
bnez v1, donevpe // No more VPE's
nop
// Disable multi-threading with a3_TC's
mftc0 v0, C0_VPECTL // read C0_VPECTL
ins v0, zero, 15, 1 // clear TE
mttc0 v0, C0_VPECTL // write C0_VPECTL
beqz a3_TC, 1f
nop
// For VPE1..n
// Clear VPA and set master VPE
mftc0 v0, C0_VPECONF0 // read C0_VPECONF0
ins v0, zero, 0, 1 // insert VPA
or v0, (1 << 1) // set MVP
mttc0 v0, C0_VPECONF0 // write C0_VPECONF0
mfc0 v0, C0_STATUS // read vpe0 C0_STATUS
mttc0 v0, C0_STATUS // write vpe1 C0_Status
li v0, 0x12345678
mttc0 v0, C0_EPC // write C0_EPC
// RAMHACK: vpe0.Cause -> vpe1.Cause (Cause.IV == 1)
mfc0 v0, C0_CAUSE // read vpe0 C0_CAUSE
mttc0 v0, C0_CAUSE // write vpe1 C0_CAUSE
mfc0 v0, C0_CONFIG // read vpe0 C0_CONFIG
mttc0 v0, C0_CONFIG // write vpe1 C0_CONFIG
mftc0 v0, C0_EBASE // read C0_EBASE
ext v0, v0, 0, 10 // extract CPUNum
mttgpr v0, r23_cpu_num
// vpe1 of each core can execute cached as it's L1 I$ has already been initialized.
// and the L2$ has been initialized or "disabled" via CCA override.
// RAMHACK: Move entry point to _start.
// la a1, __reset_vector
la a1, _start
ins a1, zero, 29, 1 // Convert to cached kseg0 address in case we linked to kseg1.
mttc0 a1, C0_TCRESTART // write C0_TCRESTART
// Yes.. this is undoing all of the work done above... :)
mftc0 v0, C0_TCSTATUS // read C0_TCSTATUS
ins v0, zero, 10, 1 // insert IXMT
ori v0, (1 << 13) // set A
mttc0 v0, C0_TCSTATUS // write C0_TCSTATUS
mttc0 zero, C0_TCHALT // write C0_TCHALT
mftc0 v0, C0_VPECONF0 // read C0_VPECONF0
ori v0, 1 // set VPA
mttc0 v0, C0_VPECONF0 // write C0_VPECONF0
1:
donevpe:
addu a3_TC, 1
sltu v1, a0_NTCS, a3_TC
beqz v1, nexttc
nop
// Exit config mode
mfc0 v0, C0_MVPCTL // read C0_MVPCtl
ori v0, 1 // set EVP will enable execution by vpe1
ins v0, zero, 1, 1 // insert VPC
mtc0 v0, C0_MVPCTL // write C0_MVPCtl
ehb
#undef a0_NTCS
#undef a2_NVPES
#undef a3_TC
done_init_vpe1:
jr ra
nop
END(init_vpe1)

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/*
* join_domain.S
*
* Created on: Jan 13, 2011
* Author: MIPS TECHNOLOGIES, INC
* For CPS cores join processing domain
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(join_domain)
beqz r11_is_cps, done_join_domain // If this is not a CPS then we are done.
nop
// Enable coherence and allow interventions from all other cores.
// (Write access enabled via GCR_ACCESS by core 0.)
li a0, 0x0f // Set Coherent domain enable for 4 cores
sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_COHERENCE)(r22_gcr_addr) // GCR_CL_COHERENCE
ehb
// Cores other than core 0 can relinquish write access to CM regs here.
move a3, zero
next_coherent_core:
sll a0, a3, 16
sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER[CoreNum]
busy_wait_coherent_core:
lw a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
beqz a0, busy_wait_coherent_core // Busy wait on cores joining.
nop
bne a3, r19_more_cores, next_coherent_core
addiu a3, 1
done_join_domain:
jr ra
nop
END(join_domain)

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/* This file is part of the CodeSourcery C Library (CSLIBC).
Copyright (c) 2009 CodeSourcery, Inc.
THIS FILE CONTAINS PROPRIETARY, CONFIDENTIAL, AND TRADE SECRET
INFORMATION OF CODESOURCERY AND/OR ITS LICENSORS.
You may not use, modify or distribute this file without the express
written permission of CodeSourcery or its authorized
distributor. Please consult your license agreement for the
applicable terms and conditions. */
/*
* Copyright (c) 1999-2007 MIPS Technologies, Inc.
* Copyright (C) 2009 CodeSourcery, LLC.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright
* notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with
* the distribution.
* * Neither the name of MIPS Technologies Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* m32c0.h : MIPS32 coprocessor 0 definitions
*/
#ifndef _M32C0_H_
#define _M32C0_H_
#ifdef __cplusplus
extern "C" {
#endif
/* MIPS32-specific MMU interface */
//#assert mmu(m32)
//#include "mips/m32tlb.h"
/*
* MIPS32 Exception Codes
*/
#define EXC_INTR 0 /* interrupt */
#define EXC_MOD 1 /* tlb modification */
#define EXC_TLBL 2 /* tlb miss (load/i-fetch) */
#define EXC_TLBS 3 /* tlb miss (store) */
#define EXC_ADEL 4 /* address error (load/i-fetch) */
#define EXC_ADES 5 /* address error (store) */
#define EXC_IBE 6 /* bus error (i-fetch) */
#define EXC_DBE 7 /* data bus error (load/store) */
#define EXC_SYS 8 /* system call */
#define EXC_BP 9 /* breakpoint */
#define EXC_RI 10 /* reserved instruction */
#define EXC_CPU 11 /* coprocessor unusable */
#define EXC_OVF 12 /* integer overflow */
#define EXC_TRAP 13 /* trap exception */
#define EXC_RES14 14
#define EXC_FPE 15 /* floating point exception */
#define EXC_IS1 16 /* implementation-specific 1 */
#define EXC_IS2 17 /* implementation-specific 2 */
#define EXC_C2E 18 /* coprocessor 2 exception */
#define EXC_RES19 19
#define EXC_RES20 20
#define EXC_RES21 21
#define EXC_MDMX 22 /* mdmx unusable */
#define EXC_WATCH 23 /* watchpoint */
#define EXC_MCHECK 24 /* machine check */
#define EXC_THREAD 25 /* thread */
#define EXC_DSPU 26 /* dsp unusable */
#define EXC_RES27 27
#define EXC_RES28 28
#define EXC_RES29 29
#define EXC_RES30 30
#define EXC_RES31 31
/*
* MIPS32 Cause Register (CP0 Register 13, Select 0)
*/
#define CR_BD 0x80000000 /* branch delay */
#define CR_TI 0x40000000 /* timer interrupt (r2) */
#define CR_CEMASK 0x30000000 /* coprocessor used */
#define CR_CESHIFT 28
#define CR_DC 0x08000000 /* disable count (r2) */
#define CR_PCI 0x04000000 /* performance counter i/u (r2) */
#define CR_IV 0x00800000 /* use special i/u vec */
#define CR_WP 0x00400000 /* deferred watchpoint */
/* interrupt pending bits */
#define CR_SINT0 0x00000100 /* s/w interrupt 0 */
#define CR_SINT1 0x00000200 /* s/w interrupt 1 */
#define CR_HINT0 0x00000400 /* h/w interrupt 0 */
#define CR_HINT1 0x00000800 /* h/w interrupt 1 */
#define CR_HINT2 0x00001000 /* h/w interrupt 2 */
#define CR_HINT3 0x00002000 /* h/w interrupt 3 */
#define CR_HINT4 0x00004000 /* h/w interrupt 4 */
#define CR_HINT5 0x00008000 /* h/w interrupt 5 */
/* alternative interrupt pending bit naming */
#define CR_IP0 0x00000100
#define CR_IP1 0x00000200
#define CR_IP2 0x00000400
#define CR_IP3 0x00000800
#define CR_IP4 0x00001000
#define CR_IP5 0x00002000
#define CR_IP6 0x00004000
#define CR_IP7 0x00008000
#define CR_IMASK 0x0000ff00 /* interrupt pending mask */
#define CR_XMASK 0x0000007c /* exception code mask */
#define CR_XCPT(x) ((x)<<2)
/*
* MIPS32 Status Register (CP0 Register 12, Select 0)
*/
#define SR_IE 0x00000001 /* interrupt enable */
#define SR_EXL 0x00000002 /* exception level */
#define SR_ERL 0x00000004 /* error level */
#define SR_UM 0x00000010 /* user mode */
#define SR_KSU_MASK 0x00000018 /* ksu mode mask */
#define SR_KSU_USER 0x00000010 /* user mode */
#define SR_KSU_SPVS 0x00000008 /* supervisor mode */
#define SR_KSU_KERN 0x00000000 /* kernel mode */
/* interrupt mask bits */
#define SR_SINT0 0x00000100 /* enable s/w interrupt 0 */
#define SR_SINT1 0x00000200 /* enable s/w interrupt 1 */
#define SR_HINT0 0x00000400 /* enable h/w interrupt 1 */
#define SR_HINT1 0x00000800 /* enable h/w interrupt 2 */
#define SR_HINT2 0x00001000 /* enable h/w interrupt 3 */
#define SR_HINT3 0x00002000 /* enable h/w interrupt 4 */
#define SR_HINT4 0x00004000 /* enable h/w interrupt 5 */
#define SR_HINT5 0x00008000 /* enable h/w interrupt 6 */
/* alternative interrupt mask naming */
#define SR_IM0 0x00000100
#define SR_IM1 0x00000200
#define SR_IM2 0x00000400
#define SR_IM3 0x00000800
#define SR_IM4 0x00001000
#define SR_IM5 0x00002000
#define SR_IM6 0x00004000
#define SR_IM7 0x00008000
#define SR_IMASK 0x0000ff00
#define SR_NMI 0x00080000 /* NMI occurred */
#define SR_SR 0x00100000 /* soft reset occurred */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_BEV 0x00400000 /* boot exception vectors */
#define SR_PX 0x00800000 /* user 64-bit reg / 32-bit addr */
#define SR_MX 0x01000000 /* enable MDMX/DSP ASE */
#define SR_RE 0x02000000 /* reverse endian (user mode) */
#define SR_FR 0x04000000 /* 64-bit fpu registers */
#define SR_RP 0x08000000 /* reduce power */
#define SR_CU0 0x10000000 /* coprocessor 0 enable */
#define SR_CU1 0x20000000 /* coprocessor 1 enable */
#define SR_CU2 0x40000000 /* coprocessor 2 enable */
#define SR_CU3 0x80000000 /* coprocessor 3 enable */
/*
* MIPS32r2 HWREna Register (CP0 Register 7, Select 0)
*/
#define HWRENA_CPUNUM 0x00000001
#define HWRENA_SYNCSTEP 0x00000002
#define HWRENA_CC 0x00000004
#define HWRENA_CCRES 0x00000008
/*
* MIPS32r2 IntCtl Register (CP0 Register 12, Select 1)
*/
#define INTCTL_IPTI 0xe0000000 /* timer i/u pending bit */
#define INTCTL_IPTI_SHIFT 29
#define INTCTL_IPPCI 0x1c000000 /* perfctr i/u pending bit */
#define INTCTL_IPPCI_SHIFT 26
#define INTCTL_VS 0x000003e0 /* vector spacing */
#define INTCTL_VS_0 (0x00<<5)
#define INTCTL_VS_32 (0x01<<5)
#define INTCTL_VS_64 (0x02<<5)
#define INTCTL_VS_128 (0x04<<5)
#define INTCTL_VS_256 (0x08<<5)
#define INTCTL_VS_512 (0x10<<5)
/*
* MIPS32r2 SRSCtl Register (CP0 Register 12, Select 2)
*/
#define SRSCTL_HSS 0x3c000000 /* highest shadow set */
#define SRSCTL_HSS_SHIFT 26
#define SRSCTL_EICSS 0x003c0000 /* EIC shadow set */
#define SRSCTL_EICSS_SHIFT 18
#define SRSCTL_ESS 0x0000f000 /* exception shadow set */
#define SRSCTL_ESS_SHIFT 12
#define SRSCTL_PSS 0x000003c0 /* previous shadow set */
#define SRSCTL_PSS_SHIFT 6
#define SRSCTL_CSS 0x0000000f /* current shadow set */
#define SRSCTL_CSS_SHIFT 0
/*
* MIPS32 Config0 Register (CP0 Register 16, Select 0)
*/
#define CFG0_M 0x80000000 /* Config1 implemented */
#define CFG0_BE 0x00008000 /* Big Endian */
#define CFG0_ATMASK 0x00006000 /* Architecture type: */
#define CFG0_AT_M32 (0<<13) /* MIPS32 */
#define CFG0_AT_M64_A32 (1<<13) /* MIPS64, 32-bit addresses */
#define CFG0_AT_M64_A64 (2<<13) /* MIPS64, 64-bit addresses */
#define CFG0_AT_RES (3<<13)
#define CFG0_ARMASK 0x00001c00
#define CFG0_ARSHIFT 10
#define CFG0_MTMASK 0x00000380
#define CFG0_MT_NONE (0<<7)
#define CFG0_MT_TLB (1<<7)
#define CFG0_MT_BAT (2<<7)
#define CFG0_MT_NONSTD (3<<7)
#define CFG0_VI 0x00000008 /* Icache is virtual */
#define CFG0_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
/*
* R4000 compatibility Config Register (actually processor dependent)
*/
#define CFG_BE CFG0_BE /* Big Endian */
#define CFG_K0MASK CFG0_K0MASK /* KSEG0 coherency algorithm */
/*
* MIPS32 Config1 Register (CP0 Register 16, Select 1)
*/
#define CFG1_M 0x80000000 /* Config2 implemented */
#define CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */
#define CFG1_MMUSSHIFT 25
#define CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */
#define CFG1_ISSHIFT 22
#define CFG1_ILMASK 0x00380000 /* icache line size 2<<n */
#define CFG1_ILSHIFT 19
#define CFG1_IAMASK 0x00070000 /* icache ways - 1 */
#define CFG1_IASHIFT 16
#define CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */
#define CFG1_DSSHIFT 13
#define CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */
#define CFG1_DLSHIFT 10
#define CFG1_DAMASK 0x00000380 /* dcache ways - 1 */
#define CFG1_DASHIFT 7
#define CFG1_C2 0x00000040 /* Coprocessor 2 present */
#define CFG1_MD 0x00000020 /* MDMX implemented */
#define CFG1_PC 0x00000010 /* performance counters implemented */
#define CFG1_WR 0x00000008 /* watch registers implemented */
#define CFG1_CA 0x00000004 /* compression (mips16) implemented */
#define CFG1_EP 0x00000002 /* ejtag implemented */
#define CFG1_FP 0x00000001 /* fpu implemented */
/*
* MIPS32r2 Config2 Register (CP0 Register 16, Select 2)
*/
#define CFG2_M 0x80000000 /* Config3 implemented */
#define CFG2_TUMASK 0x70000000 /* tertiary cache control */
#define CFG2_TUSHIFT 28
#define CFG2_TSMASK 0x0f000000 /* tcache sets per wway 64<<n */
#define CFG2_TSSHIFT 24
#define CFG2_TLMASK 0x00f00000 /* tcache line size 2<<n */
#define CFG2_TLSHIFT 20
#define CFG2_TAMASK 0x000f0000 /* tcache ways - 1 */
#define CFG2_TASHIFT 16
#define CFG2_SUMASK 0x0000f000 /* secondary cache control */
#define CFG2_SUSHIFT 12
#define CFG2_SSMASK 0x00000f00 /* scache sets per wway 64<<n */
#define CFG2_SSSHIFT 8
#define CFG2_SLMASK 0x000000f0 /* scache line size 2<<n */
#define CFG2_SLSHIFT 4
#define CFG2_SAMASK 0x0000000f /* scache ways - 1 */
#define CFG2_SASHIFT 0
/*
* MIPS32r2 Config3 Register (CP0 Register 16, Select 3)
*/
#define CFG3_M 0x80000000 /* Config4 implemented */
#define CFG3_ISAONEXC 0x00010000 /* ISA mode on exception entry */
#define CFG3_DSPP 0x00000400 /* DSP ASE present */
#define CFG3_LPA 0x00000080 /* Large physical addresses */
#define CFG3_VEIC 0x00000040 /* Vectored external i/u controller */
#define CFG3_VI 0x00000020 /* Vectored i/us */
#define CFG3_SP 0x00000010 /* Small page support */
#define CFG3_MT 0x00000004 /* MT ASE present */
#define CFG3_SM 0x00000002 /* SmartMIPS ASE */
#define CFG3_TL 0x00000001 /* Trace Logic */
/*
* Primary cache mode
*/
#define CFG_C_UNCACHED 2
#define CFG_C_WBACK 3
#define CFG_C_NONCOHERENT 3
#if 0
/* These cache modes are CPU specific */
#define CFG_C_WTHRU_NOALLOC 0
#define CFG_C_WTHRU_ALLOC 1
#define CFG_C_COHERENTXCL 4
#define CFG_C_COHERENTXCLW 5
#define CFG_C_COHERENTUPD 6
#define CFG_C_UNCACHED_ACCEL 7
#endif
/*
* Primary Cache TagLo (CP0 Register 28, Select 0/2)
*/
#define TAG_PTAG_MASK 0xffffff00 /* Primary Tag */
#define TAG_PTAG_SHIFT 8
#define TAG_PSTATE_MASK 0x000000c0 /* Primary Cache State */
#define TAG_PSTATE_SHIFT 6
#define TAG_PSTATE_LOCK 0x00000020
#define TAG_PARITY_MASK 0x00000001 /* Primary Tag Parity */
#define TAG_PARITY_SHIFT 0
/* primary cache state (XXX actually implementation specific) */
#define PSTATE_INVAL 0
#define PSTATE_SHARED 1
#define PSTATE_CLEAN_EXCL 2
#define PSTATE_DIRTY_EXCL 3
/*
* Cache operations
*/
#define Index_Invalidate_I 0x00 /* 0 0 */
#define Index_Writeback_Inv_D 0x01 /* 0 1 */
#define Index_Writeback_Inv_T 0x02 /* 0 2 */
#define Index_Writeback_Inv_S 0x03 /* 0 3 */
#define Index_Load_Tag_I 0x04 /* 1 0 */
#define Index_Load_Tag_D 0x05 /* 1 1 */
#define Index_Load_Tag_T 0x06 /* 1 2 */
#define Index_Load_Tag_S 0x07 /* 1 3 */
#define Index_Store_Tag_I 0x08 /* 2 0 */
#define Index_Store_Tag_D 0x09 /* 2 1 */
#define Index_Store_Tag_T 0x0A /* 2 2 */
#define Index_Store_Tag_S 0x0B /* 2 3 */
#define Hit_Invalidate_I 0x10 /* 4 0 */
#define Hit_Invalidate_D 0x11 /* 4 1 */
#define Hit_Invalidate_T 0x12 /* 4 2 */
#define Hit_Invalidate_S 0x13 /* 4 3 */
#define Fill_I 0x14 /* 5 0 */
#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
#define Hit_Writeback_Inv_T 0x16 /* 5 2 */
#define Hit_Writeback_Inv_S 0x17 /* 5 3 */
#define Hit_Writeback_D 0x19 /* 6 1 */
#define Hit_Writeback_T 0x1A /* 6 1 */
#define Hit_Writeback_S 0x1B /* 6 3 */
#define Fetch_Lock_I 0x1C /* 7 0 */
#define Fetch_Lock_D 0x1D /* 7 1 */
/* MIPS32 WatchLo Register (CP0 Register 18) */
#define WATCHLO_VA 0xfffffff8
#define WATCHLO_I 0x00000004
#define WATCHLO_R 0x00000002
#define WATCHLO_W 0x00000001
/* MIPS32 WatchHi Register (CP0 Register 19) */
#define WATCHHI_M 0x80000000
#define WATCHHI_G 0x40000000
#define WATCHHI_ASIDMASK 0x00ff0000
#define WATCHHI_ASIDSHIFT 16
#define WATCHHI_MASK 0x00000ffc
#define WATCHHI_I 0x00000004
#define WATCHHI_R 0x00000002
#define WATCHHI_W 0x00000001
/* MIPS32 PerfCnt Register (CP0 Register 25) */
#define PERFCNT_M 0x80000000
#define PERFCNT_EVENTMASK 0x000007e0
#define PERFCNT_EVENTSHFT 5
#define PERFCNT_IE 0x00000010
#define PERFCNT_U 0x00000008
#define PERFCNT_S 0x00000004
#define PERFCNT_K 0x00000002
#define PERFCNT_EXL 0x00000001
/* MIPS32r2 PageGrain Register (CP0 Register 5, Select 1) */
#define PAGEGRAIN_ELPA 0x20000000 /* Enable large phusical addresses */
#define PAGEGRAIN_ESP 0x10000000 /* Enable small (1KB) page support */
/* MIPS32r2 EBase Register (CP0 Register 15, Select 1) */
#define EBASE_BASE 0xfffff000 /* Exception base */
#define EBASE_CPU 0x000003ff /* CPU number */
#ifdef __ASSEMBLER__
/*
* MIPS32 Coprocessor 0 register numbers
*/
#define C0_INDEX $0
#define C0_INX $0
#define C0_RANDOM $1
#define C0_RAND $1
#define C0_ENTRYLO0 $2
#define C0_TLBLO0 $2
#define C0_ENTRYLO1 $3
#define C0_TLBLO1 $3
#define C0_CONTEXT $4
#define C0_CTXT $4
#define C0_PAGEMASK $5
#define C0_PAGEGRAIN $5,1
#define C0_WIRED $6
#define C0_HWRENA $7
#define C0_BADVADDR $8
#define C0_VADDR $8
#define C0_COUNT $9
#define C0_ENTRYHI $10
#define C0_TLBHI $10
#define C0_COMPARE $11
#define C0_STATUS $12
#define C0_SR $12
#define C0_INTCTL $12,1
#define C0_SRSCTL $12,2
#define C0_SRSMAP $12,3
#define C0_CAUSE $13
#define C0_CR $13
#define C0_EPC $14
#define C0_PRID $15
#define C0_EBASE $15,1
#define C0_CONFIG $16
#define C0_CONFIG0 $16,0
#define C0_CONFIG1 $16,1
#define C0_CONFIG2 $16,2
#define C0_CONFIG3 $16,3
#define C0_LLADDR $17
#define C0_WATCHLO $18
#define C0_WATCHHI $19
#define C0_DEBUG $23
#define C0_DEPC $24
#define C0_PERFCNT $25
#define C0_ERRCTL $26
#define C0_CACHEERR $27
#define C0_TAGLO $28
#define C0_ITAGLO $28
#define C0_DTAGLO $28,2
#define C0_TAGLO2 $28,4
#define C0_DATALO $28,1
#define C0_IDATALO $28,1
#define C0_DDATALO $28,3
#define C0_DATALO2 $28,5
#define C0_TAGHI $29
#define C0_DATAHI $29,1
#define C0_ERRPC $30
#define C0_DESAVE $31
$index = $0
$random = $1
$entrylo0 = $2
$entrylo1 = $3
$context = $4
$pagemask = $5
$wired = $6
$hwrena = $7
$vaddr = $8
$badvaddr = $8
$count = $9
$entryhi = $10
$compare = $11
$sr = $12
$cr = $13
$epc = $14
$prid = $15
$config = $16
$lladdr = $17
$watchlo = $18
$watchhi = $19
$debug = $23
$depc = $24
$perfcnt = $25
$errctl = $26
$cacheerr = $27
$taglo = $28
$taghi = $29
$errpc = $30
$desave = $31
#else /* !__ASSEMBLER__ */
/*
* Standard types
*/
typedef unsigned long reg32_t; /* a 32-bit register */
typedef unsigned long long reg64_t; /* a 64-bit register */
#if __mips == 64 || __mips64
typedef unsigned long long reg_t;
typedef signed long long sreg_t;
#else
typedef unsigned long reg_t;
typedef signed long sreg_t;
#endif
/*
* MIPS32 Coprocessor 0 register numbers
*/
#define C0_INDEX 0
#define C0_INX 0
#define C0_RANDOM 1
#define C0_RAND 1
#define C0_ENTRYLO0 2
#define C0_TLBLO0 2
#define C0_ENTRYLO1 3
#define C0_TLBLO1 3
#define C0_CONTEXT 4
#define C0_CTXT 4
#define C0_PAGEMASK 5
#define C0_WIRED 6
#define C0_HWRENA 7
#define C0_BADVADDR 8
#define C0_VADDR 8
#define C0_COUNT 9
#define C0_ENTRYHI 10
#define C0_TLBHI 10
#define C0_COMPARE 11
#define C0_STATUS 12
#define C0_SR 12
#define C0_CAUSE 13
#define C0_CR 13
#define C0_EPC 14
#define C0_PRID 15
#define C0_CONFIG 16
#define C0_LLADDR 17
#define C0_WATCHLO 18
#define C0_WATCHHI 19
#define C0_DEBUG 23
#define C0_DEPC 24
#define C0_PERFCNT 25
#define C0_ERRCTL 26
#define C0_CACHEERR 27
#define C0_TAGLO 28
#define C0_TAGHI 29
#define C0_ERRPC 30
#define C0_DESAVE 31
#define _mips_nop() \
__asm__ __volatile ("%(ssnop%)" : :)
#if ! __mips16 || __force_mips16_asm
# define _mips_sync() __asm__ __volatile__ ("sync" : : : "memory")
#else
extern void _mips_sync(void);
#endif
/* wait for unmasked interrupt */
#define _mips_wait() \
__asm__ __volatile ("wait")
/*
* Define macros for accessing the MIPS32 coprocessor 0 registers.
* Most apart from "set" return the original register value.
*/
#if ! __mips16 || __force_mips16_asm
#define _m32c0_mfc0(reg, sel) \
__extension__ ({ \
register unsigned long __r; \
__asm__ __volatile ("mfc0 %0,$%1,%2" \
: "=d" (__r) \
: "JK" (reg), "JK" (sel)); \
__r; \
})
#if __mips_isa_rev >= 2
#define _m32c0_mtc0(reg, sel, val) \
do { \
__asm__ __volatile ("%(mtc0 %z0,$%1,%2; ehb%)" \
: \
: "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \
: "memory"); \
} while (0)
#else
#define _m32c0_mtc0(reg, sel, val) \
do { \
__asm__ __volatile ("%(mtc0 %z0,$%1,%2; ssnop; ssnop; ehb%)" \
: \
: "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \
: "memory"); \
} while (0)
#endif
#define _m32c0_mxc0(reg, sel, val) \
__extension__ ({ \
register reg32_t __o; \
__o = _m32c0_mfc0 (reg, sel); \
_m32c0_mtc0 (reg, sel, val); \
__o; \
})
#else
#define _m32c0_mfc0(rn, sel) _mips_xxc0 ((rn) + (sel)*32, 0, 0)
#define _m32c0_mtc0(rn, sel, v) (void) _mips_xxc0 ((rn) + (sel)*32, ~0, v)
#define _m32c0_mxc0(rn, sel, v) _mips_xxc0 ((rn) + (sel)*32, ~0, v)
#endif /* !__mips16 */
/* generic equivalents for mips/cpu.h */
#define _mips_mfc0(r) _m32c0_mfc0(r,0)
#define _mips_mtc0(r,v) _m32c0_mtc0(r,0,v)
/* MIPS32 Config0 register */
#define mips32_getconfig0() _mips_mfc0(C0_CONFIG)
#define mips32_setconfig0(v) _mips_mtc0(C0_CONFIG,v)
#define mips32_xchconfig0(v) _mips_mxc0(C0_CONFIG,v)
#define mips32_bicconfig0(clr) _mips_bcc0(C0_CONFIG,clr)
#define mips32_bisconfig0(set) _mips_bsc0(C0_CONFIG,set)
#define mips32_bcsconfig0(c,s) _mips_bcsc0(C0_CONFIG,c,s)
/* MIPS32 Config1, 2 & 3 register */
#define mips32_getconfig1() _m32c0_mfc0(C0_CONFIG,1)
#define mips32_getconfig2() _m32c0_mfc0(C0_CONFIG,2)
#define mips32_getconfig3() _m32c0_mfc0(C0_CONFIG,3)
/* MIPS32 WatchLo register */
#define mips32_getwatchlo(sel) _mips_xxc0(C0_WATCHLO + (sel)*32, 0, 0)
#define mips32_setwatchlo(sel,v) _mips_xxc0(C0_WATCHLO + (sel)*32, ~0, v)
/* MIPS32 WatchHi register */
#define mips32_getwatchhi(sel) _mips_xxc0(C0_WATCHHI + (sel)*32, 0, 0)
#define mips32_setwatchhi(sel,v) _mips_xxc0(C0_WATCHHI + (sel)*32, ~0, v)
/* MIPS32 Debug register */
#define mips32_getdebug() _mips_mfc0(C0_DEBUG)
#define mips32_setdebug(v) _mips_mtc0(C0_DEBUG,v)
#define mips32_xchdebug(v) _mips_mxc0(C0_DEBUG,v)
#define mips32_bicdebug(clr) _mips_bcc0(C0_DEBUG,clr)
#define mips32_bisdebug(set) _mips_bsc0(C0_DEBUG,set)
#define mips32_bcsdebug(c,s) _mips_bcsc0(C0_DEBUG,c,s)
/* MIPS32 ErrCtl register */
#define mips32_geterrctl() _mips_mfc0(C0_ERRCTL)
#define mips32_seterrctl(x) _mips_mtc0(C0_ERRCTL,x)
#define mips32_xcherrctl(x) _mips_mxc0(C0_ERRCTL,x)
#define mips32_bicerrctl(clr) _mips_bcc0(C0_ERRCTL,clr)
#define mips32_biserrctl(set) _mips_bsc0(C0_ERRCTL,set)
#define mips32_bcserrctl(c,s) _mips_bcsc0(C0_ERRCTL,c,s)
/* MIPS32 TagLo register */
#define mips32_getitaglo() _mips_mfc0(C0_TAGLO) /* alias define */
#define mips32_setitaglo(x) _mips_mtc0(C0_TAGLO,x) /* alias define */
#define mips32_xchitaglo(x) _mips_mxc0(C0_TAGLO,x) /* alias define */
#define mips32_getdtaglo() _m32c0_mfc0(C0_TAGLO,2)
#define mips32_setdtaglo(x) _m32c0_mtc0(C0_TAGLO,2,x)
#define mips32_xchdtaglo(x) _m32c0_mxc0(C0_TAGLO,2,x)
#define mips32_gettaglo2() _m32c0_mfc0(C0_TAGLO,4)
#define mips32_settaglo2(x) _m32c0_mtc0(C0_TAGLO,4,x)
#define mips32_xchtaglo2(x) _m32c0_mxc0(C0_TAGLO,4,x)
/* MIPS32 DataLo register */
#define mips32_getdatalo() _m32c0_mfc0(C0_TAGLO,1)
#define mips32_setdatalo(x) _m32c0_mtc0(C0_TAGLO,1,x)
#define mips32_xchdatalo(x) _m32c0_mxc0(C0_TAGLO,1,x)
#define mips32_getidatalo() mips32_getdatalo() /* alias define */
#define mips32_setidatalo(x) mips32_setdatalo(x) /* alias define */
#define mips32_xchidatalo(x) mips32_xchdatalo(x) /* alias define */
#define mips32_getddatalo() _m32c0_mfc0(C0_TAGLO,3)
#define mips32_setddatalo(x) _m32c0_mtc0(C0_TAGLO,3,x)
#define mips32_xchddatalo(x) _m32c0_mxc0(C0_TAGLO,3,x)
#define mips32_getdatalo2() _m32c0_mfc0(C0_TAGLO,5)
#define mips32_setdatalo2(x) _m32c0_mtc0(C0_TAGLO,5,x)
#define mips32_xchdatalo2(x) _m32c0_mxc0(C0_TAGLO,5,x)
/* MIPS32r2 IntCtl register */
#define mips32_getintctl() _m32c0_mfc0(12,1)
#define mips32_setintctl(x) _m32c0_mtc0(12,1,x)
#define mips32_xchintctl(x) _m32c0_mxc0(12,1,x)
/* MIPS32r2 SRSCtl register */
#define mips32_getsrsctl() _m32c0_mfc0(12,2)
#define mips32_setsrsctl(x) _m32c0_mtc0(12,2,x)
#define mips32_xchsrsctl(x) _m32c0_mxc0(12,2,x)
/* MIPS32r2 SRSMap register */
#define mips32_getsrsmapl() _m32c0_mfc0(12,3)
#define mips32_setsrsmap(x) _m32c0_mtc0(12,3,x)
#define mips32_xchsrsmap(x) _m32c0_mxc0(12,3,x)
/* MIPS32r2/SmartMIPS PageGrain register */
#define mips32_getpagegrain() _m32c0_mfc0(5,1)
#define mips32_setpagegrain(x) _m32c0_mtc0(5,1,x)
#define mips32_xchpagegrain(x) _m32c0_mxc0(5,1,x)
/* MIPS32r2 HWREna register */
#define mips32_gethwrena() _mips_mfc0(C0_HWRENA)
#define mips32_sethwrena(v) _mips_mtc0(C0_HWRENA,v)
#define mips32_xchhwrena(v) _mips_mxc0(C0_HWRENA,v)
#define mips32_bichwrena(clr) _mips_bcc0(C0_HWRENA,clr)
#define mips32_bishwrena(set) _mips_bsc0(C0_HWRENA,set)
#define mips32_bcshwrena(c,s) _mips_bcsc0(C0_HWRENA,c,s)
/* MIPS32r2 EBase register */
#define mips32_getebase() _m32c0_mfc0(15,1)
#define mips32_setebase(x) _m32c0_mtc0(15,1,x)
#define mips32_xchebase(x) _m32c0_mxc0(15,1,x)
/* Define MIPS64 user-level intrinsics */
#include "mips/mips32.h"
/* CP0 intrinsics */
#if __mips_isa_rev >= 2 && (! __mips16 || __force_mips16_asm)
/* MIPS32r2 atomic interrupt disable */
#define _mips_intdisable() __extension__({ \
unsigned int __v; \
__asm__ __volatile__ ("di %0; ehb" : "=d" (__v)); \
__v; \
})
/* MIPS32r2 atomic interrupt restore */
#define _mips_intrestore(x) \
mips_setsr (x)
/* MIPS32r2 set SRSCtl.PSS (previous shadow set), returning old value */
extern unsigned int _mips32r2_xchsrspss (unsigned int);
#if 0
/* simpler to make this a function in mipscp0.sx */
#define _mips32r2_xchsrspss(set) \
__extension__({ \
unsigned int __tmp, __old; \
__asm __volatile ("mfc0 %0,$12,2\n\
ext %1,%0,6,4\n\
ins %0,%z2,6,4\n\
mtc0 %0,$12,2\n\
la %0,1f\n\
jr.hb %0\n\
1:"
: "=&d" (__tmp), "=&d" (__old) \
: "dJ" (set)); \
__old; \
})
#endif
/* MIPS32r2 write previous gpr */
#define _mips32r2_wrpgpr(regno, val) \
do { \
__asm __volatile ("wrpgpr $%0,%z1" \
: /* no outputs */ \
: "JK" (regno), "dJ" (val)); \
} while (0)
/* MIPS32r2 read previous gpr */
#define _mips32r2_rdpgpr(regno) \
__extension__({ \
reg_t __val; \
__asm __volatile ("rdpgpr %0,$%1" \
: "=d" (__val) \
: "JK" (regno)); \
__val; \
})
#endif /* __mips_isa_rev >= 2 && ! __mips16 */
#endif /* __ASSEMBLER__ */
/* MIPS32 PREF instruction hint codes */
#define PREF_LOAD 0
#define PREF_STORE 1
#define PREF_LOAD_STREAMED 4
#define PREF_STORE_STREAMED 5
#define PREF_LOAD_RETAINED 6
#define PREF_STORE_RETAINED 7
#define PREF_WRITEBACK_INVAL 25
#define PREF_PREPAREFORSTORE 30
#ifdef __cplusplus
}
#endif
#endif /* _M32C0_H_ */

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#ifndef __REGDEF_H
#define __REGDEF_H
#define zero $0 /* wired zero */
//#define AT $1 /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* values for function returns */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26 /* reserved for OS */
#define k1 $27 /* reserved for OS */
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* frame pointer */
#define ra $31 /* return address */
#endif /* __REGDEF_H */

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/*
* release_mp.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Release other processors so they can boot
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <regdef.h>
#include <cps.h>
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(release_mp)
blez r19_more_cores, done_release_mp // If no more cores then we are done.
li a3, 1
beqz r30_cpc_addr, release_next_core // If no CPC then use GCR_CO_RESET_RELEASE
nop // else use CPC Power Up command.
powerup_next_core:
// Send PwrUp command to next core causing execution at their reset exception vector.
move a0, a3
sll a0, 16
sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(r30_cpc_addr)
li a0, PWR_UP // "PwrUp" power domain command.
sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(r30_cpc_addr)
bne r19_more_cores, a3, powerup_next_core
add a3, a3, 1
jr ra
nop
release_next_core:
// Release next core to execute at their reset exception vector.
move a0, a3
sll a0, 16
sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER
sw zero, 0x4000(r22_gcr_addr) // GCR_CO_RESET_RELEASE
bne r19_more_cores, a3, release_next_core
add a3, a3, 1
done_release_mp:
jr ra
nop
END(release_mp)

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/*
* interAptiv/set_gpr_boot_values.S
*
* Created on: May 9, 2012
* Author: MIPS TECHNOLOGIES, INC
* Set GPR values for interAptiv Family of Cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <m32c0.h>
#include <regdef.h>
#include <cps.h>
// defines not yet in m32c0.h
#define C0_MVPCTL $0, 1
#define C0_MVPCONF0 $0, 2
#define C0_VPECTL $1, 1
#define C0_VPECONF0 $1, 2
#define C0_TCSTATUS $2, 1
#define C0_TCRESTART $2, 3
#define C0_TCHALT $2, 4
#define C0_TCBIND $2, 2
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(set_gpr_boot_values)
li r1_all_ones, 0xffffffff // Simplify code and improve clarity
mfc0 a0, C0_EBASE // Read CP0 EBase
ext r23_cpu_num, a0, 0, 4 // Extract CPUNum
li r24_malta_word, MALTA_DISP_ADDR // Need for reporting failed assertions.
la gp, _gp // All vpe share globals.
li sp, STACK_BASE_ADDR // Each vpe gets it's own stack.
ins sp, r23_cpu_num, STACK_SIZE_LOG2, 3
check_mt_ase:
mfc0 a0, C0_CONFIG1 // C0_Config1
bgez a0, no_mt_ase // bit 31 sign bit set?
mfc0 a0, C0_CONFIG2 // C0_Config2
bgez a0, no_mt_ase // bit 31 sign bit set?
mfc0 a0, C0_CONFIG3 // C0_Config3
and a0, (1 << 2) // M_Config3MT
beqz a0, no_mt_ase
li r10_has_mt_ase, 0
has_mt_ase:
li r10_has_mt_ase, 1
// Every vpe will set up the following to simplify resource initialization.
mfc0 a0, C0_TCBIND // Read CP0 TCBind
ext r9_vpe_num, a0, 0, 4 // Extract CurVPE
ext r18_tc_num, a0, 21, 8 // Extract CurTC
mfc0 a0, C0_MVPCONF0 // C0_MVPConf0
ext r21_more_tcs, a0, 0, 8 // Extract PTC
b check_cps
ext r20_more_vpes, a0, 10, 4 // Extract VPE
no_mt_ase: // This processor does not implement the MIPS32 MT ASE. Set up defaults.
sdbbp // Failed assertion: not mt.
check_cps: // Determine if there is a coherency manager present. (Implementation Dependent.)
mfc0 r25_coreid, C0_PRID // CP0 PRId.
ext a0, r25_coreid, 8, 16 // Extract Manuf and Core.
li a3, 0x01A1 // interAptiv Multi core
beq a3, a0, is_cps
nop
is_not_interAptiv: // This processor is not a InterAptive Core so exit!
sdbbp // Failed assertion: not interAptiv.
is_cps:
li r11_is_cps, 1
// Verify that we can find the GCRs.
la a1, GCR_CONFIG_ADDR // KSEG1(GCRBASE)
lw a0, GCR_BASE(a1) // read GCR_BASE
ins a1, $0, 29, 3 // Convert KSEG1 to physical address.
ins a0, $0, 0, 15 // Isolate physical base address of GCR (Clear lower bits).
beq a1, a0, gcr_found
nop
sdbbp // Can't find GCR. RTL config override of MIPS default?
gcr_found:
// Every vpe will set up the following to simplify resource initialization.
li r22_gcr_addr, GCR_CONFIG_ADDR
lw r8_core_num, (CORE_LOCAL_CONTROL_BLOCK + GCR_CL_ID) (r22_gcr_addr) // Load GCR_CL_ID
lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
ext r19_more_cores, a0, PCORES, PCORES_S // Extract PCORES
done_init_gpr:
jr ra
nop
END(set_gpr_boot_values)

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/*
* interAptiv/start.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Start of boot code for interAptiv Family of Cores
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <boot.h>
#include <m32c0.h>
#include <regdef.h>
#include <cps.h>
/* EL Change. Add address for optional user-specified vpe wakeup function. */
#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
.globl TX_THREAD_SMP_WAKEUP_LOGIC_SETUP
#endif
/* EL Change End. */
.set noreorder // Don't allow the assembler to reorder instructions.
.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
R E S E T E X C E P T I O N H A N D L E R
**************************************************************************************/
// RAMHACK: Removed boot exception handlers.
/**************************************************************************************
B O O T E X C E P T I O N H A N D L E R S
**************************************************************************************/
// RAMHACK: Removed boot exception handlers.
/**************************************************************************************
R A M E X C E P T I O N H A N D L E R S
**************************************************************************************/
.section ".vector_0x000","ax"
.globl tlb_refill_exception
tlb_refill_exception:
sdbbp
.section ".vector_0x100","ax"
.globl cache_error_exception
cache_error_exception:
sdbbp
.section ".vector_0x180","ax"
.globl general_exception
general_exception:
/* EL Change: Branch to ThreadX error handling. */
la k0, _tx_error_exceptions
jalr k1, k0
nop
/* EL Change end. */
sdbbp
.section ".vector_0x200","ax"
.globl iv1_interrupt
iv1_interrupt:
/* EL Change: Branch to ThreadX error handling. */
la k0, _tx_exception_handler
jalr k1, k0
nop
/* Disable previous exception handler, since ThreadX is taking care of all exceptions now. */
#if 0
li k0, MALTA_DISP_ADDR // Malta ASCII character display.
mfc0 k1, C0_EBASE // Get cp0 EBase
ext k1, k1, 0, 10 // Extract CPUNum
sll k1, k1, 3 // Build offset for display char.
addiu k1, 8
addu k0, k0, k1 // Pointer to a single display character.
li k1, 'H' // Indicate that this vpe is in the handler.
sw k1, 0(k0) // Write ASCII char to Malta ASCII display.
li k0, (GIC_SH_WEDGE | GIC_BASE_ADDR)
mfc0 k1, C0_EBASE // Get cp0 EBase
ext k1, k1, 0, 10 // Extract CPUNum
addiu k1, 0x20 // Offset to base of IPI interrupts.
sw k1, 0(k0) // Clear this IPI.
la k0, start_test
mfc0 k1, C0_EBASE // Get cp0 EBase
ext k1, k1, 0, 10 // Extract CPUNum
sll k1, k1, 2
addu k0, k0, k1 // index into CMP global "C" variable start_test
lw k1, 0(k0) # Pickup start_test value
addiu k1, k1, 1 # Increment start_test value
sw k1, 0(k0) // Release "cpu"/vpe to execute "C" test code.
eret
nop
#endif
/* EL Change end. */
.section ".vector_0x280","ax"
.globl xtlb_refill
xtlb_refill:
sdbbp
.section ".vector_0x300","ax"
.globl cache_error
cache_error:
sdbbp
/**************************************************************************************
**************************************************************************************/
// RAMHACK: Entry point is _start (execution is started here in (uncached) kseg0.
.section ".text","ax"
/* (with vaddr[12..0] = 0 for alignment with GCR_CO_RESET_BASE). */
.globl _start
_start:
b verify_isa # Note: Real systems might want to save/dump full context.
nop
.globl verify_isa
verify_isa: // Verify device ISA meets code requirements (MIPS32R2 or later.)
mfc0 a0, C0_CONFIG // Read CP0 Config
srl a0, 10 // Shift [AT AR] into LSBs.
andi a3, a0, 0x18 // Inspect CP0 Config[AT]
beqz a3, is_mips32 // Branch if executing on MIPS32 ISA.
andi a3, a0, 0x07 // Inspect CP0 Config[AR]
sdbbp // Failed assertion: MIPS32R2.
.globl is_mips32
is_mips32:
bnez a3, init_common_resources // Continue if ISA is MIPS32R2 or later.
nop
sdbbp // Failed assertion MIPS32R2.
/**************************************************************************************
What is initialized on execution depends on the core/vpe executing it.
(A non-MT device is treated as tc0/vpe0, non-CMP device is treated as core0.)
**************************************************************************************/
.globl init_common_resources
init_common_resources: // initializes resources for virtual or physical "cpu".
la a2,init_gpr // Fill register file with set value.
jalr a2
nop
la a2, set_gpr_boot_values // Fill register file boot info.
jalr a2
nop
// Clear Malta Display if processor 0
bnez r9_vpe_num, clear_done
lui v0, 0xbf00
li v1, 0x20
sw v1, 1048(v0)
sw v1, 1056(v0)
sw v1, 1064(v0)
sw v1, 1072(v0)
sw v1, 1080(v0)
sw v1, 1088(v0)
sw v1, 1096(v0)
sw v1, 1104(v0)
.globl clear_done
clear_done:
la a2, init_cp0 // Init CP0 Status, Count, Compare, Watch*, and Cause.
jalr a2
nop
// Determine if we have a TLB
mfc0 v1, C0_CONFIG // read C0_Config
ext v1, v1, 7, 3 // extract MT field
li a3, 0x1 // load a 1 to check against
bne v1, a3, done_tlb // no tlb?
nop
// determined if this is VPE 0 so skip shared TLB check
beqz r9_vpe_num, do_tlb // VPE 0?
nop
// Must be VPE1 determined if TLB is shared if it is skip init_tlb (already done by VPE0)
mfc0 a0, $0, 1 // MVPControl
ext a0, a0, 3, 1 // MVPControl[STLB]
beq a0, zero, done_tlb // TLB shared?
nop
do_tlb:
la a2, init_tlb // Generate unique EntryHi contents per entry pair.
jalr a2
nop
.globl done_tlb
done_tlb:
la a2, init_gic // Configure the global interrupt controller.
jalr a2
nop
bnez r9_vpe_num, init_done // If we are not a vpe0 then we are done.
nop
.globl init_core_resources
init_core_resources: // We are a vpe0.
la a2, disable_L23 // Disable L2/L3 caches
jalr a2
nop
la a2, init_icache // Initialize the L1 instruction cache. (Executing using I$ on return.)
jalr a2
nop
// The changing of Kernel mode cacheability must be done from KSEG1
// Since the code is executing from KSEG0 It needs to do a jump to KSEG1 change K0 and jump back to KSEG0
la a2, change_k0_cca
li a1, 0xf
ins a2, a1, 29, 1 // changed to KSEG1 address by setting bit 29
jalr a2
nop
// L1 Cache icache is now enabled
la a2, init_dcache // Initialize the L1 data cache
jalr a2
nop
la a2, init_itc // Initialize Inter-Thread Communications unit
jalr a2
nop
bnez r8_core_num, init_sys_resources_done // Only core0/vpe0 needs to init systems resources.
nop
.globl init_sys_resources
init_sys_resources: // We are core0 vpe0.
la a2, init_cpc // Initialize the CPS CPC (Cluster Power Controller.)
jalr a2
nop
la a2, init_cm // Initialize the CPS CM (Coherence Manager.)
jalr a2
nop
#ifdef DENALI
la a2, init_CoreFPGA6_mem // Initialize the ROC-it2 MC (Memory Controller.)
jalr a2
nop
#endif
la a2, copy_c2_ram // Copy "C" code and data to RAM and zero bss (uncached.)
jalr a2
nop
la a2, init_L23 // Initialize the unified L2 and L3 caches
jalr a2
nop
/* EL Change. Ensure that the VPE release flag is cleared ahead of BSS clear. */
la $8, _tx_thread_smp_release_cores_flag # Build address of release flag
sw $0, 0($8) # Clear the flag explicity to make other VPEs don't see it before everything is initialized
/* EL end Change. */
la a2, release_mp // Release other cores to execute this boot code.
jalr a2
nop
init_sys_resources_done: // All Cores (VPE0)
la a2, join_domain // Join the Coherence domain. (OK to use D$ on return.)
jalr a2
nop
la a2, init_vpe1 // Set up MT ASE vpe1 to execute this boot code also.
jalr a2
nop
/* EL Change. Add optional user-specified VPE wakeup setup code call. */
#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
/* Call optional user-specific code for VPE initialization. */
subu $29, 8 # Allocate space to save ra
sw $31, 4($29) # Save R31
la $9, TX_THREAD_SMP_WAKEUP_LOGIC_SETUP
jalr $9 # User-specified VPE setup logic
nop #
lw $31, 4($29) # Restore ra
addu $29, 8 # De-allocate stack storage
#endif
/* EL Change End. */
.globl init_done
init_done:
/* EL Change. Removed call to demo code and instead setup for ThreadX execution. */
/* For all VPEs, store the cpu number into the UserLocal field so it is easy to pickup. */
mtc0 r23_cpu_num, $4,2 # Save the logical VPE in UserLocal so we don't have calculate it over and over! */
/* Save the stack pointer in the array indexed by cpu number. */
la $8, _tx_thread_system_stack_ptr # Build address of base of system stack array
sll $9, r23_cpu_num, 2 # Build offset into array
addu $8, $8, $9 # Build address of array entry
sw $29, 0($8) # Store system stack for each VPE
/* Setup status register in preparation for entering ThreadX. */
mfc0 $8, $12 # Pickup SR
li $9, 0xFFFFFFF8 # Build mask to clear error, exception bits
and $8, $8, $9 # Clear bits
ori $8, $8, 1 # Disable all interrupts
mtc0 $8, $12 # Setup the status register
ehb #
/* Check for Core 0, VPE 0 for processing ThreadX initialization. All other VPEs will wait until the first
VPE has completed initialization before running. */
bne r23_cpu_num, $0, _additional_vpe # If non-zero, an additional vpe is present
nop #
/* Core 0, VPE 0 processing. */
/* Save some information in globals. */
la $8, _tx_thread_smp_detected_cores # Build address of total number of cores detected
addiu $9, r19_more_cores, 1 # Calculate the total cores
sw $9, 0($8) # Save in global variable
la $8, _tx_thread_smp_detected_vpes_per_core # Build address of VPEs per core detected
addiu $9, r20_more_vpes, 1 # Caculate the total vpes per core
sw $9, 0($8) # Save in global variable
/* Simply branch to main to finish initializing ThreadX SMP. */
bal main # Branch to main
nop #
/* If return, branch to all_done code. */
b all_done
nop
_additional_vpe:
/* Additional VPE, transfer control to ThreadX. */
b _tx_thread_smp_initialize_wait # Enter ThreadX for additional VPEs
nop
.globl all_done
all_done:
b all_done
/* Comment out the previous "init_done" code since it is replaced with ThreadX-specfic code. */
#if 0
mtc0 r23_cpu_num, $4,2 # Setup UserLocal
// Prepare for eret to main (sp and gp set up per vpe in init_gpr).
la ra, all_done // If main return then go to all_done:.
la a1, main
mtc0 a1, C0_ERRPC // ErrorEPC
// initialize global variable num_cores.
// la a1, num_cores
// RAMHACK: caches are coherent use cached reference to "C" static "num_cores".
// ins a1, r1_all_ones, 29, 1 // Uncached kseg1
// add a0, r19_more_cores, 1
// sw a0, 0(a1)
// Prepare arguments for main()
move a0, r23_cpu_num // main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
move a1, r8_core_num // main(arg1) is the core number.
move a2, r9_vpe_num // main(arg2) is the vpe number.
addiu a3, r20_more_vpes, 1 // main(arg3) is the number of vpe on this core.
// RAMHACK: Main appears to take first arg from r16 (s0) in GHS build?
move s0, r23_cpu_num // main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
eret // Exit reset exception handler for this vpe and start execution of main().
/**************************************************************************************
**************************************************************************************/
.globl all_done
all_done:
// Main returns the "cpu" number
// All cpu spin on atomic potato++
// la a1, potato
try_again:
ll a0, 0(a1)
addiu a0, a0, 1
sc a0, 0(a1) // Attempt atomic potato++
beq a0, $0, try_again // Fail, retry.
nop
b try_again // Success, do again.
nop
b all_done
nop
#endif
/* EL Change end. */

433
ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h MIPS32_interAptiv/GNU */
/* 6.x */
/* */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial release version 6.x */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/************* Define ThreadX SMP constants. *************/
/* Define the ThreadX SMP maximum number of cores. */
#ifndef TX_THREAD_SMP_MAX_CORES
#define TX_THREAD_SMP_MAX_CORES 6 /* 3 cores, 2 VPEs per core */
#endif
/* Define the ThreadX SMP core mask. */
#ifndef TX_THREAD_SMP_CORE_MASK
#define TX_THREAD_SMP_CORE_MASK 0x3F /* here bit 0 represents Core 0, bit 1 represents Core 1, etc. */
#endif
/* Define ThreadX SMP initialization macro. */
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
/* Define ThreadX SMP pre-scheduler initialization. */
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
/* Enable the inter-core interrupt logic. When commented out, inter-core interrupts are not enabled. */
#define TX_THREAD_SMP_INTER_CORE_INTERRUPT
/* Determine if the optional wakeup macro has been defined. This definition can be
made here or prior to this file being included. When TX_THREAD_SMP_WAKEUP(i) is
defined (where "i" is the core), the wakeup logic is also brought in. */
#ifdef TX_THREAD_SMP_WAKEUP
#define TX_THREAD_SMP_WAKEUP_LOGIC
#endif
/* Determine if there is customer-specific wakeup logic needed. */
#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
/* Include customer-specific wakeup code. */
#include "tx_thread_smp_core_wakeup.h"
#endif
/* Ensure that the in-line resume/suspend define is not allowed. */
#ifdef TX_INLINE_THREAD_RESUME_SUSPEND
#undef TX_INLINE_THREAD_RESUME_SUSPEND
#endif
/************* End ThreadX SMP constants. *************/
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif
/* Define the TX_MEMSET macro to remove library reference. */
#define TX_MEMSET(a,b,c) { \
UCHAR *ptr; \
UCHAR value; \
UINT i, size; \
ptr = (UCHAR *) ((VOID *) a); \
value = (UCHAR) b; \
size = (UINT) c; \
for (i = 0; i < size; i++) \
{ \
*ptr++ = value; \
} \
}
/* Ensure that the in-line resume/suspend define is not allowed. */
#ifdef TX_INLINE_THREAD_RESUME_SUSPEND
#undef TX_INLINE_THREAD_RESUME_SUSPEND
#endif
/* Define compiler library include files. */
#include <stdlib.h>
#include <string.h>
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef short SHORT;
typedef unsigned short USHORT;
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX MIPS port. */
#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */
#define TX_INT_ENABLE 0x00000001 /* Enable interrupt value */
/* Define prototype of internal time get function. */
ULONG _tx_thread_smp_time_get(void);
ULONG _tx_thread_smp_time_get_upper(void);
/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply
simulate the time-stamp source with a counter. */
#define read_tbu() _tx_thread_smp_time_get_upper()
#define read_tbl() _tx_thread_smp_time_get()
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get()
#endif
#else
#ifndef TX_TRACE_TIME_SOURCE
ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
#endif
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#ifdef TX_MISRA_ENABLE
#define TX_DISABLE_INLINE
#else
#define TX_INLINE_INITIALIZATION
#endif
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifndef TX_MISRA_ENABLE
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* The MIPS32 architecture has the CLZ instruction. Redefine the macro for calculating the
lowest bit set to use this instruction. */
#ifndef TX_DISABLE_INLINE
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \
b = __CLZ32(m); \
b = 31 - b;
#endif
/************* Define ThreadX SMP data types and function prototypes. *************/
struct TX_THREAD_STRUCT;
/* Define the ThreadX SMP protection structure. */
typedef struct TX_THREAD_SMP_PROTECT_STRUCT
{
ULONG tx_thread_smp_protect_in_force;
struct TX_THREAD_STRUCT *
tx_thread_smp_protect_thread;
ULONG tx_thread_smp_protect_core;
ULONG tx_thread_smp_protect_count;
/* Implementation specific information follows. */
ULONG tx_thread_smp_protect_get_caller;
ULONG tx_thread_smp_protect_sr;
ULONG tx_thread_smp_protect_release_caller;
} TX_THREAD_SMP_PROTECT;
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_smp_protect();
#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save);
/* Define some extra variables used by the MIPS interAptiv SMP implementation. */
#ifdef TX_THREAD_INIT
#define THREAD_SMP_DECLARE
#else
#define THREAD_SMP_DECLARE extern
#endif
THREAD_SMP_DECLARE ULONG _tx_thread_smp_detected_cores;
THREAD_SMP_DECLARE ULONG _tx_thread_smp_detected_vpes_per_core;
THREAD_SMP_DECLARE ULONG _tx_thread_smp_system_error;
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register;
#endif
/************* End ThreadX SMP data type and function prototype definitions. *************/
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
#define TX_FPU64_ENABLED 2
#else
#define TX_FPU64_ENABLED 0
#endif
#ifdef TX_ENABLE_DSP_SUPPORT
#define TX_DSP_ENABLED 4
#else
#define TX_DSP_ENABLED 0
#endif
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FPU64_ENABLED | TX_DSP_ENABLED)
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.x *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

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Microsoft's Azure RTOS ThreadX for ThreadX SMP for MIPS32 interAptiv/VPE
Using the GNU Tools
1. Installation
ThreadX for the MIPS32 interAptiv is delivered on a single CD-ROM compatible disk.
The entire distribution can be found in the sub-directory:
\threadx
To install ThreadX to your hard-disk, either run the supplied installer
program Setup.exe or copy the distribution from the CD manually.
To copy the ThreadX distribution manually, make a threadx directory on your
hard-disk (we recommend C:\threadx\mips32_interaptiv\gnu) and copy all the contents
of the threadx sub-directory on the distribution disk. The following
is an example MS-DOS copy command from the distribution directory
(assuming source is d: and c: is your hard-drive):
d:\threadx> xcopy /S *.* c:\threadx\mips32_interaptiv\gnu
2. Building the ThreadX run-time Library
First make sure you are in the ThreadX directory you have created on your
hard-drive. Also, make sure that you have setup your path and other
environment variables necessary for the GNU development environment.
At this point you may run the build_threadx.bat batch file. This will
build the ThreadX run-time environment in the ThreadX directory.
C:\threadx\mips32_interaptiv\gnu> build_threadx
You should observe assembly and compilation of a series of ThreadX source
files. At the end of the batch file, they are all combined into the
run-time library file: tx.a. This file must be linked with your
application in order to use ThreadX.
3. Demonstration System
Building the demonstration is easy; simply execute the build_threadx_demo.bat
batch file while inside your ThreadX directory on your hard-disk.
C:\threadx\mips32_interaptiv\gnu> build_threadx_demo
You should observe the compilation of demo_threadx.c (which is the demonstration
application) and linking with tx.a. The resulting file demo_threadx.out is an ELF
binary file that can be downloaded and executed under simulation or on the MIPS
MALTA evaluation board.
4. System Initialization
The system entry point using the GNU tools is at the label _start.
This is defined within the start.S file supplied by MIPS. In addition,
this is where all static and global preset C variable initialization
processing is called from.
Once the startup function finishes, main is called, which is also where ThreadX
initialization takes place. The main initialization function for ThreadX is
_tx_initialize_low_level and is located in the file tx_initialize_low_level.S.
This function is responsible for setting up various system data structures,
interrupt vectors, and the periodic timer interrupt source of ThreadX.
In addition, _tx_initialize_low_level determines where the first available
RAM memory address is located. This address is supplied to tx_application_define.
By default, the first available RAM memory address is assumed to start at the
beginning of the ThreadX symbol _free_memory. If changes are made to the
demo_threadx.ld file, the _free_memory symbol should remain the last allocated
section in the main RAM area. The starting address of this section is passed
to tx_application_define.
5. User defines
Please reference the ThreadX_SMP_User_Guide.pdf for details on build options.
6. Register Usage and Stack Frames
The GNU MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25)
are scratch registers for each function. All other registers used by a
C function must be preserved by the function. ThreadX takes advantage
of this in situations where a context switch happens as a result of making a
ThreadX service call (which is itself a C function). In such cases, the
saved context of a thread is only the non-scratch registers.
The following defines the saved context stack frames for context switches
that occur as a result of interrupt handling or from thread-level API calls.
All suspended threads have one of these two types of stack frames. The top
of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the
associated thread control block TX_THREAD.
Offset Interrupted Stack Frame Non-Interrupt Stack Frame
0x000 1 0
0x004 s8 ($30) s8 ($30)
0x008 s7 ($23) s7 ($23)
0x00C s6 ($22) s6 ($22)
0x010 s5 ($21) s5 ($21)
0x014 s4 ($20) s4 ($20)
0x018 s3 ($19) s3 ($19)
0x01C s2 ($18) s2 ($18)
0x020 s1 ($17) s1 ($17)
0x024 s0 ($16) s0 ($16)
0x028 hi hi
0x02C lo lo
0x030 t9 ($25) ra ($31)
0x034 t8 ($24) SR
0x038 t7 ($15) f31 <------------+
0x03C t6 ($14) |
0x040 t5 ($13) f30 |
0x044 t4 ($12) |
0x048 t3 ($11) f29 |
0x04C t2 ($10) |
0x050 t1 ($9) f28 |
0x054 t0 ($8) |
0x058 a3 ($7) f27 |
0x05C a2 ($6) |
0x060 a1 ($5) f26 |
0x064 a0 ($4)
0x068 v1 ($3) f25 TX_ENABLE_64BIT_FPU_SUPPORT
0x06C v0 ($2)
0x070 at ($1) f24 |
0x074 ra ($31) |
0x078 SR f23 |
0x07C EPC |
0x080 f31 <-----------+ f22 |
0x088 f30 | f21 |
0x090 f29 | f20 |
0x098 f28 | fcr31 <------------+
0x09C | not used
0x0A0 f27 |
0x0A4 |
0x0A8 f26 |
0x0AC |
0x0B0 f25 |
0x0B4 |
0x0B8 f24 |
0x0BC |
0x0C0 f23 |
0x0C8 f22 |
0x0D0 f21 |
0x0D8 f20 |
0x0E0 f19 |
0x0E8 f18 |
0x0F0 f17
0x0F8 f16 TX_ENABLE_64BIT_FPU_SUPPORT
0x100 f15
0x108 f14 |
0x110 f13 |
0x118 f12 |
0x120 f11 |
0x128 f10 |
0x130 f9 |
0x138 f8 |
0x140 f7 |
0x148 f6 |
0x150 f5 |
0x158 f4 |
0x160 f3 |
0x168 f2 |
0x170 f1 |
0x178 f0 |
0x180 fcr31 <-----------+
0x184 not used
7. Improving Performance
The distribution version of ThreadX is built without any compiler
optimizations. This makes it easy to debug because you can trace or set
breakpoints inside of ThreadX itself. Of course, this costs some
performance. To make ThreadX run faster, you can change the tx.gpj project
to disable debug information and enable the desired optimizations.
In addition, you can eliminate the ThreadX basic API error checking by
compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
defined before tx_api.h is included.
8. Interrupt Handling
ThreadX provides complete and high-performance interrupt handling for MIPS32 interAptiv
targets. The general exception handler is at address: 0x80000180 (0xA0000180 non-
cached). The ThreadX general exception handler is defined in the file
tx_initialize_low_level.S at the label _tx_exception_handler. A small piece of
code to jump to this exception handler is copied to the general exception handler
address during initialization.
8.1 Application ISRs
Multiple exceptions may be processed with a single execution of the exception
handler. This is because the Cause register could indicate more than a single
exception. Processing for each exception is also located in the general
exception handler that starts at the label: _tx_exception_handler. Application
ISRs can be added into this handler.
9. Theory of Operation - SMP
ThreadX for the MIPS interAptiv brings Symmetric Multi-Processing (SMP) technology to
the MIPS interAptiv. ThreadX application threads (of varying priority) that are "READY"
to run are dynamically allocated to VPEs during scheduling, thus taking full
advantage of all available MIPS interAptiv VPEs. This results in true SMP processing,
including automatic load balancing of application thread execution across all
available MIPS interAptiv VPEs.
Initialization is done exclusively in VPE 0, which is the default running VPE
after reset. The additional VPEs on the interAptiv are initialized by VPE 0 and simply
wait until VPE 0 completes the initialization before they start running.
During thread execution, multithreading in the MIPS interAptiv is fully enabled. This
means that application threads may be preempted by higher priority threads, may
suspend themselves, or may exit the system upon completion of their work. Protection
between VPEs is accomplished via a conditional load-store structure (see the variable
_tx_thread_smp_protection and the typedef TX_THREAD_SMP_PROTECT found in tx_thread.h).
All VPEs are eligible to handle interrupts under the direction of the application. The
ThreadX timer interrupt is by default assigned to VPE 0 for processing. Please see
the code in tx_timer_interrupt.S for the implementation.
ThreadX for the MIPS interAptiv also optionally supports the MIPS interAptiv FPU.
The number of VPEs is defined by the compile time constant TX_THREAD_SMP_MAX_CORES.
By default, this is set to 2 in tx_port.h. It may be changed to support any number
of cores either in tx_port.h or on the command line via a -D symbol definition.
10. Current Limitations
1. Hardware priority assignment for each TC is not setup.
2. DSP registers are not saved/restored.
11. Debug Information
ThreadX SMP for MIPS32 interAptiv has a built-in debug facility to capture SMP scheduling
information. This is enabled by building the system with TX_THREAD_SMP_DEBUG_ENABLE
defined. This results in the creation of circular log containing debug information.
The log is defined in the variable _tx_thread_smp_debug_info_array.
12. Revision History
For generic code revision information, please refer to the readme_threadx_generic.txt
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
xx-xx-xxxx Initial ThreadX version 6.x of MIPS32_interAptiv VPE/GNU port.
Copyright(c) 1996-2020 Microsoft Corporation
https://azure.com/rtos

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
/**************************************************************************/
/**************************************************************************/
#define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. */
INITIAL_SR = 0xFF00 # All IM bits set
SW_INTERRUPT_0 = 0x0100 # Software interrupt 0
SW_INTERRUPT_1 = 0x0200 # Software interrupt 1
INTERRUPT_0 = 0x0400 # Interrupt 0
INTERRUPT_1 = 0x0800 # Interrupt 1
INTERRUPT_2 = 0x1000 # Interrupt 2
INTERRUPT_3 = 0x2000 # Interrupt 3
INTERRUPT_4 = 0x4000 # Interrupt 4
INTERRUPT_5 = 0x8000 # Interrupt 5
EXCEPTION_VECTOR = 0x00000180 # General exception vector
TEN_MS_COUNT = 120000 # 10 ms clock rate
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
.globl _tx_initialize_low_level
_tx_initialize_low_level:
di # Ensure interrupts are disabled
ehb #
mfc0 $8, $12 # Pickup current SR
ori $8, $8, INITIAL_SR # Build initial SR
mtc0 $8, $12 # Setup SR
/* Save the system stack pointer. */
/* _tx_thread_system_stack_ptr = (VOID_PTR) (SP); */
la $8, _tx_thread_system_stack_ptr # Pickup address of system
/* # stack pointer */
sw $29, ($8) # Save system stack pointer
/* Save the first available memory address. */
/* _tx_initialize_unused_memory = (VOID_PTR) _free_memory; */
la $9, _free_memory # Pickup first free address
la $10, _tx_initialize_unused_memory # Pickup address of unused
/* # memory */
sw $9, ($10) # Save unused memory address
/* Set up the counter/compare registers to generate a periodic interrupt. */
mtc0 $0, $9 # Initialize CP0 timer count register to zero
ehb #
li $9,TEN_MS_COUNT # Default value
mtc0 $9, $11 # Set timer compare register
ehb #
/* Done, return to caller. */
j $31 # Return to caller
nop # Delay slot
/* } */
/* Define the interrupt/exception handler trampoline code. This needs to
be copied to address 0x80000180 cached or 0xA0000180 non-cache. */
.globl _tx_exception_trampoline
_tx_exception_trampoline:
la $26,_tx_exception_handler # Pickup exception handler address
j $26 # Jump to exception handler
nop # Delay slot
nop # Fill with nops....
nop #
nop #
nop #
nop #
_tx_exception_trampoline_end:
/* Define the actual interrupt/exception handler. Since this routine must handle
multiple exceptions, the context save/restore functions are called automatically.
Application specific ISR processing added to this routine must be inserted into
the proper place and use registers in accordance with the MIPS compiler, i.e.
$16-$23 (s0-s7) and $30 (s8) must be saved if they are used. C functions called
from this area will automatically save/restore these registers if they are used. */
.globl _tx_exception_handler
_tx_exception_handler:
mfc0 $26, $13 # Pickup the cause register
ehb #
andi $26, $26, 0x3C # Isolate the exception code
bne $26, $0, _tx_error_exceptions # If non-zero, an error exception is present
nop # Delay slot
la $27, _tx_thread_smp_system_error # Build address to system error flag
lw $27, ($27) # Pickup system error flag
_system_error_loop:
bne $27, $0, _system_error_loop # If error, just sit here!
nop
/* Otherwise, an interrupt exception is present. Call context save before we
process normal interrupts. */
la $26, _tx_thread_context_save # Pickup address of context save function
jalr $27,$26 # Call context save
nop # Delay slot
/* Perform interrupt processing here! When context save returns, interrupts are
disabled and all compiler scratch registers are available. Also, s0 is saved and
is used in this function to hold the contents of the CAUSE register. */
mfc0 $16, $13 # Pickup the cause register
/* Interrupts may be re-enabled after this point. */
/* Check for Interrupt 0. */
andi $8, $16, INTERRUPT_0 # Isolate interrupt 0 flag
beqz $8, _tx_not_interrupt_0 # If not set, skip interrupt 0 processing
nop # Delay slot
/* Interrupt 0 processing goes here! */
#ifdef TX_ENABLE_EVENT_TRACE
li $4,1 # Build interrupt type
la $9, _tx_trace_isr_enter_insert # Build interrupt enter logging address
jal $9 # Call interrupt enter event logging
nop #
#endif
/* Clear inter-processor interrupt (and increment counter). */
mfc0 $8, $4,2 # Pickup UserLocal (VPE number)
la $9, _tx_thread_smp_inter_core_interrupts # Address of inter-processor interrupt
sll $8, $8, 2 # Build offset to proper counter index
addu $9, $9, $8 # Build address of this VPE's counter
lw $8, 0($9) # Pickup current value
addiu $8, $8, 1 # Increment current value
sw $8, 0($9) # Store value back
li $8, GIC_SH_WEDGE #
mfc0 $9, $15, 1 # Get cp0 EBase
ext $9, $9, 0, 10 # Extract CPUNum
addiu $9, 0x20 # Offset to base of IPI interrupts.
sw $9, 0($8) # Clear this IPI.
#ifdef TX_ENABLE_EVENT_TRACE
li $4,1 # Build interrupt type
la $9, _tx_trace_isr_exit_insert # Build interrupt exit logging address
jal $9 # Call interrupt exit event logging
nop #
#endif
_tx_not_interrupt_0:
/* Check for Interrupt 1. */
andi $8, $16, INTERRUPT_1 # Isolate interrupt 1 flag
beqz $8, _tx_not_interrupt_1 # If not set, skip interrupt 1 processing
nop # Delay slot
/* Interrupt 1 processing goes here! */
_tx_not_interrupt_1:
/* Check for Interrupt 2. */
andi $8, $16, INTERRUPT_2 # Isolate interrupt 2 flag
beqz $8, _tx_not_interrupt_2 # If not set, skip interrupt 2 processing
nop # Delay slot
/* Interrupt 2 processing goes here! */
_tx_not_interrupt_2:
/* Check for Interrupt 3. */
andi $8, $16, INTERRUPT_3 # Isolate interrupt 3 flag
beqz $8, _tx_not_interrupt_3 # If not set, skip interrupt 3 processing
nop # Delay slot
/* Interrupt 3 processing goes here! */
_tx_not_interrupt_3:
/* Check for Interrupt 4. */
andi $8, $16, INTERRUPT_4 # Isolate interrupt 4 flag
beqz $8, _tx_not_interrupt_4 # If not set, skip interrupt 4 processing
nop # Delay slot
/* Interrupt 4 processing goes here! */
_tx_not_interrupt_4:
/* Check for Interrupt 5. */
andi $8, $16, INTERRUPT_5 # Isolate interrupt 5 flag
beqz $8, _tx_not_interrupt_5 # If not set, skip interrupt 5 processing
nop # Delay slot
/* Interrupt 5 processing goes here! */
/* Interrupt 5 is the count/compare timer interrupt. */
#ifdef TX_ENABLE_EVENT_TRACE
li $4,0 # Build interrupt type
la $9, _tx_trace_isr_enter_insert # Build interrupt enter logging address
jal $9 # Call interrupt enter event logging
nop #
#endif
/* Interrupt 5 is the count/compare timer interrupt. */
mtc0 $0, $9 # Initialize CP0 count register to zero
ehb #
li $9, TEN_MS_COUNT # 10 ms @ 66 MHz
mtc0 $9, $11 # Set compare register, reset count reg.
ehb #
/* Call the ThreadX timer routine. */
la $8, _tx_timer_interrupt # Build timer interrupt address
jal $8 # Call timer interrupt handler
nop #
#ifdef TX_ENABLE_EVENT_TRACE
li $4,0 # Build interrupt type
la $9, _tx_trace_isr_exit_insert # Build interrupt exit logging address
jal $9 # Call interrupt exit event logging
nop #
#endif
_tx_not_interrupt_5:
/* Check for Software Interrupt 0. */
andi $8, $16, SW_INTERRUPT_0 # Isolate software interrupt 0 flag
beqz $8, _tx_not_interrupt_sw_0 # If not set, skip sw interrupt 0 processing
nop # Delay slot
/* Software interrupt 0 processing goes here! */
_tx_not_interrupt_sw_0:
/* Check for Software Interrupt 1. */
andi $8, $16, SW_INTERRUPT_1 # Isolate software interrupt 1 flag
beqz $8, _tx_not_interrupt_sw_1 # If not set, skip sw interrupt 1 processing
nop # Delay slot
/* Software interrupt 1 processing goes here! */
_tx_not_interrupt_sw_1:
la $8, _tx_thread_context_restore # Pickup address of context restore function
j $8 # Jump to context restore - does not return!
nop # Delay slot
/* Error Exception processing goes here! */
.globl _tx_error_exceptions
_tx_error_exceptions:
b _tx_error_exceptions # Default error exception processing
nop # Delay slot
/* Reference the build options and the version ID to ensure they are part of the image. */
la $8, _tx_build_options
la $9, _tx_version_id

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_TCBind $2,2
#define C0_TCContext $2,5
#define C0_VPECtl $1,1
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_restore(VOID)
{ */
.globl _tx_thread_context_restore
_tx_thread_context_restore:
/* Lockout interrupts. */
di # Disable interrupts
ehb #
mfc0 $25, UserLocal # Pickup VPE ID
sll $24, $25, 2 # Build index based on VPE number
/* Determine if interrupts are nested. */
/* if (--_tx_thread_system_state[VPE])
{ */
la $9, _tx_thread_system_state # Pickup addr of nested interrupt count
addu $9, $9, $24 # Index by VPE
lw $8, ($9) # Pickup nested interrupt count
subu $8, $8, 1 # Decrement the nested interrupt counter
beqz $8,_tx_thread_not_nested_restore # If 0, not nested restore
sw $8, ($9) # Store new nested count
/* Interrupts are nested. */
/* Just recover the saved registers and return to the point of
interrupt. */
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0. */
bne $25, $0, _tx_skip_nest_restore # If not VPE 0, skip FPU scratch restore
nop #
lw $8, 384($29) # Recover fcr31
ctc1 $8, $31 # Setup fcr31
ldc1 $f19, 224($29) # Recover f19
ldc1 $f18, 232($29) # Recover f18
ldc1 $f17, 240($29) # Recover f17
ldc1 $f16, 248($29) # Recover f16
ldc1 $f15, 256($29) # Recover f15
ldc1 $f14, 264($29) # Recover f14
ldc1 $f13, 272($29) # Recover f13
ldc1 $f12, 280($29) # Recover f12
ldc1 $f11, 288($29) # Recover f11
ldc1 $f10, 296($29) # Recover f10
ldc1 $f9, 304($29) # Recover f9
ldc1 $f8, 312($29) # Recover f8
ldc1 $f7, 320($29) # Recover f7
ldc1 $f6, 328($29) # Recover f6
ldc1 $f5, 336($29) # Recover f5
ldc1 $f4, 344($29) # Recover f4
ldc1 $f3, 352($29) # Recover f3
ldc1 $f2, 360($29) # Recover f2
ldc1 $f1, 368($29) # Recover f1
ldc1 $f0, 376($29) # Recover f0
_tx_skip_nest_restore:
#endif
/* Recover standard registers. */
lw $16, 36($29) # Recover s0
lw $8, 40($29) # Recover hi
lw $9, 44($29) # Recover low
mthi $8 # Setup hi
mtlo $9 # Setup lo
lw $8,124($29) # Recover EPC
lw $9,120($29) # Recover SR
mtc0 $8, $14 # Setup EPC
ehb #
lw $25, 48($29) # Recover t9
mtc0 $9, $12 # Restore SR
ehb #
lw $24, 52($29) # Recover t8
lw $15, 56($29) # Recover t7
lw $14, 60($29) # Recover t6
lw $13, 64($29) # Recover t5
lw $12, 68($29) # Recover t4
lw $11, 72($29) # Recover t3
lw $10, 76($29) # Recover t2
lw $9, 80($29) # Recover t1
lw $8, 84($29) # Recover t0
lw $7, 88($29) # Recover a3
lw $6, 92($29) # Recover a2
lw $5, 96($29) # Recover a1
lw $4, 100($29) # Recover a0
lw $3, 104($29) # Recover v1
lw $2, 108($29) # Recover v0
.set noat
lw $1, 112($29) # Recover at
.set at
lw $31,116($29) # Recover ra
addu $29, $29, 392 # Recover stack frame
eret # Return to point of interrupt
nop # Delay
/* } */
_tx_thread_not_nested_restore:
/* Determine if a thread was interrupted and no preemption is required. */
/* else if (((_tx_thread_current_ptr[VPE]) && (_tx_thread_current_ptr[VPE] == _tx_thread_tc_execute_list[VPE])
|| (_tx_thread_preempt_disable))
{ */
la $9, _tx_thread_current_ptr # Pickup address of current ptr
addu $9, $9, $24 # Build address of current pointer for this VPE
lw $8, ($9) # Pickup current thread pointer
beqz $8, _tx_thread_idle_system_restore # If NULL, idle system restore
nop #
la $11, _tx_thread_execute_ptr # Pickup address of execute thread pointer
addu $11, $11, $24 # Add VPE index here to see if this is the thread
lw $10, ($11) # Pickup thread execute pointer
beq $8, $10, _tx_thread_no_preempt_restore # If the current and execute are the same then, restore the current thread
nop # Delay slot
la $10, _tx_thread_smp_protection # Build address of protection structure
lw $11, 8($10) # Pickup the VPE with protection
bne $11, $25,_tx_thread_preempt_restore # If this is a different VPE, preempt current thread
nop #
la $13, _tx_thread_preempt_disable # Pickup address of preempt disable flag
lw $12, ($13) # Pickup preempt disable flag
beq $12, $0, _tx_thread_preempt_restore # If not set, preempt interrupted thread
nop # Delay slot
_tx_thread_no_preempt_restore:
/* Restore interrupted thread or ISR. */
/* Pickup the saved stack pointer. */
/* SP = _tx_thread_current_ptr[VPE] -> tx_thread_stack_ptr; */
lw $29, 8($8) # Switch back to thread's stack
/* Recover the saved context and return to the point of interrupt. */
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0. */
lw $15, 176($8) # Pickup FPU enable flag
bne $25, $0, _tx_skip_int_restore # If not VPE 0, skip FPU scratch restore
nop # Delay
beq $15, $0, _tx_skip_int_restore # If FPU not enabled, skip FPU scratch restore
nop #
lw $9, 384($29) # Recover fcr31
ctc1 $9, $31 # Setup fcr31
ldc1 $f19, 224($29) # Recover f19
ldc1 $f18, 232($29) # Recover f18
ldc1 $f17, 240($29) # Recover f17
ldc1 $f16, 248($29) # Recover f16
ldc1 $f15, 256($29) # Recover f15
ldc1 $f14, 264($29) # Recover f14
ldc1 $f13, 272($29) # Recover f13
ldc1 $f12, 280($29) # Recover f12
ldc1 $f11, 288($29) # Recover f11
ldc1 $f10, 296($29) # Recover f10
ldc1 $f9, 304($29) # Recover f9
ldc1 $f8, 312($29) # Recover f8
ldc1 $f7, 320($29) # Recover f7
ldc1 $f6, 328($29) # Recover f6
ldc1 $f5, 336($29) # Recover f5
ldc1 $f4, 344($29) # Recover f4
ldc1 $f3, 352($29) # Recover f3
ldc1 $f2, 360($29) # Recover f2
ldc1 $f1, 368($29) # Recover f1
ldc1 $f0, 376($29) # Recover f0
_tx_skip_int_restore:
#endif
/* Recover standard registers. */
lw $16, 36($29) # Recover s0
lw $8, 40($29) # Recover hi
lw $9, 44($29) # Recover low
mthi $8 # Setup hi
mtlo $9 # Setup lo
lw $8,124($29) # Recover EPC
lw $9,120($29) # Recover SR
mtc0 $8, $14 # Setup EPC
ehb #
lw $25, 48($29) # Recover t9
mtc0 $9, $12 # Restore SR
ehb #
lw $24, 52($29) # Recover t8
lw $15, 56($29) # Recover t7
lw $14, 60($29) # Recover t6
lw $13, 64($29) # Recover t5
lw $12, 68($29) # Recover t4
lw $11, 72($29) # Recover t3
lw $10, 76($29) # Recover t2
lw $9, 80($29) # Recover t1
lw $8, 84($29) # Recover t0
lw $7, 88($29) # Recover a3
lw $6, 92($29) # Recover a2
lw $5, 96($29) # Recover a1
lw $4, 100($29) # Recover a0
lw $3, 104($29) # Recover v1
lw $2, 108($29) # Recover v0
.set noat
lw $1, 112($29) # Recover at
.set at
lw $31,116($29) # Recover ra
addu $29, $29, 392 # Recover stack frame
eret # Return to point of interrupt
nop # Delay
/* }
else
{ */
_tx_thread_preempt_restore:
/* Save remaining context on the thread's stack. */
lw $9, 8($8) # Pickup thread's stack pointer
ori $12, $0, 1 # Build interrupt stack type
sw $12, ($9) # Store stack type
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0. */
lw $15, 176($8) # Pickup FPU enable flag
bne $25, $0, _tx_skip_preserved_save # If not VPE 0, skip FPU preserved save
nop #
beq $15, $0, _tx_skip_preserved_save # If FPU not enabled, skip FPU preserved save
nop
lw $7, 384($9) # Recover fcr31
ctc1 $7, $31 # Setup fcr31
sdc1 $f31, 128($9) # Store f31
sdc1 $f30, 136($9) # Store f30
sdc1 $f29, 144($9) # Store f29
sdc1 $f28, 152($9) # Store f28
sdc1 $f27, 160($9) # Store f27
sdc1 $f26, 168($9) # Store f26
sdc1 $f25, 176($9) # Store f25
sdc1 $f24, 184($9) # Store f24
sdc1 $f23, 192($9) # Store f23
sdc1 $f22, 200($9) # Store f22
sdc1 $f21, 208($9) # Store f21
sdc1 $f20, 216($9) # Store f20
_tx_skip_preserved_save:
#endif
/* Store standard preserved registers. */
sw $30, 4($9) # Store s8
sw $23, 8($9) # Store s7
sw $22, 12($9) # Store s6
sw $21, 16($9) # Store s5
sw $20, 20($9) # Store s4
sw $19, 24($9) # Store s3
sw $18, 28($9) # Store s2
sw $17, 32($9) # Store s1
/* # Note: s0 is already stored! */
#ifdef TX_ENABLE_EVENT_LOGGING
or $17, $24, $0 # Save VPE index offset value
or $16, $8, $0 # Save thread pointer into non-volatile
or $4, $8, $0 # Move thread pointer into input register
la $9, _tx_el_thread_preempted # Build address of thread preempted event routine
jal $9 # Call event logging routine
nop # Delay slot
or $8, $16, $0 # Recover thread pointer
or $24, $17, $0 # Reciver VPE index offset value
#endif
/* Save the remaining time-slice and disable it. */
/* if (_tx_timer_time_slice[VPE])
{ */
la $10, _tx_timer_time_slice # Pickup time slice variable address
addu $10, $10, $24 # Build index into time-slice
/* Check for time-slice race condition. */
la $12, _tx_timer_interrupt_active
__time_slice_wait:
lw $13, 0($12)
bne $13, $0, __time_slice_wait
lw $9, ($10) # Pickup time slice
la $12, _tx_thread_current_ptr # Pickup current thread pointer address
addu $12, $12, $24 # Build VPE index
beqz $9, _tx_thread_dont_save_ts # If 0, skip time slice processing
nop # Delay slot
/* _tx_thread_current_ptr[VPE] -> tx_thread_time_slice = _tx_timer_time_slice[VPE]
_tx_timer_time_slice[VPE] = 0; */
sw $9, 24($8) # Save current time slice
sw $0, ($10) # Clear global time slice
/* } */
_tx_thread_dont_save_ts:
/* Clear the current task pointer. */
/* _tx_thread_current_ptr[VPE] = TX_NULL; */
sw $0, ($12) # Clear current thread pointer
/* Set bit indicating the thread is ready for scheduling. */
lw $9, 152($8) # Pickup the thread's VPE control register
ori $9, $9, 0x8000 # Set ready bit (bit 15)
sync
sw $9, 152($8) # Make this thread ready for scheduling
/* Return to the scheduler. */
/* _tx_thread_schedule(); */
_tx_thread_idle_system_restore:
/* Just return back to the scheduler! */
mfc0 $15, $12 # Pickup SR
li $8, 0xFFFFFFFD # Build mask for EXL bit
and $15, $15, $8 # Clear EXL bit
ori $15, $15, 1 # Set IE bit
mtc0 $15, $12 # Setup new SR with IE enabled
ehb #
la $8, _tx_thread_schedule # Build address of scheduling loop
jr $8 # Return to scheduler
nop # Delay slot
/* } */

295
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_TCBind $2,2
#define C0_TCContext $2,5
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ISRs */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_save(VOID)
{ */
.globl _tx_thread_context_save
_tx_thread_context_save:
/* Upon entry to this routine, it is assumed that interrupts are locked
out and the stack is exactly were it was when the interrupt occurred.
The return address is in $27 (k1). */
subu $29, $29, 392 # Allocate space for a full stack frame
/* # even though the whole thing might
# not be needed for awhile */
sw $25, 48($29) # Store t9
sw $24, 52($29) # Store t8
sw $8, 84($29) # Save t0
mfc0 $25, UserLocal # Pickup VPE ID
sll $24, $25, 2 # Build index based on VPE number
la $26, _tx_thread_system_state # Pickup address of system state
addu $26, $26, $24 # Index by VPE
lw $8, ($26) # Pickup system state
/* Check for a nested interrupt condition. */
/* if (_tx_thread_system_state[VPE]++)
{ */
beqz $8, _tx_thread_not_nested_save # If 0, first interrupt condition
addu $8, $8, 1 # Increment the nested interrupt counter
/* Nested interrupt condition. */
sw $8, ($26) # Store the interrupt counter
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0. */
bne $25, $0, _tx_skip_nest_int_save # If not VPE 0, skip FPU save
nop #
/* Save scratch floating point registers. */
cfc1 $8, $31 # Pickup floating point control reg
sdc1 $f19, 224($29) # Save f19
sdc1 $f18, 232($29) # Save f18
sdc1 $f17, 240($29) # Save f17
sdc1 $f16, 248($29) # Save f16
sdc1 $f15, 256($29) # Save f15
sdc1 $f14, 264($29) # Save f14
sdc1 $f13, 272($29) # Save f13
sdc1 $f12, 280($29) # Save f12
sdc1 $f11, 288($29) # Save f11
sdc1 $f10, 296($29) # Save f10
sdc1 $f9, 304($29) # Save f9
sdc1 $f8, 312($29) # Save f8
sdc1 $f7, 320($29) # Save f7
sdc1 $f6, 328($29) # Save f6
sdc1 $f5, 336($29) # Save f5
sdc1 $f4, 344($29) # Save f4
sdc1 $f3, 352($29) # Save f3
sdc1 $f2, 360($29) # Save f2
sdc1 $f1, 368($29) # Save f1
sdc1 $f0, 376($29) # Save f0
sw $8, 384($29) # Save fcr31
_tx_skip_nest_int_save:
#endif
/* Save the rest of the scratch registers on the stack and return to the
calling ISR. */
sw $16, 36($29) # Store s0
mfhi $8 # Pickup hi
mflo $26 # Pickup lo
sw $8, 40($29) # Store hi
sw $26, 44($29) # Store lo
sw $15, 56($29) # Store t7
sw $14, 60($29) # Store t6
sw $13, 64($29) # Store t5
sw $12, 68($29) # Store t4
sw $11, 72($29) # Store t3
sw $10, 76($29) # Store t2
sw $9, 80($29) # Store t1
sw $7, 88($29) # Store a3
sw $6, 92($29) # Store a2
sw $5, 96($29) # Store a1
sw $4, 100($29) # Store a0
sw $3, 104($29) # Store v1
sw $2, 108($29) # Store v0
.set noat
sw $1, 112($29) # Store at
.set at
sw $31, 116($29) # Store ra
mfc0 $8, $12 # Pickup SR
mfc0 $9, $14 # Pickup EPC
sw $8, 120($29) # Store SR
sw $9, 124($29) # Store EPC
/* Return to the ISR. */
j $27 # Return to ISR
nop #
_tx_thread_not_nested_save:
/* } */
/* Otherwise, not nested, check to see if a thread was running. */
/* else if (_tx_thread_current_ptr[VPE])
{ */
sw $8, ($26) # Store the interrupt counter
la $26, _tx_thread_current_ptr # Pickup address of current ptr
addu $26, $26, $24 # Build address of current pointer for this VPE
lw $8, ($26) # Pickup current thread pointer
beqz $8, _tx_thread_idle_system_save # If NULL, idle system was interrupted
sw $16, 36($29) # Store s0
/* Save minimal context of interrupted thread. */
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in TC 0. */
bne $25, $0, _tx_skip_int_save # If not VPE 0, skip FPU save
nop # Delay
lw $26, 176($8) # Pickup FPU enable flag
beq $26, $0, _tx_skip_int_save # If FPU not enabled, skip FPU save
nop # Delay
/* Save scratch floating point registers. */
cfc1 $8, $31 # Pickup floating point control reg
sdc1 $f19, 224($29) # Save f19
sdc1 $f18, 232($29) # Save f18
sdc1 $f17, 240($29) # Save f17
sdc1 $f16, 248($29) # Save f16
sdc1 $f15, 256($29) # Save f15
sdc1 $f14, 264($29) # Save f14
sdc1 $f13, 272($29) # Save f13
sdc1 $f12, 280($29) # Save f12
sdc1 $f11, 288($29) # Save f11
sdc1 $f10, 296($29) # Save f10
sdc1 $f9, 304($29) # Save f9
sdc1 $f8, 312($29) # Save f8
sdc1 $f7, 320($29) # Save f7
sdc1 $f6, 328($29) # Save f6
sdc1 $f5, 336($29) # Save f5
sdc1 $f4, 344($29) # Save f4
sdc1 $f3, 352($29) # Save f3
sdc1 $f2, 360($29) # Save f2
sdc1 $f1, 368($29) # Save f1
sdc1 $f0, 376($29) # Save f0
sw $8, 384($29) # Save fcr31
_tx_skip_int_save:
#endif
/* Save the standard scratch registers. */
mfhi $8 # Pickup hi
mflo $26 # Pickup lo
sw $8, 40($29) # Store hi
sw $26, 44($29) # Store lo
sw $15, 56($29) # Store t7
sw $14, 60($29) # Store t6
sw $13, 64($29) # Store t5
sw $12, 68($29) # Store t4
sw $11, 72($29) # Store t3
sw $10, 76($29) # Store t2
sw $9, 80($29) # Store t1
sw $7, 88($29) # Store a3
sw $6, 92($29) # Store a2
sw $5, 96($29) # Store a1
sw $4, 100($29) # Store a0
sw $3, 104($29) # Store v1
sw $2, 108($29) # Store v0
.set noat
sw $1, 112($29) # Store at
.set at
sw $31, 116($29) # Store ra
mfc0 $8, $12 # Pickup SR
mfc0 $9, $14 # Pickup EPC
sw $8, 120($29) # Store SR
sw $9, 124($29) # Store EPC
li $8, 1 # Build stack type
sw $8, ($29) # Store stack type
/* Save the current stack pointer in the thread's control block. */
/* _tx_thread_current_ptr[VPE] -> tx_thread_stack_ptr = sp; */
/* Switch to the system stack. */
/* sp = _tx_thread_system_stack_ptr[VPE]; */
la $9, _tx_thread_current_ptr # Pickup address of current ptr
addu $9, $9, $24 # Build address of current pointer for this VPE
lw $11, ($9) # Pickup current thread pointer
la $10,_tx_thread_system_stack_ptr # Pickup the stack pointer address
sw $29, 8($11) # Save stack pointer
addu $10, $10, $24 # Build offset to system stack pointer
lw $29, ($10) # Switch to system stack
j $27 # Return to ISR
nop #
/* }
else
{ */
_tx_thread_idle_system_save:
/* Interrupt occurred in the scheduling loop. */
addu $29, $29, 392 # Recover the reserved stack space
j $27 # Return to ISR
nop #
/* }
} */

88
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
RETURN_MASK = 0x0001
SET_SR_MASK_U = 0xFFFF
SET_SR_MASK_L = 0xFFFE
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_control(UINT new_posture)
{ */
.globl _tx_thread_interrupt_control
_tx_thread_interrupt_control:
/* Pickup current interrupt lockout posture. */
mfc0 $8, $12 # Pickup current SR
andi $2, $8, RETURN_MASK # Return value back to caller
/* Apply the new interrupt posture. */
lui $9, SET_SR_MASK_U # Build set SR mask
ori $9, $9, SET_SR_MASK_L #
and $8, $8, $9 # Isolate interrupt lockout bits
or $8, $8, $4 # Put new lockout bits in
mtc0 $8, $12 # Set new interrupt lockout
jr.hb $31 # Return to caller
nop # Delay slot
/* } */

369
ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_TCBind $2,2
#define C0_TCContext $2,5
#define C0_TCHalt $2,4
#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
.globl TX_MIPS32_1004K_VPE_YIELD
#endif
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function waits for a thread control block pointer to appear in */
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
/* in the variable, the corresponding thread is resumed. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* _tx_thread_system_return Return to system from thread */
/* _tx_thread_context_restore Restore thread's context */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_thread_schedule(VOID)
{ */
.globl _tx_thread_schedule_idle_system
_tx_thread_schedule_idle_system:
#ifndef TX_THREAD_SMP_WAKEUP_LOGIC
ei # Enable interrupts
ehb #
li $11,-1 #
yield $11, $11 # Yield so this VPE does not consume all the cycles
lw $8, ($9) # Pickup next thread to execute
beq $8, $0, _tx_thread_schedule_idle_system # If not-NULL, check the thread's ready bit
nop # Delay slot
#else
la $8, TX_MIPS32_1004K_VPE_YIELD # Get call-out address
jalr $8 # Make the call
or $4, $0, $9 # Pass the properly indexed _tx_thread_execute_ptr[x]
#endif
.globl _tx_thread_schedule
_tx_thread_schedule:
/* Enable interrupts. */
ei # Enable interrupts
ehb #
/* Disable interrupts. */
di # Disable interrupts
ehb #
/* Pickup the executing VPE number. */
mfc0 $25, UserLocal # Pickup VPE ID
sll $25, $25, 2 # Build index based on VPE number
/* Calculate the execute pointer for this VPE. */
la $9, _tx_thread_execute_ptr # Pickup starting address of execute list
addu $9, $9, $25 # Build address of execute pointer for this TC
/* Wait for a thread to execute. */
/* do
{ */
_tx_thread_schedule_loop:
lw $8, ($9) # Pickup next thread to execute
beq $8, $0, _tx_thread_schedule_idle_system # If not-NULL, check the thread's ready bit
nop # Delay slot
_tx_thread_check_ready_bit:
lw $9, 152($8) # Pickup the thread's VPE control register
andi $10, $9, 0x8000 # Pickup ready bit (bit 15)
bne $10, $0, _tx_thread_is_ready # If ready bit is set, actually schedule the thread
andi $9, $9, 0x7FFF # Clear the ready bit (bit 15)
b _tx_thread_schedule # Resume at the top of the scheduling loop
nop
_tx_thread_is_ready:
sw $9, 152($8) # Store the cleared ready bit to prevent any other VPE from scheduling this thread
sync
/* }
while(_tx_thread_execute_ptr[VPE] == TX_NULL); */
_tx_thread_schedule_thread:
/* Yes! We have a thread to execute. Interrupts and multithreading are locked out.
Pickup the thread's register context, enable multithreading, and transfer control to
the thread. */
/* Save this thread in the context register of the TC. */
mtc0 $8, C0_TCContext # Set TCContext to current thread
ehb #
#ifdef TX_ENABLE_EVENT_LOGGING
or $16, $8, $0 # Save thread pointer into non-volatile
or $4, $8, $0 # Move thread pointer into input register
la $9, _tx_el_thread_running # Build address of thread running event routine
jal $9 # Call event logging routine
nop # Delay slot
or $8, $16, $0 # Recover thread pointer
#endif
/* Setup the current thread pointer. */
/* _tx_thread_current_ptr[VPE] = _tx_thread_execute_ptr[VPE]; */
la $9, _tx_thread_current_ptr # Pickup current thread pointer address
addu $9, $9, $25 # Offset to VPE specific entry
sw $8, ($9) # Set current thread pointer
/* Increment the run count for this thread. */
/* _tx_thread_current_ptr[VPE] -> tx_thread_run_count++; */
lw $10, 4($8) # Pickup run count
lw $11, 24($8) # Pickup time slice value
addu $10, $10, 1 # Increment run count
sw $10, 4($8) # Store new run count
/* Setup time-slice, if present. */
/* _tx_timer_time_slice[VPE] = _tx_thread_current_ptr[VPE] -> tx_thread_time_slice; */
la $10, _tx_timer_time_slice # Pickup time-slice variable address
addu $10, $10, $25 # Offset to VPE specific time-slice
/* Switch to the thread's stack. */
/* SP = _tx_thread_current_ptr[VPE] -> tx_thread_stack_ptr; */
lw $29, 8($8) # Switch to thread's stack
lw $15, 176($8) # Pickup FPU enable flag in TX_THREAD structure
sw $11, ($10) # Store new time-slice
/* Determine if an interrupt frame or a synchronous task suspension frame
is present. */
lw $10, ($29) # Pickup stack type
beqz $10, _tx_thread_synch_return # If 0, solicited thread return
nop # Delay slot
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0. */
lw $9,120($29) # Recover SR
li $10,0xDFFFFFFF # Mask for FPU enable bit
mfc0 $8, UserLocal # Pickup VPE ID
and $9, $9, $10 # Build SR with FPU enable bit masked
bne $8, $0, _tx_skip_fpu_int_restore # If not VPE 0, skip FPU restore
li $10, 0x20000000 # Build FPU enable bit
or $9, $9, $10 # Build SR with FPU enable
beq $15, $0, _tx_skip_fpu_int_restore # If FPU not enabled, skip FPU restore
nop
lw $8, 384($29) # Recover fcr31
ctc1 $8, $31 # Setup fcr31
ldc1 $f31, 128($29) # Recover f31
ldc1 $f30, 136($29) # Recover f30
ldc1 $f29, 144($29) # Recover f29
ldc1 $f28, 152($29) # Recover f28
ldc1 $f27, 160($29) # Recover f27
ldc1 $f26, 168($29) # Recover f26
ldc1 $f25, 176($29) # Recover f25
ldc1 $f24, 184($29) # Recover f24
ldc1 $f23, 192($29) # Recover f23
ldc1 $f22, 200($29) # Recover f22
ldc1 $f21, 208($29) # Recover f21
ldc1 $f20, 216($29) # Recover f20
ldc1 $f19, 224($29) # Recover f19
ldc1 $f18, 232($29) # Recover f18
ldc1 $f17, 240($29) # Recover f17
ldc1 $f16, 248($29) # Recover f16
ldc1 $f15, 256($29) # Recover f15
ldc1 $f14, 264($29) # Recover f14
ldc1 $f13, 272($29) # Recover f13
ldc1 $f12, 280($29) # Recover f12
ldc1 $f11, 288($29) # Recover f11
ldc1 $f10, 296($29) # Recover f10
ldc1 $f9, 304($29) # Recover f9
ldc1 $f8, 312($29) # Recover f8
ldc1 $f7, 320($29) # Recover f7
ldc1 $f6, 328($29) # Recover f6
ldc1 $f5, 336($29) # Recover f5
ldc1 $f4, 344($29) # Recover f4
ldc1 $f3, 352($29) # Recover f3
ldc1 $f2, 360($29) # Recover f2
ldc1 $f1, 368($29) # Recover f1
ldc1 $f0, 376($29) # Recover f0
_tx_skip_fpu_int_restore:
sw $9,120($29) # Store new SR
#endif
/* Recover standard registers. */
lw $8,124($29) # Recover EPC
lw $9,120($29) # Recover SR
mtc0 $8, $14 # Setup EPC
ehb #
lw $30, 4($29) # Recover s8
mtc0 $9, $12 # Restore SR
ehb # Clear hazards
lw $23, 8($29) # Recover s7
lw $22, 12($29) # Recover s6
lw $21, 16($29) # Recover s5
lw $20, 20($29) # Recover s4
lw $19, 24($29) # Recover s3
lw $18, 28($29) # Recover s2
lw $17, 32($29) # Recover s1
lw $16, 36($29) # Recover s0
lw $8, 40($29) # Recover hi
lw $9, 44($29) # Recover low
mthi $8 # Setup hi
mtlo $9 # Setup lo
lw $25, 48($29) # Recover t9
lw $24, 52($29) # Recover t8
lw $15, 56($29) # Recover t7
lw $14, 60($29) # Recover t6
lw $13, 64($29) # Recover t5
lw $12, 68($29) # Recover t4
lw $11, 72($29) # Recover t3
lw $10, 76($29) # Recover t2
lw $9, 80($29) # Recover t1
lw $8, 84($29) # Recover t0
lw $7, 88($29) # Recover a3
lw $6, 92($29) # Recover a2
lw $5, 96($29) # Recover a1
lw $4, 100($29) # Recover a0
lw $3, 104($29) # Recover v1
lw $2, 108($29) # Recover v0
.set noat
lw $1, 112($29) # Recover at
.set at
lw $31,116($29) # Recover ra
addu $29, $29, 392 # Recover stack frame
emt # Enable multithreading again
eret # Return to point of interrupt
_tx_thread_synch_return:
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0. */
lw $9,52($29) # Recover SR
li $10,0xDFFFFFFF # Mask for FPU enable bit
mfc0 $8, UserLocal # Pickup VPE ID
and $9, $9, $10 # Build SR with FPU enable bit masked
bne $8, $0, _tx_skip_fpu_sync_restore # If not TC 0, skip FPU restore
li $10, 0x20000000 # Build FPU enable bit
or $9, $9, $10 # Build SR with FPU enable
beq $15, $0, _tx_skip_fpu_sync_restore # If FPU not enabled, skip FPU restore
nop
lw $8, 152($29) # Recover fcr31
ctc1 $8, $31 # Setup fcr31
ldc1 $f31, 56($29) # Recover f31
ldc1 $f30, 64($29) # Recover f30
ldc1 $f29, 72($29) # Recover f29
ldc1 $f28, 80($29) # Recover f28
ldc1 $f27, 88($29) # Recover f27
ldc1 $f26, 96($29) # Recover f26
ldc1 $f25, 104($29) # Recover f25
ldc1 $f24, 112($29) # Recover f24
ldc1 $f23, 120($29) # Recover f23
ldc1 $f22, 128($29) # Recover f22
ldc1 $f21, 136($29) # Recover f21
ldc1 $f20, 144($29) # Recover f20
_tx_skip_fpu_sync_restore:
sw $9,52($29) # Store new SR
#endif
/* Recover standard preserved registers. */
lw $30, 4($29) # Recover s8
lw $23, 8($29) # Recover s7
lw $22, 12($29) # Recover s6
lw $21, 16($29) # Recover s5
lw $20, 20($29) # Recover s4
lw $19, 24($29) # Recover s3
lw $18, 28($29) # Recover s2
lw $17, 32($29) # Recover s1
lw $16, 36($29) # Recover s0
lw $8, 40($29) # Recover hi
lw $9, 44($29) # Recover low
mthi $8 # Setup hi
mtlo $9 # Setup lo
lw $8, 52($29) # Recover SR
lw $31, 48($29) # Recover ra
addu $29, $29, 160 # Recover stack space
mtc0 $8, $12 # Restore SR
ehb # Clear hazards
emt # Enable multithreading
jr.hb $31 # Return to thread
nop #
/* } */

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the currently running core number and returns it.*/
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Core ID */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_core_get
_tx_thread_smp_core_get:
mfc0 $2, UserLocal # Pickup VPE ID
j $31 # Return to caller
and $2, $2, 0xFF # Isolate the VPE number

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. */
#define GIC_SH_COUNTER_LO 0xbbdc0010 /* Lower 32-bits of GIC common counter */
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function preempts the specified core in situations where the */
/* thread corresponding to this core is no longer ready or when the */
/* core must be used for a higher-priority thread. If the specified is */
/* the current core, this processing is skipped since the will give up */
/* control subsequently on its own. */
/* */
/* INPUT */
/* */
/* core The core to preempt */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_core_preempt
_tx_thread_smp_core_preempt:
sync
la $8, GIC_SH_WEDGE # Build address
li $9, 0x80000020 #
addu $9, $4, $9 # Build exact VPE to interrupt
sw $9, 0($8) # Interrupt the selected VPE
jr.hb $31 # Return to caller
nop # Delay slot

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current state of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_current_state_get
_tx_thread_smp_current_state_get:
di $8 # Disable interrupts
ehb #
la $12, _tx_thread_system_state # Pickup start of the current state array
mfc0 $25, UserLocal # Pickup VPE ID
sll $25, $25, 2 # Build index based on VPE number
addu $12, $12, $25 # Build address of current state for this VPE
lw $2, ($12) # Pickup current state
mtc0 $8, C0_Status # Restore interrupts
jr.hb $31 # Return to caller
nop #

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current thread of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_current_thread_get
_tx_thread_smp_current_thread_get:
di $10 # Disable interrupts
ehb #
mfc0 $25, UserLocal # Pickup VPE ID
la $12, _tx_thread_current_ptr # Pickup the current thread pointer
sll $25, $25, 2 # Build index based on VPE number
addu $12, $12, $25 # Build address of current thread pointer for this VPE
lw $2, ($12) # Pickup current thread pointer
mtc0 $10, C0_Status # Restore interrupt posture
jr.hb $31 # Return to caller
nop # Delay slot

119
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define INITIAL_SR 0xFF00 /* All IM bits set */
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is the place where additional cores wait until */
/* initialization is complete before they enter the thread scheduling */
/* loop. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* Hardware */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_initialize_wait
_tx_thread_smp_initialize_wait:
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
cfc1 $8, $31 # Pickup current FPU control reg
la $9, _tx_thread_smp_initial_fpu_control_register
sw $8, ($9) # Save FPU control reg
#endif
/* Pickup the release cores flag. */
la $8, _tx_thread_smp_release_cores_flag # Build address of release cores flag
wait_for_release:
lw $9, ($8) # Pickup release cores flag
beq $9, $0, wait_for_release # Wait here until it is set
nop
/* Core 0 has released this core. */
/* Pickup the core ID. */
mfc0 $8, UserLocal # Pickup VPE ID
sll $8, $8, 2 # Build index based on VPE number
/* Clear this core's system state variable. */
la $9, _tx_thread_system_state # Build address of system state variable
addu $9, $9, $8 #
sw $0, ($9) # Clear this VPE's system state entry
/* Now wait for core 0 to finish it's initialization. */
di # Disable interrupts
ehb #
mfc0 $8, $12 # Pickup current SR
ori $8, $8, INITIAL_SR # Build initial SR
mtc0 $8, $12 # Setup SR
core_0_wait_loop:
la $8, _tx_thread_system_state # Build address of system state variable of logical VPE 0
lw $9, ($8) # Pickup system state
bne $9, $0, core_0_wait_loop # If non-zero, keep waiting
nop #
la $8, _tx_thread_schedule # Otherwise, initialization is done
jr $8 # Enter main scheduling loop
nop #

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define C0_Status $12
#define C0_Cause $13
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function performs low-level initialization of the booting */
/* core. */
/* */
/* INPUT */
/* */
/* number_of_cores Number of cores */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_high_level ThreadX high-level init */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_low_level_initialize
_tx_thread_smp_low_level_initialize:
/* Nothing needed in this port. */
jr.hb $31 # Return to caller
nop # Clear hazards

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets protection for running inside the ThreadX */
/* source. This is ccomplished by a combination of a test-and-set */
/* flag and periodically disabling interrupts. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Previous Status Register */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_protect
_tx_thread_smp_protect:
di $2 # Disable interrupts
ehb #
sync
mfc0 $25, UserLocal # Pickup VPE ID
la $10, _tx_thread_smp_protection # Build address to protection structure
lw $9, ($10) # Pickup the protection
bne $9, $0, _already_owned # If non-zero, then the protection is already in force
nop #
ll $11, ($10) # Pickup the protection in force flag
bne $11, $0, _get_retry # Is the protection still available?
li $11, 1 # Build protection in force flag
sc $11, ($10) # Attempt to get the semaphore
beq $11, $0, _get_retry # If successful, we got the protection!
sync
sw $25, 8($10) # Save VPE
sw $11, 12($10) # Setup the initial count
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
sll $13, $25, 2 # Build index based on VPE number
la $12, _tx_thread_current_ptr # Pickup the current thread pointer
addu $12, $12, $13 # Build address of current thread pointer for this VPE
lw $9, ($12) # Pickup current thread pointer
sw $31, 16($10) # Save caller info
sw $2, 20($10) # Save SR
sw $9, 4($10) # Save the current thread pointer
#endif
j $31 # Return to caller
nop
_get_retry:
mtc0 $2, C0_Status # Restore interrupt posture
ehb #
b _tx_thread_smp_protect # Try to get the protection again
nop #
_already_owned:
lw $9, 8($10) # Pickup the owned VPE
beq $9, $25, _have_the_protection # If equal, we already have the protection
lw $12, 12($10) # Pickup protection count
mtc0 $2, C0_Status # Restore interrupt posture
ehb #
b _tx_thread_smp_protect # Try to get the protection again
nop #
_have_the_protection:
addu $12, $12, 1 # Increment
j $31 # Return to caller
sw $12, 12($10) # Store back the protection count

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define GIC_SH_COUNTER_LO 0xbbdc0010 /* Lower 32-bits of GIC common counter */
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the global time value that is used for debug */
/* information and event tracing. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* 32-bit time stamp */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_time_get
_tx_thread_smp_time_get:
la $8, GIC_SH_COUNTER_LO # Pickup address of GIC_SH_COUNTER_LO
lw $2, 0($8) # Pickup 32-bit counter
jr $31
nop
.globl _tx_thread_smp_time_get_upper
_tx_thread_smp_time_get_upper:
addu $2, $0, 0 # Just return 0 for the upper, since the time in only 32-bits
jr $31
nop

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_Status $12
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function releases previously obtained protection. The supplied */
/* previous SR is restored. If the value of _tx_thread_system_state */
/* and _tx_thread_preempt_disable are both zero, then multithreading */
/* is enabled as well. */
/* */
/* INPUT */
/* */
/* Previous Status Register */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
.globl _tx_thread_smp_unprotect
_tx_thread_smp_unprotect:
di # Disable interrupts
ehb #
sync
mfc0 $25, UserLocal # Pickup VPE ID
la $10, _tx_thread_smp_protection # Build address of protection structure
lw $9, 8($10) # Pickup owning VPE
bne $9, $25, _still_protected # Not the same VPE, protection is in force somewhere else
lw $12, 12($10) # Pickup protection count
beq $12, $0, _still_protected # If zero, protection is not in force anymore
subu $12, $12, 1 # Decrement
sw $12, 12($10) # Store back the protection count
bne $12, $0, _still_protected # If non-zero, nested protection condition
nop #
la $11, _tx_thread_preempt_disable # Build address of preempt disable flag
lw $12, ($11) # Pickup preempt disable flag
bne $12, $0, _still_protected # Don't release protection if preempt disable flag is set
li $8, 0xFFFFFFFF # Setup invalid value
sw $8, 8($10) # Mark VPE as invalid
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
sw $31, 24($10) # Remember the caller of the unprotect
#endif
_release_protect_loop:
sync
sw $0, ($10) # Clear protection
sync
_still_protected:
mtc0 $4, C0_Status # Restore interrupt posture
jr.hb $31 # Return to caller
nop #

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
INITIAL_SR = 0xFF03 # Interrupt enable previous
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function builds a stack frame on the supplied thread's stack. */
/* The stack frame results in a fake interrupt return to the supplied */
/* function pointer. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to thread control blk */
/* function_ptr Pointer to return function */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_thread_create Create thread service */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
{ */
.globl _tx_thread_stack_build
_tx_thread_stack_build:
/* Build a fake interrupt frame. The form of the fake interrupt stack
on the MIPS32_interAptiv should look like the following after it is built:
Stack Top: 1 (00) Interrupt stack frame type
$30 (04) Initial S8
$23 (08) Initial S7
$22 (12) Initial S6
$21 (16) Initial S5
$20 (20) Initial S4
$19 (24) Initial S3
$18 (28) Initial S2
$17 (32) Initial S1
$16 (36) Initial S0
hi (40) Initial HI register
lo (44) Initial LO register
$25 (48) Initial t9
$24 (52) Initial t8
$15 (56) Initial t7
$14 (60) Initial t6
$13 (64) Initial t5
$12 (68) Initial t4
$11 (72) Initial t3
$10 (76) Initial t2
$9 (80) Initial t1
$8 (84) Initial t0
$7 (88) Initial a3
$6 (92) Initial a2
$5 (96) Initial a1
$4 (100) Initial a0
$3 (104) Initial v1
$2 (108) Initial v0
$1 (112) Initial at
$31 (116) Initial ra
SR (120) Initial SR
EPC (124) Initial EPC
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
$f31 (128) Initial f31
$f30 (136) Initial f30
$f29 (144) Initial f29
$f28 (152) Initial f28
$f27 (160) Initial f27
$f26 (168) Initial f26
$f25 (176) Initial f25
$f24 (184) Initial f24
$f23 (192) Initial f23
$f22 (200) Initial f22
$f21 (208) Initial f21
$f20 (216) Initial f20
$f19 (224) Initial f19
$f18 (232) Initial f18
$f17 (240) Initial f17
$f16 (248) Initial f16
$f15 (256) Initial f15
$f14 (264) Initial f14
$f13 (272) Initial f13
$f12 (280) Initial f12
$f11 (288) Initial f11
$f10 (296) Initial f10
$f9 (304) Initial f9
$f8 (312) Initial f8
$f7 (320) Initial f7
$f6 (328) Initial f6
$f5 (336) Initial f5
$f4 (344) Initial f4
$f3 (352) Initial f3
$f2 (360) Initial f2
$f1 (368) Initial f1
$f0 (376) Initial f0
FCR31 (384) Initial fcr31
unused (388) Unused Word
#endif
Stack Bottom: (higher memory address) */
lw $8, 16($4) # Pickup end of stack area
ori $9, $0, 7 # Build double alignment mask
not $9, $9 #
and $8, $8, $9 # Make sure double word alignment
/* Actually build the stack frame. */
subu $8, $8, 392 # Allocate space for the stack frame
ori $9, $0, 1 # Build stack type
sw $9, ($8) # Place stack type on the top
sw $0, 4($8) # Initial s8
sw $0, 8($8) # Initial s7
sw $0, 12($8) # Initial s6
sw $0, 16($8) # Initial s5
sw $0, 20($8) # Initial s4
sw $0, 24($8) # Initial s3
sw $0, 28($8) # Initial s2
sw $0, 32($8) # Initial s1
sw $0, 36($8) # Initial s0
sw $0, 40($8) # Initial hi
sw $0, 44($8) # Initial lo
sw $0, 48($8) # Initial t9
sw $0, 52($8) # Initial t8
sw $0, 56($8) # Initial t7
sw $0, 60($8) # Initial t6
sw $0, 64($8) # Initial t5
sw $0, 68($8) # Initial t4
sw $0, 72($8) # Initial t3
sw $0, 76($8) # Initial t2
sw $0, 80($8) # Initial t1
sw $0, 84($8) # Initial t0
sw $0, 88($8) # Initial a3
sw $0, 92($8) # Initial a2
sw $0, 96($8) # Initial a1
sw $0, 100($8) # Initial a0
sw $0, 104($8) # Initial v1
sw $0, 108($8) # Initial v0
sw $0, 112($8) # Initial at
sw $0, 116($8) # Initial ra
mfc0 $10, $12 # Pickup current SR
li $9,0xDFFFFFFC # Preserve upper portion of SR - except for FP
and $9, $10, $9 # Clear the lower SR bits
ori $9, $9, INITIAL_SR # Build initial SR
sw $9, 120($8) # Initial SR
sw $5, 124($8) # Initial EPC
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
sw $0, 128($8) # Initial f31
sw $0, 132($8) #
sw $0, 136($8) # Initial f30
sw $0, 140($8) #
sw $0, 144($8) # Initial f29
sw $0, 148($8) #
sw $0, 152($8) # Initial f28
sw $0, 156($8) #
sw $0, 160($8) # Initial f27
sw $0, 164($8) #
sw $0, 168($8) # Initial f26
sw $0, 172($8) #
sw $0, 176($8) # Initial f25
sw $0, 180($8) #
sw $0, 184($8) # Initial f24
sw $0, 188($8) #
sw $0, 192($8) # Initial f23
sw $0, 196($8) #
sw $0, 200($8) # Initial f22
sw $0, 204($8) #
sw $0, 208($8) # Initial f21
sw $0, 212($8) #
sw $0, 216($8) # Initial f20
sw $0, 220($8) #
sw $0, 224($8) # Initial f19
sw $0, 228($8) #
sw $0, 232($8) # Initial f18
sw $0, 236($8) #
sw $0, 240($8) # Initial f17
sw $0, 244($8) #
sw $0, 248($8) # Initial f16
sw $0, 252($8) #
sw $0, 256($8) # Initial f15
sw $0, 260($8) #
sw $0, 264($8) # Initial f14
sw $0, 268($8) #
sw $0, 272($8) # Initial f13
sw $0, 276($8) #
sw $0, 280($8) # Initial f12
sw $0, 284($8) #
sw $0, 288($8) # Initial f11
sw $0, 292($8) #
sw $0, 296($8) # Initial f10
sw $0, 300($8) #
sw $0, 304($8) # Initial f9
sw $0, 308($8) #
sw $0, 312($8) # Initial f8
sw $0, 316($8) #
sw $0, 320($8) # Initial f7
sw $0, 324($8) #
sw $0, 328($8) # Initial f6
sw $0, 332($8) #
sw $0, 336($8) # Initial f5
sw $0, 340($8) #
sw $0, 344($8) # Initial f4
sw $0, 348($8) #
sw $0, 352($8) # Initial f3
sw $0, 356($8) #
sw $0, 360($8) # Initial f2
sw $0, 364($8) #
sw $0, 368($8) # Initial f1
sw $0, 372($8) #
la $9, _tx_thread_initial_fpu_control_register
lw $10, ($9) # Pickup initial FPU control registrer
sw $0, 376($8) # Initial f0
sw $0, 380($8) #
sw $10, 384($8) # Inherit initial fcr31
#endif
/* Set bit indicating the thread is ready for scheduling. */
lw $9, 152($4) # Pickup the thread's VPE control register
ori $9, $9, 0x8000 # Set ready bit (bit 15)
sw $9, 152($4) # Make this thread ready for scheduling
/* Setup stack pointer. */
/* thread_ptr -> tx_thread_stack_ptr = t0; */
j $31 # Return to caller
sw $8, 8($4) # Save stack pointer in thread's
/* # control block */
/* } */

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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_TCBind $2,2
#define C0_TCContext $2,5
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the system. Only a minimal context */
/* is saved since the compiler assumes temp registers are going to get */
/* slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_thread_system_return(VOID)
{ */
.globl _tx_thread_system_return
_tx_thread_system_return:
di $10 # Disable interrupts
ehb #
/* Save minimal context on the stack. */
subu $29, $29, 160 # Allocate space on the stack
sw $0, ($29) # Solicited stack type
sw $30, 4($29) # Save s8
sw $23, 8($29) # Save s7
sw $22, 12($29) # Save s6
sw $21, 16($29) # Save s5
sw $20, 20($29) # Save s4
sw $19, 24($29) # Save s3
sw $18, 28($29) # Save s2
sw $17, 32($29) # Save s1
sw $16, 36($29) # Save s0
mfhi $8 # Pickup hi
mflo $9 # Pickup lo
sw $8, 40($29) # Save hi
sw $9, 44($29) # Save lo
sw $31, 48($29) # Save ra
sw $10, 52($29) # Save SR
mfc0 $25, UserLocal # Pickup VPE ID
#ifdef TX_ENABLE_64BIT_FPU_SUPPORT
/* Check if FPU is enabled for this thread. Note that threads with FPU enabled will only be
scheduled in VPE 0 and thus only need to be saved for TC VPE 0. */
bne $25, $0, _tx_skip_fpu_sync_save # If not VPE 0, skip FPU save
la $9, _tx_thread_current_ptr # Pickup address of pointer
lw $8, ($9) # Pickup current thread pointer
lw $15, 176($8) # Pickup FPU enable flag
beq $15, $0, _tx_skip_fpu_sync_save # If FPU not enabled, skip FPU save
nop #
/* Save preserved floating point registers. */
cfc1 $8, $31 # Pickup floating point control reg
sdc1 $f31, 56($29) # Save f31
sdc1 $f30, 64($29) # Save f30
sdc1 $f29, 72($29) # Save f29
sdc1 $f28, 80($29) # Save f28
sdc1 $f27, 88($29) # Save f27
sdc1 $f26, 96($29) # Save f26
sdc1 $f25, 104($29) # Save f25
sdc1 $f24, 112($29) # Save f24
sdc1 $f23, 120($29) # Save f23
sdc1 $f22, 128($29) # Save f22
sdc1 $f21, 136($29) # Save f21
sdc1 $f20, 144($29) # Save f20
sw $8, 152($29) # Save fcr31
_tx_skip_fpu_sync_save:
#endif
la $9, _tx_thread_current_ptr # Pickup address of pointer
sll $25, $25, 2 # Build index based on VPE number
addu $9, $9, $25 # Build address of current thread pointer for this VPE
lw $8, ($9) # Pickup current thread pointer
la $10,_tx_thread_system_stack_ptr # Pickup stack pointer address
/* Save current stack and switch to system stack. */
/* _tx_thread_current_ptr[VPE] -> tx_thread_stack_ptr = SP;
SP = _tx_thread_system_stack_ptr[VPE]; */
sw $29, 8($8) # Save stack pointer
addu $10, $10, $25 # Build index to system stack pointer array
lw $29, ($10) # Switch to system stack
/* Determine if the time-slice is active. */
/* if (_tx_timer_time_slice[VPE])
{ */
la $13, _tx_timer_time_slice # Pickup time slice variable addr
addu $13, $13, $25 # Index into time-slice variable
lw $11, 0($13) # Pickup time slice value
la $12, _tx_thread_schedule # Pickup address of scheduling loop
beqz $11, _tx_thread_dont_save_ts # If no time-slice, don't save it
nop # Delay slot
/* Save time-slice for the thread and clear the current time-slice. */
/* _tx_thread_current_ptr[VPE] -> tx_thread_time_slice = _tx_timer_time_slice[VPE];
_tx_timer_time_slice[VPE] = 0; */
sw $11, 24($8) # Save time-slice for thread
sw $0, ($13) # Clear time-slice variable
/* } */
_tx_thread_dont_save_ts:
/* Clear the current thread pointer. */
/* _tx_thread_current_ptr[VPE] = TX_NULL; */
sw $0, ($9) # Clear current thread pointer
/* Set bit indicating the thread is ready for scheduling. */
lw $9, 152($8) # Pickup the thread's VPE control register
ori $9, $9, 0x8000 # Set ready bit (bit 15)
sync
sw $9, 152($8) # Make this thread ready for scheduling
la $10,_tx_thread_smp_protection # Build address of protection structure
lw $9, 4($10) # Pickup owning thread
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
_error_loop:
bne $8, $9, _error_loop # If the owner is not this thread, we have a problem!
nop #
#endif
la $13, _tx_thread_preempt_disable # Pickup address of preempt disable
sw $0, ($13) # Clear the preempt disable
li $11, 0xFFFFFFFF # Build invalid VPE value
sw $11, 8($10) # Set protection VPE to invalid
sw $31, 24($10) # Save caller in protect structure
_release_protect_loop:
sync
sw $0, ($10) # Release protection
sync
j $12 # Return to thread scheduler
nop
/* } */

219
ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S Normal file
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/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
/**************************************************************************/
/**************************************************************************/
#define UserLocal $4,2
#define C0_TCBind $2,2
.text
.set noreorder
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt MIPS32_interAptiv/GNU */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_smp_protect Get protection */
/* _tx_thread_smp_unprotect Release protection */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-xxxx Scott Larson Initial Version 6.x */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
.globl _tx_timer_interrupt
_tx_timer_interrupt:
/* Check VPE and throw away any timer interrupts for anything other than VPE 0. */
mfc0 $8, UserLocal # Pickup VPE ID
beq $8, $0, _handle_timer_interrupt # If 0, VPE 0 should handle the interrupt
nop
jr $31 # Other VPE simply returns
nop
_handle_timer_interrupt:
subu $29, $29, 16 # Allocate some storage on the stack
sw $31, 4($29) # Save ra
sw $16, 8($29) # Save preserved register s0
/* Get protection before the timer variables are updated. */
/* _tx_thread_smp_protect(); */
jal _tx_thread_smp_protect # Get VPE protection
nop #
addu $16, $2, 0 # Save return value
/* Increment timer interrupt active counter. */
/* _tx_timer_interrupt_active++; */
la $9, _tx_timer_interrupt_active # Build address of timer interrupt active count
lw $8, ($9) # Pickup timer interrupt active count
addu $8, $8, 1 # Increment timer interrupt active count
sw $8, ($9) # Store new timer interrupt active count
sync
/* Increment the system clock. */
/* _tx_timer_system_clock++; */
la $9, _tx_timer_system_clock # Pickup address of system clock
lw $8, ($9) # Pickup system clock
addu $8, $8, 1 # Increment system clock
sw $8, ($9) # Store new system clock
/* Test for timer expiration. */
/* if (*_tx_timer_current_ptr)
{ */
la $13, _tx_timer_expired # Pickup address of timer expired flag
lw $10, ($13) # Pickup the timer expired flag
bne $10, $0, _tx_timer_done # If already expired, skip expiration processing
nop #
la $9, _tx_timer_current_ptr # Pickup address of current ptr
lw $8, ($9) # Pickup current pointer
la $13, _tx_timer_expired # Pickup address of timer expired flag
lw $10, ($8) # Pickup the current timer entry
ori $12, $0, 1 # Build TX_TRUE flag
beqz $10, _tx_timer_no_timer # If NULL, no timer has expired
nop # Delay slot
/* Set expiration flag. */
/* _tx_timer_expired = TX_TRUE; */
ori $15, $0, 2 # Set local expired flag
b _tx_timer_done # Finished timer processing
sw $12, ($13) # Set expired flag in memory
/* }
else
{ */
_tx_timer_no_timer:
ori $15, $0, 0 # Set expired flag to false
/* No timer expired, increment the timer pointer. */
/* _tx_timer_current_ptr++; */
/* Check for wrap-around. */
/* if (_tx_timer_current_ptr == _tx_timer_list_end) */
la $12, _tx_timer_list_end # Pickup address of list end pointer
lw $11, ($12) # Pickup actual list end
addu $8, $8, 4 # Point to next timer entry
bne $8, $11, _tx_timer_skip_wrap # If not same, good pointer
sw $8, ($9) # Store new timer pointer
/* Wrap to beginning of list. */
/* _tx_timer_current_ptr = _tx_timer_list_start; */
la $12, _tx_timer_list_start # Pickup address of list start pointer
lw $10, ($12) # Pickup start of the list
sw $10, ($9) # Store new timer pointer
_tx_timer_skip_wrap:
/* } */
_tx_timer_done:
/* Did a timer expire? */
/* if (_tx_timer_expired)
{ */
beqz $15, _tx_timer_dont_activate # No, timer not expired
nop # Delay slot
/* Call the timer expiration processing. */
/* _tx_timer_expiration_process(void); */
la $9, _tx_timer_expiration_process # Build address of _tx_timer_expiratoin_process routine
jal $9 # Call _tx_timer_expiration_process
nop
lw $15, ($29) # Recover local expired flag
/* } */
_tx_timer_dont_activate:
/* Call time-slice processing. */
/* _tx_thread_time_slice(); */
la $9, _tx_thread_time_slice # Pickup address of time slice function
jal $9 # Call time slice
nop # Delay slot
/* Decrement timer interrupt active counter. */
/* _tx_timer_interrupt_active--; */
la $9, _tx_timer_interrupt_active # Build address of timer interrupt active count
lw $8, ($9) # Pickup timer interrupt active count
subu $8, $8, 1 # Decrement timer interrupt active count
sw $8, ($9) # Store new timer interrupt active count
sync
/* Release VPE protection. */
/* _tx_thread_smp_unprotect(); */
addu $4, $16, 0 # Setup input parameter
jal _tx_thread_smp_unprotect # Release protection
nop #
lw $31, 4($29) # Recover ra
lw $16, 8($29) # Recover s0
addu $29, $29, 16 # Recover stack space
j $31 # Return to caller
nop # Delay slot
/* } */

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/*
* boot.h
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define END(name)\
.##size name,.-name;\
.##end name
#define GCR_CONFIG_ADDR 0xbfbf8000 // KSEG0 address of the GCR registers
#define GIC_P_BASE_ADDR 0x1bdc0000 // physical address of the GIC
#define GIC_BASE_ADDR 0xbbdc0000 // KSEG0 address address of the GIC
#define CPC_P_BASE_ADDR 0x1bde0001 // physical address of the CPC
#define CPC_BASE_ADDR 0xbbde0000 // KSEG0 address address of the CPC
#define DENALI_CTL_SECTION 0xbbc00000
#define MALTA_DISP_ADDR 0xbf000410
#define STACK_BASE_ADDR 0x82000000 /* Change: Base on memory size. */
#define STACK_SIZE_LOG2 22 /* 4Mbytes each */
/**************************************************************************************
Register use while executing in this file: ("GLOBAL" denotes a common value.)
**************************************************************************************/
#define r1_all_ones $1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. GLOBAL! */
// $2 - $7 (v0, v1 a0 - a3) reserved for program use
#define r8_core_num $8 /* t0 Core number. Only core 0 is active after reset. */
#define r9_vpe_num $9 /* t1 MT ASE VPE number that this TC is bound to (0 if non-MT.) */
#define r10_has_mt_ase $10 /* t2 Core implements the MT ASE. */
#define r11_is_cps $11 /* t3 Core is part of a Coherent Processing System. */
// $12 - $15 (t4 - t7) are free to use
// $16, $17 (s0 and s1) reserved for program use
#define r18_tc_num $18 /* s2 MT ASE TC number (0 if non-MT.) */
#define r19_more_cores $19 /* s3 Number of cores in CPS in addition to core 0. GLOBAL! */
#define r20_more_vpes $20 /* s4 Number of vpes in this core in addition to vpe 0. */
#define r21_more_tcs $21 /* s5 Number of tcs in vpe in addition to the first. */
#define r22_gcr_addr $22 /* s6 Uncached (kseg1) base address of the Global Config Registers. */
#define r23_cpu_num $23 /* s7 Unique per vpe "cpu" identifier (CP0 EBase[CPUNUM]). */
#define r24_malta_word $24 /* t8 Uncached (kseg1) base address of Malta ascii display. GLOBAL! */
#define r25_coreid $25 /* t9 Copy of cp0 PRiD GLOBAL! */
#define r26_int_addr $26 /* k0 Interrupt handler scratch address. */
#define r27_int_data $27 /* k1 Interrupt handler scratch data. */
// $28 gp and $29 sp
#define r30_cpc_addr $30 /* s8 Address of CPC register block after cpc_init. 0 indicates no CPC. */
// $31 ra

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/*
* copy_c2_ram.S
*
* Created on: Jan 12, 2011
* Author: MIPS TECHNOLOGIES, INC
* Copy code and data to ram then clear BSS
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
#include <regdef.h>
#include <boot.h>
#define s1_all_ones s1 /* at Will hold 0xffffffff to simplify bit insertion of 1's. */
#define a0_temp_data a0 /* a0 data to be moved */
#define a1_temp_addr a1 /* from address */
#define a2_temp_dest a2 /* to address */
#define a3_temp_mark a3 /* ending address */
.set noreorder # Don't allow the assembler to reorder instructions.
.set noat # Don't allow the assembler to use r1(at) for synthetic instr.
/**************************************************************************************
**************************************************************************************/
LEAF(copy_c2_ram)
li s1_all_ones, 0xffffffff
/* RAMHACK: Link addr == load addr. No copy of code from ROM to RAM required.
// Copy code and read-only/initialized data from FLASH to (uncached) RAM.
la a1_temp_addr, _zap1
ins a1_temp_addr, s1_all_ones, 29, 1
la a2_temp_dest, _ftext_ram
ins a2_temp_dest, s1_all_ones, 29, 1
la a3_temp_mark, _edata_ram
ins a3_temp_mark, s1_all_ones, 29, 1
beq a2_temp_dest, a3_temp_mark, zero_bss
nop
next_ram_word:
lw a0_temp_data, 0(a1_temp_addr)
sw a0_temp_data, 0(a2_temp_dest)
addiu a2_temp_dest, 4
bne a3_temp_mark, a2_temp_dest, next_ram_word
addiu a1_temp_addr, 4
*/
// RAMHACK: Zero sbss in addition to bss.
zero_sbss:
la a1_temp_addr, _start_sbss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_sbss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, zero_bss
nop
next_sbss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_sbss_word
nop
zero_bss:
la a1_temp_addr, _start_bss
ins a1_temp_addr, s1_all_ones, 29, 1
la a3_temp_mark, _end_bss
ins a3_temp_mark, s1_all_ones, 29, 1
beq a1_temp_addr, a3_temp_mark, copy_c2_ram_done
nop
next_bss_word:
sw zero, 0(a1_temp_addr)
addiu a1_temp_addr, 4
bne a1_temp_addr, a3_temp_mark, next_bss_word
nop
copy_c2_ram_done:
jr ra
nop
END(copy_c2_ram)

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/*
* cps.h
*
* Created on: May 1, 2012
* Author: MIPS TECHNOLOGIES, INC
*/
/*
Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved
under the copyright laws of the United States of America and other countries.
This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
copyright laws. Violations thereof may result in criminal penalties and fines.
MIPS Technologies reserves the right to change this code to improve function, design or
otherwise. MIPS Technologies does not assume any liability arising out of the application or use
of this code, or of any error or omission in such code. Any warranties, whether express, statutory,
implied or otherwise, including but not limited to the implied warranties of merchantability or
fitness for a particular purpose, are excluded. Except as expressly provided in any written license
agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
not give recipient any license to any intellectual property rights, including any patent rights, that
cover this code.
This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
violation of the law of any country or international law, regulation, treaty, Executive Order,
statute, amendments or supplements thereto. Should a conflict arise regarding the export,
reexport, transfer, or release of this code, the laws of the United States of America shall be
the governing law.
This code may only be disclosed to the United States government ("Government"), or to
Government users, with prior written consent from MIPS Technologies or an authorized third
party. This code constitutes one or more of the following: commercial computer software,
commercial computer software documentation or other commercial items. If the user of this
code, or any related documentation of any kind, including related technical data or manuals, is an
agency, department, or other entity of the Government, the use, duplication, reproduction, release,
modification, disclosure, or transfer of this code, or any related documentation of any kind, is
restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of
this code by the Government is further restricted in accordance with the terms of the license
agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
Technologies or an authorized third party.
*/
/*
* This include file contains #defines for the memory mapped registers in a coherent Processing system
* of both single cores and multi threaded cores. It contains registers offset for all the registers,
* defines for the fields with in the registers and encodings for some of the fields.
*
* The fields in the registers are defined by a pair of #defines, one define is the starting bit position of
* the field and another, (with a "_S" appended to the name), is the size of the field. Here is an example of
* how you would use these #defines in the the extraction of a filed:
*
* li $5, GIC_BASE_ADDR # load GIC KSEG0 Address
* lw $4, GIC_SH_CONFIG($5) # Read the GIC_SH_CONFIG Register
* ext $4, NUMINTERRUPTS, NUMINTERRUPTS_S # Extract NUMINTERRUPTS
*
* The names for the registers and fields are usually the same as used in the Software Users Manual
* (SUM). The exceptions occur when the names would conflict with each other in that case the name
* is appended with something to make it unique.
*/
#ifndef CPS_H_
#define CPS_H_
// GCR Offset for GCR_CONFIG, field positions and field size
#define GCR_CONFIG 0x0000
#define NUM_ADDR_REGIONS 16
#define NUM_ADDR_REGIONS_S 4
#define NUMIOCU 8
#define NUMIOCU_S 4
#define PCORES 0
#define PCORES_S 8
// GCR Offset for GCR_BASE, field positions and field size
#define GCR_BASE 0x0008
#define GCR_BASE_ADDR 15
#define GCR_BASE_ADDR_S 17
#define CCA_DEFAULT_OVERRIDE_VALUE 5
#define CCA_DEFAULT_OVERRIDE_VALUE_S 3
#define CCA_DEFAULT_OVERRIDE_ENABLE 4
#define CCA_DEFAULT_OVERRIDE_ENABLE_S 1
#define CM_DEFAULT_TARGET 0
#define CM_DEFAULT_TARGET_S 2
// GCR Offset for GCR_CONTROL, field positions and field size
#define GCR_CONTROL 0x0010
#define SYNCCTL 16
#define SYNCCTL_S 1
#define CM_SYNC_TX_DISABLE 5
#define CM_SYNC_TX_DISABLE_S 1
#define CM_AUTO_CLR_IVU_EN 4
#define CM_AUTO_CLR_IVU_EN_S 1
#define CM_COHST_SH_ALWAYS_EN 3
#define CM_COHST_SH_ALWAYS_EN_S 1
#define CM_PARK_EN 2
#define CM_PARK_EN_S 1
#define CM_DISABLE_MMIO_LIMIT 1
#define CM_DISABLE_MMIO_LIMIT_S 1
#define CM_SPEC_READ_EN 0
#define CM_SPEC_READ_EN_S 1
// GCR Offset for GCR_CONTROL_2, field positions and field size
#define GCR_CONTROL2 0x0018
#define L2_CACHEOP_LIMIT 16
#define L2_CACHEOP_LIMIT_S 4
#define L1_CACHEOP_LIMIT 3
#define L1_CACHEOP_LIMIT_S 4
// GCR Offset for GCR_ACCESS, field positions and field size
#define GCR_ACCESS 0x0020
#define CM_ACCESS_EN 0
#define CM_ACCESS_EN_S 8
// GCR Offset for GCR_REV, field positions and field size
#define GCR_REV 0x0030
#define MAJOR_REV_GCR 8
#define MAJOR_REV_GCR_S 8
#define MINOR_REV_GCR 7
#define MINOR_REV_GCR_S 8
// GCR Offset for GCR_ERROR_MASK
#define GCR_ERROR_MASK 0x0040
// error type encoding
#define GC_WR_ERR 1
#define GC_RD_ERR 2
#define COH_WR_ERR 3
#define COH_RD_ERR 4
#define MMIO_WR_ERR 5
#define MMIO_RD_ERR 6
#define INTVN_WR_ERR 17
#define INTVN_RD_ERR 18
// GCR Offset for GCR_ERROR_CAUSE, field positions and field size
#define GCR_ERROR_CAUSE 0x0048
#define CM_ERROR_TYPE 27
#define CM_ERROR_TYPE_S 5
#define CM_ERROR_INFO 0
#define CM_ERROR_INFO_S 27
// Fields and sizes for Error Types 1 - 5
#define CCA 15
#define CCA_S 3
#define TARGET_REGION 12
#define TARGET_REGION_S 3
#define OCP_MCMD_ERROR 7
#define OCP MCMD_ERROR_S 5
#define SOURCE_TAGID 3
#define SOURCE_TAGID_S 4
#define SOURCE_PORT 0
#define SOURCE_PORT_S 3
// Fields for Error Types 16 - 17
#define COHERENT_STATE_CORE_3 19
#define COHERENT_STATE_CORE_3_S 2
#define INTERVENTION_SRESP_CORE3 18
#define INTERVENTION_SRESP_CORE3_S 1
#define COHERENT_STATE_CORE_2 16
#define COHERENT_STATE_CORE_2_S 2
#define INTERVENTION_SRESP_CORE2 15
#define INTERVENTION_SRESP_CORE2_S 1
#define COHERENT_STATE_CORE_1 13
#define COHERENT_STATE_CORE_1_S 2
#define INTERVENTION_SRESP_CORE1 12
#define INTERVENTION_SRESP_CORE1_S 1
#define COHERENT_STATE_CORE_0 10
#define COHERENT_STATE_CORE_0_S 2
#define INTERVENTION_SRESP_CORE0 9
#define INTERVENTION_SRESP_CORE0_S 1
#define FROM_STORE_CONDITIONAL 8
#define FROM_STORE_CONDITIONAL_S 1
#define OCP_MCMD 3
#define OCP_MCMD_S 5
#define SOURCE_PORT 0
#define SOURCE_PORT_S 3
// Coherent state encoding
#define CS_INVALID 0
#define CS_SHARED 1
#define CS_MODIFID 2
#define CS_EXCLUSIVE
// Intervention Response encoding
#define IR_OK 0
#define IR_DATA 1
// MCmd Encodings for CM_ERROR_INFO
#define LEGACY_WRITE 0x01
#define LEGACY_READ 0x02
#define COHERENT_READ_OWN 0x08
#define COHERENT_READ_SHARE 0x09
#define COHERENT_READ_DISCARD 0x0A
#define COHERENT_READ_SHARE_ALWAYS 0x0B
#define COHERENT_UPGRADE 0x0C
#define COHERENT_WRITEBACK 0x0D
#define COHERENT_COPYBACK 0x10
#define COHERENT_COPYBACK_INVALIADATE 0x11
#define COHERENT_INVALIADATE 0x12
#define COHERENT_WRITE_INVALIADATE 0x13
#define COHERENT_COMPLETION_SYNC 0x14
// GCR Offset for GCR_ERROR_ADDR
#define GCR_ERROR_ADDR 0x0050
// GCR Offset for GCR_ERROR_MULT
#define GCR_ERROR_MULT 0x0058
#define CM_ERROR_2ND 0
#define CM_ERROR_2ND_S 5
// GCR Offset for GCR_GIC_BASE, fields and sizes
#define GCR_GIC_BASE 0x0080
#define GIC_BASEADDRESS 17
#define GIC_BASEADDRESS_S 15
#define GIC_EN 0
#define GIC_EN_S 1
// GCR Offset for GCR_CPC_BAS, fields and sizes
#define GCR_CPC_BASE 0x0088
#define CPC_BASEADDRESS 15
#define CPC_BASEADDRESS_S 17
#define CPC_EN 0
#define CPC_EN_S 1
// GCR Offset for GCR_REGn_BASE, fields and sizes
#define GCR_REG0_BASE 0x0090
#define GCR_REG1_BASE 0x00A0
#define GCR_REG2_BASE 0x00B0
#define GCR_REG3_BASE 0x00C0
#define GCR_REG4_BASE 0x0190
#define GCR_REG5_BASE 0x01A0
#define CM_REGION_BASEADDRESS 16
#define CM_REGION_BASEADDRESS_S 16
// GCR Offset for GCR_REGn_MASK, fields, sizes and encodings
#define GCR_REG0_MASK 0x0098
#define GCR_REG1_MASK 0x00A8
#define GCR_REG2_MASK 0x00B8
#define GCR_REG3_MASK 0x00C8
#define GCR_REG4_MASK 0x0198
#define GCR_REG5_MASK 0x01A8
#define CM_REGION_ADDRESS_MASK 16
#define CM_REGION_ADDRESS_MASK_S 16
#define CCA_OVERRIDE_VALUE 5
#define CCA_OVERRIDE_VALUE_S 3
#define CCA_OVERRIDE_ENABLE 4
#define CCA_OVERRIDE_ENABLE_S 1
#define CM_REGION_TARGET 0
#define CM_REGION_TARGET_S 2
// CM_REGION_TARGET encoding
#define CM_REGION_TARGET_DISABLE 0x0
#define CM_REGION_TARGET_MEMORY 0x1
#define CM_REGION_TARGET_IOCU 0x2
// GCR Offset for GCR_GIC_STATUS, fields and sizes
#define GCR_GIC_STATUS 0x00D0
#define GIC_EX 0
#define GIC_EX_S 1
// GCR Offset for GCR_CACHE_REV, fields and sizes
#define GCR_CACHE_REV 0x00E0
#define MAJOR_REV_CACHE 8
#define MAJOR_REV_CACHE_S 8
#define MINOR_REV_CACHE 7
#define MINOR_REV_CACHE_S 8
// GCR Offset for GCR_CPC_STATUS, fields and sizes
#define GCR_CPC_STATUS 0x00F0
#define CPC_EX 0
#define CPC_EX_S 1
// GCR Offset for GCR_IOCU1_REV, fields and sizes
#define GCR_IOCU1_REV 0x0200
#define MAJOR_REV_IOCU 8
#define MAJOR_REV_IOCU_S 8
#define MINOR_REV_IOCU 7
#define MINOR_REV_IOCU_S 8
// GCR Core Local and Core other offsets
#define CORE_LOCAL_CONTROL_BLOCK 0x2000
#define CORE_OTHER_CONTROL_BLOCK 0x4000
// GCR Core Local and Other COHERENCE, fields and sizes
#define GCR_CL_COHERENCE 0x0008
#define GCR_CO_COHERENCE 0x0008
#define COH_DOMAIN_EN 0
#define COH_DOMAIN_EN_S 8
// GCR Core Local and Other CONFIG , fields and sizes
#define GCR_CL_CONFIG 0x0010
#define GCR_CO_CONFIG 0x0010
#define IOCU_TYPE 10
#define IOCU_TYPE_S 2
#define PVPE 0
#define PVPE_S 10
// GCR Core Local and Other OTHER, fields and sizes
#define GCR_CL_OTHER 0x0018
#define GCR_CO_OTHER 0x0018
#define OTHER_CORE_NUM 16
#define OTHER_CORE_NUM_S 16
// GCR Core Local and Other RESET_BASE, fields and sizes
#define GCR_CL_RESET_BASE 0x0020
#define GCR_CO_RESET_BASE 0x0020
#define BEV_EXCEPTION_BASE 12
#define BEV_EXCEPTION_BASE_S 20
// GCR Core Local and Other ID
#define GCR_CL_ID 0x0028
#define GCR_CO_ID 0x0028
// GCR Global Debug Block Offsets
#define Global_Debug_Block 0x6000
// GCR Global Debug GCR_DB_TCBCONTROLB, fields and sizes
#define GCR_DB_TCBCONTROLB 0x0008
#define WE_DB_TCBCONTROLB 31
#define WE_DB_TCBCONTROLB_S 1
#define TWSRC_WIDTH 26
#define TWSRC_WIDTH_S 2
#define TRPAD 18
#define TRPAD_S 1
#define RM 16
#define RM_S 1
#define TR 15
#define TR_S 1
#define BF 14
#define BF_S 1
#define TM 12
#define TM_S 2
#define CR 8
#define CR_S 3
#define CAL 7
#define CAL_S 1
#define OFC 1
#define OFC_S 1
#define FUNNEL_TRACE_ENABLE 0
#define FUNNEL_TRACE_ENABLE_S 1
// GCR Global Debug GCR_DB_TCBCONTROLD, fields and sizes
#define GCR_DB_TCBCONTROLD 0x0010
#define P4_CTL 24
#define P4_CTL_S 2
#define P3_CTL 22
#define P3_CTL_S 2
#define P2_CTL 20
#define P2_CTL_S 2
#define P1_CTL 18
#define P1_CTL_S 2
#define P0_CTL 16
#define P0_CTL_S 2
#define TW_SRC_VAL 8
#define TW_SRC_VAL_S 3
#define TRACE_WB 7
#define TRACE_WB_S 1
#define CM_INHIBIT_OVERFLOW 5
#define CM_INHIBIT_OVERFLOW_S 1
#define TLEV 3
#define TLEV_S 2
#define AE_PER_PORT 2
#define AE_PER_PORT_S 1
#define GLOBAL_CM_EN 1
#define GLOBAL_CM_EN_S 1
#define CM_EN 0
#define CM_EN_S 1
// GCR Global Debug GCR_DB_TCBCONTROLE, fields and sizes
#define GCR_DB_TCBCONTROLE 0x0020
#define TrIdle 8
#define TrIdle_S 1
#define PeC 0
#define PeC_S 1
// GCR Global Debug GCR_DB_TCBConfig, fields and sizes
#define GCR_DB_TCBCONFIG 0x0028
#define CF1 31
#define CF1_S 1
#define SZ 17
#define SZ_S 4
#define CRMAX 14
#define CRMAX_S 3
#define CRMIN 11
#define CRMIN_S 3
#define PW 9
#define PW_S 2
#define ONT 5
#define ONT_S 1
#define OFT 4
#define OFT_S 1
#define TCB_REV 0
#define TCB_REV_S 4
// GCR Global Debug GCR_DB_PC_CTL, fields and sizes
#define GCR_DB_PC_CTL 0x0100
#define PERF_INT_EN 30
#define PERF_INT_EN_S 1
#define PERF_OVF_STOP 29
#define PERF_OVF_STOP_S 1
#define P1_RESET 9
#define P1_RESET_S 1
#define P1_COUNT_ON 8
#define P1_COUNT_ON_S 1
#define P0_RESET 7
#define P0_RESET_S 1
#define P0_COUNT_ON 6
#define P0_COUNT_ON_S 1
#define CYCL_CNT_RESET 5
#define CYCL_CNT_RESET_S 1
#define CYCL_CNT__ON 4
#define CYCL_CNT__ON_S 1
#define PERF_NUM_CNT 0
#define PERF_NUM_CNT_S 4
// GCR Global Debug Read Pointer GCR_DB_TCBRDP
#define GCR_DB_TCBRDP 0x0108
// GCR Global Debug Write Pointer GCR_DB_TCBWDP
#define GCR_DB_TCBWRP 0x0110
// GCR Global Debug Start Pointer GCR_DB_TCBSTP
#define GCR_DB_TCBSTP 0x0118
// GCR_DB_PC_OV, fields and sizes
#define GCR_DB_PC_OV 0x0120
#define P1_OVERFLOW 2
#define P1_OVERFLOW_S 1
#define P0_OVERFLOW 1
#define P0_OVERFLOW_S 1_S 1
#define CYCL_CNT_OVERFLOW 0
#define CYCL_CNT_OVERFLOW_S 1
// GCR Global Debug GCR_DB_PC_EVENT, fields and sizes
#define GCR_DB_PC_EVENT 0x0130
#define P1_EVENT 8
#define P1_EVENT_S 8
#define P0_EVENT 0
#define P0_EVENT_S 8
// GCR Global Debug GCR_DB_PC_CYCLE
#define GCR_DB_PC_CYCLE 0x0180
// GCR Global Debug Qualifier and count registers
#define GCR_DB_PC_QUAL0 0x0190
#define GCR_DB_PC_CNT0 0x0198
#define GCR_DB_PC_QUAL1 0x01a0
#define GCR_DB_PC_CNT1 0x01a8
// GCR Global Debug Trace word access registers
#define GCR_DB_TCBTW_LO 0x0200
#define GCR_DB_TCBTW_HI 0x0208
// GIC Offsets within the Global interrupt controller
#define GIC_SH_CONFIG 0x0000
#define COUNTSTOP 28
#define COUNTSTOP_S 1
#define COUNTBITS 24
#define COUNTBITS_S 4
#define NUMINTERRUPTS 16
#define NUMINTERRUPTS_S 8
#define PVPES 0
#define PVPES_S 9
#define GIC_SH_CounterLo 0x0010
#define GIC_SH_CounterHi 0x0014
#define GIC_RevisionID 0x0020
#define GIC_SH_POL31_0 0x0100
#define GIC_SH_POL63_32 0x0104
#define GIC_SH_POL95_64 0x0108
#define GIC_SH_POL127_96 0x010c
#define GIC_SH_POL159_128 0x0110
#define GIC_SH_POL191_160 0x0114
#define GIC_SH_POL223_192 0x0118
#define GIC_SH_POL255_224 0x011c
#define GIC_SH_TRIG31_0 0x0180
#define GIC_SH_TRIG63_32 0x0184
#define GIC_SH_TRIG95_64 0x0188
#define GIC_SH_TRIG127_96 0x018c
#define GIC_SH_TRIG159_128 0x0190
#define GIC_SH_TRIG191_160 0x0194
#define GIC_SH_TRIG223_192 0x0198
#define GIC_SH_TRIG255_224 0x019c
#define GIC_SH_DUAL31_0 0x0200
#define GIC_SH_DUAL63_32 0x0204
#define GIC_SH_DUAL95_64 0x0208
#define GIC_SH_DUAL127_96 0x020c
#define GIC_SH_DUAL159_128 0x0210
#define GIC_SH_DUAL159_128 0x0210
#define GIC_SH_DUAL191_160 0x0214
#define GIC_SH_DUAL223_192 0x0218
#define GIC_SH_DUAL255_224 0x021c
#define GIC_SH_WEDGE 0x0280
#define GIC_SH_RMASK31_0 0x0300
#define GIC_SH_RMASK63_32 0x0304
#define GIC_SH_RMASK95_64 0x0308
#define GIC_SH_RMASK127_96 0x030c
#define GIC_SH_RMASK159_128 0x0310
#define GIC_SH_RMASK191_160 0x0314
#define GIC_SH_RMASK223_192 0x0318
#define GIC_SH_RMASK255_224 0x031c
#define GIC_SH_SMASK31_00 0x0380
#define GIC_SH_SMASK63_32 0x0384
#define GIC_SH_SMASK95_64 0x0388
#define GIC_SH_SMASK127_96 0x038c
#define GIC_SH_SMASK159_128 0x0390
#define GIC_SH_SMASK191_160 0x0394
#define GIC_SH_SMASK223_192 0x0398
#define GIC_SH_SMASK255_224 0x039c
#define GIC_SH_MASK31_00 0x0400
#define GIC_SH_MASK63_32 0x0404
#define GIC_SH_MASK95_64 0x0408
#define GIC_SH_MASK127_96 0x040c
#define GIC_SH_MASK159_128 0x0410
#define GIC_SH_MASK191_160 0x0414
#define GIC_SH_MASK223_192 0x0418
#define GIC_SH_MASK255_224 0x041c
#define GIC_SH_PEND31_00 0x0480
#define GIC_SH_PEND63_32 0x0484
#define GIC_SH_PEND95_64 0x0488
#define GIC_SH_PEND127_96 0x048c
#define GIC_SH_PEND159_128 0x0490
#define GIC_SH_PEND191_160 0x0494
#define GIC_SH_PEND223_192 0x0498
#define GIC_SH_PEND255_224 0x049c
// Global MAP to Pin GIC_SH_MAP_PIN + (4 x interrupt_source)
#define GIC_SH_MAP_PIN 0x0500
#define GIC_SH_MAP_SPACER 0x20
// Map source to VPEs 31 - 0 GIC_SH_MAP0_VPE31_0 + (0x20 x interrupt source)
#define GIC_SH_MAP0_VPE31_0 0x2000
// Map source to VPEs 63 - 32 GIC_SH_MAP0_VPE63_32 + (0x20 x interrupt source)
#define GIC_SH_MAP0_VPE63_32 0x2004
// Map source to core 31 - 0 GIC_SH_MAP0_CORE31_0 + (0x20 x interrupt source)
#define GIC_SH_MAP0_CORE31_0 0x2000
// Map source to core 63 - 32 GIC_SH_MAP0_CORE63_32 + (0x20 x interrupt source)
#define GIC_SH_MAP0_CORE63_32 0x2004
#define GIC_VB_DINT_SEND 0x6000
// GIC VPE Local offsets (note the VPEL)
#define GIC_VPE_LOCAL_SECTION_OFFSET 0x8000
#define GIC_VPEL_CTL 0x0000
#define GIC_VPEL_PEND 0x0004
#define GIC_VPEL_MASK 0x0008
#define GIC_VPEL_RMASK 0x000c
#define GIC_VPEL_SMASK 0x0010
#define GIC_VPEL_WD_MAP 0x0040
#define GIC_VPEL_COMPARE_MAP 0x0044
#define GIC_VPEL_TIMER_MAP (0x0048 )
#define GIC_VPEL_FDC_MAP 0x004c
#define GIC_VPEL_PERFCTR_MAP 0x0050
#define GIC_VPEL_SWInt0_MAP 0x0054
#define GIC_VPEL_SWInt1_MAP 0x0058
#define GIC_VPEL_OTHER_ADDR 0x0080
#define GIC_VPEL_IDENT 0x0088
#define GIC_VPEL_WD_CONFIG0 0x0090
#define GIC_VPEL_WD_COUNT0 0x0094
#define GIC_VPEL_WD_INITIAL0 0x0098
#define GIC_VPEL_CompareLo 0x00A0
#define GIC_VPEL_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_VPEL_EICSS + (4 x interrupt number)
#define GIC_VPEL_EICSS 0x0100
#define GIC_VL_DINT_PART 0x3000
#define GIC_VL_BRK_GROUP 0x3080
// GIC VPE Other offsets (note the VPEO)
#define GIC_VPE_OTHER_SECTION_OFFSET 0xc000
#define GIC_VPEO_CTL 0x0000
#define GIC_VPEO_PEND 0x0004
#define GIC_VPEO_MASK 0x0008
#define GIC_VPEO_RMASK 0x000c
#define GIC_VPEO_SMASK 0x0010
#define GIC_VPEO_WD_MAP 0x0040
#define GIC_VPEO_COMPARE_MAP 0x0044
#define GIC_VPEO_TIMER_MAP 0x0048
#define GIC_VPEO_FDC_MAP 0x004c
#define GIC_VPEO_PERFCTR_MAP 0x0050
#define GIC_VPEO_SWInt0_MAP 0x0054
#define GIC_VPEO_SWInt1_MAP 0x0058
#define GIC_VPEO_OTHER_ADDR 0x0080
#define GIC_VPEO_IDENT 0x0088
#define GIC_VPEO_WD_CONFIG0 0x0090
#define GIC_VPEO_WD_COUNT0 0x0094
#define GIC_VPEO_WD_INITIAL0 0x0098
#define GIC_VPEO_CompareLo 0x00A0
#define GIC_VPEO_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_VPEO_EICSS + (4 x interrupt number)
#define GIC_VPEO_EICSS 0x0100
#define GIC_VO_DINT_PART 0x3000
#define GIC_VO_BRK_GROUP 0x3080
// GIC CORE Local offsets (note the COREL)
#define GIC_CORE_LOCAL_SECTION_OFFSET 0x8000
#define GIC_COREL_CTL 0x0000
#define GIC_COREL_PEND 0x0004
#define GIC_COREL_MASK 0x0008
#define GIC_COREL_RMASK 0x000c
#define GIC_COREL_SMASK 0x0010
#define GIC_COREL_WD_MAP 0x0040
#define GIC_COREL_COMPARE_MAP 0x0044
#define GIC_COREL_TIMER_MAP 0x0048
#define GIC_COREL_FDC_MAP 0x004c
#define GIC_COREL_PERFCTR_MAP 0x0050
#define GIC_COREL_SWInt0_MAP 0x0054
#define GIC_COREL_SWInt1_MAP 0x0058
#define GIC_COREL_OTHER_ADDR 0x0080
#define GIC_COREL_IDENT 0x0088
#define GIC_COREL_WD_CONFIG0 0x0090
#define GIC_COREL_WD_COUNT0 0x0094
#define GIC_COREL_WD_INITIAL0 0x0098
#define GIC_COREL_CompareLo 0x00A0
#define GIC_COREL_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_COREL_EICSS + (4 x interrupt number)
#define GIC_COREL_EICSS 0x0100
#define GIC_COREL_DINT_PART 0x3000
#define GIC_COREL_BRK_GROUP 0x3080
// GIC CORE Other offsets (note the COREO)
#define GIC_CORE_OTHER_SECTION_OFFSET 0xc000
#define GIC_COREO_CTL 0x0000
#define GIC_COREO_PEND 0x0004
#define GIC_COREO_MASK 0x0008
#define GIC_COREO_RMASK 0x000c
#define GIC_COREO_SMASK 0x0010
#define GIC_COREO_WD_MAP 0x0040
#define GIC_COREO_COMPARE_MAP 0x0044
#define GIC_COREO_TIMER_MAP 0x0048
#define GIC_COREO_FDC_MAP 0x004c
#define GIC_COREO_PERFCTR_MAP 0x0050
#define GIC_COREO_SWInt0_MAP 0x0054
#define GIC_COREO_SWInt1_MAP 0x0058
#define GIC_COREO_OTHER_ADDR 0x0080
#define GIC_COREO_IDENT 0x0088
#define GIC_COREO_WD_CONFIG0 0x0090
#define GIC_COREO_WD_COUNT0 0x0094
#define GIC_COREO_WD_INITIAL0 0x0098
#define GIC_COREO_CompareLo 0x00A0
#define GIC_COREO_CompareHi 0x00A4
// NOTE: EIC Shadow set GIC_COREO_EICSS + (4 x interrupt number)
#define GIC_COREO_EICSS 0x0100
#define GIC_COREO_DINT_PART 0x3000
#define GIC_COREO_BRK_GROUP 0x3080
// Bit fields for Local Interrupt Control Register (GIC_COREi_CTL) or for MT (GIC_VPEi_CTL) or
#define FDC_ROUTABLE 4
#define FDC_ROUTABLE_S 1
#define SWINT_ROUTABLE 3
#define SWINT_ROUTABLE_S 1
#define PERFCOUNT_ROUTABLE 2
#define PERFCOUNT_ROUTABLE_S 1
#define TIMER_ROUTABLE 1
#define TIMER_ROUTABLE_S 1
#define EIC_MODE 0
#define EIC_MODE_S 1
// Bit fields for Local Interrupt Pending Registers (GIC_COREi_PEND) or for MT (GIC_VPEi_PEND)
#define FDC_PEND 6
#define FDC_PEND_S 1
#define SWINT1_PEND 5
#define SWINT1_PEND_S 1
#define SWINT0_PEND 4
#define SWINT0_PEND_S 1
#define PERFCOUNT_PEND 3
#define PERFCOUNT_PEND_S 1
#define TIMER_PEND 2
#define TIMER_PEND_S 1
#define COMPARE_PEND 1
#define COMPARE_PEND_S 1
#define WD_PEND 0
#define WD_PEND_S 1
// Bit fields for Local Interrupt Mask Registers (GIC_COREi_MASK) or for MT (GIC_VPEi_MASK)
#define FDC_MASK 6
#define FDC_MASK_S 1
#define SWINT1_MASK 5
#define SWINT1_MASK_S 1
#define SWINT0_MASK 4
#define SWINT0_MASK_S 1
#define PERFCOUNT_MASK 3
#define PERFCOUNT_MASK_S 1
#define TIMER_MASK 2
#define TIMER_MASK_S 1
#define COMPARE_MASK 1
#define COMPARE_MASK_S 1
#define WD_MASK 0
#define WD_MASK_S 1
// Bit fields for Local Interrupt Reset Mask Registers (GIC_COREi_RMASK) or for MT (GIC_VPEi_RMASK)
#define FDC_MASK_RESET 6
#define FDC_MASK_RESET_S 1
#define SWINT1_MASK_RESET 5
#define SWINT1_MASK_RESET_S 1
#define SWINT0_MASK_RESET 4
#define SWINT0_MASK_RESET_S 1
#define PERFCOUNT_MASK_RESET 3
#define PERFCOUNT_MASK_RESET_S 1
#define TIMER_MASK_RESET 2
#define TIMER_MASK_RESET_S 1
#define COMPARE_MASK_RESET 1
#define COMPARE_MASK_RESET_S 1
#define WD_MASK_RESET 0
#define WD_MASK_RESET_S 1
// Bit fields for Local Interrupt Set Mask Registers (GIC_COREi_SMASK) or for MT (GIC_VPEi_SMASK)
#define FDC_MASK_SET 6
#define FDC_MASK_SET_S 1
#define SWINT1_MASK_SET 5
#define SWINT1_MASK_SET_S 1
#define SWINT0_MASK_SET 4
#define SWINT0_MASK_SET_S 1
#define PERFCOUNT_MASK_SET 3
#define PERFCOUNT_MASK_SET_S 1
#define TIMER_MASK_SET 2
#define TIMER_MASK_SET_S 1
#define COMPARE_MASK_SET 1
#define COMPARE_MASK_SET_S 1
#define WD_MASK_SET 0
#define WD_MASK_SET_S 1
// Bit fields for CORE-Other or for MT VPE-Other Addressing Register
#define VPENum 0
#define VPENum_S 16
#define CORENum 0
#define CORENum_S 16
// Bit fields for Core-Local Identification Register (GIC_COREi_IDENT) or for MT (GIC_VPEi_IDENT)
#define VPENumIDENT 0
#define VPENumIDENT_S 32
#define CORENumIDENT 0
#define CORENumIDENT_S 32
// Bit fields for Local EIC Shadow Set Registers (GIC_COREi_EICSSj) or for MT (GIC_VPEi_EICSSj)
#define EIC_SS 0
#define EIC_SS_S 4
// Bit fields for Local WatchDog/Compare/PerfCount/SWIntx Map to Pin Registers
#define MAP_TO_PIN 31
#define MAP_TO_PIN_S 1
#define MAP_TO_NMI 30
#define MAP_TO_NMI_S 1
#define MAP_TO_YQ 29
#define MAP_TO_YQ_S 1
#define MAP 0
#define MAP_S 6
// Bit fields for Watchdog Timer Config Register (GIC_COREi_WD_CONFIGk) or for MT (GIC_VPEi_WD_CONFIGk)
#define WDRESET 7
#define WDRESET_S 1
#define WDINTR 6
#define WDINTR_S 1
#define WAITMODE_CNTRL 5
#define WAITMODE_CNTRL_S 1
#define DEBUGMODE_CNTRL 5
#define DEBUGMODE_CNTRL_S 1
#define TYPE 1
#define TYPE_S 3
// TYPE Filed encoding:
#define WD_One_Trip_Mode 0
#define WD_Second_Countdown_Mode 1
#define PIT_Mode 2
// Bit fields for Local DINT Group Participate Register (GIC_Cx_DINT_PART) or for MT (GIC_Vx_DINT_PART)
#define DINT_Group_Particpate 0
#define DINT_Group_Particpate_S 1
// GIC, GIC User Mode Visible Section Offsets
#define USER_MODE_VISIBLE_SECTION_OFFSET 0x10000
#define GIC_SH_COUNTERLO 0x0000
#define GIC_SH_COUNTERHI 0x0004
// Cluster Power Controller Global Section
// CPC Block CPC_ACCESS_REG, fields and sizes
#define CPC_ACCESS_REG 0x000
#define CM_ACCESS_EN 0
#define CM_ACCESS_EN_S 8
// CPC Block CPC_SEQDEL_REG, fields and sizes
#define CPC_SEQDEL_REG 0x008
#define MICROSTEP 0
#define MICROSTEP_S 10
// CPC Block CPC_RAIL_REG, fields and sizes
#define CPC_RAIL_REG 0x010
#define RAILDELAY 0
#define RAILDELAY_S 10
// CPC Block CPC_RESETLEN_REG, fields and sizes
#define CPC_RESETLEN_REG 0x018
#define RESETLEN 0
#define RESETLEN_S 10
// CPC Block CPC_REVISION_REG, fields and sizes
#define CPC_REVISION_REG 0x020
#define MAJOR_REV_CPC 8
#define MAJOR_REV_CPC_S 8
#define MINOR_REV_CPC 0
#define MINOR_REV_CPC_S 8
// Cluster Power Controller Local and Other section
#define CPS_CORE_LOCAL_CONTROL_BLOCK 0x2000
#define CPS_CORE_OTHER_CONTROL_BLOCK 0x4000
// CPC Local and Other CPC_CMD_REG, command encoding
#define CPC_CMDL_REG 0x000
#define CPC_CMDO_REG 0x000
#define CLOCK_OFF 1
#define PWR_DOWN 2
#define PWR_UP 3
#define CPC_RESET 4
// CPC Local and Other CPC_STAT_CONF, fields, sizes and encodings
#define CPC_STATL_CONF_REG 0x008
#define CPC_STATO_CONF_REG 0x008
#define PWRUP_EVENT 23
#define PWRUP_EVENT_S 1
#define SEQ_STATE 19
#define SEQ_STATE_S 4
// sequencer state encodings
#define PWR_DOWN_STATE 0x0
#define VDD_OK_STATE 0x1
#define UP_DELAY_STATE 0x2
#define UCLK_OFF_STATE 0x3
#define CPC_RESET_STATE 0x4
#define CPC_RESET_DLY_STATE 0x5
#define NON_COHERENT_EXECUTION_STATE 0x6
#define COHERENT_EXECUTION_STATE 0x7
#define ISOLATE_STATE 0x8
#define CLR_BUS_STATE 0x8
#define DCLK_OFF_STATE 0xA
#define CLKGAT_IMPL 17
#define CLKGAT_IMPL_S 1
#define PWRDN_IMPL 16
#define PWRDN_IMPL_S 1
#define EJTAG_PROBE 15
#define EJTAG_PROBE_S 1
#define PWUP_POLICY 8
#define PWUP_POLICY_S 2
// Power up state encodings
#define POLICY_PWR_DOWN 0
#define POLICY_GO_CLOCK_OFF 1
#define PLOICY_PWR_UP 2
#define IO_TRFFC_EN 4
#define IO_TRFFC_EN_S 1
#define CPC_CMD_STATE 0
#define CPC_CMD_STATE_S 4
// CPC Local and Other Addressing Register CPC_OTHER_REG, field and size
#define CPC_OTHERL_REG 0x010
#define CPC_OTHERO_REG 0x010
#define CPC_CORENUM 16
#define CPC_CORENUM_S 8
#endif /* CPS_H_ */

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/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 4096
#define DEMO_BYTE_POOL_SIZE 40000
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define MALTA constants for accessing the display. */
#define MALTA_ASCIIWORD 0xBF000410 /* ASCIIWORD bit 32:0 */
#define MALTA_ASCIIPOS0 0xBF000418 /* ASCIIPOS0 bit 7:0 */
#define MALTA_ASCIIPOS1 0xBF000420 /* ASCIIPOS1 bit 7:0 */
#define MALTA_ASCIIPOS2 0xBF000428 /* ASCIIPOS2 bit 7:0 */
#define MALTA_ASCIIPOS3 0xBF000430 /* ASCIIPOS3 bit 7:0 */
#define MALTA_ASCIIPOS4 0xBF000438 /* ASCIIPOS4 bit 7:0 */
#define MALTA_ASCIIPOS5 0xBF000440 /* ASCIIPOS5 bit 7:0 */
#define MALTA_ASCIIPOS6 0xBF000448 /* ASCIIPOS6 bit 7:0 */
#define MALTA_ASCIIPOS7 0xBF000450 /* ASCIIPOS7 bit 7:0 */
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_THREAD lcd_thread;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
ULONG lcd_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
void lcd_thread_entry(ULONG thread_input);
#ifdef TX_ENABLE_EVENT_TRACE
UCHAR event_buffer[64000];
#endif
/* Define main entry point. */
int main()
{
/* Indicate ThreadX is being entered. */
*((ULONG *) 0xBF000418) = 'T';
*((ULONG *) 0xBF000420) = 'X';
*((ULONG *) 0xBF000428) = ' ';
*((ULONG *) 0xBF000430) = 'E';
*((ULONG *) 0xBF000438) = 'N';
*((ULONG *) 0xBF000440) = 'T';
*((ULONG *) 0xBF000448) = 'E';
*((ULONG *) 0xBF000450) = 'R';
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer;
#ifdef TX_ENABLE_EVENT_TRACE
tx_trace_enable(event_buffer, sizeof(event_buffer), 32);
#endif
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for LCD thread. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the lcd thread. */
tx_thread_create(&lcd_thread, "lcd thread", lcd_thread_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
/* Indicate that we are ready to start scheduling, which will happen after
this rountine returns. */
*((ULONG *) 0xBF000418) = 'T';
*((ULONG *) 0xBF000420) = 'X';
*((ULONG *) 0xBF000428) = ' ';
*((ULONG *) 0xBF000430) = 'G';
*((ULONG *) 0xBF000438) = 'O';
*((ULONG *) 0xBF000440) = '!';
*((ULONG *) 0xBF000448) = ' ';
*((ULONG *) 0xBF000450) = ' ';
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void lcd_thread_entry(ULONG thread_input)
{
UINT state = 0;
/* Loop to continue displaying info on the LCD. */
while(1)
{
/* Sleep for a bit... */
tx_thread_sleep(100);
lcd_counter++;
switch (state)
{
case 0:
*((ULONG *) MALTA_ASCIIPOS0) = 'T';
*((ULONG *) MALTA_ASCIIPOS1) = 'H';
*((ULONG *) MALTA_ASCIIPOS2) = 'R';
*((ULONG *) MALTA_ASCIIPOS3) = 'E';
*((ULONG *) MALTA_ASCIIPOS4) = 'A';
*((ULONG *) MALTA_ASCIIPOS5) = 'D';
*((ULONG *) MALTA_ASCIIPOS6) = 'X';
*((ULONG *) MALTA_ASCIIPOS7) = ' ';
break;
case 1:
*((ULONG *) MALTA_ASCIIPOS0) = 'D';
*((ULONG *) MALTA_ASCIIPOS1) = 'e';
*((ULONG *) MALTA_ASCIIPOS2) = 'm';
*((ULONG *) MALTA_ASCIIPOS3) = 'o';
*((ULONG *) MALTA_ASCIIPOS4) = ' ';
*((ULONG *) MALTA_ASCIIPOS5) = 'F';
*((ULONG *) MALTA_ASCIIPOS6) = 'o';
*((ULONG *) MALTA_ASCIIPOS7) = 'r';
break;
case 2:
*((ULONG *) MALTA_ASCIIPOS0) = 'M';
*((ULONG *) MALTA_ASCIIPOS1) = 'I';
*((ULONG *) MALTA_ASCIIPOS2) = 'P';
*((ULONG *) MALTA_ASCIIPOS3) = 'S';
*((ULONG *) MALTA_ASCIIPOS4) = ' ';
*((ULONG *) MALTA_ASCIIPOS5) = ' ';
*((ULONG *) MALTA_ASCIIPOS6) = ' ';
*((ULONG *) MALTA_ASCIIPOS7) = ' ';
break;
case 3:
*((ULONG *) MALTA_ASCIIPOS0) = 'i';
*((ULONG *) MALTA_ASCIIPOS1) = 'n';
*((ULONG *) MALTA_ASCIIPOS2) = 't';
*((ULONG *) MALTA_ASCIIPOS3) = 'A';
*((ULONG *) MALTA_ASCIIPOS4) = 'p';
*((ULONG *) MALTA_ASCIIPOS5) = 't';
*((ULONG *) MALTA_ASCIIPOS6) = 'i';
*((ULONG *) MALTA_ASCIIPOS7) = 'v';
break;
case 7:
*((ULONG *) MALTA_ASCIIPOS0) = 'E';
*((ULONG *) MALTA_ASCIIPOS1) = 'R';
*((ULONG *) MALTA_ASCIIPOS2) = 'R';
*((ULONG *) MALTA_ASCIIPOS3) = 'O';
*((ULONG *) MALTA_ASCIIPOS4) = 'R';
*((ULONG *) MALTA_ASCIIPOS5) = ' ';
*((ULONG *) MALTA_ASCIIPOS6) = ' ';
*((ULONG *) MALTA_ASCIIPOS7) = ' ';
break;
default:
break;
}
/* Change state for new print! */
state++;
if (state > 3)
state = 0;
}
}

27
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.gpj Normal file
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@ -0,0 +1,27 @@
#!gbuild
#component ThreadX Demo
[Program]
-I.
-o demo_threadx.elf
-nostdlib
-Onone
copy_c2_ram.mip
demo_threadx.c
tx_initialize_low_level.mip
start.mip
set_gpr_boot_values.mip
init_gpr.mip
init_tlb.mip
init_itc.mip
init_caches2.mip
init_cp0.mip
init_cm.mip
release_mp.mip
join_domain.mip
init_gic.mip
init_cpc.mip
init_vpe1.mip
init_CoreFPGA6_mem.mip
tx.a
demo_threadx_ram_interAptiv.ld
demo_threadx_interAptiv.con

28
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_el.gpj Normal file
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@ -0,0 +1,28 @@
#!gbuild
#component ThreadX Demo
[Program]
-DTX_ENABLE_EVENT_LOGGING
-I.
-o demo_threadx.elf
-nostdlib
-Onone
copy_c2_ram.mip
demo_threadx.c
tx_initialize_low_level.mip
start.mip
set_gpr_boot_values.mip
init_gpr.mip
init_tlb.mip
init_itc.mip
init_caches2.mip
init_cp0.mip
init_cm.mip
release_mp.mip
join_domain.mip
init_gic.mip
init_cpc.mip
init_vpe1.mip
init_CoreFPGA6_mem.mip
txe.a
demo_threadx_ram_interAptiv.ld
demo_threadx_interAptiv.con

17
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_interAptiv.con Normal file
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@ -0,0 +1,17 @@
target_connection {
{
title = "GHS_Probe_interAptiv_3c2v4t"
type = "Green Hills Debug Probe (mpserv)"
short_type = "mpserv"
args = " -usb"
command = "mpserv -usb"
logfile = ""
mode = ""
setup_script = "demo_threadx_ram_interAptiv_3c2v4t.mbs"
run_mode_partner = ""
run_mode_policy = ""
sane = "yes"
log = "no"
timestamp = "0"
}
}

75
ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_ram_interAptiv.ld Normal file
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@ -0,0 +1,75 @@
MEMORY {
zero_memory : ORIGIN = 0xffff8000, LENGTH = 64K
dram_rsvd1 : ORIGIN = 0x80000000, LENGTH = 0
vector_0x000 : ORIGIN = . LENGTH = 0x100
vector_0x100 : ORIGIN = . LENGTH = 0x080
vector_0x180 : ORIGIN = . LENGTH = 0x080
vector_0x200 : ORIGIN = . LENGTH = 0x080
vector_0x280 : ORIGIN = . LENGTH = 0x080
vector_0x300 : ORIGIN = . LENGTH = 0x080
monitor : ORIGIN = . LENGTH = 1M - 0x380
dram_memory : ORIGIN = . LENGTH = 10M - 1M
dram_rsvd2 : ORIGIN = ., LENGTH = 0
flash_rsvd1 : ORIGIN = 0xbfc00000, LENGTH = 32K
flash_memory : ORIGIN = ., LENGTH = 10M - 32K
flash_rsvd2 : ORIGIN = ., LENGTH = 0
}
DEFAULTS {
heap_reserve = 2M
stack_reserve = 512K
}
//
// Program layout for running out of RAM.
//
//
SECTIONS
{
.zdata ABS : > zero_memory
.zbss ABS : > .
.rozdata ABS : > .
.vector_0x000 : > vector_0x000
.vector_0x100 : > vector_0x100
.vector_0x180 : > vector_0x180
.vector_0x200 : > vector_0x200
.vector_0x280 : > vector_0x280
.vector_0x300 : > vector_0x300
.text : { "start.o(.text) *(.text)" } > dram_memory
.syscall : > .
.secinfo : > .
.fixaddr : > .
.fixtype : > .
.robase ALIGN(8) : > .
.rodata ALIGN(8) : > .
.sdabase ALIGN(8) : > .
.sdata ALIGN(8) : > .
_start_sbss = . ;
.sbss ALIGN(8) : > .
_end_sbss = . ;
.rosdata ALIGN(8) : > .
.data ALIGN(8) : > .
.profile ALIGN(8) : > .
_start_bss = . ;
.bss ALIGN(8) : > .
_end_bss = . ;
.heap ALIGN(8) PAD(heap_reserve) : > .
.stack ALIGN(8) PAD(stack_reserve) : > .
.eventlog align(16) pad(0x10000) :
.free_mem align(16) pad(0x10000) :
//
// These special symbols mark the bounds of RAM and ROM memory.
// They are used by the MULTI debugger.
//
__ghs_ramstart = MEMADDR(dram_rsvd1);
__ghs_ramend = MEMENDADDR(dram_rsvd2);
__ghs_romstart = MEMADDR(flash_rsvd1);
__ghs_romend = MEMENDADDR(flash_rsvd2);
}

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