mirror of
https://github.com/azure-rtos/threadx
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ac3b6b326c
af5702cbf Include tx_user.h only when TX_INCLUDE_USER_DEFINE_FILE is defined for assembly files
207 lines
8.6 KiB
C
207 lines
8.6 KiB
C
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/**************************************************************************/
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/* Copyright (c) Cadence Design Systems, Inc. */
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/* */
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/* Permission is hereby granted, free of charge, to any person obtaining */
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/* a copy of this software and associated documentation files (the */
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/* "Software"), to deal in the Software without restriction, including */
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/* without limitation the rights to use, copy, modify, merge, publish, */
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/* distribute, sublicense, and/or sell copies of the Software, and to */
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/* permit persons to whom the Software is furnished to do so, subject to */
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/* the following conditions: */
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/* */
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/* The above copyright notice and this permission notice shall be */
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/* included in all copies or substantial portions of the Software. */
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/* */
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/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
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/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
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/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
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/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
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/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
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/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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/**************************************************************************/
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/**************************************************************************
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RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
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This header is the primary glue between generic Xtensa RTOS support
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sources and a specific RTOS port for Xtensa. It contains definitions
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and macros for use primarily by Xtensa assembly coded source files.
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Macros in this header map callouts from generic Xtensa files to specific
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RTOS functions. It may also be included in C source files.
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Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
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architecture, using the Xtensa hardware abstraction layer (HAL) to deal
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with configuration specifics.
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Should be included by all Xtensa generic and RTOS port-specific sources.
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***************************************************************************/
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#ifndef XTENSA_RTOS_H
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#define XTENSA_RTOS_H
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#else
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#include <stdint.h>
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#include <xtensa/config/core.h>
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#endif
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/simcall.h>
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/*
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Include any RTOS specific definitions that are needed by this header.
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*/
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#ifdef TX_INCLUDE_USER_DEFINE_FILE
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#include "tx_user.h"
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#endif
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/*
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Name of RTOS (for messages).
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*/
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#define XT_RTOS_NAME ThreadX
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/*
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Check some Xtensa configuration requirements and report error if not met.
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Error messages can be customize to the RTOS port.
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*/
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#if !XCHAL_HAVE_XEA2 && !XCHAL_HAVE_XEA3
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#error "ThreadX/Xtensa requires Xtensa Exception Architecture v2 (XEA2) or higher."
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#endif
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/***************************************************************************
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RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
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Define callout macros used in generic Xtensa code to interact with the RTOS.
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The macros are simply the function names for use in calls from assembler code.
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Some of these functions may call back to generic functions in xtensa_context.h .
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***************************************************************************/
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/*
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Inform RTOS of entry into an interrupt handler that will affect it.
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Allows RTOS to manage switch to any system stack and count nesting level.
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Called after minimal context has been saved, with interrupts disabled.
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RTOS port can call0 _xt_context_save to save the rest of the context.
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May only be called from assembly code by the 'call0' instruction.
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*/
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// void XT_RTOS_INT_ENTER(void)
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#define XT_RTOS_INT_ENTER _tx_thread_context_save
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/*
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Inform RTOS of completion of an interrupt handler, and give control to
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RTOS to perform thread/task scheduling, switch back from any system stack
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and restore the context, and return to the exit dispatcher saved in the
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stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
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to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
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leaving only a minimal part of the context to be restored by the exit
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dispatcher. This function does not return to the place it was called from.
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May only be called from assembly code by the 'call0' instruction.
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*/
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// void XT_RTOS_INT_EXIT(void)
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#define XT_RTOS_INT_EXIT _tx_thread_context_restore
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/*
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Convenience macros to disable and enable interrupts.
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*/
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#if XCHAL_HAVE_XEA3
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#define XT_INTS_DISABLE(reg) movi reg, PS_DI; xps reg, reg
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#define XT_INTS_ENABLE(reg) wsr reg, PS; rsync
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#else
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#define XT_INTS_DISABLE(reg) rsil reg, XCHAL_EXCM_LEVEL
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#define XT_INTS_ENABLE(reg) wsr reg, PS; rsync
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#endif
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/*
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Inform RTOS of the occurrence of a tick timer interrupt.
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If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
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May be coded in or called from C or assembly, per ABI conventions.
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*/
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#ifndef TX_NO_TIMER
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// void XT_RTOS_TIMER_INT(void)
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#define XT_RTOS_TIMER_INT _tx_timer_interrupt
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#endif
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/*
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Return in a15 the base address of the co-processor state save area for the
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thread that triggered a co-processor exception, or 0 if no thread was running.
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The state save area is structured as defined in xtensa_context.h and has size
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XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
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in interrupt handlers or the RTOS kernel. May only be called from assembly code
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and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
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The implementation may use only a2-4, a15 (all other regs must be preserved).
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*/
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// void* XT_RTOS_CP_STATE(void)
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#define XT_RTOS_CP_STATE _tx_thread_coproc_state
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/***************************************************************************
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HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
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This Xtensa RTOS port provides hooks for dynamically installing exception
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and interrupt handlers to facilitate automated testing where each test
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case can install its own handler for user exceptions and each interrupt
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priority (level). This consists of an array of function pointers indexed
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by interrupt priority, with index 0 being the user exception handler hook.
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Each entry in the array is initially 0, and may be replaced by a function
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pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
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The handler for low and medium priority obeys ABI conventions so may be coded
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in C. For the exception handler, the cause is the contents of the EXCCAUSE
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reg, and the result is -1 if handled, else the cause (still needs handling).
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For interrupt handlers, the cause is a mask of pending enabled interrupts at
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that level, and the result is the same mask with the bits for the handled
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interrupts cleared (those not cleared still need handling). This allows a test
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case to either pre-handle or override the default handling for the exception
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or interrupt level (see xtensa_vectors.S).
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High priority handlers (including NMI) must be coded in assembly, are always
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called by 'call0' regardless of ABI, must preserve all registers except a0,
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and must not use or modify the interrupted stack. The hook argument 'cause'
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is not passed and the result is ignored, so as not to burden the caller with
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saving and restoring a2 (it assumes only one interrupt per level - see the
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discussion in high priority interrupts in xtensa_vectors.S). The handler
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therefore should be coded to prototype 'void h(void)' even though it plugs
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into an array of handlers of prototype 'uint32_t h(uint32_t)'.
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To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
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***************************************************************************/
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#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
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#ifndef __ASSEMBLER__
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typedef uint32_t (*XT_INTEXC_HOOK)(uint32_t cause);
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extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
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#endif
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/***************************************************************************
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CONVENIENCE INCLUSIONS.
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Ensures RTOS specific files need only include this one Xtensa-generic header.
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These headers are included last so they can use the RTOS definitions above.
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***************************************************************************/
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#include "xtensa_context.h"
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#ifdef XT_RTOS_TIMER_INT
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#include "xtensa_timer.h"
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#endif
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#endif /* XTENSA_RTOS_H */
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