mirror of
https://github.com/azure-rtos/threadx
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249 lines
9.5 KiB
Plaintext
249 lines
9.5 KiB
Plaintext
Microsoft's Azure RTOS ThreadX for TMS320C667x
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Using the TI Code Composer Tools
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1. Installation
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TI Code Composer Studio and the TI MCSDK must be installed prior to
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building ThreadX. The following links can be used to download these
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packages:
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http://processors.wiki.ti.com/index.php/Download_CCS
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http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html
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It is assumed the tools are installed in the default directories:
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CCS path by default - c:\ti\ccsv(version number)
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MCSDK path by default - c:\ti
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If the packages are installed in different directories, the ThreadX project
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settings must be adjusted.
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2. Open the Azure RTOS Workspace
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In order to build the ThreadX library and the ThreadX demonstration first open
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the Azure RTOS Workspace inside your ThreadX installation directory.
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3. Building the ThreadX run-time Library
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Building the ThreadX library is easy; simply import the CCS project file
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"tx" and then select the build button. You should now observe the compilation
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and assembly of the ThreadX library. This project build produces the ThreadX
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library file tx.lib.
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4. Demonstration System
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The ThreadX demonstration is designed to execute on the C6678EVM evaluation board.
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Building the demonstration is easy; simply import the "sample_threadx_c6678evm" project.
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Now select "Project -> Build Active Project" to build the ThreadX demonstration,
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which produces the sample_threadx.out file in the "Debug" directory. You are now
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ready to run the ThreadX demonstration on the C6678EVM evaluation board.
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Please refer to Chapter 6 of the ThreadX User Guide for a complete description
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of this demonstration.
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5. System Initialization
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The entry point in ThreadX for the TMS320C667x using the TI tools is at label
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_c_int00. This is defined within the TI library. In addition, this is
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where all static and global pre-set C variable initialization processing
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takes place.
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The ThreadX initialization file tx_initialize_low_level.asm is responsible
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for setting up various system data structures, the vector area, and a periodic
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timer interrupt source. By default, the vector area is defined to be located in
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the "vectors" section, which is defined at the top of tx_initialize_low_level.asm.
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This area is located at address 0 for the demonstration.
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tx_initialize_low_level.asm is also where initialization of a periodic timer
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interrupt source should take place.
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In addition, _tx_initialize_low_level determines the first available address
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for use by the application. By default, free memory is assumed to start after
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the .zend section in RAM (defined in tx_initialize_low_level). This section
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must be placed at the end of your other RAM sections. Please see sample_threadx.cmd
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for an example. The address of this section is passed to the application definition
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function, tx_application_define.
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6. Register Usage and Stack Frames
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The TI TMS320C667x compiler assumes that registers A0-A9, A16-A31, B0-B9, and
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B16-B31 are scratch registers for each function. All other registers used by
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a C function must be preserved by the function. ThreadX takes advantage of this
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in situations where a context switch happens as a result of making a ThreadX
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service call (which is itself a C function). In such cases, the saved context
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of a thread is only the non-scratch registers.
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The following defines the saved context stack frames for context switches
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that occur as a result of interrupt handling or from thread-level API calls.
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All suspended threads have one of these two types of stack frames. The top
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of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the
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associated thread control block TX_THREAD.
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Offset Interrupted Stack Frame Non-Interrupt Stack Frame
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0x04 1 0
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0x08 CSR CSR
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0x0C IPR B3
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0x10 AMR AMR
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0x14 A0 A10
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0x18 A1 A11
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0x1C A2 A12
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0x20 A3 A13
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0x24 A4 A14
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0x28 A5 A15
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0x2C A6 B10
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0x30 A7 B11
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0x34 A8 B12
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0x38 A9 B13
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0x3C A10 ILC
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0x40 A11 RILC
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0x44 A12
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0x48 A13
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0x4C A14
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0x50 A15
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0x54 B0
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0x58 B1
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0x5C B2
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0x60 B3
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0x64 B4
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0x68 B5
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0x6C B6
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0x70 B7
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0x74 B8
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0x78 B9
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0x7C B10
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0x80 B11
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0x84 B12
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0x88 B13
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0x8C A16
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0x90 A17
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0x94 A18
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0x98 A19
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0x9C A20
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0xA0 A21
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0xA4 A22
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0xA8 A23
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0xAC A24
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0xB0 A25
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0xB4 A26
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0xB8 A27
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0xBC A28
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0xC0 A29
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0xC4 A30
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0xC8 A31
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0xCC B16
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0xD0 B17
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0xD4 B18
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0xD8 B19
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0xDC B20
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0xE0 B21
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0xE4 B22
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0xE8 B23
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0xEC B24
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0xF0 B25
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0xF4 B26
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0xF8 B27
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0xFC B28
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0x100 B29
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0x104 B30
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0x108 B31
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0x10C ILC
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0x110 RILC
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0x114 ITSR
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7. Improving Performance
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The distribution version of ThreadX is built without any compiler
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optimizations. This makes it easy to debug because you can trace or set
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breakpoints inside of ThreadX itself. Of course, this costs some performance.
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To make it run faster, you can replace the -g compiler option
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to a -O3 in the ThreadX project file to enable all compiler optimizations.
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In addition, you can eliminate the ThreadX basic API error checking by
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compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
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defined.
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8. Interrupt Handling
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ThreadX provides complete and high-performance interrupt handling for
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TMS320C667x targets. There are a certain set of requirements that are
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defined in the following sub-sections:
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8.1 Vector Area
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The TMS320C667x interrupt vectors at in the section "vectors" and is defined at
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the top of tx_initialize_low_level.asm. Each interrupt vector entry contains
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a jump to a template interrupt processing shell.
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8.2 Interrupt Service Routine Shells
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The following interrupt processing shells are defined at the bottom of
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tx_initialize_low_level.asm:
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__tx_int4_ISR
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__tx_int5_ISR
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__tx_int6_ISR
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__tx_int7_ISR
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__tx_int8_ISR
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__tx_int9_ISR
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__tx_int10_ISR
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__tx_int11_ISR
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__tx_int12_ISR
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__tx_int13_ISR
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__tx_int14_ISR
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__tx_int15_ISR
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Each interrupt ISR is entered with B3, A0-A4 is available (these registers are
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saved in the initial vector processing). The default interrupt handling
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includes calls to __tx_thread_context_save and __tx_thread_context_restore.
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Application ISR processing can be added between the context save/restore
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calls. Note that only the compiler scratch registers are available for use
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after context save return to the ISR.
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High-frequency interrupt handlers might not want to perform context
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save/restore processing on each interrupt. If this is the case, any
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additional registers used must be saved and restored by the ISR and
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the interrupt return processing must restore the registers saved by the
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initial vector processing. This can be accomplished by adding the
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following code to the end of the custom ISR handling:
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LDW *+SP(20),A0 ; Recover A0
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LDW *+SP(24),A1 ; Recover A1
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LDW *+SP(28),A2 ; Recover A2
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LDW *+SP(32),A3 ; Recover A3
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B IRP ; Return to point of interrupt
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|| LDW *+SP(36),A4 ; Recover A4
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LDW *+SP(96),B3 ; Recover B3
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ADDK.S2 288,SP ; Recover stack space
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NOP 3 ; Delay slots
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9. Revision History
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For generic code revision information, please refer to the readme_threadx_generic.txt
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file, which is included in your distribution. The following details the revision
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information associated with this specific port of ThreadX:
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09-30-2020 Initial ThreadX 6.1 version for TMS320C667x using TI Code Composer tools.
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Copyright(c) 1996-2020 Microsoft Corporation
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https://azure.com/rtos
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