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85 lines
3.3 KiB
C
85 lines
3.3 KiB
C
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/**********************************************************************
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* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.h 2011-12-07
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*//**
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* @file lpc43xx_emc.h
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* @brief Contains all functions support for Clock Generation and Control
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* firmware library on lpc43xx
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* @version 1.0
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* @date 07. December. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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#define __CRYSTAL (12000000UL) /* Crystal Oscillator frequency */
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#define __PLLMULT (15)
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#define __PLLOUTHZ (__CRYSTAL * __PLLMULT)
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#define __EMCDIV (2)
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#define __EMCHZ (__PLLOUTHZ / __EMCDIV)
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void MemoryPinInit(void);
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void EMCFlashInit(void);
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/* SDRAM Address Base for DYCS0*/
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#define SDRAM_BASE_ADDR 0x28000000
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#define FLASH_BASE_ADDR 0x1C000000
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#define EMC_SDRAM_WIDTH_8_BITS 0
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#define EMC_SDRAM_WIDTH_16_BITS 1
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#define EMC_SDRAM_WIDTH_32_BITS 2
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#define EMC_SDRAM_SIZE_16_MBITS 0
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#define EMC_SDRAM_SIZE_64_MBITS 1
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#define EMC_SDRAM_SIZE_128_MBITS 2
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#define EMC_SDRAM_SIZE_256_MBITS 3
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#define EMC_SDRAM_SIZE_512_MBITS 4
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#define EMC_SDRAM_DATA_BUS_16_BITS 0
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#define EMC_SDRAM_DATA_BUS_32_BITS 1
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#define EMC_B_ENABLE (1 << 19)
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#define EMC_ENABLE (1 << 0)
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#define EMC_CE_ENABLE (1 << 0)
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#define EMC_CS_ENABLE (1 << 1)
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#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
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#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
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#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
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#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
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#define EMC_INIT(i) ((i) << 7)
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#define EMC_NORMAL (0)
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#define EMC_MODE (1)
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#define EMC_PRECHARGE_ALL (2)
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#define EMC_NOP (3)
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/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
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#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
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#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
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#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
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#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
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#define SDRAM_COL_ADDR_BITS 8
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#define CLK0_DELAY 6
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void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
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void emc_WaitUS(volatile uint32_t us);
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void emc_WaitMS(uint32_t ms);
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