2019-10-02 23:02:55 -04:00
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/*
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2019-03-20 16:11:42 +07:00
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* The MIT License (MIT)
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*
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2019-05-14 11:48:05 +07:00
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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2019-03-20 16:11:42 +07:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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2018-11-07 23:04:34 -08:00
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#include "tusb_option.h"
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#if TUSB_OPT_DEVICE_ENABLED
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#include "tusb.h"
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#include "device/usbd_pvt.h"
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2019-06-10 18:46:00 +07:00
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#include "dcd.h"
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2018-11-07 23:04:34 -08:00
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2018-11-16 21:56:39 +07:00
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enum
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{
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EDPT_CTRL_OUT = 0x00,
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EDPT_CTRL_IN = 0x80
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};
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2018-11-16 22:20:13 +07:00
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typedef struct
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{
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tusb_control_request_t request;
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2018-11-16 21:56:39 +07:00
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2019-11-02 23:29:35 +07:00
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uint8_t* buffer;
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uint16_t data_len;
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uint16_t total_xferred;
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2018-11-16 21:56:39 +07:00
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2018-11-16 22:20:13 +07:00
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bool (*complete_cb) (uint8_t, tusb_control_request_t const *);
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} usbd_control_xfer_t;
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2018-11-16 21:56:39 +07:00
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2019-11-02 23:29:35 +07:00
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static usbd_control_xfer_t _ctrl_xfer;
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2018-11-07 23:04:34 -08:00
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2019-11-05 10:17:36 +07:00
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CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
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2018-11-14 16:03:58 +07:00
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2019-11-02 23:29:35 +07:00
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//--------------------------------------------------------------------+
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// Application API
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//--------------------------------------------------------------------+
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2018-11-07 23:04:34 -08:00
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2019-11-05 10:17:36 +07:00
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static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
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2018-11-07 23:04:34 -08:00
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{
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2018-11-16 21:56:39 +07:00
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// status direction is reversed to one in the setup packet
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return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0);
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2018-11-07 23:04:34 -08:00
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}
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2019-11-05 10:17:36 +07:00
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bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
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{
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = NULL;
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_ctrl_xfer.total_xferred = 0;
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_ctrl_xfer.data_len = 0;
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return _status_stage_xact(rhport, request);
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}
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2019-11-02 23:29:35 +07:00
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// Transfer an transaction in Data Stage
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// Each transaction has up to Endpoint0's max packet size.
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// This function can also transfer an zero-length packet
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static bool _data_stage_xact(uint8_t rhport)
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{
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2019-11-02 23:29:35 +07:00
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uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE);
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2018-11-07 23:04:34 -08:00
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2018-11-16 21:56:39 +07:00
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uint8_t ep_addr = EDPT_CTRL_OUT;
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2018-11-07 23:04:34 -08:00
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2019-11-02 23:29:35 +07:00
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if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN )
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2018-11-07 23:04:34 -08:00
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{
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2018-11-16 21:56:39 +07:00
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ep_addr = EDPT_CTRL_IN;
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2019-11-02 23:29:35 +07:00
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if ( xact_len ) memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len);
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2018-11-07 23:04:34 -08:00
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}
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2019-11-02 23:29:35 +07:00
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return dcd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len);
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2018-11-07 23:04:34 -08:00
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}
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2019-07-16 18:14:47 +07:00
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bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len)
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2018-11-16 21:56:39 +07:00
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{
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2019-11-02 23:29:35 +07:00
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = (uint8_t*) buffer;
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_ctrl_xfer.total_xferred = 0;
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_ctrl_xfer.data_len = tu_min16(len, request->wLength);
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if ( _ctrl_xfer.data_len )
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2018-11-07 23:04:34 -08:00
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{
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2019-05-12 14:09:35 +07:00
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TU_ASSERT(buffer);
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2018-11-16 21:56:39 +07:00
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// Data stage
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2019-11-02 23:29:35 +07:00
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TU_ASSERT( _data_stage_xact(rhport) );
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2018-11-16 21:56:39 +07:00
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}else
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{
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// Status stage
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2019-11-05 10:17:36 +07:00
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TU_ASSERT( _status_stage_xact(rhport, request) );
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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return true;
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2018-11-07 23:04:34 -08:00
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}
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2019-11-02 23:29:35 +07:00
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//--------------------------------------------------------------------+
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// USBD API
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//--------------------------------------------------------------------+
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void usbd_control_reset (uint8_t rhport)
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{
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(void) rhport;
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tu_varclr(&_ctrl_xfer);
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}
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// TODO may find a better way
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void usbd_control_set_complete_callback( bool (*fp) (uint8_t, tusb_control_request_t const * ) )
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{
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_ctrl_xfer.complete_cb = fp;
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}
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2019-10-03 23:50:55 -04:00
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2018-11-16 21:56:39 +07:00
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// callback when a transaction complete on DATA stage of control endpoint
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2018-11-26 12:25:28 +07:00
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bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
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{
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2018-11-26 12:25:28 +07:00
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(void) result;
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2019-11-02 23:29:35 +07:00
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// Endpoint Address is opposite to direction bit, this is Status Stage complete event
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if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
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{
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TU_ASSERT(0 == xferred_bytes);
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2019-11-03 18:00:07 +07:00
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if (dcd_control_status_complete) dcd_control_status_complete(rhport);
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2019-11-02 23:29:35 +07:00
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return true;
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}
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if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT )
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2018-11-16 21:56:39 +07:00
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{
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2019-11-02 23:29:35 +07:00
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TU_VERIFY(_ctrl_xfer.buffer);
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memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
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2018-11-07 23:04:34 -08:00
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}
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2019-11-02 23:29:35 +07:00
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_ctrl_xfer.total_xferred += xferred_bytes;
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_ctrl_xfer.buffer += xferred_bytes;
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2018-11-16 21:56:39 +07:00
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2019-11-02 23:29:35 +07:00
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// Data Stage is complete when all request's length are transferred or
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// a short packet is sent including zero-length packet.
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if ( (_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || xferred_bytes < CFG_TUD_ENDPOINT0_SIZE )
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2018-11-16 21:56:39 +07:00
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{
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// DATA stage is complete
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bool is_ok = true;
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// invoke complete callback if set
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// callback can still stall control in status phase e.g out data does not make sense
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2019-11-02 23:29:35 +07:00
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if ( _ctrl_xfer.complete_cb )
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2018-11-16 21:56:39 +07:00
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{
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2019-11-02 23:29:35 +07:00
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is_ok = _ctrl_xfer.complete_cb(rhport, &_ctrl_xfer.request);
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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if ( is_ok )
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{
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// Send status
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2019-11-05 10:17:36 +07:00
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TU_ASSERT( _status_stage_xact(rhport, &_ctrl_xfer.request) );
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2018-11-16 21:56:39 +07:00
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}else
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{
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2019-03-27 16:26:52 +07:00
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// Stall both IN and OUT control endpoint
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dcd_edpt_stall(rhport, EDPT_CTRL_OUT);
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dcd_edpt_stall(rhport, EDPT_CTRL_IN);
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2018-11-07 23:04:34 -08:00
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}
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}
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2018-11-16 21:56:39 +07:00
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else
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{
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// More data to transfer
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2019-11-02 23:29:35 +07:00
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TU_ASSERT( _data_stage_xact(rhport) );
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2018-11-16 21:56:39 +07:00
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}
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2018-11-20 17:25:41 +07:00
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return true;
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2018-11-07 23:04:34 -08:00
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}
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#endif
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