2018-11-07 23:04:34 -08:00
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/**************************************************************************/
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/*!
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2018-11-16 22:00:16 +07:00
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@file usbd_control.c
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2018-11-07 23:04:34 -08:00
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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#include "tusb_option.h"
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#if TUSB_OPT_DEVICE_ENABLED
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#define _TINY_USB_SOURCE_FILE_
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#include "tusb.h"
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#include "device/usbd_pvt.h"
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2018-11-16 21:56:39 +07:00
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enum
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{
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EDPT_CTRL_OUT = 0x00,
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EDPT_CTRL_IN = 0x80
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};
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2018-11-16 22:20:13 +07:00
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typedef struct
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{
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tusb_control_request_t request;
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2018-11-16 21:56:39 +07:00
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2018-11-16 22:20:13 +07:00
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void* buffer;
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uint16_t total_len;
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uint16_t total_transferred;
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2018-11-16 21:56:39 +07:00
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2018-11-16 22:20:13 +07:00
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bool (*complete_cb) (uint8_t, tusb_control_request_t const *);
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} usbd_control_xfer_t;
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2018-11-16 21:56:39 +07:00
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2018-11-16 22:20:13 +07:00
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static usbd_control_xfer_t _control_state;
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2018-11-16 21:56:39 +07:00
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CFG_TUSB_ATTR_USBRAM CFG_TUSB_MEM_ALIGN uint8_t _usbd_ctrl_buf[CFG_TUD_ENDOINT0_SIZE];
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2018-11-14 16:03:58 +07:00
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2018-11-16 21:56:39 +07:00
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void usbd_control_reset (uint8_t rhport)
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{
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2018-11-16 22:20:13 +07:00
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tu_varclr(&_control_state);
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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void usbd_control_stall(uint8_t rhport)
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{
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dcd_edpt_stall(rhport, 0);
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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bool usbd_control_status(uint8_t rhport, tusb_control_request_t const * request)
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{
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2018-11-16 21:56:39 +07:00
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// status direction is reversed to one in the setup packet
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return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0);
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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// Each transaction is up to endpoint0's max packet size
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static bool start_control_data_xact(uint8_t rhport)
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{
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uint16_t const xact_len = tu_min16(_control_state.total_len - _control_state.total_transferred, CFG_TUD_ENDOINT0_SIZE);
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2018-11-16 21:56:39 +07:00
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uint8_t ep_addr = EDPT_CTRL_OUT;
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2018-11-16 22:20:13 +07:00
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if ( _control_state.request.bmRequestType_bit.direction == TUSB_DIR_IN )
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{
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ep_addr = EDPT_CTRL_IN;
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2018-11-16 22:20:13 +07:00
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memcpy(_usbd_ctrl_buf, _control_state.buffer, xact_len);
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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return dcd_edpt_xfer(rhport, ep_addr, _usbd_ctrl_buf, xact_len);
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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// TODO may find a better way
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void usbd_control_set_complete_callback( bool (*fp) (uint8_t, tusb_control_request_t const * ) )
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{
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_control_state.complete_cb = fp;
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}
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2018-11-16 21:56:39 +07:00
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bool usbd_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len)
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{
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2018-11-16 22:20:13 +07:00
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_control_state.request = (*request);
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_control_state.buffer = buffer;
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_control_state.total_len = tu_min16(len, request->wLength);
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_control_state.total_transferred = 0;
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2018-11-07 23:04:34 -08:00
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2018-11-16 21:56:39 +07:00
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if ( buffer != NULL && len )
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{
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2018-11-16 21:56:39 +07:00
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// Data stage
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TU_ASSERT( start_control_data_xact(rhport) );
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}else
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{
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// Status stage
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TU_ASSERT( usbd_control_status(rhport, request) );
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}
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2018-11-16 21:56:39 +07:00
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return true;
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2018-11-07 23:04:34 -08:00
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}
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2018-11-16 21:56:39 +07:00
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// callback when a transaction complete on DATA stage of control endpoint
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tusb_error_t usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, tusb_event_t event, uint32_t xferred_bytes)
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{
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2018-11-16 22:20:13 +07:00
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if ( _control_state.request.bmRequestType_bit.direction == TUSB_DIR_OUT )
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{
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2018-11-16 22:20:13 +07:00
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memcpy(_control_state.buffer, _usbd_ctrl_buf, xferred_bytes);
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}
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2018-11-16 22:20:13 +07:00
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_control_state.total_transferred += xferred_bytes;
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_control_state.buffer += xferred_bytes;
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2018-11-16 21:56:39 +07:00
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2018-11-16 22:20:13 +07:00
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if ( _control_state.total_len == _control_state.total_transferred || xferred_bytes < CFG_TUD_ENDOINT0_SIZE )
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{
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// DATA stage is complete
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bool is_ok = true;
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// invoke complete callback if set
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// callback can still stall control in status phase e.g out data does not make sense
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2018-11-16 22:20:13 +07:00
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if ( _control_state.complete_cb )
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{
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is_ok = _control_state.complete_cb(rhport, &_control_state.request);
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}
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if ( is_ok )
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{
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// Send status
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2018-11-16 22:20:13 +07:00
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TU_ASSERT( usbd_control_status(rhport, &_control_state.request), TUSB_ERROR_FAILED );
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}else
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{
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// stall due to callback
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usbd_control_stall(rhport);
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}
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}
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2018-11-16 21:56:39 +07:00
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else
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{
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// More data to transfer
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TU_ASSERT(start_control_data_xact(rhport), TUSB_ERROR_FAILED);
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}
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return TUSB_ERROR_NONE;
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2018-11-07 23:04:34 -08:00
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}
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#endif
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