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<div class="title">emac.h</div> </div>
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<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> <span class="preprocessor">#ifndef __EMAC_H</span></div>
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<div class="line"><a name="l00002"></a><span class="lineno"> 2</span> <span class="preprocessor"></span><span class="preprocessor">#define __EMAC_H</span></div>
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<div class="line"><a name="l00003"></a><span class="lineno"> 3</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00004"></a><span class="lineno"> 4</span> </div>
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<div class="line"><a name="l00005"></a><span class="lineno"> 5</span> <span class="comment">/* Configuration */</span></div>
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<div class="line"><a name="l00006"></a><span class="lineno"> 6</span> </div>
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<div class="line"><a name="l00007"></a><span class="lineno"> 7</span> <span class="comment">/* Interface Selection */</span></div>
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<div class="line"><a name="l00008"></a><span class="lineno"> 8</span> <span class="preprocessor">#define MII 0 // =0 RMII - =1 MII</span></div>
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<div class="line"><a name="l00009"></a><span class="lineno"> 9</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00010"></a><span class="lineno"> 10</span> <span class="comment">/* MAC Configuration */</span></div>
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<div class="line"><a name="l00011"></a><span class="lineno"> 11</span> <span class="preprocessor">#define MYMAC_1 0x1EU </span><span class="comment">/* our ethernet (MAC) address */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00012"></a><span class="lineno"> 12</span> <span class="preprocessor"></span><span class="preprocessor">#define MYMAC_2 0x30U </span><span class="comment">/* (MUST be unique in LAN!) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00013"></a><span class="lineno"> 13</span> <span class="preprocessor"></span><span class="preprocessor">#define MYMAC_3 0x6cU</span></div>
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<div class="line"><a name="l00014"></a><span class="lineno"> 14</span> <span class="preprocessor"></span><span class="preprocessor">#define MYMAC_4 0xa2U</span></div>
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<div class="line"><a name="l00015"></a><span class="lineno"> 15</span> <span class="preprocessor"></span><span class="preprocessor">#define MYMAC_5 0x45U</span></div>
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<div class="line"><a name="l00016"></a><span class="lineno"> 16</span> <span class="preprocessor"></span><span class="preprocessor">#define MYMAC_6 0x5eU</span></div>
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<div class="line"><a name="l00017"></a><span class="lineno"> 17</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00018"></a><span class="lineno"> 18</span> </div>
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<div class="line"><a name="l00019"></a><span class="lineno"> 19</span> <span class="preprocessor">#define ETH_FRAG_SIZE 1536 </span></div>
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<div class="line"><a name="l00020"></a><span class="lineno"> 20</span> <span class="preprocessor"></span><span class="preprocessor">#define NUM_RX_DESC 3</span></div>
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<div class="line"><a name="l00021"></a><span class="lineno"> 21</span> <span class="preprocessor"></span><span class="preprocessor">#define NUM_TX_DESC 3</span></div>
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<div class="line"><a name="l00022"></a><span class="lineno"> 22</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00023"></a><span class="lineno"> 23</span> <span class="comment">/* End of Configuration */</span></div>
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<div class="line"><a name="l00024"></a><span class="lineno"> 24</span> </div>
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<div class="line"><a name="l00025"></a><span class="lineno"> 25</span> </div>
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<div class="line"><a name="l00026"></a><span class="lineno"> 26</span> <span class="comment">/* EMAC Descriptors and Buffers located in 16K SRAM */</span></div>
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<div class="line"><a name="l00027"></a><span class="lineno"> 27</span> <span class="comment">/* Rx Descriptors */</span></div>
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<div class="line"><a name="l00028"></a><span class="lineno"> 28</span> <span class="preprocessor">#define RX_DESC_BASE 0x20008000</span></div>
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<div class="line"><a name="l00029"></a><span class="lineno"> 29</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_STAT_BASE RX_DESC_BASE</span></div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_CTRL_BASE (RX_STAT_BASE + 4)</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_BUFADDR_BASE (RX_CTRL_BASE + 4)</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_NEXTDESC_BASE (RX_BUFADDR_BASE + 4)</span></div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_BUF_BASE (RX_DESC_BASE + NUM_RX_DESC*16) </span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define RX_DESC_STAT(i) (*(unsigned int *)(RX_STAT_BASE + 16*i)) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_CTRL_BASE + 16*i))</span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_BUFADDR(i) (*(unsigned int *)(RX_BUFADDR_BASE + 16*i))</span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_NEXTDESC(i) (*(unsigned int *)(RX_NEXTDESC_BASE + 16*i))</span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)</span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="comment">/* Tx Descriptors */</span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define TX_DESC_BASE RX_BUF_BASE + (ETH_FRAG_SIZE * NUM_RX_DESC)</span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_STAT_BASE TX_DESC_BASE</span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_CTRL_BASE (TX_STAT_BASE + 4)</span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_BUFADDR_BASE (TX_CTRL_BASE + 4)</span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_NEXTDESC_BASE (TX_BUFADDR_BASE + 4)</span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_BUF_BASE (TX_DESC_BASE + NUM_TX_DESC*16)</span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define TX_DESC_STAT(i) (*(unsigned int *)(TX_STAT_BASE + 16*i))</span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_CTRL_BASE + 16*i))</span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_BUFADDR(i) (*(unsigned int *)(TX_BUFADDR_BASE + 16*i))</span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_NEXTDESC(i) (*(unsigned int *)(TX_NEXTDESC_BASE + 16*i))</span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="comment">/* Descriptors Fields bits */</span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define OWN_BIT (1U<<31) </span><span class="comment">/* Own bit in RDES0 & TDES0 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_END_RING (1<<15) </span><span class="comment">/* Receive End of Ring bit in RDES1 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor"></span><span class="preprocessor">#define RX_NXTDESC_FLAG (1<<14) </span><span class="comment">/* Second Address Chained bit in RDES1 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_LAST_SEGM (1<<29) </span><span class="comment">/* Last Segment bit in TDES0 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_FIRST_SEGM (1<<28) </span><span class="comment">/* First Segment bit in TDES0 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_END_RING (1<<21) </span><span class="comment">/* Transmit End of Ring bit in TDES0 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor"></span><span class="preprocessor">#define TX_NXTDESC_FLAG (1<<20) </span><span class="comment">/* Second Address Chained bit in TDES0 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> </div>
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<div class="line"><a name="l00065"></a><span class="lineno"> 65</span> </div>
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<div class="line"><a name="l00066"></a><span class="lineno"> 66</span> </div>
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<div class="line"><a name="l00067"></a><span class="lineno"> 67</span> </div>
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<div class="line"><a name="l00068"></a><span class="lineno"> 68</span> <span class="comment">/* EMAC Control and Status bits */</span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"> 69</span> <span class="preprocessor">#define MAC_RX_ENABLE (1<<2) </span><span class="comment">/* Receiver Enable in MAC_CONFIG reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"> 70</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_TX_ENABLE (1<<3) </span><span class="comment">/* Transmitter Enable in MAC_CONFIG reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"> 71</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_PADCRC_STRIP (1<<7) </span><span class="comment">/* Automatic Pad-CRC Stripping in MAC_CONFIG reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"> 72</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_DUPMODE (1<<11) </span><span class="comment">/* Duplex Mode in MAC_CONFIG reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_100MPS (1<<14) </span><span class="comment">/* Speed is 100Mbps in MAC_CONFIG reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"> 74</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_PROMISCUOUS (1U<<0) </span><span class="comment">/* Promiscuous Mode bit in MAC_FRAME_FILTER reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"> 75</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_DIS_BROAD (1U<<5) </span><span class="comment">/* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"> 76</span> <span class="preprocessor"></span><span class="preprocessor">#define MAC_RECEIVEALL (1U<<31) </span><span class="comment">/* Receive All bit in MAC_FRAME_FILTER reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"> 77</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_SOFT_RESET 0x01 </span><span class="comment">/* Software Reset bit in DMA_BUS_MODE reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"> 78</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_SS_RECEIVE (1<<1) </span><span class="comment">/* Start/Stop Receive bit in DMA_OP_MODE reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"> 79</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_SS_TRANSMIT (1<<13) </span><span class="comment">/* Start/Stop Transmission bit in DMA_OP_MODE reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"> 80</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_INT_TRANSMIT (1<<0) </span><span class="comment">/* Transmit Interrupt Enable bit in DMA_INT_EN reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_INT_OVERFLOW (1<<4) </span><span class="comment">/* Overflow Interrupt Enable bit in DMA_INT_EN reg */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"> 82</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_INT_UNDERFLW (1<<5) </span><span class="comment">/* Underflow Interrupt Enable bit in DMA_INT_EN reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_INT_RECEIVE (1<<6) </span><span class="comment">/* Receive Interrupt Enable bit in DMA_INT_EN reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_INT_ABN_SUM (1<<15) </span><span class="comment">/* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor"></span><span class="preprocessor">#define DMA_INT_NOR_SUM (1<<16) </span><span class="comment">/* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="comment">/* MII Management Command Register */</span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#define GMII_READ (0<<1) </span><span class="comment">/* GMII Read PHY */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor"></span><span class="preprocessor">#define GMII_WRITE (1<<1) </span><span class="comment">/* GMII Write PHY */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor"></span><span class="preprocessor">#define GMII_BUSY 0x00000001 </span><span class="comment">/* GMII is Busy / Start Read/Write */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor"></span><span class="preprocessor">#define MII_WR_TOUT 0x00050000 </span><span class="comment">/* MII Write timeout count */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor"></span><span class="preprocessor">#define MII_RD_TOUT 0x00050000 </span><span class="comment">/* MII Read timeout count */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="comment">/* MII Management Address Register */</span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#define MADR_PHY_ADR 0x00001F00 </span><span class="comment">/* PHY Address Mask */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="comment">/* DP83848C PHY Registers */</span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define PHY_REG_BMCR 0x00 </span><span class="comment">/* Basic Mode Control Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_BMSR 0x01 </span><span class="comment">/* Basic Mode Status Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_IDR1 0x02 </span><span class="comment">/* PHY Identifier 1 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_IDR2 0x03 </span><span class="comment">/* PHY Identifier 2 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_ANAR 0x04 </span><span class="comment">/* Auto-Negotiation Advertisement */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_ANLPAR 0x05 </span><span class="comment">/* Auto-Neg. Link Partner Abitily */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_ANER 0x06 </span><span class="comment">/* Auto-Neg. Expansion Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_ANNPTR 0x07 </span><span class="comment">/* Auto-Neg. Next Page TX */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="comment">/* PHY Extended Registers */</span></div>
|
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor">#define PHY_REG_STS 0x10 </span><span class="comment">/* Status Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_MICR 0x11 </span><span class="comment">/* MII Interrupt Control Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00110"></a><span class="lineno"> 110</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_MISR 0x12 </span><span class="comment">/* MII Interrupt Status Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_FCSCR 0x14 </span><span class="comment">/* False Carrier Sense Counter */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_RECR 0x15 </span><span class="comment">/* Receive Error Counter */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_PCSR 0x16 </span><span class="comment">/* PCS Sublayer Config. and Status */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00114"></a><span class="lineno"> 114</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_RBR 0x17 </span><span class="comment">/* RMII and Bypass Register */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_LEDCR 0x18 </span><span class="comment">/* LED Direct Control Register */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00116"></a><span class="lineno"> 116</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_PHYCR 0x19 </span><span class="comment">/* PHY Control Register */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00117"></a><span class="lineno"> 117</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_10BTSCR 0x1A </span><span class="comment">/* 10Base-T Status/Control Register */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00118"></a><span class="lineno"> 118</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_CDCTRL1 0x1B </span><span class="comment">/* CD Test Control and BIST Extens. */</span><span class="preprocessor"></span></div>
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||
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<div class="line"><a name="l00119"></a><span class="lineno"> 119</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_EDCR 0x1D </span><span class="comment">/* Energy Detect Control Register */</span><span class="preprocessor"></span></div>
|
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<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> <span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00121"></a><span class="lineno"> 121</span> <span class="comment">/* PHY Control and Status bits */</span></div>
|
||
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|
<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor">#define PHY_FULLD_100M 0x2100 </span><span class="comment">/* Full Duplex 100Mbit */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_HALFD_100M 0x2000 </span><span class="comment">/* Half Duplex 100Mbit */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_FULLD_10M 0x0100 </span><span class="comment">/* Full Duplex 10Mbit */</span><span class="preprocessor"></span></div>
|
||
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|
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_HALFD_10M 0x0000 </span><span class="comment">/* Half Duplex 10MBit */</span><span class="preprocessor"></span></div>
|
||
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|
<div class="line"><a name="l00126"></a><span class="lineno"> 126</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_AUTO_NEG 0x1000 </span><span class="comment">/* Select Auto Negotiation */</span><span class="preprocessor"></span></div>
|
||
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|
<div class="line"><a name="l00127"></a><span class="lineno"> 127</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_AUTO_NEG_DONE 0x0020 </span><span class="comment">/* AutoNegotiation Complete in BMSR PHY reg */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00128"></a><span class="lineno"> 128</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_BMCR_RESET 0x8000 </span><span class="comment">/* Reset bit at BMCR PHY reg */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00129"></a><span class="lineno"> 129</span> <span class="preprocessor"></span><span class="preprocessor">#define LINK_VALID_STS 0x0001 </span><span class="comment">/* Link Valid Status at REG_STS PHY reg */</span><span class="preprocessor"></span></div>
|
||
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|
<div class="line"><a name="l00130"></a><span class="lineno"> 130</span> <span class="preprocessor"></span><span class="preprocessor">#define FULL_DUP_STS 0x0004 </span><span class="comment">/* Full Duplex Status at REG_STS PHY reg */</span><span class="preprocessor"></span></div>
|
||
|
|
<div class="line"><a name="l00131"></a><span class="lineno"> 131</span> <span class="preprocessor"></span><span class="preprocessor">#define SPEED_10M_STS 0x0002 </span><span class="comment">/* 10Mbps Status at REG_STS PHY reg */</span><span class="preprocessor"></span></div>
|
||
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|
<div class="line"><a name="l00132"></a><span class="lineno"> 132</span> <span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00133"></a><span class="lineno"> 133</span> <span class="preprocessor">#define DP83848C_DEF_ADR 0x01 </span><span class="comment">/* Default PHY device address */</span><span class="preprocessor"></span></div>
|
||
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|
<div class="line"><a name="l00134"></a><span class="lineno"> 134</span> <span class="preprocessor"></span><span class="preprocessor">#define DP83848C_ID 0x20005C90 </span><span class="comment">/* PHY Identifier (without Rev. info */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00135"></a><span class="lineno"> 135</span> <span class="preprocessor"></span></div>
|
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<div class="line"><a name="l00136"></a><span class="lineno"> 136</span> <span class="preprocessor">#define LAN8720_ID 0x0007C0F0 </span><span class="comment">/* PHY Identifier */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00137"></a><span class="lineno"> 137</span> <span class="preprocessor"></span><span class="preprocessor">#define PHY_REG_SCSR 0x1F </span><span class="comment">/* PHY Special Control/Status Register */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00138"></a><span class="lineno"> 138</span> <span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00139"></a><span class="lineno"> 139</span> <span class="comment">/* Misc */</span></div>
|
||
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|
<div class="line"><a name="l00140"></a><span class="lineno"> 140</span> <span class="preprocessor">#define ETHERNET_RST 22 </span><span class="comment">/* Reset Output for EMAC at RGU */</span><span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00141"></a><span class="lineno"> 141</span> <span class="preprocessor"></span><span class="preprocessor">#define RMII_SELECT 0x04 </span><span class="comment">/* Select RMII in EMACCFG */</span><span class="preprocessor"></span></div>
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||
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<div class="line"><a name="l00142"></a><span class="lineno"> 142</span> <span class="preprocessor"></span></div>
|
||
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<div class="line"><a name="l00143"></a><span class="lineno"> 143</span> </div>
|
||
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|
<div class="line"><a name="l00144"></a><span class="lineno"> 144</span> <span class="comment">/* Prototypes */</span></div>
|
||
|
|
<div class="line"><a name="l00145"></a><span class="lineno"> 145</span> <span class="keywordtype">void</span> Init_EMAC(<span class="keywordtype">void</span>);</div>
|
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<div class="line"><a name="l00146"></a><span class="lineno"> 146</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> ReadFrameBE_EMAC(<span class="keywordtype">void</span>);</div>
|
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<div class="line"><a name="l00147"></a><span class="lineno"> 147</span> <span class="keywordtype">void</span> CopyToFrame_EMAC(<span class="keywordtype">void</span> *Source, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> Size);</div>
|
||
|
|
<div class="line"><a name="l00148"></a><span class="lineno"> 148</span> <span class="keywordtype">void</span> CopyFromFrame_EMAC(<span class="keywordtype">void</span> *Dest, <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> Size);</div>
|
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<div class="line"><a name="l00149"></a><span class="lineno"> 149</span> <span class="keywordtype">void</span> DummyReadFrame_EMAC(<span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> Size);</div>
|
||
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<div class="line"><a name="l00150"></a><span class="lineno"> 150</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> StartReadFrame(<span class="keywordtype">void</span>);</div>
|
||
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<div class="line"><a name="l00151"></a><span class="lineno"> 151</span> <span class="keywordtype">void</span> EndReadFrame(<span class="keywordtype">void</span>);</div>
|
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<div class="line"><a name="l00152"></a><span class="lineno"> 152</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> CheckFrameReceived(<span class="keywordtype">void</span>);</div>
|
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<div class="line"><a name="l00153"></a><span class="lineno"> 153</span> <span class="keywordtype">void</span> RequestSend(<span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> FrameSize);</div>
|
||
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<div class="line"><a name="l00154"></a><span class="lineno"> 154</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> Rdy4Tx(<span class="keywordtype">void</span>);</div>
|
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<div class="line"><a name="l00155"></a><span class="lineno"> 155</span> </div>
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<div class="line"><a name="l00156"></a><span class="lineno"> 156</span> </div>
|
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<div class="line"><a name="l00157"></a><span class="lineno"> 157</span> <span class="preprocessor">#endif</span></div>
|
||
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</div><!-- fragment --></div><!-- contents -->
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<li class="footer">Generated on Wed Mar 26 2014 16:23:15 for tinyusb by
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