__IOuint32_tCONSET;/*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__Iuint32_tSTAT;/*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IOuint32_tDAT;/*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IOuint32_tADR0;/*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IOuint32_tSCLH;/*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IOuint32_tSCLL;/*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__Ouint32_tCONCLR;/*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IOuint32_tMMCTRL;/*!< (@ 0x4000001C) Monitor mode control register. */
union{
__IOuint32_tADR[3];/*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
struct{
__IOuint32_tADR1;
__IOuint32_tADR2;
__IOuint32_tADR3;
};
};
__Iuint32_tDATA_BUFFER;/*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
union{
__IOuint32_tMASK[4];/*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
__IOuint32_tMOD;/*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IOuint32_tTC;/*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
__Ouint32_tFEED;/*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__Iuint32_tTV;/*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
__IOuint32_tDLL;/*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__Ouint32_tTHR;/*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__Iuint32_tRBR;/*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union{
__IOuint32_tIER;/*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IOuint32_tDLM;/*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union{
__Ouint32_tFCR;/*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__Iuint32_tIIR;/*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IOuint32_tLCR;/*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IOuint32_tMCR;/*!< (@ 0x40008010) Modem Control Register. */
__Iuint32_tLSR;/*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__Iuint32_tMSR;/*!< (@ 0x40008018) Modem Status Register. */
__IOuint32_tSCR;/*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IOuint32_tACR;/*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IOuint32_tICR;/*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IOuint32_tFDR;/*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IOuint32_tOSR;/*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IOuint32_tTER;/*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__IOuint32_tIR;/*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IOuint32_tTCR;/*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IOuint32_tTC;/*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IOuint32_tPR;/*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IOuint32_tPC;/*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IOuint32_tMCR;/*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union{
__IOuint32_tMR[4];/*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IOuint32_tMR0;/*!< (@ 0x4000C018) Match Register. MR0 */
__IOuint32_tMR1;/*!< (@ 0x4000C01C) Match Register. MR1 */
__IOuint32_tMR2;/*!< (@ 0x4000C020) Match Register. MR2 */
__IOuint32_tMR3;/*!< (@ 0x4000C024) Match Register. MR3 */
};
};
__IOuint32_tCCR;/*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__Iuint32_tCR[4];/*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
__IOuint32_tEMR;/*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
__Iuint32_tRESERVED0[12];
__IOuint32_tCTCR;/*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IOuint32_tPWMC;/*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
__IOuint32_tIR;/*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IOuint32_tTCR;/*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IOuint32_tTC;/*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IOuint32_tPR;/*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IOuint32_tPC;/*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IOuint32_tMCR;/*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union{
__IOuint32_tMR[4];/*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IOuint32_tMR0;/*!< (@ 0x40010018) Match Register. MR0 */
__IOuint32_tMR1;/*!< (@ 0x4001001C) Match Register. MR1 */
__IOuint32_tMR2;/*!< (@ 0x40010020) Match Register. MR2 */
__IOuint32_tMR3;/*!< (@ 0x40010024) Match Register. MR3 */
};
};
__IOuint32_tCCR;/*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__Iuint32_tCR[4];/*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
__IOuint32_tEMR;/*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
__Iuint32_tRESERVED0[12];
__IOuint32_tCTCR;/*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IOuint32_tPWMC;/*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
__IOuint32_tIR;/*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IOuint32_tTCR;/*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IOuint32_tTC;/*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IOuint32_tPR;/*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IOuint32_tPC;/*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IOuint32_tMCR;/*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union{
__IOuint32_tMR[4];/*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IOuint32_tMR0;/*!< (@ 0x40014018) Match Register. MR0 */
__IOuint32_tMR1;/*!< (@ 0x4001401C) Match Register. MR1 */
__IOuint32_tMR2;/*!< (@ 0x40014020) Match Register. MR2 */
__IOuint32_tMR3;/*!< (@ 0x40014024) Match Register. MR3 */
};
};
__IOuint32_tCCR;/*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__Iuint32_tCR[4];/*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
__IOuint32_tEMR;/*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__Iuint32_tRESERVED0[12];
__IOuint32_tCTCR;/*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IOuint32_tPWMC;/*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
__IOuint32_tIR;/*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IOuint32_tTCR;/*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IOuint32_tTC;/*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IOuint32_tPR;/*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IOuint32_tPC;/*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IOuint32_tMCR;/*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union{
__IOuint32_tMR[4];/*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IOuint32_tMR0;/*!< (@ 0x40018018) Match Register. MR0 */
__IOuint32_tMR1;/*!< (@ 0x4001801C) Match Register. MR1 */
__IOuint32_tMR2;/*!< (@ 0x40018020) Match Register. MR2 */
__IOuint32_tMR3;/*!< (@ 0x40018024) Match Register. MR3 */
};
};
__IOuint32_tCCR;/*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__Iuint32_tCR[4];/*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
__IOuint32_tEMR;/*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__Iuint32_tRESERVED0[12];
__IOuint32_tCTCR;/*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IOuint32_tPWMC;/*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
__IOuint32_tCR;/*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
__IOuint32_tGDR;/*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__Iuint32_tRESERVED0[1];
__IOuint32_tINTEN;/*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
union{
__Iuint32_tDR[8];/*!< (@ 0x4001C010) A/D Channel Data Register*/
struct{
__Iuint32_tDR0;/*!< (@ 0x4001C010) A/D Channel Data Register 0*/
__Iuint32_tDR1;/*!< (@ 0x4001C014) A/D Channel Data Register 1*/
__Iuint32_tDR2;/*!< (@ 0x4001C018) A/D Channel Data Register 2*/
__Iuint32_tDR3;/*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
__Iuint32_tDR4;/*!< (@ 0x4001C020) A/D Channel Data Register 4*/
__Iuint32_tDR5;/*!< (@ 0x4001C024) A/D Channel Data Register 5*/
__Iuint32_tDR6;/*!< (@ 0x4001C028) A/D Channel Data Register 6*/
__Iuint32_tDR7;/*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
};
};
__Iuint32_tSTAT;/*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
