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[STM32 FSDEV] Simplify toggle bit logic

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This commit is contained in:
Okarss 2024-06-14 18:16:09 +03:00
parent 0ac0c37078
commit 00062ddb0c
2 changed files with 8 additions and 28 deletions
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12
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
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@ -215,20 +215,20 @@ void dcd_init(uint8_t rhport)
/* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL. /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL.
* Here, the RM is followed. */ * Here, the RM is followed. */
for (uint32_t i = 0; i < 200; i++) { // should be a few us for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP"); __DSB();
} }
// Perform USB peripheral reset // Perform USB peripheral reset
USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN; USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
for (uint32_t i = 0; i < 200; i++) { // should be a few us for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP"); __DSB();
} }
USB->CNTR &= ~USB_CNTR_PDWN; USB->CNTR &= ~USB_CNTR_PDWN;
// Wait startup time, for F042 and F070, this is <= 1 us. // Wait startup time, for F042 and F070, this is <= 1 us.
for (uint32_t i = 0; i < 200; i++) { // should be a few us for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP"); __DSB();
} }
USB->CNTR = 0; // Enable USB USB->CNTR = 0; // Enable USB

24
src/portable/st/stm32_fsdev/fsdev_common.h
View File

@ -295,18 +295,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, u
TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) {
uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
regVal &= USB_EPTX_DTOGMASK; regVal &= USB_EPTX_DTOGMASK;
regVal ^= wState;
/* toggle first bit ? */
if((USB_EPTX_DTOG1 & (wState))!= 0U)
{
regVal ^= USB_EPTX_DTOG1;
}
/* toggle second bit ? */
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
{
regVal ^= USB_EPTX_DTOG2;
}
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpIdx, regVal); pcd_set_endpoint(USBx, bEpIdx, regVal);
} }
@ -322,16 +311,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx
TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) { TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) {
uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx); uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
regVal &= USB_EPRX_DTOGMASK; regVal &= USB_EPRX_DTOGMASK;
regVal ^= wState;
/* toggle first bit ? */
if((USB_EPRX_DTOG1 & wState)!= 0U) {
regVal ^= USB_EPRX_DTOG1;
}
/* toggle second bit ? */
if((USB_EPRX_DTOG2 & wState)!= 0U) {
regVal ^= USB_EPRX_DTOG2;
}
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpIdx, regVal); pcd_set_endpoint(USBx, bEpIdx, regVal);
} }