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flush fifo in dcd_edpt_close_all()

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This commit is contained in:
HiFiPhile 2024-04-10 22:21:53 +02:00
parent f1944f2b37
commit 03cfe90f3e
1 changed files with 19 additions and 14 deletions
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33
src/portable/synopsys/dwc2/dcd_dwc2.c
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@ -101,6 +101,19 @@ static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
static bool _sof_en; static bool _sof_en;
static inline void fifo_flush(uint8_t rhport)
{
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// flush all TX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
}
// Calculate the RX FIFO size according to minimum recommendations from reference manual // Calculate the RX FIFO size according to minimum recommendations from reference manual
// RxFIFO = (5 * number of control endpoints + 8) + // RxFIFO = (5 * number of control endpoints + 8) +
// ((largest USB packet used / 4) + 1 for status information) + // ((largest USB packet used / 4) + 1 for status information) +
@ -270,13 +283,7 @@ static void bus_reset(uint8_t rhport) {
dwc2->epout[n].doepctl |= DOEPCTL_SNAK; dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
} }
// flush all TX fifo and wait for it cleared fifo_flush(rhport);
dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
// 2. Set up interrupt mask // 2. Set up interrupt mask
dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
@ -584,13 +591,7 @@ void dcd_init(uint8_t rhport) {
// (non zero-length packet), send STALL back and discard. // (non zero-length packet), send STALL back and discard.
dwc2->dcfg |= DCFG_NZLSOHSK; dwc2->dcfg |= DCFG_NZLSOHSK;
// flush all TX fifo and wait for it cleared fifo_flush(rhport);
dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
// Clear all interrupts // Clear all interrupts
uint32_t int_mask = dwc2->gintsts; uint32_t int_mask = dwc2->gintsts;
@ -708,8 +709,12 @@ void dcd_edpt_close_all(uint8_t rhport) {
xfer_status[n][TUSB_DIR_IN].max_size = 0; xfer_status[n][TUSB_DIR_IN].max_size = 0;
} }
// reset allocated fifo OUT
dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
// reset allocated fifo IN // reset allocated fifo IN
_allocated_fifo_words_tx = 16; _allocated_fifo_words_tx = 16;
fifo_flush(rhport);
} }
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {