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https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
clean up, disable SOF for dcd trans since we don't use it for now
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hathach
parent
3208fe00b6
commit
04d8671641
@ -39,18 +39,19 @@
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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#define DCD_REGS_BASE { (dcd_registers_t*) USB_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn };
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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#define DCD_REGS_BASE { (dcd_registers_t*) USB_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn };
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// RT1050, RT1060 has 2 USB controllers
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#else
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#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
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#endif
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// RT1050, RT1060 has 2 USB controllers
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#else
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#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
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#endif
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#else
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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#define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
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IRQn_Type DCD_IRQn[] = { USB0_IRQn, USB1_IRQn };
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@ -218,19 +219,19 @@ typedef struct
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uint32_t : 0 ;
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// Word 1: Current qTD Pointer
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volatile uint32_t qtd_addr;
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volatile uint32_t qtd_addr;
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// Word 2-9: Transfer Overlay
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volatile dcd_qtd_t qtd_overlay;
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// Word 2-9: Transfer Overlay
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volatile dcd_qtd_t qtd_overlay;
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// Word 10-11: Setup request (control OUT only)
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volatile tusb_control_request_t setup_request;
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// Word 10-11: Setup request (control OUT only)
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volatile tusb_control_request_t setup_request;
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//--------------------------------------------------------------------+
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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} dcd_qhd_t;
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TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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@ -251,6 +252,12 @@ typedef struct {
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static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
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static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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#define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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#endif
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//--------------------------------------------------------------------+
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// CONTROLLER API
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//--------------------------------------------------------------------+
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@ -289,11 +296,11 @@ static void bus_reset(uint8_t rhport)
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
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_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
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_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
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_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
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_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0].int_on_setup = 1; // OUT only
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_dcd_data.qhd[0].int_on_setup = 1; // OUT only
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}
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void dcd_init(uint8_t rhport)
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@ -313,13 +320,11 @@ void dcd_init(uint8_t rhport)
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// TODO Force fullspeed on non-highspeed port
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// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND /*| INTR_SOF*/;
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dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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dcd_reg->USBCMD |= TU_BIT(0); // connect
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@ -423,9 +428,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// Enable EP Control
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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@ -451,17 +454,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
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// address to 32-byte boundaries.
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
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//------------- Prepare qtd -------------//
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qtd_init(p_qtd, buffer, total_bytes);
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p_qtd->int_on_complete = true;
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// start transfer
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DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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@ -502,9 +502,7 @@ void dcd_isr(uint8_t rhport)
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}
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// Make sure we read the latest version of _dcd_data.
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// TODO disconnection does not generate interrupt !!!!!!
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// if (int_status & INTR_PORT_CHANGE)
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