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Merge pull request #275 from hathach/develop
rt10xx: correct max endpoint count is 8
This commit is contained in:
Ha Thach
GitHub
commit
0d3a7257f5
@ -120,6 +120,7 @@ endif
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# Flash using jlink
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flash-jlink: $(BUILD)/$(BOARD)-firmware.hex
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@echo halt > $(BUILD)/$(BOARD).jlink
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@echo r > $(BUILD)/$(BOARD).jlink
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@echo loadfile $^ >> $(BUILD)/$(BOARD).jlink
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@echo r >> $(BUILD)/$(BOARD).jlink
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@echo go >> $(BUILD)/$(BOARD).jlink
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@ -355,7 +355,7 @@ bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32
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// nothing to do with in and notif endpoint
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return TUSB_ERROR_NONE;
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return true;
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}
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#endif
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@ -38,22 +38,15 @@
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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#define DCD_REGS_BASE { (dcd_registers_t*) USB_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn };
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// RT1050, RT1060 has 2 USB controllers
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#else
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#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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#endif
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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#include "chip.h"
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#define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
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IRQn_Type DCD_IRQn[] = { USB0_IRQn, USB1_IRQn };
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#define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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#endif
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//--------------------------------------------------------------------+
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@ -130,48 +123,48 @@ enum {
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typedef struct
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{
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//------------- ID + HW Parameter Registers-------------//
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__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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//------------- Capability Registers-------------//
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t TU_RESERVED[1];
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t TU_RESERVED[5];
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint8_t TU_RESERVED[2];
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t TU_RESERVED[6];
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//------------- Operational Registers -------------//
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__I uint32_t TU_RESERVED;
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__I uint32_t TU_RESERVED;
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__I uint32_t TU_RESERVED;
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__I uint32_t TU_RESERVED[7];
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} dcd_registers_t;
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@ -218,20 +211,20 @@ typedef struct
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uint32_t : 0 ;
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// Word 1: Current qTD Pointer
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volatile uint32_t qtd_addr;
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volatile uint32_t qtd_addr;
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// Word 2-9: Transfer Overlay
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volatile dcd_qtd_t qtd_overlay;
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// Word 2-9: Transfer Overlay
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volatile dcd_qtd_t qtd_overlay;
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// Word 10-11: Setup request (control OUT only)
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volatile tusb_control_request_t setup_request;
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// Word 10-11: Setup request (control OUT only)
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volatile tusb_control_request_t setup_request;
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//--------------------------------------------------------------------+
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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} dcd_qhd_t;
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/// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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} dcd_qhd_t;
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TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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@ -239,17 +232,48 @@ TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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// Variables
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//--------------------------------------------------------------------+
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#define QHD_MAX 12
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typedef struct
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{
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dcd_registers_t* regs; // registers
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_count; // Max bi-directional Endpoints
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}dcd_controller_t;
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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// Each endpoint with direction (IN/OUT) occupies a queue head
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// Therefore QHD_MAX is 2 x max endpoint count
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#define QHD_MAX (8*2)
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dcd_controller_t _dcd_controller[] =
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{
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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{ .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
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#else
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{ .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
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{ .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
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#endif
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};
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#else
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#define QHD_MAX (6*2)
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dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
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{ .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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};
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#endif
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#define QTD_NEXT_INVALID 0x01
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typedef struct {
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// Must be at 2K alignment
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dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
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dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
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dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd
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}dcd_data_t;
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static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
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static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
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//--------------------------------------------------------------------+
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// CONTROLLER API
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@ -258,16 +282,14 @@ static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = DCD_REGS[rhport];
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must bechanged from the control type to any other
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// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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// endpoint type of the unused direction must be changed from the control type to any other
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// type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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// USB0 has 5 but USB1 only has 3 non-control endpoints
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for( int i=1; i < (rhport ? 6 : 4); i++)
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for( int i=1; i < _dcd_controller[rhport].ep_count; i++)
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{
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dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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@ -279,9 +301,9 @@ static void bus_reset(uint8_t rhport)
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dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
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dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE;
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while (dcd_reg->ENDPTPRIME);
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while (dcd_reg->ENDPTPRIME) {}
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dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
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while (dcd_reg->ENDPTFLUSH);
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while (dcd_reg->ENDPTFLUSH) {}
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// read reset bit in portsc
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@ -289,18 +311,18 @@ static void bus_reset(uint8_t rhport)
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
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_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
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_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
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_dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
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_dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0].int_on_setup = 1; // OUT only
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_dcd_data.qhd[0].int_on_setup = 1; // OUT only
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}
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void dcd_init(uint8_t rhport)
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{
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
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dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
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// Reset controller
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dcd_reg->USBCMD |= USBCMD_RESET;
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@ -313,13 +335,11 @@ void dcd_init(uint8_t rhport)
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// TODO Force fullspeed on non-highspeed port
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// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND /*| INTR_SOF*/;
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dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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dcd_reg->USBCMD |= TU_BIT(0); // connect
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@ -327,12 +347,12 @@ void dcd_init(uint8_t rhport)
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void dcd_int_enable(uint8_t rhport)
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{
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NVIC_EnableIRQ(DCD_IRQn[rhport]);
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NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(DCD_IRQn[rhport]);
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NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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@ -340,7 +360,8 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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DCD_REGS[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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}
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void dcd_set_config(uint8_t rhport, uint8_t config_num)
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@ -390,7 +411,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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@ -399,8 +421,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// data toggle also need to be reset
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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DCD_REGS[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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@ -412,8 +435,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const ep_idx = 2*epnum + dir;
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// USB0 has 5, USB1 has 3 non-control endpoints
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TU_ASSERT( epnum <= (rhport ? 3 : 5) );
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// Must not exceed max endpoint number
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TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
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//------------- Prepare Queue Head -------------//
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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@ -423,18 +446,18 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// Enable EP Control
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
uint8_t const ep_idx = 2*epnum + dir;
|
||||
@ -443,7 +466,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
|
||||
{
|
||||
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
|
||||
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
|
||||
while(DCD_REGS[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
|
||||
while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
|
||||
}
|
||||
|
||||
dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
|
||||
@ -451,20 +474,17 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
|
||||
|
||||
// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
|
||||
// address to 32-byte boundaries.
|
||||
#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
|
||||
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
|
||||
#endif
|
||||
CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
|
||||
|
||||
//------------- Prepare qtd -------------//
|
||||
qtd_init(p_qtd, buffer, total_bytes);
|
||||
p_qtd->int_on_complete = true;
|
||||
p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
|
||||
#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
|
||||
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
||||
#endif
|
||||
|
||||
CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
||||
|
||||
// start transfer
|
||||
DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
|
||||
dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -474,7 +494,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
|
||||
//--------------------------------------------------------------------+
|
||||
void dcd_isr(uint8_t rhport)
|
||||
{
|
||||
dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
|
||||
dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
|
||||
|
||||
uint32_t const int_enable = dcd_reg->USBINTR;
|
||||
uint32_t const int_status = dcd_reg->USBSTS & int_enable;
|
||||
@ -502,9 +522,7 @@ void dcd_isr(uint8_t rhport)
|
||||
}
|
||||
|
||||
// Make sure we read the latest version of _dcd_data.
|
||||
#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
|
||||
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
||||
#endif
|
||||
CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
|
||||
|
||||
// TODO disconnection does not generate interrupt !!!!!!
|
||||
// if (int_status & INTR_PORT_CHANGE)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user