Initial Commit for MAX32 Support

Initial commit for the port of TUSB to MAX32xxx parts, staring with MAX32690
 - Added dcd_max32.c (based on dcd_musb.c) for interfacing with the peripheral
 - Added MAX32690 part family support
 - Added max32690evkit board support
 - Updated examples for unique EP number requirement
 - Updated get_deps.py to fetch the MSDK

Known Issues / Additional Testing Required
 - msc_dual_lun only shown 1 volume on Windows
 - USBTMC does not have a valid Windowsdriver
 - DFU does not have a valid Windows driver
 - WebUSB is "Device not Recognized"
 - Need to test build scripts with IAR and Clang

examples/device/cdc_msc/src/usb_descriptors.c

@@ -125,6 +125,16 @@ enum {
   #define EPNUM_MSC_OUT     0x04
   #define EPNUM_MSC_IN      0x85
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+  #define EPNUM_MSC_OUT     0x04
+  #define EPNUM_MSC_IN      0x85
+
 #else
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02

examples/device/cdc_msc_freertos/src/usb_descriptors.c

@@ -106,6 +106,16 @@ enum
   #define EPNUM_MSC_OUT     0x04
   #define EPNUM_MSC_IN      0x85
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+  #define EPNUM_MSC_OUT     0x04
+  #define EPNUM_MSC_IN      0x85
+
 #else
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02

examples/device/cdc_uac2/src/usb_descriptors.c

@@ -117,6 +117,16 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_CDC_OUT     0x04
   #define EPNUM_CDC_IN      0x85
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x04
+  #define EPNUM_CDC_IN      0x85
+
 #else
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x01

examples/device/dynamic_configuration/src/usb_descriptors.c

@@ -158,6 +158,19 @@ enum
   #define EPNUM_1_MSC_OUT     0x01
   #define EPNUM_1_MSC_IN      0x82
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_0_CDC_NOTIF   0x81
+  #define EPNUM_0_CDC_OUT     0x02
+  #define EPNUM_0_CDC_IN      0x83
+
+  #define EPNUM_0_MIDI_OUT    0x04
+  #define EPNUM_0_MIDI_IN     0x85
+
+  #define EPNUM_1_MSC_OUT     0x01
+  #define EPNUM_1_MSC_IN      0x82
+
 #else
   #define EPNUM_0_CDC_NOTIF   0x81
   #define EPNUM_0_CDC_OUT     0x02

examples/device/midi_test/src/usb_descriptors.c

@@ -90,6 +90,10 @@ enum
   // On Bridgetek FT9xx endpoint numbers must be unique...
   #define EPNUM_MIDI_OUT   0x02
   #define EPNUM_MIDI_IN   0x03
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // On MAX32 endpoint numbers must be unique...
+  #define EPNUM_MIDI_OUT   0x02
+  #define EPNUM_MIDI_IN   0x03
 #else
   #define EPNUM_MIDI_OUT   0x01
   #define EPNUM_MIDI_IN   0x01

examples/device/msc_dual_lun/src/usb_descriptors.c

@@ -97,6 +97,12 @@ enum
   #define EPNUM_MSC_OUT   0x01
   #define EPNUM_MSC_IN    0x82
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_MSC_OUT   0x01
+  #define EPNUM_MSC_IN    0x82
+
 #else
   #define EPNUM_MSC_OUT   0x01
   #define EPNUM_MSC_IN    0x81

examples/device/net_lwip_webserver/src/tusb_config.h

@@ -91,6 +91,8 @@ extern "C" {
   #define USE_ECM 1
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1)
   #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_MAX32690)
+  #define USE_ECM 1
 #else
   #define USE_ECM 0
   #define INCLUDE_IPERF

examples/device/net_lwip_webserver/src/usb_descriptors.c

@@ -120,6 +120,13 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_NET_OUT     0x02
   #define EPNUM_NET_IN      0x83
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_NET_NOTIF   0x81
+  #define EPNUM_NET_OUT     0x02
+  #define EPNUM_NET_IN      0x83
+
 #else
   #define EPNUM_NET_NOTIF   0x81
   #define EPNUM_NET_OUT     0x02

examples/device/uac2_headset/src/usb_descriptors.c

@@ -104,6 +104,13 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_AUDIO_OUT   0x02
   #define EPNUM_AUDIO_INT   0x03
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+  #define EPNUM_AUDIO_INT   0x03
+
 #else
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x01

examples/device/webusb_serial/src/usb_descriptors.c

@@ -105,6 +105,13 @@ enum
   #define EPNUM_CDC_OUT    3
   #define EPNUM_VENDOR_IN  4
   #define EPNUM_VENDOR_OUT 5
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  // MAX32 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_IN     2
+  #define EPNUM_CDC_OUT    3
+  #define EPNUM_VENDOR_IN  4
+  #define EPNUM_VENDOR_OUT 5
 #else
   #define EPNUM_CDC_IN     2
   #define EPNUM_CDC_OUT    2

hw/bsp/board_mcu.h

@@ -170,6 +170,9 @@
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   // no header needed
 
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+  #include "max32690.h"
+
 #else
   #error "Missing MCU header"
 #endif

hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h

@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif

hw/bsp/max32690/boards/max32690evkit/board.cmake

@@ -0,0 +1 @@
+# Nothing to be done at the board level

hw/bsp/max32690/boards/max32690evkit/board.h

@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              MXC_GPIO0
+#define LED_PIN               MXC_GPIO_PIN_14
+#define LED_VDDIO             MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           MXC_GPIO4
+#define BUTTON_PIN            MXC_GPIO_PIN_0
+#define BUTTON_PULL           MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM              2
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */

hw/bsp/max32690/boards/max32690evkit/board.mk

@@ -0,0 +1 @@
+# No specific build requirements for the board.

hw/bsp/max32690/family.c

@@ -0,0 +1,159 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board_api.h"
+#include "board.h"
+#include "mxc_device.h"
+#include "mcr_regs.h"
+#include "uart.h"
+#include "gpio.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+  mxc_gpio_cfg_t gpioConfig;
+
+  // LED
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_OUT;
+  gpioConfig.mask = LED_PIN;
+  gpioConfig.pad = MXC_GPIO_PAD_NONE;
+  gpioConfig.port = LED_PORT;
+  gpioConfig.vssel = LED_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+  board_led_write(false);
+
+  // Button
+  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+  gpioConfig.func = MXC_GPIO_FUNC_IN;
+  gpioConfig.mask = BUTTON_PIN;
+  gpioConfig.pad = BUTTON_PULL;
+  gpioConfig.port = BUTTON_PORT;
+  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+  MXC_GPIO_Config(&gpioConfig);
+
+  // UART
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+
+  //USB
+  MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  #if LED_STATE_ON
+    state = !state;
+  #endif
+  if(state) {
+    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+  } else {
+    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+  }
+}
+
+uint32_t board_button_read(void) {
+  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+  return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer
+  /* All other 2nd parameter is optional checkum buffer */
+   MXC_SYS_GetUSN(hw_id, NULL);
+
+  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+  memcpy(id, hw_id, act_len);
+  return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  int uart_val;
+  int act_len = 0;
+
+  while( act_len < len ) {
+    if((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+      break;
+    } else {
+      *buf++ = (uint8_t)uart_val;
+      act_len++;
+    }
+  }
+  return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+  int act_len = 0;
+  const uint8_t* ch_ptr = (const uint8_t*)buf;
+  while(act_len < len){
+    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+    act_len++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}

hw/bsp/max32690/family.cmake

@@ -0,0 +1,152 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32690)
+
+set(FAMILY_MCUS MAX32690 CACHE INTERNAL "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TARGET=MAX32690
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    MAX32690
+    FLASH_ORIGIN=0x10000000
+    FLASH_SIZE=0x340000
+    SRAM_ORIGIN=0x20000000
+    SRAM_SIZE=0x100000
+    IAR_PRAGMAS=0
+    CFG_TUSB_MCU=OPT_MCU_MAX32690
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s)
+
+  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+  add_library(${BOARD_TARGET} STATIC
+    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c
+    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c
+    ${PERIPH_SRC}/SYS/mxc_assert.c
+    ${PERIPH_SRC}/SYS/mxc_delay.c
+    ${PERIPH_SRC}/SYS/mxc_lock.c
+    ${PERIPH_SRC}/SYS/nvic_table.c
+    ${PERIPH_SRC}/SYS/pins_me18.c
+    ${PERIPH_SRC}/SYS/sys_me18.c
+    ${PERIPH_SRC}/CTB/ctb_me18.c
+    ${PERIPH_SRC}/CTB/ctb_reva.c
+    ${PERIPH_SRC}/CTB/ctb_common.c
+    ${PERIPH_SRC}/FLC/flc_common.c
+    ${PERIPH_SRC}/FLC/flc_me18.c
+    ${PERIPH_SRC}/FLC/flc_reva.c
+    ${PERIPH_SRC}/GPIO/gpio_common.c
+    ${PERIPH_SRC}/GPIO/gpio_me18.c
+    ${PERIPH_SRC}/GPIO/gpio_reva.c
+    ${PERIPH_SRC}/ICC/icc_me18.c
+    ${PERIPH_SRC}/ICC/icc_reva.c
+    ${PERIPH_SRC}/UART/uart_common.c
+    ${PERIPH_SRC}/UART/uart_me18.c
+    ${PERIPH_SRC}/UART/uart_revb.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${MAX32_CMSIS}/Include
+    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include
+    ${MAX32_PERIPH}/Include/MAX32690
+    ${PERIPH_SRC}/SYS
+    ${PERIPH_SRC}/GPIO
+    ${PERIPH_SRC}/CTB
+    ${PERIPH_SRC}/ICC
+    ${PERIPH_SRC}/FLC
+    ${PERIPH_SRC}/UART
+    )
+
+  target_compile_options(${TARGET} PRIVATE
+  -Wno-error=strict-prototypes
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/analog/max32/dcd_max32.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+  target_compile_options(${TARGET}-tinyusb PRIVATE
+  -Wno-error=strict-prototypes
+  )
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()

hw/bsp/max32690/family.mk

@@ -0,0 +1,106 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s
+LD_FILE = $(FAMILY_PATH)/max32690.ld
+
+# IAR
+SRC_S_IAR += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32690 SDK
+CFLAGS +=   -DTARGET=MAX32690 \
+			-DTARGET_REV=0x4131 \
+			-DMXC_ASSERT_ENABLE \
+			-DMAX32690 \
+			-DFLASH_ORIGIN=0x10000000 \
+			-DFLASH_SIZE=0x340000 \
+			-DSRAM_ORIGIN=0x20000000 \
+			-DSRAM_SIZE=0x100000 \
+			-DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += 	-Wno-error=unused-parameter \
+			-Wno-error=strict-prototypes \
+			-Wno-error=old-style-declaration \
+			-Wno-error=sign-compare \
+			-Wno-error=cast-qual \
+			-Wno-lto-type-mismatch
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max32690
+
+# flash target using Jlik
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk:
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max32690.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+	src/portable/analog/max32/dcd_max32.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \
+	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \
+	$(PERIPH_SRC)/SYS/mxc_assert.c \
+	$(PERIPH_SRC)/SYS/mxc_delay.c \
+	$(PERIPH_SRC)/SYS/mxc_lock.c \
+	$(PERIPH_SRC)/SYS/nvic_table.c \
+	$(PERIPH_SRC)/SYS/pins_me18.c \
+	$(PERIPH_SRC)/SYS/sys_me18.c \
+	$(PERIPH_SRC)/CTB/ctb_me18.c \
+	$(PERIPH_SRC)/CTB/ctb_reva.c \
+	$(PERIPH_SRC)/CTB/ctb_common.c \
+	$(PERIPH_SRC)/FLC/flc_common.c \
+	$(PERIPH_SRC)/FLC/flc_me18.c \
+	$(PERIPH_SRC)/FLC/flc_reva.c \
+	$(PERIPH_SRC)/GPIO/gpio_common.c \
+	$(PERIPH_SRC)/GPIO/gpio_me18.c \
+	$(PERIPH_SRC)/GPIO/gpio_reva.c \
+	$(PERIPH_SRC)/ICC/icc_me18.c \
+	$(PERIPH_SRC)/ICC/icc_reva.c \
+	$(PERIPH_SRC)/UART/uart_common.c \
+	$(PERIPH_SRC)/UART/uart_me18.c \
+	$(PERIPH_SRC)/UART/uart_revb.c \
+
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MAX32_CMSIS)/Include \
+	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \
+	$(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \
+	$(PERIPH_SRC)/SYS \
+	$(PERIPH_SRC)/GPIO \
+	$(PERIPH_SRC)/CTB \
+	$(PERIPH_SRC)/ICC \
+	$(PERIPH_SRC)/FLC \
+	$(PERIPH_SRC)/UART

hw/bsp/max32690/max32690.ld

@@ -0,0 +1,162 @@
+MEMORY {
+    ROM        (rx) : ORIGIN = 0x00000000,    LENGTH = 0x00020000 /* 128kB ROM */
+    FLASH      (rx) : ORIGIN = 0x10000000,    LENGTH = 0x00340000
+    SRAM      (rwx) : ORIGIN = 0x20000000,    LENGTH = 0x00100000
+
+	/*
+     * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1
+     * The following mappings are selected for simplicity
+     */
+    HPB_CS0 (rwx)  : ORIGIN = 0x60000000, LENGTH = 0x10000000  /* External Hyperbus/Xccelabus chip select 0 */
+    HPB_CS1 (rwx)  : ORIGIN = 0x70000000, LENGTH = 0x10000000  /* External Hyperbus/Xccelabus chip select 1 */
+}
+
+SECTIONS {
+    .rom :
+    {
+        KEEP(*(.rom_vector))
+        *(.rom_handlers*)
+    } > ROM
+
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        EXCLUDE_FILE (*riscv.o) *(.text*)    /* program code, exclude RISCV code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    /* These sections allow code to be compiled/linked for HPB addresses, but reside in
+     * flash until copied by code to the external HPB flash device
+     */
+    .hpb_cs0_section :
+    {
+	__hpb_cs0_start = ABSOLUTE(.);
+        KEEP(*(.hpb_cs0_section*))
+    } > HPB_CS0 AT>FLASH
+
+    __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section);
+    __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section);
+
+    .hpb_cs1_section :
+    {
+    	__hpb_cs1_start = ABSOLUTE(.);
+        KEEP(*(.hpb_cs1_section*))
+    } > HPB_CS1 AT>FLASH
+
+    __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section);
+    __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section);
+
+    /* Binary import */
+    .bin_storage :
+    {
+       FILL(0xFF)
+      _bin_start_ = .;
+      KEEP(*(.bin_storage_img))
+      _bin_end_ = .;
+      . = ALIGN(4);
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(vtable)
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        /* Run the flash programming functions from SRAM */
+        *(.flashprog)
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}

src/common/tusb_mcu.h

@@ -452,6 +452,14 @@
   #define TUP_RHPORT_HIGHSPEED    CFG_TUD_WCH_USBIP_USBHS
   #define TUP_DCD_ENDPOINT_MAX    (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
 
+//--------------------------------------------------------------------+
+// Analog Devices
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_MAX32690)
+  #define TUP_DCD_ENDPOINT_MAX    12
+  #define TUP_RHPORT_HIGHSPEED    1
+
+
 #endif
 
 //--------------------------------------------------------------------+

src/portable/analog/max32/dcd_max32.c

@@ -0,0 +1,841 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji KITAYAMA
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690)
+
+#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
+/* GCC warns that an address may be unaligned, even though
+ * the target CPU has the capability for unaligned memory access. */
+_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
+#endif
+
+#include "device/dcd.h"
+
+#include "mxc_delay.h"
+#include "mxc_device.h"
+#include "mxc_sys.h"
+#include "nvic_table.h"
+#include "usbhs_regs.h"
+
+#define USBHS_M31_CLOCK_RECOVERY
+
+/*------------------------------------------------------------------
+ * MACRO TYPEDEF CONSTANT ENUM DECLARATION
+ *------------------------------------------------------------------*/
+#define REQUEST_TYPE_INVALID  (0xFFu)
+
+
+typedef union {
+  uint8_t   u8;
+  uint16_t  u16;
+  uint32_t  u32;
+} hw_fifo_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+} pipe_state_t;
+
+typedef struct
+{
+  tusb_control_request_t setup_packet;
+  uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
+  int8_t       status_out;
+  pipe_state_t pipe0;
+  pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1];   /* pipe[direction][endpoint number - 1] */
+  uint16_t     pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */
+} dcd_data_t;
+
+/*------------------------------------------------------------------
+ * INTERNAL OBJECT & FUNCTION DECLARATION
+ *------------------------------------------------------------------*/
+static dcd_data_t _dcd;
+
+
+static volatile void* edpt_get_fifo_ptr(unsigned epnum)
+{
+    volatile uint32_t *ptr;
+
+    ptr = &MXC_USBHS->fifo0;
+    ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */
+
+    return (volatile void *)ptr;
+}
+
+static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 4) {
+    reg->u32 = *(uint32_t const *)addr;
+    addr += 4;
+    len  -= 4;
+  }
+  if (len >= 2) {
+    reg->u16 = *(uint16_t const *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(uint8_t const *)addr;
+  }
+}
+
+static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 4) {
+    *(uint32_t *)addr = reg->u32;
+    addr += 4;
+    len  -= 4;
+  }
+  if (len >= 2) {
+    *(uint16_t *)addr = reg->u16;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    *(uint8_t *)addr = reg->u8;
+  }
+}
+
+static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
+{
+  static const struct {
+    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
+    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
+    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
+  } ops[] = {
+    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
+    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
+  };
+  tu_fifo_buffer_info_t info;
+  ops[dir].tu_fifo_get_info(f, &info);
+  unsigned total_len = len;
+  len = TU_MIN(total_len, info.len_lin);
+  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+  unsigned rem = total_len - len;
+  if (rem) {
+    len = TU_MIN(rem, info.len_wrap);
+    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
+    rem -= len;
+  }
+  ops[dir].tu_fifo_advance(f, total_len - rem);
+}
+
+static void process_setup_packet(uint8_t rhport)
+{
+  uint32_t *p = (void*)&_dcd.setup_packet;
+  p[0]        = MXC_USBHS->fifo0;
+  p[1]        = MXC_USBHS->fifo0;
+
+  _dcd.pipe0.buf       = NULL;
+  _dcd.pipe0.length    = 0;
+  _dcd.pipe0.remaining = 0;
+  dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true);
+
+  const unsigned len    = _dcd.setup_packet.wLength;
+  _dcd.remaining_ctrl   = len;
+  const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType);
+  /* Clear RX FIFO and reverse the transaction direction */
+  if (len && dir_in) {
+    MXC_USBHS->index = 0;
+    MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY;
+  }
+}
+
+static bool handle_xfer_in(uint_fast8_t ep_addr)
+{
+  unsigned epnum = tu_edpt_number(ep_addr);
+  unsigned epnum_minus1 = epnum - 1;
+  pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
+  const unsigned rem  = pipe->remaining;
+
+  //This function should not be for ep0
+  TU_ASSERT(epnum);
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  MXC_USBHS->index = epnum;
+  const unsigned mps = MXC_USBHS->inmaxp;
+  const unsigned len = TU_MIN(mps, rem);
+  void          *buf = pipe->buf;
+  volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum);
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
+  if (len) {
+    if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
+      pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN);
+    } else {
+      pipe_write_packet(buf,fifo_ptr, len);
+      pipe->buf       = buf + len;
+    }
+    pipe->remaining = rem - len;
+  }
+  MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY; //TODO: Verify a | isnt needed
+
+  return false;
+}
+
+static bool handle_xfer_out(uint_fast8_t ep_addr)
+{
+  unsigned epnum = tu_edpt_number(ep_addr);
+  unsigned epnum_minus1 = epnum - 1;
+  pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
+
+  //This function should not be for ep0
+  TU_ASSERT(epnum);
+
+  MXC_USBHS->index = epnum;
+
+  TU_ASSERT(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY);
+
+  const unsigned mps = MXC_USBHS->outmaxp;
+  const unsigned rem = pipe->remaining;
+  const unsigned vld = MXC_USBHS->outcount;
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum);
+  if (len) {
+    if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
+      pipe_read_write_packet_ff(buf,fifo_ptr, len, TUSB_DIR_OUT);
+    } else {
+      pipe_read_packet(buf, fifo_ptr, len);
+      pipe->buf       = buf + len;
+    }
+    pipe->remaining = rem - len;
+  }
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit */ //TODO: Verify just setting to 0 is ok
+  return false;
+}
+
+static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+
+  unsigned epnum        = tu_edpt_number(ep_addr);
+  unsigned epnum_minus1 = epnum - 1;
+  unsigned dir_in       = tu_edpt_dir(ep_addr);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1];
+  pipe->buf          = buffer;
+  pipe->length       = total_bytes;
+  pipe->remaining    = total_bytes;
+
+  if (dir_in) {
+    handle_xfer_in(ep_addr);
+  } else {
+    MXC_USBHS->index = epnum;
+    if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY){
+      MXC_USBHS->outcsrl = 0; //TODO: Verify just setting to 0 is ok
+    }
+  }
+  return true;
+}
+
+static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */
+
+  const unsigned req = _dcd.setup_packet.bmRequestType;
+  TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0);
+
+  if (req == REQUEST_TYPE_INVALID || _dcd.status_out) {
+    /* STATUS OUT stage.
+     * MUSB controller automatically handles STATUS OUT packets without
+     * software helps. We do not have to do anything. And STATUS stage
+     * may have already finished and received the next setup packet
+     * without calling this function, so we have no choice but to
+     * invoke the callback function of status packet here. */
+    _dcd.status_out = 0;
+    if (req == REQUEST_TYPE_INVALID) {
+      dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
+    } else {
+      /* The next setup packet has already been received, it aborts
+       * invoking callback function to avoid confusing TUSB stack. */
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
+    }
+    return true;
+  }
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  MXC_USBHS->index = 0;
+  if (tu_edpt_dir(req) == dir_in) { /* DATA stage */
+    TU_ASSERT(total_bytes <= _dcd.remaining_ctrl);
+    const unsigned rem = _dcd.remaining_ctrl;
+    const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes);
+    volatile void* fifo_ptr = edpt_get_fifo_ptr(0);
+    if (dir_in) {
+      pipe_write_packet(buffer, fifo_ptr, len);
+
+      _dcd.pipe0.buf       = buffer + len;
+      _dcd.pipe0.length    = len;
+      _dcd.pipe0.remaining = 0;
+
+      _dcd.remaining_ctrl  = rem - len;
+      if ((len < 64) || (rem == len)) {
+        _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
+        _dcd.status_out = 1;
+        /* Flush TX FIFO and reverse the transaction direction. */
+        MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY | MXC_F_USBHS_CSR0_DATA_END;
+      } else {
+        MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */
+      }
+    } else {
+      _dcd.pipe0.buf       = buffer;
+      _dcd.pipe0.length    = len;
+      _dcd.pipe0.remaining = len;
+      MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */
+    }
+  } else if (dir_in) {
+    _dcd.pipe0.buf = NULL;
+    _dcd.pipe0.length    = 0;
+    _dcd.pipe0.remaining = 0;
+    /* Clear RX FIFO and reverse the transaction direction */
+    MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END;
+  }
+  return true;
+}
+
+static void process_ep0(uint8_t rhport)
+{
+  MXC_USBHS->index = 0;
+  uint_fast8_t csrl = MXC_USBHS->csr0;
+
+  if (csrl & MXC_F_USBHS_CSR0_SENT_STALL) {
+    /* Returned STALL packet to HOST. */
+    MXC_USBHS->csr0 = 0; /* Clear STALL */
+    return;
+  }
+
+  unsigned req = _dcd.setup_packet.bmRequestType;
+  if (csrl & MXC_F_USBHS_CSR0_SETUP_END) {
+    TU_LOG1("   ABORT by the next packets\r\n");
+    MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_SETUP_END;
+    if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
+      /* DATA stage was aborted by receiving STATUS or SETUP packet. */
+      _dcd.pipe0.buf = NULL;
+      _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+      dcd_event_xfer_complete(rhport,
+                              req & TUSB_DIR_IN_MASK,
+                              _dcd.pipe0.length - _dcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    req = REQUEST_TYPE_INVALID;
+    if (!(csrl & MXC_F_USBHS_CSR0_OUTPKTRDY)) return; /* Received SETUP packet */
+  }
+
+  if (csrl & MXC_F_USBHS_CSR0_OUTPKTRDY) {
+    /* Received SETUP or DATA OUT packet */
+    if (req == REQUEST_TYPE_INVALID) {
+      /* SETUP */
+      TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0,);
+      process_setup_packet(rhport);
+      return;
+    }
+    if (_dcd.pipe0.buf) {
+      /* DATA OUT */
+      const unsigned vld = MXC_USBHS->count0;
+      const unsigned rem = _dcd.pipe0.remaining;
+      const unsigned len = TU_MIN(TU_MIN(rem, 64), vld);
+      volatile void* fifo_ptr = edpt_get_fifo_ptr(0);
+      pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len);
+
+      _dcd.pipe0.remaining = rem - len;
+      _dcd.remaining_ctrl -= len;
+
+      _dcd.pipe0.buf = NULL;
+      dcd_event_xfer_complete(rhport,
+                              tu_edpt_addr(0, TUSB_DIR_OUT),
+                              _dcd.pipe0.length - _dcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    return;
+  }
+
+  /* When CSRL0 is zero, it means that completion of sending a any length packet
+   * or receiving a zero length packet. */
+  if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) {
+    /* STATUS IN */
+    if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) {
+      /* The address must be changed on completion of the control transfer. */
+      MXC_USBHS->faddr = (uint8_t)_dcd.setup_packet.wValue;
+    }
+    _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+    dcd_event_xfer_complete(rhport,
+                            tu_edpt_addr(0, TUSB_DIR_IN),
+                            _dcd.pipe0.length - _dcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+    return;
+  }
+  if (_dcd.pipe0.buf) {
+    /* DATA IN */
+    _dcd.pipe0.buf = NULL;
+    dcd_event_xfer_complete(rhport,
+                            tu_edpt_addr(0, TUSB_DIR_IN),
+                            _dcd.pipe0.length - _dcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
+{
+  bool completed;
+  const unsigned dir_in     = tu_edpt_dir(ep_addr);
+  const unsigned epnum      = tu_edpt_number(ep_addr);
+
+  MXC_USBHS->index = epnum;
+
+  if (dir_in) {
+    if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_SENTSTALL) {
+      MXC_USBHS->incsrl &= ~(MXC_F_USBHS_INCSRL_SENTSTALL | MXC_F_USBHS_INCSRL_UNDERRUN);
+      return;
+    }
+    completed = handle_xfer_in(ep_addr);
+  } else {
+    if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_SENTSTALL) {
+      MXC_USBHS->outcsrl &= ~(MXC_F_USBHS_OUTCSRL_SENTSTALL | MXC_F_USBHS_OUTCSRL_OVERRUN);
+      return;
+    }
+    completed = handle_xfer_out(ep_addr);
+  }
+
+  if (completed) {
+    pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1];
+    dcd_event_xfer_complete(rhport, ep_addr,
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  (void)rhport;
+  TU_LOG0("------Bus Reset\r\n");
+  /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF),
+   * a control transfer state is SETUP or STATUS stage. */
+  _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+  _dcd.status_out = 0;
+  /* When pipe0.buf has not NULL, DATA stage works in progress. */
+  _dcd.pipe0.buf = NULL;
+
+  MXC_USBHS->intrinen = 1; /* Enable only EP0 */
+  MXC_USBHS->introuten = 0;
+
+
+  /* Clear FIFO settings */
+  for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
+    MXC_USBHS->index = i;
+    if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) {
+          /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */
+          MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO;
+      }
+
+      if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) {
+          /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */
+          MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO;
+      }
+  }
+  dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true);
+}
+
+/*------------------------------------------------------------------
+ * Device API
+ *------------------------------------------------------------------*/
+
+void dcd_init(uint8_t rhport)
+{
+  (void)rhport;
+  MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN;
+
+  //Interrupt for VBUS disconnect
+  MXC_USBHS->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS;
+
+  NVIC_ClearPendingIRQ(USB_IRQn);
+  dcd_edpt_close_all(rhport);
+
+  //Unsuspend the MAC
+  MXC_USBHS->mxm_suspend = 0;
+
+  /* Configure PHY */
+  MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11);
+  MXC_USBHS->m31_phy_xcfgi_63_32 = 0;
+  MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72-64);
+  MXC_USBHS->m31_phy_xcfgi_127_96 = 0;
+
+
+#ifdef USBHS_M31_CLOCK_RECOVERY
+  MXC_USBHS->m31_phy_noncry_rstb = 1;
+  MXC_USBHS->m31_phy_noncry_en = 1;
+  MXC_USBHS->m31_phy_outclksel = 0;
+  MXC_USBHS->m31_phy_coreclkin = 0;
+  MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */
+#else
+  /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */
+  /* As it depends on the system core clock, this should probably be done at the SYS level */
+  MXC_USBHS->m31_phy_noncry_rstb = 0;
+  MXC_USBHS->m31_phy_noncry_en = 0;
+  MXC_USBHS->m31_phy_outclksel = 1;
+  MXC_USBHS->m31_phy_coreclkin = 1;
+  MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */
+#endif
+  MXC_USBHS->m31_phy_pll_en = 1;
+  MXC_USBHS->m31_phy_oscouten = 1;
+
+  /* Reset PHY */
+  MXC_USBHS->m31_phy_ponrst = 0;
+  MXC_USBHS->m31_phy_ponrst = 1;
+
+  dcd_connect(rhport);
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_DisableIRQ(USB_IRQn);
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  (void)dev_addr;
+  _dcd.pipe0.buf       = NULL;
+  _dcd.pipe0.length    = 0;
+  _dcd.pipe0.remaining = 0;
+  /* Clear RX FIFO to return ACK. */
+  MXC_USBHS->index = 0;
+  MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END;
+}
+
+// Wake up host
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void)rhport;
+  MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME;
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_task_delay(10);
+#else
+  MXC_Delay(MXC_DELAY_MSEC(10));
+#endif
+
+  MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME;
+}
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+  (void)rhport;
+  MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0;
+  MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN;
+}
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+  (void)rhport;
+  MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned dir_in  = tu_edpt_dir(ep_addr);
+  const unsigned xfer    = ep_desc->bmAttributes.xfer;
+  const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
+  TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
+  pipe->buf       = NULL;
+  pipe->length    = 0;
+  pipe->remaining = 0;
+
+  MXC_USBHS->index = epn;
+
+  if (dir_in) {
+    MXC_USBHS->inmaxp = mps;
+    MXC_USBHS->incsru = (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_INCSRU_ISO : 0);
+    if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG;
+    }
+    MXC_USBHS->intrinen |= TU_BIT(epn);
+  } else {
+    MXC_USBHS->outmaxp = mps;
+    MXC_USBHS->outcsru = (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_OUTCSRU_ISO : 0);
+    if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG;
+    }
+    MXC_USBHS->introuten |= TU_BIT(epn);
+  }
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  (void) rhport;
+
+  MXC_SYS_Crit_Enter();
+  MXC_USBHS->intrinen = 1; /* Enable only EP0 */
+  MXC_USBHS->introuten = 0;
+
+  for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
+    MXC_USBHS->index = i;
+    MXC_USBHS->inmaxp = 0;
+    MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS;
+
+    if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG;
+    }
+
+    MXC_USBHS->outmaxp = 0;
+    MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS;
+
+    if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG;
+    }
+  }
+  MXC_SYS_Crit_Exit();
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn    = tu_edpt_number(ep_addr);
+  unsigned const dir_in = tu_edpt_dir(ep_addr);
+
+  MXC_SYS_Crit_Enter();
+  MXC_USBHS->index = epn;
+  if (dir_in) {
+    MXC_USBHS->intrinen &= ~TU_BIT(epn);
+    MXC_USBHS->inmaxp = 0;
+    MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS;
+    if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG;
+    }
+  } else {
+    MXC_USBHS->introuten  &= ~TU_BIT(epn);
+    MXC_USBHS->outmaxp = 0;
+    MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS;
+    if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG;
+    }
+  }
+  MXC_SYS_Crit_Exit();
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  bool ret;
+  unsigned const epnum = tu_edpt_number(ep_addr);
+  MXC_SYS_Crit_Enter();
+  if (epnum) {
+    _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1);
+    ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
+  } else
+    ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
+  MXC_SYS_Crit_Exit();
+  return ret;
+}
+
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  (void)rhport;
+  bool ret;
+  unsigned const epnum = tu_edpt_number(ep_addr);
+  TU_ASSERT(epnum);
+  MXC_SYS_Crit_Enter();
+  _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1);
+  ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes);
+  MXC_SYS_Crit_Exit();
+  return ret;
+}
+
+// Stall endpoint
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  MXC_SYS_Crit_Enter();
+  MXC_USBHS->index = epn;
+  if (0 == epn) {
+    if (!ep_addr) { /* Ignore EP80 */
+      _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+      _dcd.pipe0.buf = NULL;
+      MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SEND_STALL;
+    }
+  } else {
+    if (tu_edpt_dir(ep_addr)) { /* IN */
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL;
+    } else { /* OUT */
+      TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY),);
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL;
+    }
+  }
+  MXC_SYS_Crit_Exit();
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  MXC_SYS_Crit_Enter();
+  MXC_USBHS->index = epn;
+  if (tu_edpt_dir(ep_addr)) { /* IN */
+    /* IN endpoint */
+    if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) {
+      /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG;
+    }
+  } else { /* OUT */
+    /* Otherwise, must be OUT endpoint */
+    if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) {
+      /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO;
+    } else {
+      MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG;
+    }
+  }
+  MXC_SYS_Crit_Exit();
+}
+
+/*-------------------------------------------------------------------
+ * ISR
+ *-------------------------------------------------------------------*/
+void dcd_int_handler(uint8_t rhport)
+{
+  uint_fast8_t is, txis, rxis;
+  uint32_t mxm_int, mxm_int_en, mxm_is;
+  uint32_t saved_index;
+
+  /* Save current index register */
+  saved_index = MXC_USBHS->index;
+
+  is   = MXC_USBHS->intrusb; /* read and clear interrupt status */
+  txis = MXC_USBHS->intrin;  /* read and clear interrupt status */
+  rxis = MXC_USBHS->introut; /* read and clear interrupt status */
+
+  /* These USB interrupt flags are W1C. */
+  /* Order of volatile accesses must be separated for IAR */
+  mxm_int = MXC_USBHS->mxm_int;
+  mxm_int_en = MXC_USBHS->mxm_int_en;
+  mxm_is = mxm_int & mxm_int_en;
+  MXC_USBHS->mxm_int = mxm_is;
+
+  is &= MXC_USBHS->intrusben; /* Clear disabled interrupts */
+
+  if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+  }
+  if (is & MXC_F_USBHS_INTRUSB_SOF_INT) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+  if (is & MXC_F_USBHS_INTRUSB_RESET_INT) {
+    process_bus_reset(rhport);
+  }
+  if (is & MXC_F_USBHS_INTRUSB_RESUME_INT) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  }
+  if (is & MXC_F_USBHS_INTRUSB_SUSPEND_INT) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+  }
+
+  txis &= MXC_USBHS->intrinen; /* Clear disabled interrupts */
+  if (txis & MXC_F_USBHS_INTRIN_EP0_IN_INT) {
+    process_ep0(rhport);
+    txis &= ~TU_BIT(0);
+  }
+  while (txis) {
+    unsigned const num = __builtin_ctz(txis);
+    process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN));
+    txis &= ~TU_BIT(num);
+  }
+  rxis &= MXC_USBHS->introuten; /* Clear disabled interrupts */
+  while (rxis) {
+    unsigned const num = __builtin_ctz(rxis);
+    process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT));
+    rxis &= ~TU_BIT(num);
+  }
+
+  /* Restore register index before exiting ISR */
+  MXC_USBHS->index = saved_index;
+}
+
+#endif

src/tusb_option.h

@@ -188,6 +188,9 @@
 #define OPT_MCU_MCXN9            2300  ///< NXP MCX N9 Series
 #define OPT_MCU_MCXA15           2301  ///< NXP MCX A15 Series
 
+// Analog Devices
+#define OPT_MCU_MAX32690         2400  ///< ADI MAX32690
+
 // Check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)    (CFG_TUSB_MCU == _m)

tools/get_deps.py

@@ -24,6 +24,9 @@ deps_optional = {
     'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git',
                          '8e5e89e8e132c0fd90e72d5422e5d3d68232b756',
                          'fc100s'],
+    'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git',
+                             'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75',
+                             'max32690'],
     'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git',
                                          '91060164afe239fcb394122e8bf9eb24d3194eb1',
                                          'brtmm90x'],