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https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
simplify tusb_dcd_edpt_xfer API
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0cb1604686
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16aa3eb437
@ -412,7 +412,7 @@ bool tusb_dcd_edpt_open (uint8_t port, tusb_descriptor_endpoint_t const * desc_e
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return true;
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}
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bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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(void) port;
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@ -365,11 +365,11 @@ bool tusb_dcd_edpt_queue_xfer(uint8_t port, uint8_t ep_addr, uint8_t * buffer, u
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return pipe_add_xfer(port, ep_idx, buffer, total_bytes, false);
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}
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bool tusb_dcd_edpt_xfer(uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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bool tusb_dcd_edpt_xfer(uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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VERIFY ( pipe_add_xfer(port, ep_idx, buffer, total_bytes, int_on_complete) );
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VERIFY ( pipe_add_xfer(port, ep_idx, buffer, total_bytes, true) );
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dcd_qhd_t* p_qhd = &dcd_data_ptr[port]->qhd[ ep_idx ];
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dcd_qtd_t* p_qtd = &dcd_data_ptr[port]->qtd[ p_qhd->list_qtd_idx[0] ];
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@ -199,7 +199,7 @@ tusb_error_t cdcd_open(uint8_t port, tusb_descriptor_interface_t const * p_inter
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p_cdc->interface_number = p_interface_desc->bInterfaceNumber;
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// Prepare for incoming data
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf), true), TUSB_ERROR_DCD_EDPT_XFER);
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
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return TUSB_ERROR_NONE;
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@ -277,7 +277,7 @@ tusb_error_t cdcd_xfer_cb(uint8_t port, uint8_t ep_addr, tusb_event_t event, uin
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fifo_write_n(&_rx_ff, _tmp_rx_buf, xferred_bytes);
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// preparing for next
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TU_ASSERT(tusb_dcd_edpt_xfer(port, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf), true), TUSB_ERROR_DCD_EDPT_XFER);
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TU_ASSERT(tusb_dcd_edpt_xfer(port, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
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// fire callback
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tud_cdc_rx_cb(port);
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@ -294,9 +294,8 @@ bool tud_n_cdc_flush (uint8_t port)
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VERIFY( !tusb_dcd_edpt_busy(port, edpt) );
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uint16_t count = fifo_read_n(&_tx_ff, _tmp_tx_buf, sizeof(_tmp_tx_buf));
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TU_ASSERT( tusb_dcd_edpt_xfer(port, edpt, _tmp_tx_buf, count, false) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, edpt, _tmp_tx_buf, count) );
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return true;
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}
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@ -119,7 +119,7 @@ tusb_error_t tud_hid_keyboard_send(uint8_t port, hid_keyboard_report_t const *p_
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hidd_interface_t * p_kbd = &keyboardd_data; // TODO &keyboardd_data[port];
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_kbd->edpt_addr, (void*) p_report, sizeof(hid_keyboard_report_t), true), TUSB_ERROR_DCD_EDPT_XFER ) ;
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_kbd->edpt_addr, (void*) p_report, sizeof(hid_keyboard_report_t)), TUSB_ERROR_DCD_EDPT_XFER ) ;
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return TUSB_ERROR_NONE;
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}
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@ -142,7 +142,7 @@ tusb_error_t tud_hid_mouse_send(uint8_t port, hid_mouse_report_t const *p_report
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hidd_interface_t * p_mouse = &moused_data; // TODO &keyboardd_data[port];
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_mouse->edpt_addr, (void*) p_report, sizeof(hid_mouse_report_t), true), TUSB_ERROR_DCD_EDPT_XFER ) ;
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_mouse->edpt_addr, (void*) p_report, sizeof(hid_mouse_report_t)), TUSB_ERROR_DCD_EDPT_XFER ) ;
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return TUSB_ERROR_NONE;
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}
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@ -126,7 +126,7 @@ tusb_error_t mscd_open(uint8_t port, tusb_descriptor_interface_t const * p_inter
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(*p_length) += sizeof(tusb_descriptor_interface_t) + 2*sizeof(tusb_descriptor_endpoint_t);
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//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t), true), TUSB_ERROR_DCD_EDPT_XFER );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_DCD_EDPT_XFER );
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return TUSB_ERROR_NONE;
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}
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@ -251,10 +251,10 @@ tusb_error_t mscd_xfer_cb(uint8_t port, uint8_t ep_addr, tusb_event_t event, uin
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// Move to default CMD stage after sending status
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p_msc->stage = MSC_STAGE_CMD;
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t), true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
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//------------- Queue the next CBW -------------//
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t), true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
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}
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return TUSB_ERROR_NONE;
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@ -300,7 +300,7 @@ static bool read10_write10_data_xfer(uint8_t port, mscd_interface_t* p_msc)
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return true;
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} else if (xfer_block < block_count)
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{
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TU_ASSERT( tusb_dcd_edpt_xfer(port, ep_addr, p_buffer, xfer_byte, true), TUSB_ERROR_DCD_EDPT_XFER );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, ep_addr, p_buffer, xfer_byte), TUSB_ERROR_DCD_EDPT_XFER );
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// adjust lba, block_count, xfer_bytes for the next call
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p_readwrite->lba = __n2be(lba+xfer_block);
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@ -89,7 +89,7 @@ bool tusb_dcd_control_xfer (uint8_t port, tusb_dir_t dir, uint8_t * buffer,
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//------------- Other Endpoints -------------//
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bool tusb_dcd_edpt_open (uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc);
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bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete);
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bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
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bool tusb_dcd_edpt_queue_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes); // only queue, not transferring yet
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bool tusb_dcd_edpt_busy (uint8_t port, uint8_t ep_addr);
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