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https://github.com/hathach/tinyusb.git
synced 2025-01-31 05:52:55 +08:00
add dcd_edpt_close and iso xfer.
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864d8381a7
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@ -239,8 +239,9 @@ void dcd_init(uint8_t rhport)
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dcd_reg->USBMODE = USBMODE_CM_DEVICE;
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dcd_reg->USBMODE = USBMODE_CM_DEVICE;
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dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
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dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
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// TODO Force fullspeed on non-highspeed port
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#if !TUD_OPT_HIGH_SPEED
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// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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#endif
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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@ -373,9 +374,6 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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{
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{
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// TODO not support ISO yet
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TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
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uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const ep_idx = 2*epnum + dir;
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uint8_t const ep_idx = 2*epnum + dir;
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@ -387,14 +385,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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p_qhd->zero_length_termination = 1;
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
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{
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p_qhd->iso_mult = 1;
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} else
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{
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p_qhd->zero_length_termination = 1;
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}
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// Enable EP Control
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// Enable EP Control
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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// Clear EP type
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dcd_reg->ENDPTCTRL[epnum] &=~(0x03 << (dir ? 18 : 2));
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dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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return true;
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@ -406,6 +415,22 @@ void dcd_edpt_close_all (uint8_t rhport)
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// TODO implement dcd_edpt_close_all()
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// TODO implement dcd_edpt_close_all()
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}
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}
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void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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// Flush EP
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uint32_t flush_mask = TU_BIT(epnum) << (dir ? 16 : 0);
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dcd_reg->ENDPTFLUSH = flush_mask;
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while(dcd_reg->ENDPTFLUSH & flush_mask);
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// Clear EP enable
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dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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@ -461,11 +486,10 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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tu_fifo_buffer_info_t fifo_info;
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tu_fifo_buffer_info_t fifo_info;
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if(dir == TUSB_DIR_IN)
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if (dir)
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{
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{
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tu_fifo_get_read_info(ff, &fifo_info);
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tu_fifo_get_read_info(ff, &fifo_info);
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}
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} else
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else
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{
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{
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tu_fifo_get_write_info(ff, &fifo_info);
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tu_fifo_get_write_info(ff, &fifo_info);
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}
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}
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@ -475,10 +499,9 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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// Limit transfer length to total_bytes
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// Limit transfer length to total_bytes
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fifo_info.len_wrap = 0;
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fifo_info.len_wrap = 0;
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fifo_info.len_lin = total_bytes;
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fifo_info.len_lin = total_bytes;
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}
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} else
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else
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{
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{
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// Class driver ensure at least total_bytes elements in fifo
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// Class driver need to ensure at least total_bytes elements in fifo
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fifo_info.len_wrap = total_bytes - fifo_info.len_lin;
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fifo_info.len_wrap = total_bytes - fifo_info.len_lin;
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}
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}
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// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
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// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
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@ -486,8 +509,9 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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// void* cast to suppress cast-align warning, buffer must be
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// void* cast to suppress cast-align warning, buffer must be
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CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31);
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CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31);
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if (fifo_info.len_wrap > 0)
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if (fifo_info.len_wrap > 0)
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{
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CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
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CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
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}
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//------------- Prepare qtd -------------//
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//------------- Prepare qtd -------------//
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qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
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qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
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p_qtd->int_on_complete = true;
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p_qtd->int_on_complete = true;
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@ -581,11 +605,10 @@ void dcd_int_handler(uint8_t rhport)
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if (p_qhd->ff)
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if (p_qhd->ff)
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{
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{
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if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN)
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if (tu_edpt_dir(ep_addr))
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{
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{
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tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
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tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
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}
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} else
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else
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{
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{
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tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
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tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
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}
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}
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