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Merge pull request #165 from pigrew/fsdev_smallPacket
Fsdev small packet
This commit is contained in:
hathach
GitHub
commit
199a628c79
4
.gitignore
vendored
4
.gitignore
vendored
@ -15,3 +15,7 @@ latex
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test_old/
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tests_obsolete/
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_build
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# coverity intermediate files
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cov-int
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# cppcheck build directories
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*-build-dir
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@ -147,31 +147,33 @@
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* Checks, structs, defines, function definitions, etc.
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*/
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TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT,"Only 8 endpoints supported on the hardware");
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TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
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TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH),
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"BTABLE does not fit in PMA RAM");
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TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
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// Max size of a USB FS packet is 64...
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#define MAX_PACKET_SIZE 64
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// One of these for every EP IN & OUT, uses a bit of RAM....
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typedef struct
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{
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uint8_t * buffer;
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uint16_t total_len;
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uint16_t queued_len;
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uint16_t max_packet_size;
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} xfer_ctl_t;
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static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
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#define XFER_CTL_BASE(_epnum, _dir) &xfer_status[_epnum][_dir]
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static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
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static xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
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{
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return &xfer_status[epnum][dir];
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}
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t newDADDR; // Used to set the new device address during the CTR IRQ handler
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static uint8_t remoteWakeCountdown; // When wake is requested
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// EP Buffers assigned from end of memory location, to minimize their chance of crashing
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// into the stack.
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@ -224,7 +226,7 @@ void dcd_init (uint8_t rhport)
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for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
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{
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// This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
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PCD_GET_ENDPOINT(USB,i) = 0u;
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pcd_set_endpoint(USB,i,0u);
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}
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// Initialize the BTABLE for EP0 at this point (though setting up the EP0R is unneeded)
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@ -233,7 +235,7 @@ void dcd_init (uint8_t rhport)
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{
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pma[PMA_STRIDE*(DCD_STM32_BTABLE_BASE + i)] = 0u;
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}
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USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
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USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
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dcd_handle_bus_reset();
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// And finally enable pull-up, which may trigger the RESET IRQ if the host is connected.
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@ -251,12 +253,8 @@ void dcd_int_enable (uint8_t rhport)
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{
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(void)rhport;
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#if defined(STM32F0)
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NVIC_SetPriority(USB_IRQn, 0);
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NVIC_EnableIRQ(USB_IRQn);
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#elif defined(STM32F3)
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NVIC_SetPriority(USB_HP_CAN_TX_IRQn, 0);
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NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0);
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NVIC_SetPriority(USBWakeUp_IRQn, 0);
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NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
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NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
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NVIC_EnableIRQ(USBWakeUp_IRQn);
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@ -276,6 +274,10 @@ void dcd_int_disable(uint8_t rhport)
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#else
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#error Unknown arch in USB driver
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#endif
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// I'm not convinced that memory synchronization is completely necessary, but
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// it isn't a bad idea.
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__DSB();
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__ISB();
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}
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// Receive Set Address request, mcu port must also include status IN response
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@ -302,6 +304,9 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num)
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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USB->CNTR |= (uint16_t)USB_CNTR_RESUME;
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remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
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}
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// I'm getting a weird warning about missing braces here that I don't
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@ -334,7 +339,7 @@ static void dcd_handle_bus_reset(void)
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// Clear all EPREG (or maybe this is automatic? I'm not sure)
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for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
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{
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PCD_GET_ENDPOINT(USB,i) = 0u;
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pcd_set_endpoint(USB,i,0u);
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}
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ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
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@ -342,13 +347,13 @@ static void dcd_handle_bus_reset(void)
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dcd_edpt_open (0, &ep0IN_desc);
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newDADDR = 0u;
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USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
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PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID); // And start accepting SETUP on EP0
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pcd_set_ep_rx_status(USB, 0, USB_EP_RX_VALID); // And start accepting SETUP on EP0
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}
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// FIXME: Defined to return uint16 so that ASSERT can be used, even though a return value is not needed.
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static uint16_t dcd_ep_ctr_handler(void)
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{
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uint16_t count=0U;
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uint32_t count=0U;
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uint8_t EPindex;
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__IO uint16_t wIstr;
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__IO uint16_t wEPVal = 0U;
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@ -370,9 +375,9 @@ static uint16_t dcd_ep_ctr_handler(void)
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{
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/* DIR = 0 => IN int */
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/* DIR = 0 implies that (EP_CTR_TX = 1) always */
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PCD_CLEAR_TX_EP_CTR(USB, 0);
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pcd_clear_tx_ep_ctr(USB, 0);
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xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
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xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
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if((xfer->total_len == xfer->queued_len))
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{
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@ -381,12 +386,12 @@ static uint16_t dcd_ep_ctr_handler(void)
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{
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// Delayed setting of the DADDR after the 0-len DATA packet acking the request is sent.
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reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
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USB->DADDR |= (uint16_t)newDADDR; // leave the enable bit set
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USB->DADDR = (uint16_t)(USB->DADDR | newDADDR); // leave the enable bit set
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newDADDR = 0;
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}
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if(xfer->total_len == 0) // Probably a status message?
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{
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PCD_CLEAR_RX_DTOG(USB,EPindex);
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pcd_clear_rx_dtog(USB,EPindex);
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}
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}
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else
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@ -399,10 +404,10 @@ static uint16_t dcd_ep_ctr_handler(void)
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/* DIR = 1 & CTR_RX => SETUP or OUT int */
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/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
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xfer_ctl_t *xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
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xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
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//ep = &hpcd->OUT_ep[0];
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wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
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wEPVal = pcd_get_endpoint(USB, EPindex);
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if ((wEPVal & USB_EP_SETUP) != 0U) // SETUP
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{
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@ -410,38 +415,38 @@ static uint16_t dcd_ep_ctr_handler(void)
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// user memory, to allow for the 32-bit access that memcpy performs.
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uint8_t userMemBuf[8];
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/* Get SETUP Packet*/
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count = PCD_GET_EP_RX_CNT(USB, EPindex);
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count = pcd_get_ep_rx_cnt(USB, EPindex);
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//TU_ASSERT_ERR(count == 8);
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dcd_read_packet_memory(userMemBuf, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), 8);
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dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
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/* SETUP bit kept frozen while CTR_RX = 1*/
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dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
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PCD_CLEAR_RX_EP_CTR(USB, EPindex);
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pcd_clear_rx_ep_ctr(USB, EPindex);
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}
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else if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
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{
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PCD_CLEAR_RX_EP_CTR(USB, EPindex);
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pcd_clear_rx_ep_ctr(USB, EPindex);
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/* Get Control Data OUT Packet */
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count = PCD_GET_EP_RX_CNT(USB,EPindex);
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count = pcd_get_ep_rx_cnt(USB,EPindex);
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if (count != 0U)
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{
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dcd_read_packet_memory(xfer->buffer, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
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dcd_read_packet_memory(xfer->buffer, *pcd_ep_rx_address_ptr(USB,EPindex), count);
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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/* Process Control Data OUT status Packet*/
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if(EPindex == 0u && xfer->total_len == 0u)
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{
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PCD_CLEAR_EP_KIND(USB,0); // Good, so allow non-zero length packets now.
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pcd_clear_ep_kind(USB,0); // Good, so allow non-zero length packets now.
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}
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dcd_event_xfer_complete(0, EPindex, xfer->total_len, XFER_RESULT_SUCCESS, true);
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PCD_SET_EP_RX_CNT(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
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pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
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if(EPindex == 0u && xfer->total_len == 0u)
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{
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PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
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pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
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}
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}
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@ -452,27 +457,27 @@ static uint16_t dcd_ep_ctr_handler(void)
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{
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/* process related endpoint register */
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wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
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wEPVal = pcd_get_endpoint(USB, EPindex);
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if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
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{
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/* clear int flag */
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PCD_CLEAR_RX_EP_CTR(USB, EPindex);
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pcd_clear_rx_ep_ctr(USB, EPindex);
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xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
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xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
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//ep = &hpcd->OUT_ep[EPindex];
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count = PCD_GET_EP_RX_CNT(USB, EPindex);
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count = pcd_get_ep_rx_cnt(USB, EPindex);
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if (count != 0U)
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{
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dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]),
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*PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
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*pcd_ep_rx_address_ptr(USB,EPindex), count);
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}
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/*multi-packet on the NON control OUT endpoint */
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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if ((count < 64) || (xfer->queued_len == xfer->total_len))
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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{
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/* RX COMPLETE */
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dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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@ -481,14 +486,14 @@ static uint16_t dcd_ep_ctr_handler(void)
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}
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else
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{
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uint16_t remaining = (uint16_t)(xfer->total_len - xfer->queued_len);
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if(remaining >=64) {
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PCD_SET_EP_RX_CNT(USB, EPindex,64);
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uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
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if(remaining >= xfer->max_packet_size) {
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pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
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} else {
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PCD_SET_EP_RX_CNT(USB, EPindex,remaining);
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pcd_set_ep_rx_cnt(USB, EPindex,remaining);
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}
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PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);
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pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
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}
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} /* if((wEPVal & EP_CTR_RX) */
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@ -496,9 +501,9 @@ static uint16_t dcd_ep_ctr_handler(void)
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if ((wEPVal & USB_EP_CTR_TX) != 0U) // IN
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{
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/* clear int flag */
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PCD_CLEAR_TX_EP_CTR(USB, EPindex);
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pcd_clear_tx_ep_ctr(USB, EPindex);
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xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
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xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
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if (xfer->queued_len != xfer->total_len) // data remaining in transfer?
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{
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@ -532,10 +537,10 @@ static void dcd_fs_irqHandler(void) {
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}
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if (int_status & USB_ISTR_WKUP)
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{
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reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE);
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reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP);
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reg16_clear_bits(&USB->ISTR, USB_ISTR_WKUP);
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dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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}
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if (int_status & USB_ISTR_SUSP)
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@ -546,12 +551,25 @@ static void dcd_fs_irqHandler(void) {
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/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
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reg16_clear_bits(&USB->ISTR, USB_ISTR_SUSP);
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dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
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}
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if(int_status & USB_ISTR_SOF) {
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reg16_clear_bits(&USB->ISTR, USB_ISTR_SOF);
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dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
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}
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if(int_status & USB_ISTR_ESOF) {
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if(remoteWakeCountdown == 1u)
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{
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USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
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}
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if(remoteWakeCountdown > 0u)
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{
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remoteWakeCountdown--;
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}
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reg16_clear_bits(&USB->ISTR, USB_ISTR_ESOF);
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}
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}
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//--------------------------------------------------------------------+
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@ -566,47 +584,55 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
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(void)rhport;
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uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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const uint16_t epMaxPktSize = p_endpoint_desc->wMaxPacketSize.size;
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// Isochronous not supported (yet), and some other driver assumptions.
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TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= MAX_PACKET_SIZE);
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TU_ASSERT(epnum < MAX_EP_COUNT);
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TU_ASSERT((p_endpoint_desc->wMaxPacketSize.size %2) == 0);
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// __IO uint16_t * const epreg = &(EPREG(epnum));
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TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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TU_ASSERT(epnum < MAX_EP_COUNT);
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// Set type
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switch(p_endpoint_desc->bmAttributes.xfer) {
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case TUSB_XFER_CONTROL:
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PCD_SET_EPTYPE(USB, epnum, USB_EP_CONTROL); break;
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case TUSB_XFER_ISOCHRONOUS:
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PCD_SET_EPTYPE(USB, epnum, USB_EP_ISOCHRONOUS); break;
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pcd_set_eptype(USB, epnum, USB_EP_CONTROL);
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break;
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#if (0)
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case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported
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pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); break;
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break;
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#endif
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case TUSB_XFER_BULK:
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PCD_SET_EPTYPE(USB, epnum, USB_EP_BULK); break;
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pcd_set_eptype(USB, epnum, USB_EP_BULK);
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break;
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case TUSB_XFER_INTERRUPT:
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PCD_SET_EPTYPE(USB, epnum, USB_EP_INTERRUPT); break;
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pcd_set_eptype(USB, epnum, USB_EP_INTERRUPT);
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break;
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default:
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TU_ASSERT(false);
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return false;
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}
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PCD_SET_EP_ADDRESS(USB, epnum, epnum);
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PCD_CLEAR_EP_KIND(USB,0); // Be normal, for now, instead of only accepting zero-byte packets
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pcd_set_ep_address(USB, epnum, epnum);
|
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pcd_clear_ep_kind(USB,0); // Be normal, for now, instead of only accepting zero-byte packets
|
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|
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if(dir == TUSB_DIR_IN)
|
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{
|
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*PCD_EP_TX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
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PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
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PCD_CLEAR_TX_DTOG(USB, epnum);
|
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PCD_SET_EP_TX_STATUS(USB,epnum,USB_EP_TX_NAK);
|
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*pcd_ep_tx_address_ptr(USB, epnum) = ep_buf_ptr;
|
||||
pcd_set_ep_tx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
||||
pcd_clear_tx_dtog(USB, epnum);
|
||||
pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK);
|
||||
}
|
||||
else
|
||||
{
|
||||
*PCD_EP_RX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
|
||||
PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
||||
PCD_CLEAR_RX_DTOG(USB, epnum);
|
||||
PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_NAK);
|
||||
*pcd_ep_rx_address_ptr(USB, epnum) = ep_buf_ptr;
|
||||
pcd_set_ep_rx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
||||
pcd_clear_rx_dtog(USB, epnum);
|
||||
pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
|
||||
}
|
||||
|
||||
xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize;
|
||||
ep_buf_ptr = (uint16_t)(ep_buf_ptr + p_endpoint_desc->wMaxPacketSize.size); // increment buffer pointer
|
||||
|
||||
return true;
|
||||
@ -618,15 +644,16 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
|
||||
{
|
||||
uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
|
||||
|
||||
if(len > 64u) // max packet size for FS transfer
|
||||
if(len > xfer->max_packet_size) // max packet size for FS transfer
|
||||
{
|
||||
len = 64u;
|
||||
len = xfer->max_packet_size;
|
||||
}
|
||||
dcd_write_packet_memory(*PCD_EP_TX_ADDRESS_PTR(USB,ep_ix), &(xfer->buffer[xfer->queued_len]), len);
|
||||
uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix);
|
||||
dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len);
|
||||
xfer->queued_len = (uint16_t)(xfer->queued_len + len);
|
||||
|
||||
PCD_SET_EP_TX_CNT(USB,ep_ix,len);
|
||||
PCD_SET_EP_TX_STATUS(USB, ep_ix, USB_EP_TX_VALID);
|
||||
pcd_set_ep_tx_cnt(USB,ep_ix,len);
|
||||
pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
||||
@ -636,7 +663,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum,dir);
|
||||
xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
|
||||
|
||||
xfer->buffer = buffer;
|
||||
xfer->total_len = total_bytes;
|
||||
@ -649,15 +676,15 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
||||
if (epnum == 0 && buffer == NULL)
|
||||
{
|
||||
xfer->buffer = (uint8_t*)_setup_packet;
|
||||
PCD_SET_EP_KIND(USB,0); // Expect a zero-byte INPUT
|
||||
pcd_set_ep_kind(USB,0); // Expect a zero-byte INPUT
|
||||
}
|
||||
if(total_bytes > 64)
|
||||
if(total_bytes > xfer->max_packet_size)
|
||||
{
|
||||
PCD_SET_EP_RX_CNT(USB,epnum,64);
|
||||
pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
|
||||
} else {
|
||||
PCD_SET_EP_RX_CNT(USB,epnum,total_bytes);
|
||||
pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
|
||||
}
|
||||
PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_VALID);
|
||||
pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
|
||||
}
|
||||
else // IN
|
||||
{
|
||||
@ -671,14 +698,14 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
(void)rhport;
|
||||
|
||||
if (ep_addr == 0) { // CTRL EP0 (OUT for setup)
|
||||
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
|
||||
pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_STALL);
|
||||
}
|
||||
|
||||
if (ep_addr & 0x80) { // IN
|
||||
ep_addr &= 0x7F;
|
||||
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
|
||||
pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_STALL);
|
||||
} else { // OUT
|
||||
PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_STALL);
|
||||
pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_STALL);
|
||||
}
|
||||
}
|
||||
|
||||
@ -687,24 +714,24 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
(void)rhport;
|
||||
if (ep_addr == 0)
|
||||
{
|
||||
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
|
||||
pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
|
||||
}
|
||||
|
||||
if (ep_addr & 0x80)
|
||||
{ // IN
|
||||
ep_addr &= 0x7F;
|
||||
|
||||
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
|
||||
pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
|
||||
|
||||
/* Reset to DATA0 if clearing stall condition. */
|
||||
PCD_CLEAR_TX_DTOG(USB,ep_addr);
|
||||
pcd_clear_tx_dtog(USB,ep_addr);
|
||||
}
|
||||
else
|
||||
{ // OUT
|
||||
/* Reset to DATA0 if clearing stall condition. */
|
||||
PCD_CLEAR_RX_DTOG(USB,ep_addr);
|
||||
pcd_clear_rx_dtog(USB,ep_addr);
|
||||
|
||||
PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_VALID);
|
||||
pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_VALID);
|
||||
}
|
||||
}
|
||||
|
||||
@ -721,18 +748,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
*/
|
||||
static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
|
||||
{
|
||||
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
|
||||
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1U;
|
||||
uint32_t i;
|
||||
uint16_t temp1, temp2;
|
||||
const uint8_t * srcVal;
|
||||
|
||||
#ifdef DEBUG
|
||||
# if (DCD_STM32_BTABLE_BASE > 0u)
|
||||
TU_ASSERT(dst >= DCD_STM32_BTABLE_BASE);
|
||||
# endif
|
||||
TU_ASSERT(((dst%2) == 0) && (dst + wNBytes) <= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH));
|
||||
#endif
|
||||
|
||||
// The GCC optimizer will combine access to 32-bit sizes if we let it. Force
|
||||
// it volatile so that it won't do that.
|
||||
__IO uint16_t *pdwVal;
|
||||
@ -767,14 +787,6 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
|
||||
__IO const uint16_t *pdwVal;
|
||||
uint32_t temp;
|
||||
|
||||
#ifdef DEBUG
|
||||
# if (DCD_STM32_BTABLE_BASE > 0u)
|
||||
TU_ASSERT(src >= DCD_STM32_BTABLE_BASE);
|
||||
# endif
|
||||
TU_ASSERT(((src%2) == 0) && (src + wNBytes) <= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH));
|
||||
#endif
|
||||
|
||||
|
||||
pdwVal = &pma[PMA_STRIDE*(src>>1)];
|
||||
uint8_t *dstVal = (uint8_t*)dst;
|
||||
|
||||
|
||||
@ -46,7 +46,7 @@
|
||||
defined(STM32F072xB) | \
|
||||
defined(STM32F078xx)
|
||||
#include "stm32f0xx.h"
|
||||
#define PMA_LENGTH 1024
|
||||
#define PMA_LENGTH (1024u)
|
||||
// F0x2 models are crystal-less
|
||||
// All have internal D+ pull-up
|
||||
// 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
|
||||
@ -55,7 +55,7 @@
|
||||
defined(STM32F103x6) | defined(STM32F103xB) | \
|
||||
defined(STM32F103xE) | defined(STM32F103xB)
|
||||
#include "stm32f1xx.h"
|
||||
#define PMA_LENGTH 512u
|
||||
#define PMA_LENGTH (512u)
|
||||
// NO internal Pull-ups
|
||||
// *B, and *C: 2 x 16 bits/word
|
||||
#error The F102/F103 driver is expected not to work, but it might? Try it?
|
||||
@ -64,7 +64,7 @@
|
||||
defined(STM32F303xB) | defined(STM32F303xC) | \
|
||||
defined(STM32F373xC)
|
||||
#include "stm32f3xx.h"
|
||||
#define PMA_LENGTH 512u
|
||||
#define PMA_LENGTH (512u)
|
||||
// NO internal Pull-ups
|
||||
// *B, and *C: 1 x 16 bits/word
|
||||
// PMA dedicated to USB (no sharing with CAN)
|
||||
@ -72,7 +72,7 @@
|
||||
defined(STM32F302xD) | defined(STM32F302xE) | \
|
||||
defined(STM32F303xD) | defined(STM32F303xE) | \
|
||||
#include "stm32f3xx.h"
|
||||
#define PMA_LENGTH 1024u
|
||||
#define PMA_LENGTH (1024u)
|
||||
// NO internal Pull-ups
|
||||
// *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
|
||||
// When CAN clock is enabled, USB can use first 768 bytes ONLY.
|
||||
@ -83,9 +83,9 @@
|
||||
|
||||
// For purposes of accessing the packet
|
||||
#if ((PMA_LENGTH) == 512u)
|
||||
# define PMA_STRIDE (2u)
|
||||
#define PMA_STRIDE (2u)
|
||||
#elif ((PMA_LENGTH) == 1024u)
|
||||
# define PMA_STRIDE (1u)
|
||||
#define PMA_STRIDE (1u)
|
||||
#endif
|
||||
|
||||
// And for type-safety create a new macro for the volatile address of PMAADDR
|
||||
@ -93,32 +93,75 @@
|
||||
// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
|
||||
static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
(((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX)))
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
|
||||
// prototypes
|
||||
static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
|
||||
static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
|
||||
static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
|
||||
|
||||
|
||||
/* SetENDPOINT */
|
||||
static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
|
||||
{
|
||||
__O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u);
|
||||
*reg = (uint16_t)wRegValue;
|
||||
}
|
||||
|
||||
/* GetENDPOINT */
|
||||
static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) {
|
||||
__I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u);
|
||||
return *reg;
|
||||
}
|
||||
|
||||
static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= (uint32_t)USB_EP_T_MASK;
|
||||
regVal |= wType;
|
||||
regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
}
|
||||
|
||||
static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EP_T_FIELD;
|
||||
return regVal;
|
||||
}
|
||||
/**
|
||||
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
|
||||
static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= 0x7FFFu & USB_EPREG_MASK;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
}
|
||||
static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= regVal & 0xFF7FU & USB_EPREG_MASK;
|
||||
pcd_set_endpoint(USBx, bEpNum,regVal);
|
||||
}
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT_PTR((USBx), (bEpNum))) & 0x3ffU)
|
||||
#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT_PTR((USBx), (bEpNum))) & 0x3ffU)
|
||||
static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
__I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
|
||||
return *regPtr & 0x3ffU;
|
||||
}
|
||||
|
||||
static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
__I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
|
||||
return *regPtr & 0x3ffU;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets counter of rx buffer with no. of blocks.
|
||||
@ -127,38 +170,30 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param wNBlocks no. of Blocks.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
|
||||
(wNBlocks) = (uint32_t)((wCount) >> 5U);\
|
||||
if(((wCount) & 0x1fU) == 0U)\
|
||||
{ \
|
||||
(wNBlocks)--;\
|
||||
} \
|
||||
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
|
||||
}/* PCD_CALC_BLK32 */
|
||||
|
||||
|
||||
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
|
||||
(wNBlocks) = (uint32_t)((wCount) >> 1U); \
|
||||
if(((wCount) & 0x1U) != 0U)\
|
||||
{ \
|
||||
(wNBlocks)++;\
|
||||
} \
|
||||
*pdwReg = (uint16_t)((wNBlocks) << 10U);\
|
||||
}/* PCD_CALC_BLK2 */
|
||||
|
||||
|
||||
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
|
||||
uint32_t wNBlocks;\
|
||||
if((wCount) > 62U) \
|
||||
{ \
|
||||
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
|
||||
} \
|
||||
}/* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount) {
|
||||
uint32_t wNBlocks;
|
||||
if(wCount > 62u)
|
||||
{
|
||||
wNBlocks = wCount >> 5u;
|
||||
if((wCount & 0x1fU) == 0u)
|
||||
{
|
||||
wNBlocks--;
|
||||
}
|
||||
wNBlocks = wNBlocks << 10u;
|
||||
wNBlocks |= 0x8000u; // Mark block size as 32byte
|
||||
*pdwReg = (uint16_t)wNBlocks;
|
||||
}
|
||||
else
|
||||
{
|
||||
wNBlocks = wCount >> 1u;
|
||||
if((wCount & 0x1U) != 0u)
|
||||
{
|
||||
wNBlocks++;
|
||||
}
|
||||
*pdwReg = (uint16_t)((wNBlocks) << 10u);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@ -168,23 +203,52 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param bAddr Address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
|
||||
static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t bAddr)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EPREG_MASK;
|
||||
regVal |= bAddr;
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
|
||||
pcd_set_endpoint(USBx, bEpNum,regVal);
|
||||
}
|
||||
|
||||
#define PCD_BTABLE_WORD_PTR(USBx,x) (&(pma[PMA_STRIDE*((((USBx)->BTABLE)>>1) + x)]))
|
||||
static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
|
||||
{
|
||||
size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
|
||||
total_word_offset *= PMA_STRIDE;
|
||||
return &(pma[total_word_offset]);
|
||||
}
|
||||
|
||||
// Pointers to the PMA table entries (using the ARM address space)
|
||||
#define PCD_EP_TX_ADDRESS_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 0u))
|
||||
#define PCD_EP_TX_CNT_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 1u))
|
||||
static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u);
|
||||
}
|
||||
static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u);
|
||||
}
|
||||
|
||||
#define PCD_EP_RX_ADDRESS_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 2u))
|
||||
#define PCD_EP_RX_CNT_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 3u))
|
||||
static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u);
|
||||
}
|
||||
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT_PTR((USBx), (bEpNum)) = (wCount))
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) do {\
|
||||
__IO uint16_t *pdwReg =PCD_EP_RX_CNT_PTR((USBx),(bEpNum)); \
|
||||
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
|
||||
} while(0)
|
||||
static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u);
|
||||
}
|
||||
|
||||
static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount)
|
||||
{
|
||||
*pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount;
|
||||
}
|
||||
|
||||
static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount)
|
||||
{
|
||||
__IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
|
||||
pcd_set_ep_cnt_rx_reg(pdwReg, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
@ -193,21 +257,24 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
|
||||
\
|
||||
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPTX_DTOG1 & (wState))!= 0U)\
|
||||
{ \
|
||||
_wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
|
||||
} /* PCD_SET_EP_TX_STATUS */
|
||||
static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EPTX_DTOGMASK;
|
||||
|
||||
/* toggle first bit ? */
|
||||
if((USB_EPTX_DTOG1 & (wState))!= 0U)
|
||||
{
|
||||
regVal ^= USB_EPTX_DTOG1;
|
||||
}
|
||||
/* toggle second bit ? */
|
||||
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
|
||||
{
|
||||
regVal ^= USB_EPTX_DTOG2;
|
||||
}
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
} /* pcd_set_ep_tx_status */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
@ -216,22 +283,25 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPRX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||
} /* PCD_SET_EP_RX_STATUS */
|
||||
|
||||
static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EPRX_DTOGMASK;
|
||||
|
||||
/* toggle first bit ? */
|
||||
if((USB_EPRX_DTOG1 & wState)!= 0U)
|
||||
{
|
||||
regVal ^= USB_EPRX_DTOG1;
|
||||
}
|
||||
/* toggle second bit ? */
|
||||
if((USB_EPRX_DTOG2 & wState)!= 0U)
|
||||
{
|
||||
regVal ^= USB_EPRX_DTOG2;
|
||||
}
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
} /* pcd_set_ep_rx_status */
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
@ -239,10 +309,21 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
|
||||
static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EPREG_MASK;
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
}
|
||||
|
||||
static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EPREG_MASK;
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
@ -250,14 +331,24 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
|
||||
{ \
|
||||
PCD_RX_DTOG((USBx),(bEpNum));\
|
||||
}
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
|
||||
{\
|
||||
PCD_TX_DTOG((USBx),(bEpNum));\
|
||||
}
|
||||
|
||||
static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
if((regVal & USB_EP_DTOG_RX) != 0)
|
||||
{
|
||||
pcd_rx_dtog(USBx,bEpNum);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
if((regVal & USB_EP_DTOG_TX) != 0)
|
||||
{
|
||||
pcd_tx_dtog(USBx,bEpNum);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set & clear EP_KIND bit.
|
||||
@ -265,11 +356,22 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
|
||||
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))))
|
||||
static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal |= USB_EP_KIND;
|
||||
regVal &= USB_EPREG_MASK;
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
}
|
||||
static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
|
||||
{
|
||||
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
|
||||
regVal &= USB_EPKIND_MASK;
|
||||
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
|
||||
pcd_set_endpoint(USBx, bEpNum, regVal);
|
||||
}
|
||||
|
||||
// This checks if the device has "LPM"
|
||||
#if defined(USB_ISTR_L1REQ)
|
||||
@ -282,6 +384,6 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
|
||||
USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
|
||||
|
||||
// Number of endpoints in hardware
|
||||
#define STFSDEV_EP_COUNT (8)
|
||||
#define STFSDEV_EP_COUNT (8u)
|
||||
|
||||
#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user