Add board support for gd32vf103 longan nano

.gitmodules

@@ -124,3 +124,6 @@
 [submodule "hw/mcu/mindmotion/mm32sdk"]
 	path = hw/mcu/mindmotion/mm32sdk
 	url = https://github.com/zhangslice/mm32sdk.git
+[submodule "hw/mcu/gd/nuclei-sdk"]
+	path = hw/mcu/gd/nuclei-sdk
+	url = git@github.com:Nuclei-Software/nuclei-sdk.git

hw/bsp/board_mcu.h

@@ -130,6 +130,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
   // no header needed
 
+#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
+  #include "gd32vf103.h"
+
 #else
   #error "Missing MCU header"
 #endif

hw/bsp/gd32vf103_longan_nano/board.mk

@@ -0,0 +1,59 @@
+CROSS_COMPILE = riscv32-unknown-elf-
+
+DEPS_SUBMODULES += hw/mcu/gd/nuclei-sdk
+
+NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
+GD32VF103_SDK_SOC_COMMON = $(NUCLEI_SDK)/SoC/gd32vf103/Common
+GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC_COMMON)/Source/Drivers
+SKIP_NANOLIB = 1
+
+CFLAGS += \
+  -march=rv32imac \
+  -mabi=ilp32 \
+  -mcmodel=medlow \
+  -mstrict-align \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
+  -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
+  -DGD32VF103 
+
+# mcu driver cause following warnings
+#CFLAGS += -Wno-error=unused-parameter
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103xb_flashxip.ld # 128kb ROM 32kb RAM
+# LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103x8_flashxip.ld # 64kb ROM 20kb RAM Longan Nano Lite
+
+SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
+	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_fmc.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/sbrk.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/close.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/isatty.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/fstat.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/lseek.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/read.c 
+
+SRC_S += \
+  $(GD32VF103_SDK_SOC_COMMON)/Source/GCC/startup_gd32vf103.S \
+  $(GD32VF103_SDK_SOC_COMMON)/Source/GCC/intexc_gd32vf103.S
+
+INC += \
+  $(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(NUCLEI_SDK)/NMSIS/Core/Include \
+	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include \
+	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include/Usb \
+
+# For freeRTOS port source
+#FREERTOS_PORT = ARM_CM3
+
+# For flash-jlink target
+JLINK_DEVICE = gd32vf103cb
+
+# flash target ROM bootloader
+flash: $(BUILD)/$(PROJECT).bin
+	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<

hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2019 - 2020 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     gcc_gd32vf103x8_flashxip.ld
+ * @brief    GNU Linker Script for gd32vf103x8 based device
+ * @version  V1.0.0
+ * @date     1. Dec 2020
+ ******************************************************************************/
+
+/*********** Use Configuration Wizard in Context Menu *************************/
+
+OUTPUT_ARCH( "riscv" )
+/********************* Flash Configuration ************************************
+ * <h> Flash Configuration
+ * <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ * <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00010000;
+
+/*--------------------- ILM RAM Configuration ---------------------------
+ * <h> ILM RAM Configuration
+ * <o0> ILM RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ILM_RAM_BASE = 0x80000000;
+__ILM_RAM_SIZE = 0x00010000;
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+ * <h> RAM Configuration
+ * <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00005000;
+
+/********************* Stack / Heap Configuration ****************************
+ * <h> Stack / Heap Configuration
+ * <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__STACK_SIZE = 0x00000800;
+__HEAP_SIZE  = 0x00000800;
+
+/**************************** end of configuration section ********************/
+
+/* Define base address and length of flash and ram */
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH,ILM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   _Start : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   _ilm_lma
+ *   _ilm
+ *   __etext
+ *   _etext
+ *   etext
+ *   _eilm
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   _data_lma
+ *   _edata
+ *   edata
+ *   __data_end__
+ *   __bss_start
+ *   __fbss
+ *   _end
+ *   end
+ *   __heap_end
+ *   __StackLimit
+ *   __StackTop
+ *   __STACK_SIZE
+ */
+/* Define entry label of program */
+ENTRY(_start)
+SECTIONS
+{
+  __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
+
+  .init           :
+  {
+    /* vector table locate at flash */
+    *(.vtable)
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    /* Create a section label as _ilm_lma which located at flash */
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash
+
+  .ialign         :
+  {
+    /* Create a section label as _ilm which located at flash */
+    PROVIDE( _ilm = . );
+  } >flash AT>flash
+
+  /* Code section located at flash */
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash
+
+  .rodata : ALIGN(4)
+  {
+    . = ALIGN(4);
+    *(.rdata)
+    *(.rodata .rodata.*)
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    *(.gnu.linkonce.r.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >flash AT>flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  PROVIDE( _eilm = . );
+
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+     * the constructors, so we make sure it is
+     * first.  Because this is a wildcard, it
+     * doesn't matter if the user does not
+     * actually link against crtbegin.o; the
+     * linker won't look for a file to match a
+     * wildcard.  The wildcard also means that it
+     * doesn't matter which directory crtbegin.o
+     * is in.
+     */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+     * the crtend.o file until after the sorted ctors.
+     * The .ctor section from the crtend file contains the
+     * end of ctors marker and it must be last
+     */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash
+
+  /* Define data section virtual address is ram and physical address is flash */
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.* .sdata*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+  /* Define stack and head location at ram */
+  .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
+  {
+    PROVIDE( _heap_end = . );
+    . = __STACK_SIZE;
+    PROVIDE( _sp = . );
+  } >ram AT>ram
+}

hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2019 - 2020 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     gcc_gd32vf103xb_flashxip.ld
+ * @brief    GNU Linker Script for gd32vf103xb based device
+ * @version  V1.0.0
+ * @date     1. Dec 2020
+ ******************************************************************************/
+
+/*********** Use Configuration Wizard in Context Menu *************************/
+
+OUTPUT_ARCH( "riscv" )
+/********************* Flash Configuration ************************************
+ * <h> Flash Configuration
+ * <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ * <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00020000;
+
+/*--------------------- ILM RAM Configuration ---------------------------
+ * <h> ILM RAM Configuration
+ * <o0> ILM RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ILM_RAM_BASE = 0x80000000;
+__ILM_RAM_SIZE = 0x00010000;
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+ * <h> RAM Configuration
+ * <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00008000;
+
+/********************* Stack / Heap Configuration ****************************
+ * <h> Stack / Heap Configuration
+ * <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__STACK_SIZE = 0x00000800;
+__HEAP_SIZE  = 0x00000800;
+
+/**************************** end of configuration section ********************/
+
+/* Define base address and length of flash and ram */
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH,ILM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   _Start : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   _ilm_lma
+ *   _ilm
+ *   __etext
+ *   _etext
+ *   etext
+ *   _eilm
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   _data_lma
+ *   _edata
+ *   edata
+ *   __data_end__
+ *   __bss_start
+ *   __fbss
+ *   _end
+ *   end
+ *   __heap_end
+ *   __StackLimit
+ *   __StackTop
+ *   __STACK_SIZE
+ */
+/* Define entry label of program */
+ENTRY(_start)
+SECTIONS
+{
+  __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
+
+  .init           :
+  {
+    /* vector table locate at flash */
+    *(.vtable)
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    /* Create a section label as _ilm_lma which located at flash */
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash
+
+  .ialign         :
+  {
+    /* Create a section label as _ilm which located at flash */
+    PROVIDE( _ilm = . );
+  } >flash AT>flash
+
+  /* Code section located at flash */
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash
+
+  .rodata : ALIGN(4)
+  {
+    . = ALIGN(4);
+    *(.rdata)
+    *(.rodata .rodata.*)
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    *(.gnu.linkonce.r.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >flash AT>flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  PROVIDE( _eilm = . );
+
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+     * the constructors, so we make sure it is
+     * first.  Because this is a wildcard, it
+     * doesn't matter if the user does not
+     * actually link against crtbegin.o; the
+     * linker won't look for a file to match a
+     * wildcard.  The wildcard also means that it
+     * doesn't matter which directory crtbegin.o
+     * is in.
+     */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+     * the crtend.o file until after the sorted ctors.
+     * The .ctor section from the crtend file contains the
+     * end of ctors marker and it must be last
+     */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash
+
+  /* Define data section virtual address is ram and physical address is flash */
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.* .sdata*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+  /* Define stack and head location at ram */
+  .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
+  {
+    PROVIDE( _heap_end = . );
+    . = __STACK_SIZE;
+    PROVIDE( _sp = . );
+  } >ram AT>ram
+}

hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c

@@ -0,0 +1,274 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "nuclei_sdk_hal.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+void USBFS_IRQHandler(void) { tud_int_handler(0); }
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+#define HXTAL_VALUE \
+  ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
+#define USB_NO_VBUS_PIN 1
+
+//--------------------------------------------------------------------+
+// LED
+//--------------------------------------------------------------------+
+
+#define LED_PORT GPIOC
+#define LED_PIN GPIO_PIN_13
+#define LED_STATE_ON 1
+
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE 1
+
+//--------------------------------------------------------------------+
+// UART
+//--------------------------------------------------------------------+
+
+#define UART_DEV USART0
+#define UART_GPIO_PORT GPIOA
+#define UART_TX_PIN GPIO_PIN_9
+#define UART_RX_PIN GPIO_PIN_10
+
+/* sipeed longan nano board UART com port */
+#define GD32_COM0 USART0
+#define GD32_COM_CLK RCU_USART0
+#define GD32_COM_TX_PIN GPIO_PIN_9
+#define GD32_COM_RX_PIN GPIO_PIN_10
+#define GD32_COM_TX_GPIO_PORT GPIOA
+#define GD32_COM_RX_GPIO_PORT GPIOA
+#define GD32_COM_TX_GPIO_CLK RCU_GPIOA
+#define GD32_COM_RX_GPIO_CLK RCU_GPIOA
+
+void board_init(void) {
+  /* Disable interrupts during init */
+  __disable_irq();
+
+  /* Reset eclic configuration registers */
+  ECLIC->CFG = 0;
+  ECLIC->MTH = 0;
+
+  /* Reset eclic interrupt registers */
+  for (int32_t i = 0; i < SOC_INT_MAX; i++) {
+    ECLIC->CTRL[0].INTIP = 0;
+    ECLIC->CTRL[0].INTIE = 0;
+    ECLIC->CTRL[0].INTATTR = 0;
+    ECLIC->CTRL[0].INTCTRL = 0;
+  }
+
+  /* Set 4 bits for interrupt level and 0 bits for priority */
+  __ECLIC_SetCfgNlbits(4);
+
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTimer_SetLoadValue(0);
+  SysTimer_SetCompareValue(SystemCoreClock / 1000);
+  ECLIC_SetLevelIRQ(SysTimer_IRQn, 3);
+  ECLIC_SetTrigIRQ(SysTimer_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
+  ECLIC_EnableIRQ(SysTimer_IRQn);
+  SysTimer_Start();
+#endif
+
+  rcu_periph_clock_enable(RCU_GPIOA);
+  rcu_periph_clock_enable(RCU_GPIOB);
+  rcu_periph_clock_enable(RCU_GPIOC);
+  rcu_periph_clock_enable(RCU_GPIOD);
+  rcu_periph_clock_enable(RCU_AF);
+
+#ifdef BUTTON_PIN
+  gpio_init(BUTTON_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, BUTTON_PIN);
+#endif
+
+#ifdef LED_PIN
+  gpio_init(LED_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LED_PIN);
+  board_led_write(0);
+#endif
+
+#if defined(UART_DEV) && CFG_TUSB_DEBUG
+  /* enable GPIO TX and RX clock */
+  rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK);
+  rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK);
+
+  /* enable USART clock */
+  rcu_periph_clock_enable(GD32_COM_CLK);
+
+  /* connect port to USARTx_Tx */
+  gpio_init(GD32_COM_TX_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
+            GD32_COM_TX_PIN);
+
+  /* connect port to USARTx_Rx */
+  gpio_init(GD32_COM_RX_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ,
+            GD32_COM_RX_PIN);
+
+  /* USART configure */
+  usart_deinit(UART_DEV);
+  usart_baudrate_set(UART_DEV, 115200U);
+  usart_word_length_set(UART_DEV, USART_WL_8BIT);
+  usart_stop_bit_set(UART_DEV, USART_STB_1BIT);
+  usart_parity_config(UART_DEV, USART_PM_NONE);
+  usart_hardware_flow_rts_config(UART_DEV, USART_RTS_DISABLE);
+  usart_hardware_flow_cts_config(UART_DEV, USART_CTS_DISABLE);
+  usart_receive_config(UART_DEV, USART_RECEIVE_ENABLE);
+  usart_transmit_config(UART_DEV, USART_TRANSMIT_ENABLE);
+  usart_enable(UART_DEV);
+#endif
+
+  /* USB D+ and D- pins don't need to be configured. */
+  /* Configure VBUS Pin */
+#ifndef USB_NO_VBUS_PIN
+  gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
+#endif
+
+  /* This for ID line debug */
+  // gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
+
+  /* Enable USB OTG clock */
+  usb_rcu_config();
+
+  /* Reset USB OTG peripheral */
+  rcu_periph_reset_enable(RCU_USBFSRST);
+  rcu_periph_reset_disable(RCU_USBFSRST);
+
+  /* Set IRQ priority and trigger */
+  ECLIC_SetLevelIRQ(USBFS_IRQn, 15);
+  ECLIC_SetTrigIRQ(USBFS_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
+
+  /* Retrieve otg core registers */
+  usb_gr* otg_core_regs = (usb_gr*)(USBFS_REG_BASE + USB_REG_OFFSET_CORE);
+
+#ifdef USB_NO_VBUS_PIN
+  /* Disable VBUS sense*/
+  otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
+#else
+  /* Enable VBUS sense via pin PA9 */
+  otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
+  otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
+#endif
+
+  /* Enable interrupts globaly */
+  __enable_irq();
+}
+
+#include "gd32vf103_dbg.h"
+
+#define DBG_KEY_UNLOCK 0x4B5A6978
+#define DBG_CMD_RESET 0x1
+
+#define DBG_KEY REG32(DBG + 0x0C)
+#define DBG_CMD REG32(DBG + 0x08)
+
+void gd32vf103_reset(void) {
+  /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
+   * register to generate a software reset request.
+   * BUT instead two undocumented registers in the debug peripheral
+   * that allow issueing a software reset.
+   * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h
+   */
+  DBG_KEY = DBG_KEY_UNLOCK;
+  DBG_CMD = DBG_CMD_RESET;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  gpio_bit_write(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+#if defined(UART_DEV) && CFG_TUSB_DEBUG
+
+  int rxsize = len;
+  while (rxsize--) {
+    *(uint8_t*)buf = usart_read(UART_DEV);
+    buf++;
+  }
+  return len;
+#else
+  (void)buf;
+  (void)len;
+  return 0;
+#endif
+}
+
+int board_uart_write(void const* buf, int len) {
+#if defined(UART_DEV) && CFG_TUSB_DEBUG
+
+  int txsize = len;
+  while (txsize--) {
+    usart_write(UART_DEV, *(uint8_t*)buf);
+    buf++;
+  }
+  return len;
+#else
+  (void)buf;
+  (void)len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void eclic_mtip_handler(void) { system_ticks++; }
+uint32_t board_millis(void) { return system_ticks; }
+#endif
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(char* file, uint32_t line) {
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line
+     number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
+   */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+// void _init(void) {}

hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h

@@ -0,0 +1,20 @@
+// See LICENSE for license details.
+#ifndef _NUCLEI_SDK_HAL_H
+#define _NUCLEI_SDK_HAL_H
+
+#include "nmsis_gcc.h"
+#include "gd32vf103.h"
+#include "gd32vf103_libopt.h"
+#include "drv_usb_hw.h"
+#include "drv_usb_dev.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_DEBUG_UART      USART0
+
+#ifdef __cplusplus
+}
+#endif
+#endif

hw/mcu/gd/nuclei-sdk

@@ -0,0 +1 @@
+Subproject commit 834e02fa7fcc9bb1823cf517003296e01adaa7c7