mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-31 05:52:55 +08:00
enable CFG_TUD/THU_MEM_DCACHE_ENABLE for imxrt with M7 by default
This commit is contained in:
hathach
parent
a39e30db92
commit
22a6777c2d
@ -11,11 +11,11 @@
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v12.0
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product: Clocks v14.0
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processor: MIMXRT1176xxxxx
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package_id: MIMXRT1176DVMAA
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mcu_data: ksdk2_0
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processor_version: 14.0.1
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processor_version: 16.3.0
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board: MIMXRT1170-EVKB
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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@ -335,7 +335,6 @@ void BOARD_BootClockRUN(void)
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/* Init OSC RC 400M */
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CLOCK_OSC_EnableOscRc400M();
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CLOCK_OSC_GateOscRc400M(false);
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/* Init OSC RC 48M */
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CLOCK_OSC_EnableOsc48M(true);
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@ -349,22 +348,29 @@ void BOARD_BootClockRUN(void)
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{
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}
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/* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
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/* Switch core M7 clock root to OscRC48MDiv2 first */
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#if __CORTEX_M == 7
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rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
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rootCfg.div = 1;
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CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
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#endif
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/* Switch core M7 systick clock root to OscRC48MDiv2 first */
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#if __CORTEX_M == 7
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rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
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rootCfg.div = 1;
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CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
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#endif
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/* Switch core M4 clock root to OscRC48MDiv2 first */
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#if __CORTEX_M == 4
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rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
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rootCfg.div = 1;
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CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
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#endif
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/* Switch the Bus_Lpsr clock root to OscRC48MDiv2 first */
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#if __CORTEX_M == 4
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rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
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rootCfg.div = 1;
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CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
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@ -48,7 +48,7 @@ void BOARD_InitBootClocks(void);
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#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
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#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
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#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */
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#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
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#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IEE__IEE_RT1170, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
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#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */
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#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */
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#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */
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@ -6,11 +6,11 @@
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Pins v14.0
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product: Pins v16.0
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processor: MIMXRT1176xxxxx
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package_id: MIMXRT1176DVMAA
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mcu_data: ksdk2_0
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processor_version: 14.0.1
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processor_version: 16.3.0
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board: MIMXRT1170-EVKB
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external_user_signals: {}
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pin_labels:
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@ -90,7 +90,7 @@ void BOARD_InitPins(void) {
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IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */
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0x02U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high drive strength
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Pull / Keep Select Field: Pull Disable, Highz
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Pull / Keep Select Field: Pull Disable
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Pull Up / Down Config. Field: Weak pull down
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Open Drain Field: Disabled
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Domain write protection: Both cores are allowed
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@ -99,7 +99,7 @@ void BOARD_InitPins(void) {
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IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
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0x02U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high drive strength
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Pull / Keep Select Field: Pull Disable, Highz
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Pull / Keep Select Field: Pull Disable
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Pull Up / Down Config. Field: Weak pull down
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Open Drain Field: Disabled
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Domain write protection: Both cores are allowed
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@ -108,22 +108,19 @@ void BOARD_InitPins(void) {
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IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
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0x02U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high drive strength
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Pull / Keep Select Field: Pull Disable, Highz
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Pull / Keep Select Field: Pull Disable
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Pull Up / Down Config. Field: Weak pull down
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Open Drain Field: Disabled
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Domain write protection: Both cores are allowed
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Domain write protection lock: Neither of DWP bits is locked */
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IOMUXC_SetPinConfig(
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IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */
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0x0EU); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high driver
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Pull / Keep Select Field: Pull Enable
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0x0EU); /* Pull / Keep Select Field: Pull Enable
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Pull Up / Down Config. Field: Weak pull up
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Open Drain SNVS Field: Disabled
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Domain write protection: Both cores are allowed
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Domain write protection lock: Neither of DWP bits is locked */
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}
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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@ -46,7 +46,7 @@ void BOARD_InitBootPins(void);
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#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */
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#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
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/* WAKEUP (coord T8), USER_BUTTON */
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/* WAKEUP (coord T8), USER_BUTTON/SW7 */
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/* Routed pin properties */
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#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO13 /*!< Peripheral name */
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#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
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@ -1,5 +1,5 @@
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<?xml version="1.0" encoding= "UTF-8" ?>
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<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_14 http://mcuxpresso.nxp.com/XSD/mex_configuration_14.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="14" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_14" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_16 http://mcuxpresso.nxp.com/XSD/mex_configuration_16.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="16" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_16" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<common>
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<processor>MIMXRT1176xxxxx</processor>
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<package>MIMXRT1176DVMAA</package>
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@ -19,18 +19,17 @@
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<generate_registers_defines>false</generate_registers_defines>
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</preferences>
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<tools>
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<pins name="Pins" version="14.0" enabled="true" update_project_code="true">
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<pins name="Pins" version="16.0" enabled="true" update_project_code="true">
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<generated_project_files>
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<file path="board/pin_mux.c" update_enabled="true"/>
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<file path="board/pin_mux.h" update_enabled="true"/>
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</generated_project_files>
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<pins_profile>
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<processor_version>14.0.1</processor_version>
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<processor_version>16.3.0</processor_version>
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<pin_labels>
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<pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED;USER_LED"/>
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</pin_labels>
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<external_user_signals>
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<routingDetailsColumns/>
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<properties/>
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</external_user_signals>
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<power_domains/>
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@ -44,7 +43,7 @@
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<enableClock>true</enableClock>
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</options>
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<dependencies>
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<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
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<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
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<feature name="initialized" evaluation="equal">
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<data>true</data>
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</feature>
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@ -104,13 +103,13 @@
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</function>
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</functions_list>
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</pins>
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<clocks name="Clocks" version="12.0" enabled="true" update_project_code="true">
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<clocks name="Clocks" version="14.0" enabled="true" update_project_code="true">
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<generated_project_files>
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<file path="board/clock_config.c" update_enabled="true"/>
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<file path="board/clock_config.h" update_enabled="true"/>
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</generated_project_files>
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<clocks_profile>
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<processor_version>14.0.1</processor_version>
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<processor_version>16.3.0</processor_version>
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</clocks_profile>
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<clock_configurations>
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<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
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@ -24,10 +24,10 @@
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* This file is part of the TinyUSB stack.
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*/
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#include "board.h"
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#include "bsp/board_api.h"
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#include "board/clock_config.h"
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#include "board/pin_mux.h"
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#include "bsp/board_api.h"
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#include "board.h"
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// Suppress warning caused by mcu driver
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#ifdef __GNUC__
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@ -47,14 +47,14 @@
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#endif
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/* --- Note about USB buffer RAM ---
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For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default)
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Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU():
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- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
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- (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N
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For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default)
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Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU():
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- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
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- (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N
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For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used:
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- __NCACHE_REGION_SIZE is defined by the linker script by default
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- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
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For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used:
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- __NCACHE_REGION_SIZE is defined by the linker script by default
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- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
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*/
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static void BOARD_ConfigMPU(void);
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@ -148,7 +148,112 @@ void board_init(void) {
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#endif
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}
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/* MPU configuration. */
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//--------------------------------------------------------------------+
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// USB Interrupt Handler
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//--------------------------------------------------------------------+
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void USB_OTG1_IRQHandler(void) {
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tusb_int_handler(0, true);
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}
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void USB_OTG2_IRQHandler(void) {
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tusb_int_handler(1, true);
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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void board_led_write(bool state) {
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GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
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}
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uint32_t board_button_read(void) {
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return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
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}
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size_t board_get_unique_id(uint8_t id[], size_t max_len) {
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(void) max_len;
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#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
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OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
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#else
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OCOTP_Init(OCOTP, 0u);
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#endif
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// Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
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// into 8 bit wide destination, avoiding punning.
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for (int i = 0; i < 4; ++i) {
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uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1);
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for (int j = 0; j < 4; j++) {
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id[i * 4 + j] = wr & 0xff;
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wr >>= 8;
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}
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}
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OCOTP_Deinit(OCOTP);
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return 16;
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}
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int board_uart_read(uint8_t *buf, int len) {
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int count = 0;
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while (count < len) {
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uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT);
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if (!rx_count) {
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// clear all error flag if any
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uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT);
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status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag |
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kLPUART_NoiseErrorFlag);
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LPUART_ClearStatusFlags(UART_PORT, status_flags);
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break;
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}
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for (int i = 0; i < rx_count; i++) {
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buf[count] = LPUART_ReadByte(UART_PORT);
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count++;
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}
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}
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return count;
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}
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int board_uart_write(void const *buf, int len) {
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LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len);
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return len;
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void SysTick_Handler(void) {
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system_ticks++;
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}
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uint32_t board_millis(void) {
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return system_ticks;
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}
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#endif
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#ifndef __ICCARM__
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// Implement _start() since we use linker flag '-nostartfiles'.
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// Requires defined __STARTUP_CLEAR_BSS,
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extern int main(void);
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TU_ATTR_UNUSED void _start(void) {
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// called by startup code
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main();
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while (1) {}
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}
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#ifdef __clang__
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void _exit(int __status) {
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while (1) {}
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}
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#endif
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#endif
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//--------------------------------------------------------------------
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// MPU configuration
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//--------------------------------------------------------------------
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#if __CORTEX_M == 7
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static void BOARD_ConfigMPU(void) {
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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@ -343,7 +448,9 @@ static void BOARD_ConfigMPU(void) {
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SCB_EnableICache();
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#endif
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}
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#elif __CORTEX_M == 4
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void BOARD_ConfigMPU(void) {
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$RW_m_ncache$$Base[];
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||||
@ -525,107 +632,3 @@ void BOARD_ConfigMPU(void) {
|
||||
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
|
||||
}
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USB Interrupt Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void USB_OTG1_IRQHandler(void) {
|
||||
tusb_int_handler(0, true);
|
||||
}
|
||||
|
||||
void USB_OTG2_IRQHandler(void) {
|
||||
tusb_int_handler(1, true);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state) {
|
||||
GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void) {
|
||||
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
|
||||
}
|
||||
|
||||
size_t board_get_unique_id(uint8_t id[], size_t max_len) {
|
||||
(void) max_len;
|
||||
|
||||
#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
|
||||
OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
|
||||
#else
|
||||
OCOTP_Init(OCOTP, 0u);
|
||||
#endif
|
||||
|
||||
// Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
|
||||
// into 8 bit wide destination, avoiding punning.
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1);
|
||||
for (int j = 0; j < 4; j++) {
|
||||
id[i * 4 + j] = wr & 0xff;
|
||||
wr >>= 8;
|
||||
}
|
||||
}
|
||||
OCOTP_Deinit(OCOTP);
|
||||
|
||||
return 16;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len) {
|
||||
int count = 0;
|
||||
|
||||
while (count < len) {
|
||||
uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT);
|
||||
if (!rx_count) {
|
||||
// clear all error flag if any
|
||||
uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT);
|
||||
status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag |
|
||||
kLPUART_NoiseErrorFlag);
|
||||
LPUART_ClearStatusFlags(UART_PORT, status_flags);
|
||||
break;
|
||||
}
|
||||
|
||||
for (int i = 0; i < rx_count; i++) {
|
||||
buf[count] = LPUART_ReadByte(UART_PORT);
|
||||
count++;
|
||||
}
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len) {
|
||||
LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len);
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void) {
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void) {
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM__
|
||||
// Implement _start() since we use linker flag '-nostartfiles'.
|
||||
// Requires defined __STARTUP_CLEAR_BSS,
|
||||
extern int main(void);
|
||||
TU_ATTR_UNUSED void _start(void) {
|
||||
// called by startup code
|
||||
main();
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
#ifdef __clang__
|
||||
void _exit(int __status) {
|
||||
while (1) {}
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -108,12 +108,20 @@
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
#define TUP_USBIP_CHIPIDEA_HS
|
||||
#define TUP_USBIP_EHCI
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#define TUP_RHPORT_HIGHSPEED 1
|
||||
|
||||
#if __CORTEX_M == 7
|
||||
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
|
||||
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
|
||||
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
|
||||
#endif
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
|
||||
#define TUP_USBIP_CHIPIDEA_FS
|
||||
#define TUP_USBIP_CHIPIDEA_FS_KINETIS
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user