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Cleaner approach.
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4938128ccc
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@ -84,17 +84,16 @@ extern "C" {
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#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
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#include "stm32u5xx.h"
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// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
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#ifdef USB_OTG_FS
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#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
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#define EP_MAX_FS 6
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#define EP_FIFO_SIZE_FS 1280
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#define USB_OTG_FS_IRQN OTG_FS_IRQn
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// U53x/U54x are fullspeed with built-in FS PHY but not OTG
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#elif defined(USB_DRD_FS)
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#define USB_OTG_FS_PERIPH_BASE USB_DRD_BASE
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#define USB_DRD_FS_PERIPH_BASE USB_DRD_BASE
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#define EP_MAX_FS 6
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#define EP_FIFO_SIZE_FS 1280
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#define USB_OTG_FS_IRQN USB_IRQn
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// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
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#else
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#define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE
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#define EP_MAX_HS 9
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@ -114,6 +113,10 @@ extern "C" {
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// On STM32 for consistency we associate
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// - Port0 to OTG_FS, and Port1 to OTG_HS
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static const dwc2_controller_t _dwc2_controller[] = {
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#ifdef USB_DRD_FS_PERIPH_BASE
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{ .reg_base = USB_DRD_FS_PERIPH_BASE, .irqnum = USB_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
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#endif
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#ifdef USB_OTG_FS_PERIPH_BASE
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{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = USB_OTG_FS_IRQN, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
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#endif
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