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add sndfifo owner info to skip rewriting data for retrying NAKed
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hathach
parent
c7851e8dcb
commit
27ddf19631
@ -197,7 +197,7 @@ Docs
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- `Structure`_
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- `Porting`_
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.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg
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.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/build.yml/badge.svg
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:target: https://github.com/hathach/tinyusb/actions
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.. |CircleCI Status| image:: https://dl.circleci.com/status-badge/img/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master.svg?style=svg
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:target: https://dl.circleci.com/status-badge/redirect/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master
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@ -418,6 +418,12 @@ exit"
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COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
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VERBATIM
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)
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# optional flash post build
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# add_custom_command(TARGET ${TARGET} POST_BUILD
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# COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
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# VERBATIM
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# )
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endfunction()
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@ -81,7 +81,7 @@ enum {
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};
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typedef struct {
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uint8_t max_nak; // max NAK per endpoint per frame
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uint8_t max_nak; // max NAK per endpoint per frame to save CPU/SPI bus usage
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uint8_t cpuctl; // R16: CPU Control Register
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uint8_t pinctl; // R17: Pin Control Register. FDUPSPI bit is ignored
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} tuh_configure_max3421_t;
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@ -168,14 +168,14 @@ enum {
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};
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enum {
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MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame
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MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame to save CPU/SPI bus usage
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};
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enum {
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EP_STATE_IDLE = 0,
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EP_STATE_COMPLETE = 1,
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EP_STATE_ABORTING = 2,
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EP_STATE_ATTEMPT_1 = 3, // pending 1st attempt
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EP_STATE_ATTEMPT_1 = 3, // Number of attempts to transfer in a frame. Incremented after each NAK
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EP_STATE_ATTEMPT_MAX = 15
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};
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@ -183,17 +183,20 @@ enum {
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//
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//--------------------------------------------------------------------+
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typedef struct TU_ATTR_PACKED {
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uint8_t ep_num : 4;
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uint8_t is_setup : 1;
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uint8_t is_out : 1;
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uint8_t is_iso : 1;
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} hxfr_bm_t;
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TU_VERIFY_STATIC(sizeof(hxfr_bm_t) == 1, "size is not correct");
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typedef struct {
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uint8_t daddr;
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union { ;
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struct TU_ATTR_PACKED {
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uint8_t ep_num : 4;
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uint8_t is_setup : 1;
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uint8_t is_out : 1;
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uint8_t is_iso : 1;
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}hxfr_bm;
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union {
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hxfr_bm_t hxfr_bm;
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uint8_t hxfr;
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};
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@ -203,13 +206,12 @@ typedef struct {
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uint16_t packet_size : 11;
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};
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bool received_nak;
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uint16_t total_len;
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uint16_t xferred_len;
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uint8_t* buf;
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} max3421_ep_t;
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TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 16, "size is not correct");
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TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct");
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typedef struct {
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volatile uint16_t frame_count;
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@ -220,7 +222,16 @@ typedef struct {
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uint8_t hien;
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uint8_t mode;
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uint8_t peraddr;
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uint8_t hxfr;
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union {
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hxfr_bm_t hxfr_bm;
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uint8_t hxfr;
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};
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// owner of data in SNDFIFO, for retrying NAKed without re-writing to FIFO
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struct {
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uint8_t daddr;
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uint8_t hxfr;
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}sndfifo_owner;
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atomic_flag busy; // busy transferring
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@ -318,33 +329,9 @@ bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_is
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return ret;
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}
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static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
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uint8_t hirq;
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reg |= CMDBYTE_WRITE;
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
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max3421_spi_unlock(rhport, in_isr);
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}
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static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
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uint8_t hirq;
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uint8_t const reg = RCVVFIFO_ADDR;
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
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max3421_spi_unlock(rhport, in_isr);
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}
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//------------- register write helper -------------//
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//--------------------------------------------------------------------
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// Register helper
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//--------------------------------------------------------------------
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TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
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reg_write(rhport, HIRQ_ADDR, data, in_isr);
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// HIRQ write 1 is clear
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@ -378,6 +365,47 @@ TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t dat
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reg_write(rhport, SNDBC_ADDR, data, in_isr);
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}
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//--------------------------------------------------------------------
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// FIFO access (receive, send, setup)
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//--------------------------------------------------------------------
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static void hwfifo_write(uint8_t rhport, uint8_t reg, const uint8_t* buffer, uint8_t len, bool in_isr) {
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uint8_t hirq;
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reg |= CMDBYTE_WRITE;
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
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max3421_spi_unlock(rhport, in_isr);
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}
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// Write to SNDFIFO if len > 0 and update SNDBC
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TU_ATTR_ALWAYS_INLINE static inline void hwfifo_send(uint8_t rhport, const uint8_t* buffer, uint8_t len, bool in_isr) {
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if (len) {
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hwfifo_write(rhport, SNDFIFO_ADDR, buffer, len, in_isr);
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}
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sndbc_write(rhport, len, in_isr);
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}
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TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint8_t* buffer, bool in_isr) {
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hwfifo_write(rhport, SUDFIFO_ADDR, buffer, 8, in_isr);
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}
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static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
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uint8_t hirq;
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uint8_t const reg = RCVVFIFO_ADDR;
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
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max3421_spi_unlock(rhport, in_isr);
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}
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//--------------------------------------------------------------------+
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// Endpoint helper
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//--------------------------------------------------------------------+
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@ -418,7 +446,7 @@ static void free_ep(uint8_t daddr) {
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}
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}
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// Check if endpoint has an queued transfer and not reach max NAK
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// Check if endpoint has a queued transfer and not reach max NAK in this frame
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TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) {
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uint8_t const state = ep->state;
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return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) &&
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@ -488,6 +516,7 @@ bool hcd_init(uint8_t rhport) {
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reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false);
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// v1 is 0x01, v2 is 0x12, v3 is 0x13
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// Note: v1 and v2 has host OUT errata whose workaround is not implemented in this driver
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uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
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TU_LOG2_HEX(revision);
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TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
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@ -616,27 +645,44 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
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return true;
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}
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/* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes.
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* Then the microcontroller writes the SNDBC register, which this does three things:
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* 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send.
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* 2. Connects the SNDFIFO and SNDBC register to the USB logic for USB transmission.
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* 3. Clears the SNDBAVIRQ interrupt flag. If the second FIFO is available for µC loading, the SNDBAVIRQ immediately re-asserts.
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+-----------+
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--->| SNDBC-A |
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/ | SNDFIFO-A |
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/ +-----------+
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+------+ +-------------+ / +----------+
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| MCU |------>| R2: SNDFIFO |---- << Write R7 Flip >> ---| MAX3241E |
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|(hcd) | | R7: SNDBC | / | SIE |
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+------+ +-------------+ / +----------+
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+-----------+ /
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| SNDBC-B | /
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| SNDFIFO-B |<---
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+-----------+
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Note: xact_out() is called when starting a new transfer, continue a transfer (isr) or retry a transfer (NAK)
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For NAK retry, we do not need to write to FIFO or SNDBC register again.
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*/
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static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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// Page 12: Programming BULK-OUT Transfers
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// TODO double buffered
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// TODO: double buffering for ISO transfer
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if (switch_ep) {
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peraddr_write(rhport, ep->daddr, in_isr);
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uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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const uint8_t hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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reg_write(rhport, HCTL_ADDR, hctl, in_isr);
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}
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if (!ep->received_nak){
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// do not write to fifo or sdnbc register again if previous attempt got NAK
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uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
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if (xact_len) {
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// only check SNDBAV IRQ if there is data to send
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TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
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fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
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}
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sndbc_write(rhport, xact_len, in_isr);
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// Only write to sndfifo and sdnbc register if it is not a NAKed retry
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if (!(ep->daddr == _hcd_data.sndfifo_owner.daddr && ep->hxfr == _hcd_data.sndfifo_owner.hxfr)) {
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// skip SNDBAV IRQ check, overwrite sndfifo if needed
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const uint8_t xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
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hwfifo_send(rhport, ep->buf, xact_len, in_isr);
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}
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_hcd_data.sndfifo_owner.daddr = ep->daddr;
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_hcd_data.sndfifo_owner.hxfr = ep->hxfr;
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hxfr_write(rhport, ep->hxfr, in_isr);
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}
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@ -655,7 +701,7 @@ static void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_is
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static void xact_setup(uint8_t rhport, max3421_ep_t *ep, bool in_isr) {
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peraddr_write(rhport, ep->daddr, in_isr);
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fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
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hwfifo_setup(rhport, ep->buf, in_isr);
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hxfr_write(rhport, HXFR_SETUP, in_isr);
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}
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@ -669,7 +715,7 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool
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// status
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if (ep->buf == NULL || ep->total_len == 0) {
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uint8_t const hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN));
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const uint8_t hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN));
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peraddr_write(rhport, ep->daddr, in_isr);
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hxfr_write(rhport, hxfr, in_isr);
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return;
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@ -830,11 +876,11 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
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}
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static void handle_xfer_done(uint8_t rhport, bool in_isr) {
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uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
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uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
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uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
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uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
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const uint8_t hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
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const uint8_t hresult = hrsl & HRSL_RESULT_MASK;
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const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num;
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const uint8_t hxfr_type = _hcd_data.hxfr & 0xf0;
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const uint8_t ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
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max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
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TU_VERIFY(ep, );
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@ -849,9 +895,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
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// control endpoint -> retry immediately and return
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hxfr_write(rhport, _hcd_data.hxfr, in_isr);
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return;
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} else if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) {
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}
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if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) {
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ep->state++;
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ep->received_nak = true;
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}
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}
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@ -861,7 +907,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
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hxfr_write(rhport, _hcd_data.hxfr, in_isr);
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} else if (next_ep) {
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// switch to next pending endpoint
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// TODO could have issue with double buffered if not clear previously out data
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xact_generic(rhport, next_ep, true, in_isr);
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} else {
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// no more pending in this frame -> clear busy
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@ -875,7 +920,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
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case HRSL_SUCCESS:
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xfer_result = XFER_RESULT_SUCCESS;
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ep->received_nak = false;
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break;
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case HRSL_STALL:
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@ -905,11 +949,15 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
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if (ep->state == EP_STATE_COMPLETE) {
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xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
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}else {
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// more to transfer
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hxfr_write(rhport, _hcd_data.hxfr, in_isr);
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hxfr_write(rhport, _hcd_data.hxfr, in_isr); // more to transfer
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}
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} else {
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// SETUP or OUT transfer
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// clear sndfifo owner since data is sent
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_hcd_data.sndfifo_owner.daddr = 0xff;
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_hcd_data.sndfifo_owner.hxfr = 0xff;
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uint8_t xact_len;
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if (hxfr_type & HXFR_SETUP) {
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@ -926,8 +974,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
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if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
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xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
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} else {
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// more to transfer
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xact_out(rhport, ep, false, in_isr);
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xact_out(rhport, ep, false, in_isr); // more to transfer
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}
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}
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}
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@ -987,16 +1034,16 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
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// not call this handler again. So we need to loop until all IRQ are cleared
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while (hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ)) {
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if (hirq & HIRQ_RCVDAV_IRQ) {
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uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num;
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max3421_ep_t* ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
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uint8_t xact_len = 0;
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// RCVDAV_IRQ can trigger 2 times (dual buffered)
|
||||
while (hirq & HIRQ_RCVDAV_IRQ) {
|
||||
uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
|
||||
const uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
|
||||
xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
|
||||
if (xact_len) {
|
||||
fifo_read(rhport, ep->buf, xact_len, in_isr);
|
||||
hwfifo_receive(rhport, ep->buf, xact_len, in_isr);
|
||||
ep->buf += xact_len;
|
||||
ep->xferred_len += xact_len;
|
||||
}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user