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clean up
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parent
451a415663
commit
2d041aaa1d
@ -60,15 +60,13 @@
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// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#define TU_BREAKPOINT() do \
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{ \
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volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
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if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
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} while(0)
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#define TU_BREAKPOINT() do \
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{ \
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volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
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if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
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} while(0)
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#else
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#define TU_BREAKPOINT()
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#define TU_BREAKPOINT()
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#endif
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/*------------------------------------------------------------------*/
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@ -69,7 +69,7 @@
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* - M3/M4 can transfer nbytes = 1023 (maximum)
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*/
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enum {
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#ifdef __ARM_ARCH_6M__ // Cortex M0/M0+
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#if __ARM_ARCH_6M__ == 1 // Cortex M0/M0+
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DMA_NBYTES_MAX = 64
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#else
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DMA_NBYTES_MAX = 1023
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