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Merge pull request #528 from jgressmann/port-atsame51-to-tinyusb
Adds files for the open source D5035-01 hardware
This commit is contained in:
Ha Thach
GitHub
commit
30c23719f6
@ -4,7 +4,7 @@ The board support code is only used for self-contained examples and testing. It
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- One LED : for status
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- One Button : to get input from user
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- One UART : optional for device, but required for host examples
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## Supported Boards
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This code base already had supported for a handful of following boards (sorted alphabetically)
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@ -28,6 +28,7 @@ This code base already had supported for a handful of following boards (sorted a
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- [Adafruit ItsyBitsy M4 Express](https://www.adafruit.com/product/3800)
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- [Adafruit Metro M0 Express](https://www.adafruit.com/product/3505)
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- [Adafruit Metro M4 Express](https://www.adafruit.com/product/3382)
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- [D5035-01](https://github.com/RudolphRiedel/USB_CAN-FD)
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- [Great Scott Gadgets LUNA](https://greatscottgadgets.com/luna/)
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- [Microchip SAMD11 Xplained](https://www.microchip.com/developmenttools/ProductDetails/atsamd11-xpro)
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- [Microchip SAMG55 Xplained Pro Evaluation Kit](https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO)
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@ -114,7 +115,7 @@ This code base already had supported for a handful of following boards (sorted a
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### TI
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- [MSP430F5529 USB LaunchPad Evaluation Kit](http://www.ti.com/tool/MSP-EXP430F5529LP)
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### Tomu
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- [Fomu](https://www.crowdsupply.com/sutajio-kosagi/fomu)
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@ -1,4 +1,4 @@
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/*
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020, Ha Thach (tinyusb.org)
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@ -52,7 +52,8 @@
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#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
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#include "nrf.h"
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#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || CFG_TUSB_MCU == OPT_MCU_SAMD51
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#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
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CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X
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#include "sam.h"
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#elif CFG_TUSB_MCU == OPT_MCU_SAMG
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63
hw/bsp/d5035_01/board.mk
Normal file
63
hw/bsp/d5035_01/board.mk
Normal file
@ -0,0 +1,63 @@
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mlong-calls \
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-mcpu=cortex-m4 \
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-mfloat-abi=hard \
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-mfpu=fpv4-sp-d16 \
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-nostdlib -nostartfiles \
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-D__SAME51J19A__ \
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-DCONF_CPU_FREQUENCY=80000000 \
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-DCONF_GCLK_USB_FREQUENCY=48000000 \
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-DCFG_TUSB_MCU=OPT_MCU_SAME5X \
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-DD5035_01=1 \
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-DBOARD_NAME="\"D5035-01\"" \
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-DSVC_Handler=SVCall_Handler
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HWREV ?= 1
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CFLAGS += -DHWREV=$(HWREV)
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
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SRC_C += \
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hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \
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hw/mcu/microchip/same51/gcc/system_same51.c \
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ifdef SYSCALLS
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ifneq ($(SYSCALLS),0)
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SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
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endif
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endif
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ifdef LOG
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ifneq ($(LOG),0)
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SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
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endif
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endif
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INC += \
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$(TOP)/hw/mcu/microchip/same51/ \
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$(TOP)/hw/mcu/microchip/same51/config \
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$(TOP)/hw/mcu/microchip/same51/include \
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$(TOP)/hw/mcu/microchip/same51/hal/include \
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$(TOP)/hw/mcu/microchip/same51/hal/utils/include \
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$(TOP)/hw/mcu/microchip/same51/hpl/port \
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$(TOP)/hw/mcu/microchip/same51/hri \
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$(TOP)/hw/mcu/microchip/same51/CMSIS/Core/Include
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# For TinyUSB port source
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VENDOR = microchip
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CHIP_FAMILY = samd
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM4F
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# For flash-jlink target
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JLINK_DEVICE = ATSAME51J19
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JLINK_IF = swd
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# flash using jlink
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flash: flash-jlink
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353
hw/bsp/d5035_01/d5035_01.c
Normal file
353
hw/bsp/d5035_01/d5035_01.c
Normal file
@ -0,0 +1,353 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Jean Gressmann <jean@0x42.de>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include <sam.h>
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#include "bsp/board.h"
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#include <hal/include/hal_gpio.h>
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#if CONF_CPU_FREQUENCY != 80000000
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# error "CONF_CPU_FREQUENCY" must 80000000
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#endif
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#if CONF_GCLK_USB_FREQUENCY != 48000000
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# error "CONF_GCLK_USB_FREQUENCY" must 48000000
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#endif
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#if !defined(HWREV)
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# error Define "HWREV"
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#endif
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void USB_0_Handler (void)
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{
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tud_int_handler(0);
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}
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void USB_1_Handler (void)
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{
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tud_int_handler(0);
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}
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void USB_2_Handler (void)
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{
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tud_int_handler(0);
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}
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void USB_3_Handler (void)
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{
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tud_int_handler(0);
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}
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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#define LED_PIN PIN_PA02
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#if HWREV < 3
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# define BOARD_SERCOM SERCOM5
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#else
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# define BOARD_SERCOM SERCOM0
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#endif
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static inline void init_clock(void)
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{
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/* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */
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#if HWREV == 1
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/* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */
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OSCCTRL->XOSCCTRL[1].reg =
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OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms
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OSCCTRL_XOSCCTRL_RUNSTDBY |
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OSCCTRL_XOSCCTRL_ENALC |
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OSCCTRL_XOSCCTRL_IMULT(4) |
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OSCCTRL_XOSCCTRL_IPTAT(3) |
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OSCCTRL_XOSCCTRL_XTALEN |
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OSCCTRL_XOSCCTRL_ENABLE;
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while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
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while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
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OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */
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OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
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while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
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#else // HWREV >= 1
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/* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */
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OSCCTRL->XOSCCTRL[0].reg =
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OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms
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OSCCTRL_XOSCCTRL_RUNSTDBY |
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OSCCTRL_XOSCCTRL_ENALC |
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OSCCTRL_XOSCCTRL_IMULT(4) |
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OSCCTRL_XOSCCTRL_IPTAT(3) |
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OSCCTRL_XOSCCTRL_XTALEN |
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OSCCTRL_XOSCCTRL_ENABLE;
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while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
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while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
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OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */
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OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
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while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
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#endif // HWREV
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/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
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GCLK->GENCTRL[0].reg =
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GCLK_GENCTRL_DIV(0) |
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GCLK_GENCTRL_RUNSTDBY |
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GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_DPLL0 | /* DPLL0 */
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GCLK_GENCTRL_IDC ;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
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/* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
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GCLK->GENCTRL[1].reg =
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GCLK_GENCTRL_DIV(0) |
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GCLK_GENCTRL_RUNSTDBY |
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GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_DPLL1 |
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GCLK_GENCTRL_IDC ;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
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/* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */
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GCLK->GENCTRL[2].reg =
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GCLK_GENCTRL_DIV(1) | /* 80MHz */
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GCLK_GENCTRL_RUNSTDBY |
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GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_DPLL0 |
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GCLK_GENCTRL_IDC ;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
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}
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static inline void uart_init(void)
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{
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#if HWREV < 3
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/* configure SERCOM5 on PB02 */
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PORT->Group[1].WRCONFIG.reg =
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PORT_WRCONFIG_WRPINCFG |
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PORT_WRCONFIG_WRPMUX |
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PORT_WRCONFIG_PMUX(3) | /* function D */
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PORT_WRCONFIG_DRVSTR |
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PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */
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PORT_WRCONFIG_PMUXEN;
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MCLK->APBDMASK.bit.SERCOM5_ = 1;
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GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
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SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
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while(SERCOM5->USART.SYNCBUSY.bit.ENABLE);
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SERCOM5->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
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SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
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// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
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SERCOM_USART_CTRLA_DORD | /* LSB first */
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SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
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SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
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SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
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SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
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SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
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SERCOM5->USART.CTRLC.reg = 0x00;
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// 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
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SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
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// SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
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SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
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while(SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
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#else
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/* configure SERCOM0 on PA08 */
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PORT->Group[0].WRCONFIG.reg =
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PORT_WRCONFIG_WRPINCFG |
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PORT_WRCONFIG_WRPMUX |
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PORT_WRCONFIG_PMUX(2) | /* function C */
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PORT_WRCONFIG_DRVSTR |
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PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */
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PORT_WRCONFIG_PMUXEN;
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MCLK->APBAMASK.bit.SERCOM0_ = 1;
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GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
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SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
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while(SERCOM0->USART.SYNCBUSY.bit.ENABLE);
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SERCOM0->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
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SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
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// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
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SERCOM_USART_CTRLA_DORD | /* LSB first */
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SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
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SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
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SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
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SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
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SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
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SERCOM0->USART.CTRLC.reg = 0x00;
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// 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
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SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
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// SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
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SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
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while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
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#endif
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}
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static inline void uart_send_buffer(uint8_t const *text, size_t len)
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{
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for (size_t i = 0; i < len; ++i) {
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BOARD_SERCOM->USART.DATA.reg = text[i];
|
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while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
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}
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}
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static inline void uart_send_str(const char* text)
|
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{
|
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while (*text) {
|
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BOARD_SERCOM->USART.DATA.reg = *text++;
|
||||
while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
|
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}
|
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}
|
||||
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void board_init(void)
|
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{
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init_clock();
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||||
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||||
SystemCoreClock = CONF_CPU_FREQUENCY;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config(CONF_CPU_FREQUENCY / 1000);
|
||||
#endif
|
||||
|
||||
uart_init();
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
uart_send_str(BOARD_NAME " UART initialized\n");
|
||||
tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
|
||||
#endif
|
||||
|
||||
// Led init
|
||||
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(LED_PIN, 0);
|
||||
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
uart_send_str(BOARD_NAME " LED pin configured\n");
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
|
||||
#if TUSB_OPT_DEVICE_ENABLED
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
uart_send_str(BOARD_NAME " USB device enabled\n");
|
||||
#endif
|
||||
|
||||
/* USB clock init
|
||||
* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
|
||||
* for low speed and full speed operation. */
|
||||
hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
|
||||
hri_mclk_set_AHBMASK_USB_bit(MCLK);
|
||||
hri_mclk_set_APBBMASK_USB_bit(MCLK);
|
||||
|
||||
// USB pin init
|
||||
gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(PIN_PA24, false);
|
||||
gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
|
||||
gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(PIN_PA25, false);
|
||||
gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
|
||||
|
||||
gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
|
||||
gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
|
||||
|
||||
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
uart_send_str(BOARD_NAME " USB device configured\n");
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
gpio_set_pin_level(LED_PIN, state);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
// this board has no button
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
(void) buf; (void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const * buf, int len)
|
||||
{
|
||||
if (len < 0) {
|
||||
uart_send_str(buf);
|
||||
} else {
|
||||
uart_send_buffer(buf, len);
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Required by __libc_init_array in startup code if we are compiling using
|
||||
// -nostdlib/-nostartfiles.
|
||||
void _init(void)
|
||||
{
|
||||
|
||||
}
|
||||
163
hw/bsp/d5035_01/same51j19a_flash.ld
Normal file
163
hw/bsp/d5035_01/same51j19a_flash.ld
Normal file
@ -0,0 +1,163 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
@ -1 +1 @@
|
||||
Subproject commit 168322aa7100f60d6837505f5705fd61454dac27
|
||||
Subproject commit df9970f6c26967ace144a83219cf7378831f6181
|
||||
Loading…
x
Reference in New Issue
Block a user