From 61aacf07d62a0d927e500bf2f39acae4609b9fc4 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Mon, 5 Oct 2020 18:35:35 +0200 Subject: [PATCH 1/7] Adds files for the open source D5035-01 hardware The board's files are here: https://github.com/RudolphRiedel/USB_CAN-FD --- hw/bsp/board_mcu.h | 10 +- hw/bsp/d5035-01/board.mk | 61 +++++ hw/bsp/d5035-01/d5035_01.c | 353 +++++++++++++++++++++++++ hw/bsp/d5035-01/same51j19a_flash.ld | 163 ++++++++++++ hw/mcu/microchip | 2 +- src/portable/microchip/samd/dcd_samd.c | 6 +- src/tusb_option.h | 1 + 7 files changed, 591 insertions(+), 5 deletions(-) create mode 100644 hw/bsp/d5035-01/board.mk create mode 100644 hw/bsp/d5035-01/d5035_01.c create mode 100644 hw/bsp/d5035-01/same51j19a_flash.ld diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 3382d465d..6585ef9a6 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020, Ha Thach (tinyusb.org) @@ -52,9 +52,15 @@ #elif CFG_TUSB_MCU == OPT_MCU_NRF5X #include "nrf.h" -#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || CFG_TUSB_MCU == OPT_MCU_SAMD51 +#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ + CFG_TUSB_MCU == OPT_MCU_SAME51 #include "sam.h" + #if CFG_TUSB_MCU == OPT_MCU_SAME51 + #define SVC_Handler SVCall_Handler + #endif + #elif CFG_TUSB_MCU == OPT_MCU_SAMG #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined #include "sam.h" diff --git a/hw/bsp/d5035-01/board.mk b/hw/bsp/d5035-01/board.mk new file mode 100644 index 000000000..cbc653d19 --- /dev/null +++ b/hw/bsp/d5035-01/board.mk @@ -0,0 +1,61 @@ +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -mlong-calls \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -nostdlib -nostartfiles \ + -D__SAME51J19A__ \ + -DCONF_CPU_FREQUENCY=80000000 \ + -DCONF_GCLK_USB_FREQUENCY=48000000 \ + -DCFG_TUSB_MCU=OPT_MCU_SAME51 \ + -DD5035_01=1 \ + -DBOARD_NAME="\"D5035-01\"" + +ifdef HWREV + CFLAGS += -DHWREV=$(HWREV) +endif + +# All source paths should be relative to the top level. +LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld + +SRC_C += \ + hw/mcu/microchip/same/asf4/same51/gcc/gcc/startup_same51.c \ + hw/mcu/microchip/same/asf4/same51/gcc/system_same51.c \ + +ifdef SYSCALLS +ifneq ($(SYSCALLS),0) + SRC_C += hw/mcu/microchip/same/asf4/same51/hal/utils/src/utils_syscalls.c +endif +endif + +ifdef LOG +ifneq ($(LOG),0) + SRC_C += hw/mcu/microchip/same/asf4/same51/hal/utils/src/utils_syscalls.c +endif +endif + +INC += \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/ \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/config \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/include \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/hal/include \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/hal/utils/include \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/hpl/port \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/hri \ + $(TOP)/hw/mcu/microchip/same/asf4/same51/CMSIS/Core/Include + +# For TinyUSB port source +VENDOR = microchip +CHIP_FAMILY = samd + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM4F + +# For flash-jlink target +JLINK_DEVICE = ATSAME51J19 +JLINK_IF = swd + +# flash using jlink +flash: flash-jlink diff --git a/hw/bsp/d5035-01/d5035_01.c b/hw/bsp/d5035-01/d5035_01.c new file mode 100644 index 000000000..5685ff16f --- /dev/null +++ b/hw/bsp/d5035-01/d5035_01.c @@ -0,0 +1,353 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Jean Gressmann + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include "bsp/board.h" + +#include + +#if CONF_CPU_FREQUENCY != 80000000 +# error "CONF_CPU_FREQUENCY" must 80000000 +#endif + +#if CONF_GCLK_USB_FREQUENCY != 48000000 +# error "CONF_GCLK_USB_FREQUENCY" must 48000000 +#endif + +#if !defined(HWREV) +# error Define "HWREV" +#endif + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_0_Handler (void) +{ + tud_int_handler(0); +} + +void USB_1_Handler (void) +{ + tud_int_handler(0); +} + +void USB_2_Handler (void) +{ + tud_int_handler(0); +} + +void USB_3_Handler (void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +#define LED_PIN PIN_PA02 + +#if HWREV < 3 +# define BOARD_SERCOM SERCOM5 +#else +# define BOARD_SERCOM SERCOM0 +#endif + +static inline void init_clock(void) +{ + /* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */ +#if HWREV == 1 + /* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */ + OSCCTRL->XOSCCTRL[1].reg = + OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms + OSCCTRL_XOSCCTRL_RUNSTDBY | + OSCCTRL_XOSCCTRL_ENALC | + OSCCTRL_XOSCCTRL_IMULT(4) | + OSCCTRL_XOSCCTRL_IPTAT(3) | + OSCCTRL_XOSCCTRL_XTALEN | + OSCCTRL_XOSCCTRL_ENABLE; + while(0 == OSCCTRL->STATUS.bit.XOSCRDY1); + + OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */ + OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */ + OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; + while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */ + + OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */ + OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */ + OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; + while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */ +#else // HWREV >= 1 + /* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */ + OSCCTRL->XOSCCTRL[0].reg = + OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms + OSCCTRL_XOSCCTRL_RUNSTDBY | + OSCCTRL_XOSCCTRL_ENALC | + OSCCTRL_XOSCCTRL_IMULT(4) | + OSCCTRL_XOSCCTRL_IPTAT(3) | + OSCCTRL_XOSCCTRL_XTALEN | + OSCCTRL_XOSCCTRL_ENABLE; + while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + + OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */ + OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */ + OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; + while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */ + + OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */ + OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */ + OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; + while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */ +#endif // HWREV + + /* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */ + GCLK->GENCTRL[0].reg = + GCLK_GENCTRL_DIV(0) | + GCLK_GENCTRL_RUNSTDBY | + GCLK_GENCTRL_GENEN | + GCLK_GENCTRL_SRC_DPLL0 | /* DPLL0 */ + GCLK_GENCTRL_IDC ; + while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */ + + /* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */ + GCLK->GENCTRL[1].reg = + GCLK_GENCTRL_DIV(0) | + GCLK_GENCTRL_RUNSTDBY | + GCLK_GENCTRL_GENEN | + GCLK_GENCTRL_SRC_DPLL1 | + GCLK_GENCTRL_IDC ; + while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */ + + /* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */ + GCLK->GENCTRL[2].reg = + GCLK_GENCTRL_DIV(1) | /* 80MHz */ + GCLK_GENCTRL_RUNSTDBY | + GCLK_GENCTRL_GENEN | + GCLK_GENCTRL_SRC_DPLL0 | + GCLK_GENCTRL_IDC ; + while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */ +} + +static inline void uart_init(void) +{ +#if HWREV < 3 + /* configure SERCOM5 on PB02 */ + PORT->Group[1].WRCONFIG.reg = + PORT_WRCONFIG_WRPINCFG | + PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_PMUX(3) | /* function D */ + PORT_WRCONFIG_DRVSTR | + PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */ + PORT_WRCONFIG_PMUXEN; + + MCLK->APBDMASK.bit.SERCOM5_ = 1; + GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */ + + SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */ + while(SERCOM5->USART.SYNCBUSY.bit.ENABLE); + + SERCOM5->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */ + SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */ +// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */ + SERCOM_USART_CTRLA_DORD | /* LSB first */ + SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */ + SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */ + SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */ + + SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */ + SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */ + SERCOM5->USART.CTRLC.reg = 0x00; + // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E + SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21); + +// SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */ + while(SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */ +#else +/* configure SERCOM0 on PA08 */ + PORT->Group[0].WRCONFIG.reg = + PORT_WRCONFIG_WRPINCFG | + PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_PMUX(2) | /* function C */ + PORT_WRCONFIG_DRVSTR | + PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */ + PORT_WRCONFIG_PMUXEN; + + MCLK->APBAMASK.bit.SERCOM0_ = 1; + GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */ + + SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */ + while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); + + SERCOM0->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */ + SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */ +// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */ + SERCOM_USART_CTRLA_DORD | /* LSB first */ + SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */ + SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */ + SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */ + + SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */ + SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */ + SERCOM0->USART.CTRLC.reg = 0x00; + // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E + SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21); + +// SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */ + while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */ +#endif +} + +static inline void uart_send_buffer(uint8_t const *text, size_t len) +{ + for (size_t i = 0; i < len; ++i) { + BOARD_SERCOM->USART.DATA.reg = text[i]; + while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0); + } +} + +static inline void uart_send_str(const char* text) +{ + while (*text) { + BOARD_SERCOM->USART.DATA.reg = *text++; + while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0); + } +} + + +void board_init(void) +{ + init_clock(); + + SystemCoreClock = CONF_CPU_FREQUENCY; + +#if CFG_TUSB_OS == OPT_OS_NONE + SysTick_Config(CONF_CPU_FREQUENCY / 1000); +#endif + + uart_init(); +#if CFG_TUSB_DEBUG >= 2 + uart_send_str(BOARD_NAME " UART initialized\n"); + tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg); +#endif + + // Led init + gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_level(LED_PIN, 0); + +#if CFG_TUSB_DEBUG >= 2 + uart_send_str(BOARD_NAME " LED pin configured\n"); +#endif + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + +#if TUSB_OPT_DEVICE_ENABLED +#if CFG_TUSB_DEBUG >= 2 + uart_send_str(BOARD_NAME " USB device enabled\n"); +#endif + + /* USB clock init + * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock + * for low speed and full speed operation. */ + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); + + // USB pin init + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA24, false); + gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA25, false); + gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); + + gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); + + +#if CFG_TUSB_DEBUG >= 2 + uart_send_str(BOARD_NAME " USB device configured\n"); +#endif +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + gpio_set_pin_level(LED_PIN, state); +} + +uint32_t board_button_read(void) +{ + // this board has no button + return 0; +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + if (len < 0) { + uart_send_str(buf); + } else { + uart_send_buffer(buf, len); + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} diff --git a/hw/bsp/d5035-01/same51j19a_flash.ld b/hw/bsp/d5035-01/same51j19a_flash.ld new file mode 100644 index 000000000..328d1c72f --- /dev/null +++ b/hw/bsp/d5035-01/same51j19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME51J19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/hw/mcu/microchip b/hw/mcu/microchip index 168322aa7..c5dc8b65d 160000 --- a/hw/mcu/microchip +++ b/hw/mcu/microchip @@ -1 +1 @@ -Subproject commit 168322aa7100f60d6837505f5705fd61454dac27 +Subproject commit c5dc8b65d4ab37b0ec8b2bc7fbd46a6aecc0ff43 diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index f1dca88a5..460be3ac2 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -28,7 +28,8 @@ #if TUSB_OPT_DEVICE_ENABLED && \ (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X) + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ + CFG_TUSB_MCU == OPT_MCU_SAME51) #include "sam.h" #include "device/dcd.h" @@ -94,7 +95,8 @@ void dcd_init (uint8_t rhport) USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST; } -#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X +#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ + CFG_TUSB_MCU == OPT_MCU_SAME51 void dcd_int_enable(uint8_t rhport) { diff --git a/src/tusb_option.h b/src/tusb_option.h index 7e486bff0..70ef4de8c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -59,6 +59,7 @@ #define OPT_MCU_SAMD21 200 ///< MicroChip SAMD21 #define OPT_MCU_SAMD51 201 ///< MicroChip SAMD51 #define OPT_MCU_SAME5X 203 ///< MicroChip SAM E5x +#define OPT_MCU_SAME51 205 ///< MicroChip SAME51 #define OPT_MCU_SAMG 202 ///< MicroChip SAMDG series // STM32 From 862f6ac81ec3ff5bc7708204268e535f7f3d7732 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Mon, 5 Oct 2020 20:06:39 +0200 Subject: [PATCH 2/7] Update Microchip submodule commit --- hw/mcu/microchip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mcu/microchip b/hw/mcu/microchip index c5dc8b65d..df9970f6c 160000 --- a/hw/mcu/microchip +++ b/hw/mcu/microchip @@ -1 +1 @@ -Subproject commit c5dc8b65d4ab37b0ec8b2bc7fbd46a6aecc0ff43 +Subproject commit df9970f6c26967ace144a83219cf7378831f6181 From 1730a5dcba522600a046837c0aafbf7bd5508dba Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Mon, 5 Oct 2020 20:30:04 +0200 Subject: [PATCH 3/7] D5035-01 bsp: fix paths, default to hw rev 1 (automated build) --- hw/bsp/d5035-01/board.mk | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/hw/bsp/d5035-01/board.mk b/hw/bsp/d5035-01/board.mk index cbc653d19..20ce0fac3 100644 --- a/hw/bsp/d5035-01/board.mk +++ b/hw/bsp/d5035-01/board.mk @@ -15,36 +15,38 @@ CFLAGS += \ ifdef HWREV CFLAGS += -DHWREV=$(HWREV) +else + CFLAGS += -DHWREV=1 endif # All source paths should be relative to the top level. LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld SRC_C += \ - hw/mcu/microchip/same/asf4/same51/gcc/gcc/startup_same51.c \ - hw/mcu/microchip/same/asf4/same51/gcc/system_same51.c \ + hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \ + hw/mcu/microchip/same51/gcc/system_same51.c \ ifdef SYSCALLS ifneq ($(SYSCALLS),0) - SRC_C += hw/mcu/microchip/same/asf4/same51/hal/utils/src/utils_syscalls.c + SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c endif endif ifdef LOG ifneq ($(LOG),0) - SRC_C += hw/mcu/microchip/same/asf4/same51/hal/utils/src/utils_syscalls.c + SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c endif endif INC += \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/ \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/config \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/include \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/hal/include \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/hal/utils/include \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/hpl/port \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/hri \ - $(TOP)/hw/mcu/microchip/same/asf4/same51/CMSIS/Core/Include + $(TOP)/hw/mcu/microchip/same51/ \ + $(TOP)/hw/mcu/microchip/same51/config \ + $(TOP)/hw/mcu/microchip/same51/include \ + $(TOP)/hw/mcu/microchip/same51/hal/include \ + $(TOP)/hw/mcu/microchip/same51/hal/utils/include \ + $(TOP)/hw/mcu/microchip/same51/hpl/port \ + $(TOP)/hw/mcu/microchip/same51/hri \ + $(TOP)/hw/mcu/microchip/same51/CMSIS/Core/Include # For TinyUSB port source VENDOR = microchip From a2379060b6d47eec6d5e9499258bc62eb5a015d7 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Tue, 6 Oct 2020 17:36:11 +0200 Subject: [PATCH 4/7] Adds D5035-01 to the list of supported boards --- docs/boards.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/boards.md b/docs/boards.md index 309f5e5d9..f49b247ac 100644 --- a/docs/boards.md +++ b/docs/boards.md @@ -4,7 +4,7 @@ The board support code is only used for self-contained examples and testing. It - One LED : for status - One Button : to get input from user - One UART : optional for device, but required for host examples - + ## Supported Boards This code base already had supported for a handful of following boards (sorted alphabetically) @@ -28,6 +28,7 @@ This code base already had supported for a handful of following boards (sorted a - [Adafruit ItsyBitsy M4 Express](https://www.adafruit.com/product/3800) - [Adafruit Metro M0 Express](https://www.adafruit.com/product/3505) - [Adafruit Metro M4 Express](https://www.adafruit.com/product/3382) +- [D5035-01](https://github.com/RudolphRiedel/USB_CAN-FD) - [Great Scott Gadgets LUNA](https://greatscottgadgets.com/luna/) - [Microchip SAMD11 Xplained](https://www.microchip.com/developmenttools/ProductDetails/atsamd11-xpro) - [Microchip SAMG55 Xplained Pro Evaluation Kit](https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO) @@ -114,7 +115,7 @@ This code base already had supported for a handful of following boards (sorted a ### TI - [MSP430F5529 USB LaunchPad Evaluation Kit](http://www.ti.com/tool/MSP-EXP430F5529LP) - + ### Tomu - [Fomu](https://www.crowdsupply.com/sutajio-kosagi/fomu) From f92fe1e23e3e8689b6f001c5232a5960acdb3b7f Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Tue, 6 Oct 2020 17:39:36 +0200 Subject: [PATCH 5/7] D5035-01: more natural Makefile variable use --- hw/bsp/d5035-01/board.mk | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/bsp/d5035-01/board.mk b/hw/bsp/d5035-01/board.mk index 20ce0fac3..ac2146475 100644 --- a/hw/bsp/d5035-01/board.mk +++ b/hw/bsp/d5035-01/board.mk @@ -13,11 +13,9 @@ CFLAGS += \ -DD5035_01=1 \ -DBOARD_NAME="\"D5035-01\"" -ifdef HWREV - CFLAGS += -DHWREV=$(HWREV) -else - CFLAGS += -DHWREV=1 -endif +HWREV ?= 1 + +CFLAGS += -DHWREV=$(HWREV) # All source paths should be relative to the top level. LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld From f02b5bfdfaf20a76054dc2f57d37c46de4be6534 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Wed, 7 Oct 2020 19:12:34 +0200 Subject: [PATCH 6/7] Address various issues raised by TinyUSB maintainers - remove OPT_MCU_SAME51 in favor of OPT_MCU_SAME5X and working around differences in the Atmel bsp locally in the D5035-01 bsp. - rename board folder to d5035_01 for consistency with other boards --- hw/bsp/board_mcu.h | 7 +------ hw/bsp/{d5035-01 => d5035_01}/board.mk | 8 +++++--- hw/bsp/{d5035-01 => d5035_01}/d5035_01.c | 0 hw/bsp/{d5035-01 => d5035_01}/same51j19a_flash.ld | 0 src/portable/microchip/samd/dcd_samd.c | 6 ++---- src/tusb_option.h | 1 - 6 files changed, 8 insertions(+), 14 deletions(-) rename hw/bsp/{d5035-01 => d5035_01}/board.mk (92%) rename hw/bsp/{d5035-01 => d5035_01}/d5035_01.c (100%) rename hw/bsp/{d5035-01 => d5035_01}/same51j19a_flash.ld (100%) diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 6585ef9a6..eedae43f7 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -53,14 +53,9 @@ #include "nrf.h" #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAME51 + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X #include "sam.h" - #if CFG_TUSB_MCU == OPT_MCU_SAME51 - #define SVC_Handler SVCall_Handler - #endif - #elif CFG_TUSB_MCU == OPT_MCU_SAMG #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined #include "sam.h" diff --git a/hw/bsp/d5035-01/board.mk b/hw/bsp/d5035_01/board.mk similarity index 92% rename from hw/bsp/d5035-01/board.mk rename to hw/bsp/d5035_01/board.mk index ac2146475..1f2b467a0 100644 --- a/hw/bsp/d5035-01/board.mk +++ b/hw/bsp/d5035_01/board.mk @@ -9,14 +9,16 @@ CFLAGS += \ -D__SAME51J19A__ \ -DCONF_CPU_FREQUENCY=80000000 \ -DCONF_GCLK_USB_FREQUENCY=48000000 \ - -DCFG_TUSB_MCU=OPT_MCU_SAME51 \ + -DCFG_TUSB_MCU=OPT_MCU_SAME5X \ -DD5035_01=1 \ - -DBOARD_NAME="\"D5035-01\"" + -DBOARD_NAME="\"D5035-01\"" \ + -DSVC_Handler=SVCall_Handler -HWREV ?= 1 +HWRED ?= 1 CFLAGS += -DHWREV=$(HWREV) + # All source paths should be relative to the top level. LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld diff --git a/hw/bsp/d5035-01/d5035_01.c b/hw/bsp/d5035_01/d5035_01.c similarity index 100% rename from hw/bsp/d5035-01/d5035_01.c rename to hw/bsp/d5035_01/d5035_01.c diff --git a/hw/bsp/d5035-01/same51j19a_flash.ld b/hw/bsp/d5035_01/same51j19a_flash.ld similarity index 100% rename from hw/bsp/d5035-01/same51j19a_flash.ld rename to hw/bsp/d5035_01/same51j19a_flash.ld diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 460be3ac2..f1dca88a5 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -28,8 +28,7 @@ #if TUSB_OPT_DEVICE_ENABLED && \ (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAME51) + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X) #include "sam.h" #include "device/dcd.h" @@ -95,8 +94,7 @@ void dcd_init (uint8_t rhport) USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST; } -#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAME51 +#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X void dcd_int_enable(uint8_t rhport) { diff --git a/src/tusb_option.h b/src/tusb_option.h index 70ef4de8c..7e486bff0 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -59,7 +59,6 @@ #define OPT_MCU_SAMD21 200 ///< MicroChip SAMD21 #define OPT_MCU_SAMD51 201 ///< MicroChip SAMD51 #define OPT_MCU_SAME5X 203 ///< MicroChip SAM E5x -#define OPT_MCU_SAME51 205 ///< MicroChip SAME51 #define OPT_MCU_SAMG 202 ///< MicroChip SAMDG series // STM32 From 3295b5692b9a5e90c4798b1b72f5e83a7b9a7618 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Wed, 7 Oct 2020 19:26:13 +0200 Subject: [PATCH 7/7] D5035-01 bsp: fix typo --- hw/bsp/d5035_01/board.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk index 1f2b467a0..cbc9ca5bb 100644 --- a/hw/bsp/d5035_01/board.mk +++ b/hw/bsp/d5035_01/board.mk @@ -14,7 +14,7 @@ CFLAGS += \ -DBOARD_NAME="\"D5035-01\"" \ -DSVC_Handler=SVCall_Handler -HWRED ?= 1 +HWREV ?= 1 CFLAGS += -DHWREV=$(HWREV)