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https://github.com/hathach/tinyusb.git
synced 2025-01-31 05:52:55 +08:00
fix portenta build, added core-m85.cmake/mk
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parent
ad0ac6780d
commit
380bfc0a63
25
examples/build_system/cmake/cpu/cortex-m85.cmake
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25
examples/build_system/cmake/cpu/cortex-m85.cmake
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@ -0,0 +1,25 @@
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if (TOOLCHAIN STREQUAL "gcc")
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set(TOOLCHAIN_COMMON_FLAGS
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-mthumb
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-mcpu=cortex-m85
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-mfloat-abi=hard
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-mfpu=fpv5-d16
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)
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set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
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elseif (TOOLCHAIN STREQUAL "clang")
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set(TOOLCHAIN_COMMON_FLAGS
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--target=arm-none-eabi
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-mcpu=cortex-m85
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-mfpu=fpv5-d16
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)
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set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
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elseif (TOOLCHAIN STREQUAL "iar")
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set(TOOLCHAIN_COMMON_FLAGS
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--cpu cortex-m85
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--fpu VFPv5_D16
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)
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set(FREERTOS_PORT IAR_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
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endif ()
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27
examples/build_system/make/cpu/cortex-m85.mk
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27
examples/build_system/make/cpu/cortex-m85.mk
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@ -0,0 +1,27 @@
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ifeq ($(TOOLCHAIN),gcc)
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CFLAGS += \
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-mthumb \
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-mcpu=cortex-m85 \
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-mfloat-abi=hard \
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-mfpu=fpv5-d16 \
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else ifeq ($(TOOLCHAIN),clang)
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CFLAGS += \
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--target=arm-none-eabi \
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-mcpu=cortex-m85 \
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-mfpu=fpv5-d16 \
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else ifeq ($(TOOLCHAIN),iar)
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CFLAGS += \
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--cpu cortex-m85 \
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--fpu VFPv5_D16 \
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ASFLAGS += \
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--cpu cortex-m85 \
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--fpu VFPv5_D16 \
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else
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$(error "TOOLCHAIN is not supported")
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endif
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FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM85_NTZ/non_secure
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@ -4,22 +4,13 @@ set(MCU_VARIANT ra6m5)
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set(JLINK_DEVICE R7FA6M5BH)
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set(DFU_UTIL_VID_PID 2341:0368)
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set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
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# Device port default to PORT1 Highspeed
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if (NOT DEFINED PORT)
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set(PORT 1)
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# device default to PORT 1 High Speed
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if (NOT DEFINED RHPORT_DEVICE)
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set(RHPORT_DEVICE 1)
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endif()
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if (NOT DEFINED RHPORT_HOST)
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set(RHPORT_HOST 0)
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endif()
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# Host port will be the other port
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set(HOST_PORT $<NOT:${PORT}>)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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BOARD_TUD_RHPORT=${PORT}
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BOARD_TUH_RHPORT=${HOST_PORT}
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# port 0 is fullspeed, port 1 is highspeed
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BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
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BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
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)
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endfunction()
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@ -2,7 +2,8 @@ CPU_CORE = cortex-m33
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MCU_VARIANT = ra6m5
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# Port 1 is highspeed
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PORT ?= 1
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RHPORT_DEVICE ?= 1
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RHPORT_HOST ?= 0
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JLINK_DEVICE = R7FA6M5BH
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DFU_UTIL_OPTION = -d 2341:0368 -a 0
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@ -0,0 +1,17 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_PIN_CFG_H_
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#define BSP_PIN_CFG_H_
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#include "r_ioport.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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#define LED1 (BSP_IO_PORT_01_PIN_07)
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#define SW1 (BSP_IO_PORT_04_PIN_08)
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extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
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void BSP_PinConfigSecurityInit();
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif /* BSP_PIN_CFG_H_ */
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11
hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
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11
hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
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@ -0,0 +1,11 @@
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/* generated common source file - do not edit */
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#include "common_data.h"
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ioport_instance_ctrl_t g_ioport_ctrl;
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const ioport_instance_t g_ioport =
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{
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.p_api = &g_ioport_on_ioport,
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.p_ctrl = &g_ioport_ctrl,
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.p_cfg = &g_bsp_pin_cfg,
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};
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void g_common_init(void) {
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}
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20
hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
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20
hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
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@ -0,0 +1,20 @@
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/* generated common header file - do not edit */
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#ifndef COMMON_DATA_H_
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#define COMMON_DATA_H_
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#include <stdint.h>
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#include "bsp_api.h"
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#include "r_ioport.h"
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#include "bsp_pin_cfg.h"
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FSP_HEADER
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#define IOPORT_CFG_NAME g_bsp_pin_cfg
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#define IOPORT_CFG_OPEN R_IOPORT_Open
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#define IOPORT_CFG_CTRL g_ioport_ctrl
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/* IOPORT Instance */
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extern const ioport_instance_t g_ioport;
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/* IOPORT control structure. */
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extern ioport_instance_ctrl_t g_ioport_ctrl;
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void g_common_init(void);
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FSP_FOOTER
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#endif /* COMMON_DATA_H_ */
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71
hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
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71
hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
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@ -0,0 +1,71 @@
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/* generated pin source file - do not edit */
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#include "bsp_api.h"
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#include "r_ioport.h"
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const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
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{
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.pin = BSP_IO_PORT_01_PIN_07,
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.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
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},
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{
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.pin = BSP_IO_PORT_01_PIN_08,
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.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
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},
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{
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.pin = BSP_IO_PORT_03_PIN_00,
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.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
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},
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{
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.pin = BSP_IO_PORT_04_PIN_07,
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.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
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},
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{
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.pin = BSP_IO_PORT_04_PIN_08,
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.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
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},
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{
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.pin = BSP_IO_PORT_11_PIN_01,
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.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
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},
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};
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const ioport_cfg_t g_bsp_pin_cfg = {
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.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
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.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
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};
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#if BSP_TZ_SECURE_BUILD
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void R_BSP_PinCfgSecurityInit(void);
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/* Initialize SAR registers for secure pins. */
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void R_BSP_PinCfgSecurityInit(void)
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{
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#if (2U == BSP_FEATURE_IOPORT_VERSION)
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uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
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#else
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uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
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#endif
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memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
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for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
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{
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uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
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uint32_t port = port_pin >> 8U;
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uint32_t pin = port_pin & 0xFFU;
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pmsar[port] &= (uint16_t) ~(1U << pin);
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}
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for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
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{
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#if (2U == BSP_FEATURE_IOPORT_VERSION)
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R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
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#else
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R_PMISC->PMSAR[i].PMSAR = pmsar[i];
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#endif
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}
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}
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#endif
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