diff --git a/examples/build_system/cmake/cpu/cortex-m85.cmake b/examples/build_system/cmake/cpu/cortex-m85.cmake
new file mode 100644
index 000000000..30314acbc
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m85.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m85
+    -mfloat-abi=hard
+    -mfpu=fpv5-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=cortex-m85
+    -mfpu=fpv5-d16
+    )
+  set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m85
+    --fpu VFPv5_D16
+    )
+  set(FREERTOS_PORT IAR_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/make/cpu/cortex-m85.mk b/examples/build_system/make/cpu/cortex-m85.mk
new file mode 100644
index 000000000..75e8f3aaf
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m85.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m85 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m85 \
+	  -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+  	--cpu cortex-m85 \
+  	--fpu VFPv5_D16 \
+
+  ASFLAGS += \
+		--cpu cortex-m85 \
+		--fpu VFPv5_D16 \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM85_NTZ/non_secure
diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake
index 1837d8450..520686daa 100644
--- a/hw/bsp/ra/boards/portenta_c33/board.cmake
+++ b/hw/bsp/ra/boards/portenta_c33/board.cmake
@@ -4,22 +4,13 @@ set(MCU_VARIANT ra6m5)
 set(JLINK_DEVICE R7FA6M5BH)
 set(DFU_UTIL_VID_PID 2341:0368)
 
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
-
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-set(PORT 1)
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
 endif()
 
-# Host port will be the other port
-set(HOST_PORT $<NOT:${PORT}>)
-
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    BOARD_TUD_RHPORT=${PORT}
-    BOARD_TUH_RHPORT=${HOST_PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
 endfunction()
diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk
index 4da34306e..ab814cda6 100644
--- a/hw/bsp/ra/boards/portenta_c33/board.mk
+++ b/hw/bsp/ra/boards/portenta_c33/board.mk
@@ -2,7 +2,8 @@ CPU_CORE = cortex-m33
 MCU_VARIANT = ra6m5
 
 # Port 1 is highspeed
-PORT ?= 1
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
 
 JLINK_DEVICE = R7FA6M5BH
 DFU_UTIL_OPTION = -d 2341:0368 -a 0
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..c411386c1
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_01_PIN_07)
+#define SW1 (BSP_IO_PORT_04_PIN_08)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
new file mode 100644
index 000000000..50036c0ad
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+        {
+            .p_api = &g_ioport_on_ioport,
+            .p_ctrl = &g_ioport_ctrl,
+            .p_cfg = &g_bsp_pin_cfg,
+        };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
new file mode 100644
index 000000000..6a08cbee0
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
new file mode 100644
index 000000000..fad79741a
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
@@ -0,0 +1,71 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+    {
+        .pin = BSP_IO_PORT_01_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+    },
+    {
+        .pin = BSP_IO_PORT_01_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_03_PIN_00,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_07,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+    },
+    {
+        .pin = BSP_IO_PORT_04_PIN_08,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+    },
+    {
+        .pin = BSP_IO_PORT_11_PIN_01,
+        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+    },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+    .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+    }
+
+}
+#endif