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update qspi
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parent
154daf584c
commit
3b79ba8451
@ -68,28 +68,24 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
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{
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uint32_t addr = lba * CFG_TUD_MSC_BLOCK_SZ + offset;
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switch ( _fl_state )
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{
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case FLASH_STATE_IDLE:
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_fl_state = FLASH_STATE_BUSY;
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flash_read(buffer, addr, bufsize);
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return 0; // data not ready
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// switch ( _fl_state )
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// {
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// case FLASH_STATE_IDLE:
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// _fl_state = FLASH_STATE_BUSY;
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// flash_read(buffer, addr, bufsize);
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// return 0; // data not ready
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//
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// case FLASH_STATE_BUSY:
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// return 0; // data not ready
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//
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// case FLASH_STATE_COMPLETE:
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// _fl_state = FLASH_STATE_IDLE;
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// return bufsize;
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//
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// default:
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// _fl_state = FLASH_STATE_IDLE;
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// return -1;
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// }
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case FLASH_STATE_BUSY:
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return 0; // data not ready
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flash_read(buffer, addr, bufsize);
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return bufsize;
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case FLASH_STATE_COMPLETE:
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_fl_state = FLASH_STATE_IDLE;
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return bufsize;
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default:
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_fl_state = FLASH_STATE_IDLE;
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return -1;
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}
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}
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// Callback invoked when received WRITE10 command.
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@ -128,16 +124,16 @@ void flash_flush (void)
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if ( _fl_addr == NO_CACHE ) return;
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TU_ASSERT(NRFX_SUCCESS == nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, _fl_addr),);
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// while ( _fl_state != FLASH_STATE_COMPLETE )
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// {
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// }
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// _fl_state = FLASH_STATE_IDLE;
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while ( _fl_state != FLASH_STATE_COMPLETE )
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{
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}
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_fl_state = FLASH_STATE_IDLE;
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TU_ASSERT(NRFX_SUCCESS == nrfx_qspi_write(_fl_buf, FLASH_PAGE_SIZE, _fl_addr),);
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// while ( _fl_state != FLASH_STATE_COMPLETE )
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// {
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// }
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// _fl_state = FLASH_STATE_IDLE;
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while ( _fl_state != FLASH_STATE_COMPLETE )
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{
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}
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_fl_state = FLASH_STATE_IDLE;
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_fl_addr = NO_CACHE;
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}
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@ -153,6 +149,7 @@ void flash_write (uint32_t dst, const void *src, int len)
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flash_read(_fl_buf, newAddr, FLASH_PAGE_SIZE);
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}
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memcpy(_fl_buf + (dst & (FLASH_PAGE_SIZE - 1)), src, len);
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}
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@ -127,12 +127,12 @@ void board_init(void)
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},
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.prot_if = {
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.readoc = NRF_QSPI_READOC_READ4IO,
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.writeoc = NRF_QSPI_WRITEOC_PP,
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.writeoc = NRF_QSPI_WRITEOC_PP4IO,
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.addrmode = NRF_QSPI_ADDRMODE_24BIT,
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.dpmconfig = false, // deep power down
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},
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.phy_if = {
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.sck_freq = NRF_QSPI_FREQ_32MDIV4,
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.sck_freq = NRF_QSPI_FREQ_32MDIV1,
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.sck_delay = 1,
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.spi_mode = NRF_QSPI_MODE_0,
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.dpmen = false
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@ -140,8 +140,7 @@ void board_init(void)
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.irq_priority = 7,
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};
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nrfx_qspi_init(&qspi_cfg, NULL, NULL);
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// nrfx_qspi_init(&qspi_cfg, qflash_hdl, NULL);
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nrfx_qspi_init(&qspi_cfg, qflash_hdl, NULL);
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = 0,
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