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Disable ULPI clock during sleep on stm32f7 when using internal phy
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@ -149,7 +149,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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// https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
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// https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
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// H7 running on full-speed phy need to disable ULPI clock in sleep mode.
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// H7 running on full-speed phy need to disable ULPI clock in sleep mode.
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// Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS.
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// Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS.
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// Note: there may be other family that is affected by this, but only H7 is tested so far
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// Note: there may be other family that is affected by this, but only H7 and F7 is tested so far
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#if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN)
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#if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN)
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if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) {
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if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) {
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RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN;
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RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN;
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@ -161,6 +161,13 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN;
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RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN;
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}
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}
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#endif
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#endif
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#if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_OTGHSULPILPEN)
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if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
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RCC->AHB1LPENR &= ~RCC_AHB1LPENR_OTGHSULPILPEN;
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}
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#endif
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} else {
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} else {
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#if CFG_TUSB_MCU != OPT_MCU_STM32U5
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#if CFG_TUSB_MCU != OPT_MCU_STM32U5
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// Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
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// Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
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