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https://github.com/hathach/tinyusb.git
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feature(dcd_dwc2): Added cache synchronization
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@ -47,20 +47,7 @@
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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#ifdef DWC2_MEM_CACHE_LINE_SIZE
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CFG_TUD_MEM_SECTION struct {
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union {
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uint32_t data[2];
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uint8_t buffer[DWC2_MEM_CACHE_LINE_SIZE];
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};
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} _cache_aligned_setup_packet;
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#define _setup_packet _cache_aligned_setup_packet.data
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#define _sizeof_setup_packet() DWC2_MEM_CACHE_LINE_SIZE
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#else
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static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
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#define _sizeof_setup_packet() sizeof(_setup_packet)
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#endif // DWC2_MEM_CACHE_LINE_SIZE
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typedef struct {
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uint8_t* buffer;
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@ -361,11 +348,6 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
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const bool is_dma = dma_device_enabled(dwc2);
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if(is_dma) {
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if (dir == TUSB_DIR_IN && total_bytes != 0) {
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// CACHE HINT
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// The xfer->buffer has new data for Host, move it to memory for DMA to transfer it
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dcd_dcache_clean(xfer->buffer, total_bytes);
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}
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dep->diepdma = (uintptr_t) xfer->buffer;
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}
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@ -865,11 +847,6 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
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if (doepint_bm.setup_phase_done) {
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dma_setup_prepare(rhport);
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// CACHE HINT
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// When cache is enabled, _setup_packet must have cache line size alignment
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// and there should be no valuable data in memory after.
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// Thus, specific struct is used as a buffer for setup packet data
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dcd_dcache_invalidate((uint8_t*) _setup_packet, _sizeof_setup_packet());
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dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
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return;
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}
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@ -895,9 +872,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
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if(epnum == 0 && xfer->total_len == 0) {
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dma_setup_prepare(rhport);
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}
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// CACHE HINT
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// Some data has been received by DMA, fetch the data from memory to cache
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dcd_dcache_invalidate(xfer->buffer, xfer->total_len);
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dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
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}
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}
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@ -39,14 +39,6 @@
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#include "soc/periph_defs.h"
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#include "soc/usb_wrap_struct.h"
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#if (CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
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#include "sdkconfig.h"
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#include "esp_cache.h"
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#include "esp_log.h"
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#define DWC2_MEM_CACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE
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#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
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#define DWC2_FS_REG_BASE 0x60080000UL
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#define DWC2_EP_MAX 7
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@ -119,25 +111,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint
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// maybe usb_utmi_hal_disable()
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}
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#if (CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
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void dcd_dcache_clean(void const* addr, uint32_t data_size) {
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int flags = ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED;
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if (addr != NULL && data_size) {
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esp_err_t ret = esp_cache_msync((void *) addr, data_size, flags);
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assert(ret == ESP_OK);
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}
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}
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void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
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int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C;
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if (addr != NULL && data_size) {
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data_size = (data_size < DWC2_MEM_CACHE_LINE_SIZE)? DWC2_MEM_CACHE_LINE_SIZE : data_size;
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esp_err_t ret = esp_cache_msync((void *) addr, data_size, flags);
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assert(ret == ESP_OK);
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}
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}
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#endif // CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#ifdef __cplusplus
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}
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#endif
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