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fix ci

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This commit is contained in:
hathach 2020-11-09 01:23:19 +07:00
parent 7ab3da1e03
commit 496c7c701a
3 changed files with 7 additions and 16 deletions
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5
hw/bsp/same70_xplained/board.mk
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@ -41,8 +41,9 @@ INC += \
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include $(TOP)/$(ASF_DIR)/CMSIS/Core/Include
# For TinyUSB port source # For TinyUSB port source
VENDOR = microchip #SRC_C += src/portable/template/dcd_template.c
CHIP_FAMILY = samg VENDOR = .
CHIP_FAMILY = template
# For freeRTOS port source # For freeRTOS port source
FREERTOS_PORT = ARM_CM7 FREERTOS_PORT = ARM_CM7

14
src/portable/template/dcd_template.c
View File

@ -45,20 +45,6 @@ void dcd_init (uint8_t rhport)
(void) rhport; (void) rhport;
} }
#if HAS_INTERNAL_PULLUP
// Enable internal D+/D- pullup
void dcd_connect(uint8_t rhport) TU_ATTR_WEAK
{
(void) rhport;
}
// Disable internal D+/D- pullup
void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK
{
(void) rhport;
}
#endif
// Enable device interrupt // Enable device interrupt
void dcd_int_enable (uint8_t rhport) void dcd_int_enable (uint8_t rhport)
{ {

4
tools/build_all.py
View File

@ -76,6 +76,10 @@ def skip_example(example, board):
if 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk_contents: if 'CROSS_COMPILE = xtensa-esp32s2-elf-' in mk_contents:
return 1 return 1
# Skip all OPT_MCU_NONE these are WIP port
if '-DCFG_TUSB_MCU=OPT_MCU_NONE' in mk_contents:
return 1
# Skip if CFG_TUSB_MCU in board.mk to match skip file # Skip if CFG_TUSB_MCU in board.mk to match skip file
for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'): for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'):
mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2] mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2]