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https://github.com/hathach/tinyusb.git
synced 2025-01-31 05:52:55 +08:00
use unaligned access read for hw fifo
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4bbacb1008
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@ -260,11 +260,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
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#else
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#else
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// MCU that could access unaligned memory natively
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// MCU that could access unaligned memory natively
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem) { return *((uint32_t const *) mem); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) {
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TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem) { return *((uint16_t const *) mem); }
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return *((uint32_t const *) mem);
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}
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
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TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) {
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
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return *((uint16_t const *) mem);
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}
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) {
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*((uint32_t *) mem) = value;
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}
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) {
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*((uint16_t *) mem) = value;
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}
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#endif
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#endif
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@ -34,10 +34,16 @@
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//------------- Unaligned Memory Access -------------//
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//------------- Unaligned Memory Access -------------//
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// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
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#ifdef __ARM_ARCH
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#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
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// ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access
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#define TUP_ARCH_STRICT_ALIGN 0
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#if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1
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#define TUP_ARCH_STRICT_ALIGN 0
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#else
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#define TUP_ARCH_STRICT_ALIGN 1
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#endif
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#else
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#else
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// TODO default to strict align for others
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// Should investigate other architecture such as risv, xtensa, mips for optimal setting
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#define TUP_ARCH_STRICT_ALIGN 1
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#define TUP_ARCH_STRICT_ALIGN 1
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#endif
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#endif
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@ -220,6 +220,11 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
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while ( !rusb->D0FIFOCTR_b.FRDY ) {}
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while ( !rusb->D0FIFOCTR_b.FRDY ) {}
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}
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}
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//--------------------------------------------------------------------+
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// Pipe FIFO
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//--------------------------------------------------------------------+
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// Write data buffer --> hw fifo
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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{
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{
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#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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@ -228,54 +233,68 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
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volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
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#endif
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#endif
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uintptr_t addr = (uintptr_t)buf;
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uint8_t const* buf8 = (uint8_t const*) buf;
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while (len >= 2) {
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while (len >= 2) {
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reg->u16 = *(const uint16_t *)addr;
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reg->u16 = tu_unaligned_read16(buf8);
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addr += 2;
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buf8 += 2;
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len -= 2;
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len -= 2;
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}
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}
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if (len > 0) {
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if (len > 0) {
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reg->u8 = *(const uint8_t *)addr;
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reg->u8 = *buf8;
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++addr;
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++buf8;
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}
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}
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}
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}
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// Read data buffer <-- hw fifo
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static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
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static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
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{
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{
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uint8_t *p = (uint8_t*)buf;
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uint8_t *p = (uint8_t*)buf;
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volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */
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volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */
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while (len--) *p++ = *reg;
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while (len--) *p++ = *reg;
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}
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}
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static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
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// Write data sw fifo --> hw fifo
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{
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static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
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static const struct {
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void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
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void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
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void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
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} ops[] = {
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/* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
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/* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
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};
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tu_fifo_buffer_info_t info;
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tu_fifo_buffer_info_t info;
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ops[dir].tu_fifo_get_info(f, &info);
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tu_fifo_get_read_info(f, &info);
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unsigned total_len = len;
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uint16_t count = tu_min16(total_len, info.len_lin);
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len = TU_MIN(total_len, info.len_lin);
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pipe_write_packet(info.ptr_lin, fifo, count);
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ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
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unsigned rem = total_len - len;
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uint16_t rem = total_len - count;
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if (rem) {
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if (rem) {
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len = TU_MIN(rem, info.len_wrap);
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rem = tu_min16(rem, info.len_wrap);
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ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
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pipe_write_packet(info.ptr_wrap, fifo, rem);
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rem -= len;
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count += rem;
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}
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}
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ops[dir].tu_fifo_advance(f, total_len - rem);
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tu_fifo_advance_read_pointer(f, count);
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}
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}
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// Read data sw fifo <-- hw fifo
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static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
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tu_fifo_buffer_info_t info;
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tu_fifo_get_write_info(f, &info);
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uint16_t count = tu_min16(total_len, info.len_lin);
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pipe_read_packet(info.ptr_lin, fifo, count);
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uint16_t rem = total_len - count;
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if (rem) {
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rem = tu_min16(rem, info.len_wrap);
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pipe_read_packet(info.ptr_wrap, fifo, rem);
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count += rem;
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}
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tu_fifo_advance_write_pointer(f, count);
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}
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//--------------------------------------------------------------------+
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// Pipe Transfer
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//--------------------------------------------------------------------+
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static bool pipe0_xfer_in(rusb2_reg_t* rusb)
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static bool pipe0_xfer_in(rusb2_reg_t* rusb)
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{
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{
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pipe_state_t *pipe = &_dcd.pipe[0];
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pipe_state_t *pipe = &_dcd.pipe[0];
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@ -292,7 +311,7 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb)
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if (len) {
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if (len) {
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if (pipe->ff) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN);
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pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
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} else {
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} else {
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pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
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pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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pipe->buf = (uint8_t*)buf + len;
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@ -319,7 +338,7 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb)
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if (len) {
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if (len) {
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if (pipe->ff) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT);
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pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
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} else {
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} else {
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pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
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pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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pipe->buf = (uint8_t*)buf + len;
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@ -357,7 +376,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
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if (len) {
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if (len) {
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if (pipe->ff) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN);
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pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
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} else {
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} else {
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pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
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pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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pipe->buf = (uint8_t*)buf + len;
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@ -391,7 +410,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
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if (len) {
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if (len) {
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if (pipe->ff) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT);
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pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
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} else {
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} else {
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pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
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pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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pipe->buf = (uint8_t*)buf + len;
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