mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
rasc ra2a1_ek, but usb does not seem to work. Note fsp.ld need extra 0x100 byte for ROM registers to work.
This commit is contained in:
hathach
parent
ec1c8b99e2
commit
4d1f945096
7
.idea/cmake.xml
generated
7
.idea/cmake.xml
generated
@ -118,11 +118,12 @@
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<configuration PROFILE_NAME="stm32wb55nucleo" ENABLED="false" GENERATION_OPTIONS="-DBOARD=stm32wb55nucleo" />
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<configuration PROFILE_NAME="ra2a1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra2a1_ek -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="ra4m1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="ra6m1_ek" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="ra6m5_ek" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="ra4m3_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m3_ek -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="ra6m1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="ra6m5_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="ra6m5_ek PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
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<configuration PROFILE_NAME="ra8m1_ek" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra8m1_ek -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=1" />
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<configuration PROFILE_NAME="lpcxpresso11u37" ENABLED="false" GENERATION_OPTIONS="-DBOARD=lpcxpresso11u37" />
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<configuration PROFILE_NAME="lpcxpresso11u68" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso11u68 -DLOG=1 -DLOGGER=RTT" />
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@ -31,21 +31,9 @@
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extern "C" {
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#endif
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#define LED1 BSP_IO_PORT_02_PIN_05
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#define LED_STATE_ON 1
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#define SW1 BSP_IO_PORT_02_PIN_06
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#define LED_STATE_ON 1
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#define BUTTON_STATE_ACTIVE 0
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static const ioport_pin_cfg_t board_pin_cfg[] = {
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{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
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{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
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// USB FS D+, D-, VBus
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{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
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{.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
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{.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
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};
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#ifdef __cplusplus
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}
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#endif
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@ -5,58 +5,58 @@
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x400)
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#define BSP_CFG_HEAP_BYTES (0x400)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x400)
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#define BSP_CFG_HEAP_BYTES (0x400)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */
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@ -2,10 +2,10 @@
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA2A1AB3CFM
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (262144)
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#define BSP_RAM_SIZE_BYTES (32768)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (64)
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (262144)
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#define BSP_RAM_SIZE_BYTES (32768)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (64)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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@ -5,17 +5,17 @@
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extern "C" {
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#endif
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA2A1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (24000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA2A1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (24000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (32000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 4
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#define BSP_HOCO_HZ (48000000)
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@ -25,60 +25,65 @@
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
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#define BSP_CFG_INLINE_IRQ_FUNCTIONS (0)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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/*
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ID Code
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Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
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WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
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*/
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#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
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/*
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ID Code
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Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
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WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
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*/
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#if defined(BSP_ID_CODE_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#ifdef __cplusplus
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#if (0)
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#define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap")
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_MCU_FAMILY_CFG_H_ */
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17
hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
17
hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
@ -0,0 +1,17 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_PIN_CFG_H_
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#define BSP_PIN_CFG_H_
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#include "r_ioport.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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#define LED1 (BSP_IO_PORT_02_PIN_05)
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#define SW1 (BSP_IO_PORT_02_PIN_06)
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA2A1-EK.pincfg */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
@ -8,7 +8,7 @@
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
|
||||
#define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */
|
||||
#define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */
|
||||
|
||||
11
hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c
Normal file
11
hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* generated common source file - do not edit */
|
||||
#include "common_data.h"
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport =
|
||||
{
|
||||
.p_api = &g_ioport_on_ioport,
|
||||
.p_ctrl = &g_ioport_ctrl,
|
||||
.p_cfg = &g_bsp_pin_cfg,
|
||||
};
|
||||
void g_common_init(void) {
|
||||
}
|
||||
20
hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h
Normal file
20
hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* generated common header file - do not edit */
|
||||
#ifndef COMMON_DATA_H_
|
||||
#define COMMON_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "bsp_pin_cfg.h"
|
||||
FSP_HEADER
|
||||
#define IOPORT_CFG_NAME g_bsp_pin_cfg
|
||||
#define IOPORT_CFG_OPEN R_IOPORT_Open
|
||||
#define IOPORT_CFG_CTRL g_ioport_ctrl
|
||||
|
||||
/* IOPORT Instance */
|
||||
extern const ioport_instance_t g_ioport;
|
||||
|
||||
/* IOPORT control structure. */
|
||||
extern ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
void g_common_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* COMMON_DATA_H_ */
|
||||
115
hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c
Normal file
115
hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c
Normal file
@ -0,0 +1,115 @@
|
||||
/* generated pin source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_09_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_09_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
|
||||
void R_BSP_PinCfgSecurityInit(void);
|
||||
|
||||
/* Initialize SAR registers for secure pins. */
|
||||
void R_BSP_PinCfgSecurityInit(void)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#else
|
||||
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#endif
|
||||
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
|
||||
|
||||
|
||||
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
|
||||
{
|
||||
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
|
||||
uint32_t port = port_pin >> 8U;
|
||||
uint32_t pin = port_pin & 0xFFU;
|
||||
pmsar[port] &= (uint16_t) ~(1U << pin);
|
||||
}
|
||||
|
||||
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
|
||||
#else
|
||||
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
769
hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld
Normal file
769
hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld
Normal file
@ -0,0 +1,769 @@
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
INCLUDE memory_regions.ld
|
||||
|
||||
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
|
||||
/*
|
||||
XIP_SECONDARY_SLOT_IMAGE = 1;
|
||||
*/
|
||||
|
||||
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
|
||||
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
|
||||
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
|
||||
|
||||
/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
|
||||
__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
|
||||
|
||||
ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
|
||||
ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
|
||||
DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
|
||||
DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
|
||||
|
||||
OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
|
||||
|
||||
/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
|
||||
* Bootloader images do not configure option settings because they are owned by the bootloader.
|
||||
* FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
|
||||
__bl_FSP_BOOTABLE_IMAGE = 1;
|
||||
__bln_FSP_BOOTABLE_IMAGE = 1;
|
||||
PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
|
||||
__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
(DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
|
||||
__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
|
||||
__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
|
||||
__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
__bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
|
||||
__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
|
||||
__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
|
||||
XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
|
||||
FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
|
||||
XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
|
||||
FLASH_IMAGE_START;
|
||||
LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
|
||||
DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
|
||||
FLASH_LENGTH;
|
||||
OPTION_SETTING_SAS_SIZE = 0x34;
|
||||
OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
|
||||
OPTION_SETTING_LENGTH == 0 ? 0 :
|
||||
OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
|
||||
DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
|
||||
FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
|
||||
OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
|
||||
OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be DEFINED in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
* __qspi_flash_start__
|
||||
* __qspi_flash_end__
|
||||
* __qspi_flash_code_size__
|
||||
* __qspi_region_max_size__
|
||||
* __qspi_region_start_address__
|
||||
* __qspi_region_end_address__
|
||||
* __ospi_device_0_start__
|
||||
* __ospi_device_0_end__
|
||||
* __ospi_device_0_code_size__
|
||||
* __ospi_device_0_region_max_size__
|
||||
* __ospi_device_0_region_start_address__
|
||||
* __ospi_device_0_region_end_address__
|
||||
* __ospi_device_1_start__
|
||||
* __ospi_device_1_end__
|
||||
* __ospi_device_1_code_size__
|
||||
* __ospi_device_1_region_max_size__
|
||||
* __ospi_device_1_region_start_address__
|
||||
* __ospi_device_1_region_end_address__
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* Some devices have a gap of code flash between the vector table and ROM Registers.
|
||||
* The flash gap section allows applications to place code and data in this section. */
|
||||
*(.flash_gap*)
|
||||
|
||||
/* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
|
||||
|
||||
/* Allocate flash write-boundary-aligned
|
||||
* space for sce9 wrapped public keys for mcuboot if the module is used.
|
||||
*/
|
||||
KEEP(*(.mcuboot_sce9_key*))
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
. = .;
|
||||
__itcm_data_pre_location = .;
|
||||
|
||||
/* Initialized ITCM data. */
|
||||
/* Aligned to FCACHE2 for RA8. */
|
||||
.itcm_data : ALIGN(16)
|
||||
{
|
||||
/* Start of ITCM Secure Trustzone region. */
|
||||
__tz_ITCM_S = ABSOLUTE(ITCM_START);
|
||||
|
||||
/* All ITCM data start */
|
||||
__itcm_data_start = .;
|
||||
|
||||
KEEP(*(.itcm_data*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* All ITCM data end */
|
||||
__itcm_data_end = .;
|
||||
|
||||
/*
|
||||
* Start of the ITCM Non-Secure Trustzone region.
|
||||
* ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
|
||||
} > ITCM AT > FLASH = 0x00
|
||||
|
||||
/* Addresses exported for ITCM initialization. */
|
||||
__itcm_data_init_start = LOADADDR(.itcm_data);
|
||||
__itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
|
||||
|
||||
ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
|
||||
ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
|
||||
ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
|
||||
|
||||
/* Restore location counter. */
|
||||
/* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
|
||||
/* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
|
||||
. = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
|
||||
|
||||
__exidx_start = .;
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
}
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
__tz_RAM_S = ORIGIN(RAM);
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
. = .;
|
||||
__dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/* Initialized DTCM data. */
|
||||
/* Aligned to FCACHE2 for RA8. */
|
||||
.dtcm_data : ALIGN(16)
|
||||
{
|
||||
/* Start of DTCM Secure Trustzone region. */
|
||||
__tz_DTCM_S = ABSOLUTE(DTCM_START);
|
||||
|
||||
/* Initialized DTCM data start */
|
||||
__dtcm_data_start = .;
|
||||
|
||||
KEEP(*(.dtcm_data*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Initialized DTCM data end */
|
||||
__dtcm_data_end = .;
|
||||
} > DTCM AT > FLASH = 0x00
|
||||
|
||||
. = __dtcm_data_end;
|
||||
/* Uninitialized DTCM data. */
|
||||
/* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
|
||||
.dtcm_bss ALIGN(8) (NOLOAD) :
|
||||
{
|
||||
/* Uninitialized DTCM data start */
|
||||
__dtcm_bss_start = .;
|
||||
|
||||
KEEP(*(.dtcm_bss*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Uninitialized DTCM data end */
|
||||
__dtcm_bss_end = .;
|
||||
|
||||
/*
|
||||
* Start of the DTCM Non-Secure Trustzone region.
|
||||
* DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
|
||||
} > DTCM
|
||||
|
||||
/* Addresses exported for DTCM initialization. */
|
||||
__dtcm_data_init_start = LOADADDR(.dtcm_data);
|
||||
__dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
|
||||
|
||||
ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
|
||||
ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
|
||||
ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
|
||||
ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
|
||||
ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
|
||||
ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
|
||||
|
||||
/* Restore location counter. */
|
||||
/* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
|
||||
/* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
|
||||
. = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section */
|
||||
|
||||
/* Store location counter for SPI non-retentive sections. */
|
||||
sgstubs_pre_location = .;
|
||||
|
||||
/* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
|
||||
SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
|
||||
.gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
|
||||
{
|
||||
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
_start_sg = .;
|
||||
*(.gnu.sgstubs*)
|
||||
. = ALIGN(32);
|
||||
_end_sg = .;
|
||||
} > FLASH
|
||||
|
||||
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
|
||||
FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
|
||||
|
||||
/* QSPI_FLASH section to be downloaded via debugger */
|
||||
.qspi_flash :
|
||||
{
|
||||
__qspi_flash_start__ = .;
|
||||
KEEP(*(.qspi_flash*))
|
||||
KEEP(*(.code_in_qspi*))
|
||||
__qspi_flash_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = sgstubs_pre_location;
|
||||
.qspi_non_retentive : AT(__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
__qspi_non_retentive_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
|
||||
|
||||
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
|
||||
__qspi_region_start_address__ = __qspi_flash_start__;
|
||||
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
|
||||
|
||||
/* Support for OctaRAM */
|
||||
.OSPI_DEVICE_0_NO_LOAD (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ospi_device_0_start__ = .;
|
||||
*(.ospi_device_0_no_load*)
|
||||
. = ALIGN(4);
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0_RAM
|
||||
|
||||
.OSPI_DEVICE_1_NO_LOAD (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ospi_device_1_start__ = .;
|
||||
*(.ospi_device_1_no_load*)
|
||||
. = ALIGN(4);
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1_RAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
|
||||
|
||||
/* OSPI_DEVICE_0 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_0 :
|
||||
{
|
||||
__ospi_device_0_start__ = .;
|
||||
KEEP(*(.ospi_device_0*))
|
||||
KEEP(*(.code_in_ospi_device_0*))
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
|
||||
.ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
__ospi_device_0_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
|
||||
|
||||
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
|
||||
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
|
||||
|
||||
/* OSPI_DEVICE_1 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_1 :
|
||||
{
|
||||
__ospi_device_1_start__ = .;
|
||||
KEEP(*(.ospi_device_1*))
|
||||
KEEP(*(.code_in_ospi_device_1*))
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
|
||||
.ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
__ospi_device_1_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
|
||||
|
||||
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
|
||||
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
|
||||
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
|
||||
|
||||
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
|
||||
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
|
||||
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
|
||||
|
||||
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
|
||||
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
|
||||
.ns_buffer (NOLOAD):
|
||||
{
|
||||
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
|
||||
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
|
||||
|
||||
KEEP(*(.ns_buffer*))
|
||||
} > RAM
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
. = ORIGIN(DATA_FLASH);
|
||||
__tz_DATA_FLASH_S = .;
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
|
||||
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
|
||||
} > DATA_FLASH
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_S = ORIGIN(SDRAM);
|
||||
|
||||
/* SDRAM */
|
||||
.sdram (NOLOAD):
|
||||
{
|
||||
__SDRAM_Start = .;
|
||||
KEEP(*(.sdram*))
|
||||
KEEP(*(.frame*))
|
||||
__SDRAM_End = .;
|
||||
} > SDRAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_N = __SDRAM_End;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
|
||||
* Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
|
||||
* memory region between TrustZone projects. */
|
||||
__tz_ID_CODE_N = __tz_ID_CODE_S;
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
|
||||
|
||||
.option_setting_ofs :
|
||||
{
|
||||
__OPTION_SETTING_OFS_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
|
||||
KEEP(*(.option_setting_ofs2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
__OPTION_SETTING_OFS_End = .;
|
||||
} > OPTION_SETTING_OFS = 0xFF
|
||||
|
||||
.option_setting_sas :
|
||||
{
|
||||
__OPTION_SETTING_SAS_Start = .;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_SAS_End = .;
|
||||
} > OPTION_SETTING_SAS = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
|
||||
|
||||
.option_setting_ns :
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_ofs3))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps3))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps3))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
|
||||
|
||||
.option_setting_s :
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs3_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec3))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec3))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} > OPTION_SETTING_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
|
||||
}
|
||||
22
hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld
Normal file
22
hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld
Normal file
@ -0,0 +1,22 @@
|
||||
|
||||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x8000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x40000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x01010018;
|
||||
ID_CODE_LENGTH = 0x20;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
258
hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml
Normal file
258
hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml
Normal file
@ -0,0 +1,258 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="9">
|
||||
<generalSettings>
|
||||
<option key="#Board#" value="board.ra2a1_ek"/>
|
||||
<option key="CPU" value="RA2A1"/>
|
||||
<option key="Core" value="CM23"/>
|
||||
<option key="#TargetName#" value="R7FA2A1AB3CFM"/>
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m23"/>
|
||||
<option key="#DeviceCommand#" value="R7FA2A1AB"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA2A1AB3CFM.pincfg"/>
|
||||
<option key="#FSPVersion#" value="5.6.0"/>
|
||||
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2a1_ek##"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra2a1.R7FA2A1AB3CFM">
|
||||
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||
<property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
|
||||
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
|
||||
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||
<property id="config.bsp.irq_count_hidden" value="32"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra2a1">
|
||||
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra2a1.fsp">
|
||||
<property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
|
||||
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
|
||||
<property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_start" value="0x000FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_end" value="0x000FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_start" value="0x000FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_end" value="0x000FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_start" value="0x000FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_end" value="0x000FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
|
||||
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="32000000"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="3333333"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="8000000"/>
|
||||
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="16000000"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
|
||||
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
|
||||
<property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
|
||||
<property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
|
||||
<property id="config.bsp.common.id1" value=""/>
|
||||
<property id="config.bsp.common.id2" value=""/>
|
||||
<property id="config.bsp.common.id3" value=""/>
|
||||
<property id="config.bsp.common.id4" value=""/>
|
||||
<property id="config.bsp.common.id_fixed" value=""/>
|
||||
<property id="config.bsp.common.fill_flash_gap" value="config.bsp.common.fill_flash_gap.disabled"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x400"/>
|
||||
<property id="config.bsp.common.heap" value="0x400"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
|
||||
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
|
||||
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
|
||||
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
|
||||
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
|
||||
</config>
|
||||
</raBspConfiguration>
|
||||
<raClockConfiguration>
|
||||
<node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
|
||||
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
|
||||
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
|
||||
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
|
||||
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
|
||||
<node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
|
||||
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
|
||||
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
|
||||
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
|
||||
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
|
||||
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
|
||||
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
|
||||
<node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
|
||||
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
|
||||
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
|
||||
<node id="board.clock.sdadcclk.source" option="board.clock.sdadcclk.source.hoco"/>
|
||||
<node id="board.clock.sdadcclk.div" option="board.clock.sdadcclk.div.12"/>
|
||||
<node id="board.clock.sdadcclk.display" option="board.clock.sdadcclk.display.value"/>
|
||||
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
|
||||
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
|
||||
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
|
||||
</raClockConfiguration>
|
||||
<raComponentSelection>
|
||||
<component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Simple application that blinks an LED. No RTOS included.</description>
|
||||
<originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board Support Package Common Files</description>
|
||||
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>I/O Port</description>
|
||||
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
|
||||
<description>Arm CMSIS Version 6 - Core (M)</description>
|
||||
<originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra2a1_ek" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>RA2A1-EK Board Support Files</description>
|
||||
<originalPack>Renesas.RA_board_ra2a1_ek.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="R7FA2A1AB3CFM" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for R7FA2A1AB3CFM</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA2A1</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA2A1 - FSP Data</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA2A1 - Events</description>
|
||||
<originalPack>Renesas.RA_mcu_ra2a1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<symbolicName propertyId="p205.symbolic_name" value="LED1"/>
|
||||
<symbolicName propertyId="p206.symbolic_name" value="SW1"/>
|
||||
<pincfg active="true" name="RA2A1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="adc0.an06.p003" configurationId="adc0.an06"/>
|
||||
<configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
|
||||
<configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
|
||||
<configSetting altId="ctsu0.ts15.p001" configurationId="ctsu0.ts15"/>
|
||||
<configSetting altId="ctsu0.tscap.p409" configurationId="ctsu0.tscap"/>
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p001.ctsu0.ts15" configurationId="p001"/>
|
||||
<configSetting altId="p001.gpio_mode.gpio_mode_peripheral" configurationId="p001.gpio_mode"/>
|
||||
<configSetting altId="p003.adc0.an06" configurationId="p003"/>
|
||||
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p111.spi0.rspck" configurationId="p111"/>
|
||||
<configSetting altId="p111.gpio_mode.gpio_mode_peripheral" configurationId="p111.gpio_mode"/>
|
||||
<configSetting altId="p112.spi0.ssl0" configurationId="p112"/>
|
||||
<configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/>
|
||||
<configSetting altId="p201.input" configurationId="p201"/>
|
||||
<configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/>
|
||||
<configSetting altId="p204.sci0.rxd" configurationId="p204"/>
|
||||
<configSetting altId="p204.gpio_mode.gpio_mode_peripheral" configurationId="p204.gpio_mode"/>
|
||||
<configSetting altId="p205.output.low" configurationId="p205"/>
|
||||
<configSetting altId="p205.gpio_mode.gpio_mode_out.low" configurationId="p205.gpio_mode"/>
|
||||
<configSetting altId="p206.input" configurationId="p206"/>
|
||||
<configSetting altId="p206.gpio_mode.gpio_mode_in" configurationId="p206.gpio_mode"/>
|
||||
<configSetting altId="p206.gpio_pupd.gpio_pupd_ip_up" configurationId="p206.gpio_pupd"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p303.spi0.mosi" configurationId="p303"/>
|
||||
<configSetting altId="p303.gpio_mode.gpio_mode_peripheral" configurationId="p303.gpio_mode"/>
|
||||
<configSetting altId="p304.spi0.miso" configurationId="p304"/>
|
||||
<configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/>
|
||||
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="p409.ctsu0.tscap" configurationId="p409"/>
|
||||
<configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/>
|
||||
<configSetting altId="p411.sci0.txd" configurationId="p411"/>
|
||||
<configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
|
||||
<configSetting altId="p914.usbfs0.dp" configurationId="p914"/>
|
||||
<configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
|
||||
<configSetting altId="p915.usbfs0.dm" configurationId="p915"/>
|
||||
<configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
|
||||
<configSetting altId="sci0.mode.asynchronous.free" configurationId="sci0.mode"/>
|
||||
<configSetting altId="sci0.rxd.p204" configurationId="sci0.rxd"/>
|
||||
<configSetting altId="sci0.txd.p411" configurationId="sci0.txd"/>
|
||||
<configSetting altId="spi0.miso.p304" configurationId="spi0.miso"/>
|
||||
<configSetting altId="spi0.mode.enabled.b" configurationId="spi0.mode"/>
|
||||
<configSetting altId="spi0.mosi.p303" configurationId="spi0.mosi"/>
|
||||
<configSetting altId="spi0.pairing.b" configurationId="spi0.pairing"/>
|
||||
<configSetting altId="spi0.rspck.p111" configurationId="spi0.rspck"/>
|
||||
<configSetting altId="spi0.ssl0.p112" configurationId="spi0.ssl0"/>
|
||||
<configSetting altId="usbfs0.dm.p915" configurationId="usbfs0.dm"/>
|
||||
<configSetting altId="usbfs0.dp.p914" configurationId="usbfs0.dp"/>
|
||||
<configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R7FA2A1AB3CFM.pincfg" selected="false" symbol="">
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
271
hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml
Normal file
271
hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml
Normal file
@ -0,0 +1,271 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="9">
|
||||
<generalSettings>
|
||||
<option key="#Board#" value="board.ra4m1ek"/>
|
||||
<option key="CPU" value="RA4M1"/>
|
||||
<option key="Core" value="CM4"/>
|
||||
<option key="#TargetName#" value="R7FA4M1AB3CFP"/>
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m4"/>
|
||||
<option key="#DeviceCommand#" value="R7FA4M1AB"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA4M1AB3CFP.pincfg"/>
|
||||
<option key="#FSPVersion#" value="5.6.0"/>
|
||||
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra4m1_ek##"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra4m1.R7FA4M1AB3CFP">
|
||||
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||
<property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
|
||||
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
|
||||
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||
<property id="config.bsp.irq_count_hidden" value="32"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra4m1">
|
||||
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra4m1.fsp">
|
||||
<property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
|
||||
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
|
||||
<property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_start" value="0x00FFFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc0_end" value="0x00FFFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_start" value="0x00FFFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_pc1_end" value="0x00FFFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
|
||||
<property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
|
||||
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="6666666"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="12000000"/>
|
||||
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="24000000"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
|
||||
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
|
||||
<property id="config.bsp.fsp.mcu.slcdc.1_4_bias_method" value="1"/>
|
||||
<property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
|
||||
<property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
|
||||
<property id="config.bsp.common.id1" value=""/>
|
||||
<property id="config.bsp.common.id2" value=""/>
|
||||
<property id="config.bsp.common.id3" value=""/>
|
||||
<property id="config.bsp.common.id4" value=""/>
|
||||
<property id="config.bsp.common.id_fixed" value=""/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x800"/>
|
||||
<property id="config.bsp.common.heap" value="0x1000"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
|
||||
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
|
||||
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
|
||||
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
|
||||
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
|
||||
</config>
|
||||
</raBspConfiguration>
|
||||
<raClockConfiguration>
|
||||
<node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
|
||||
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
|
||||
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.24m"/>
|
||||
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
|
||||
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
|
||||
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
|
||||
<node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
|
||||
<node id="board.clock.pll.mul" option="board.clock.pll.mul.8"/>
|
||||
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
|
||||
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
|
||||
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
|
||||
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
|
||||
<node id="board.clock.pclka.div" option="board.clock.pclka.div.1"/>
|
||||
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
|
||||
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
|
||||
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
|
||||
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.1"/>
|
||||
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
|
||||
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
|
||||
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
|
||||
<node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
|
||||
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
|
||||
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
|
||||
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
|
||||
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
|
||||
<node id="board.clock.uclk.source" option="board.clock.uclk.source.pll"/>
|
||||
<node id="board.clock.uclk.display" option="board.clock.clkout.display.value"/>
|
||||
</raClockConfiguration>
|
||||
<raComponentSelection>
|
||||
<component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Simple application that blinks an LED. No RTOS included.</description>
|
||||
<originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board Support Package Common Files</description>
|
||||
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>I/O Port</description>
|
||||
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
|
||||
<description>Arm CMSIS Version 6 - Core (M)</description>
|
||||
<originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra4m1_ek" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>RA4M1-EK Board Support Files</description>
|
||||
<originalPack>Renesas.RA_board_ra4m1_ek.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="R7FA4M1AB3CFP" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for R7FA4M1AB3CFP</description>
|
||||
<originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA4M1</description>
|
||||
<originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA4M1 - FSP Data</description>
|
||||
<originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra4m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA4M1 - Events</description>
|
||||
<originalPack>Renesas.RA_mcu_ra4m1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<symbolicName propertyId="p105.symbolic_name" value="SW1"/>
|
||||
<symbolicName propertyId="p106.symbolic_name" value="LED1"/>
|
||||
<pincfg active="true" name="RA4M1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="adc0.an04.p004" configurationId="adc0.an04"/>
|
||||
<configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
|
||||
<configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
|
||||
<configSetting altId="ctsu0.ts35.p115" configurationId="ctsu0.ts35"/>
|
||||
<configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/>
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p004.adc0.an04" configurationId="p004"/>
|
||||
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
|
||||
<configSetting altId="p100.spi0.miso" configurationId="p100"/>
|
||||
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
|
||||
<configSetting altId="p101.spi0.mosi" configurationId="p101"/>
|
||||
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
|
||||
<configSetting altId="p102.spi0.rspck" configurationId="p102"/>
|
||||
<configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
|
||||
<configSetting altId="p103.spi0.ssl0" configurationId="p103"/>
|
||||
<configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
|
||||
<configSetting altId="p105.input" configurationId="p105"/>
|
||||
<configSetting altId="p105.gpio_mode.gpio_mode_in" configurationId="p105.gpio_mode"/>
|
||||
<configSetting altId="p105.gpio_pupd.gpio_pupd_ip_up" configurationId="p105.gpio_pupd"/>
|
||||
<configSetting altId="p106.output.low" configurationId="p106"/>
|
||||
<configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p115.ctsu0.ts35" configurationId="p115"/>
|
||||
<configSetting altId="p115.gpio_mode.gpio_mode_peripheral" configurationId="p115.gpio_mode"/>
|
||||
<configSetting altId="p205.ctsu0.tscap" configurationId="p205"/>
|
||||
<configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p400.output.low" configurationId="p400"/>
|
||||
<configSetting altId="p400.gpio_mode.gpio_mode_out.low" configurationId="p400.gpio_mode"/>
|
||||
<configSetting altId="p401.sci1.txd" configurationId="p401"/>
|
||||
<configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
|
||||
<configSetting altId="p402.sci1.rxd" configurationId="p402"/>
|
||||
<configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/>
|
||||
<configSetting altId="p403.output.low" configurationId="p403"/>
|
||||
<configSetting altId="p403.gpio_mode.gpio_mode_out.low" configurationId="p403.gpio_mode"/>
|
||||
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="p914.usbfs0.usbdp" configurationId="p914"/>
|
||||
<configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
|
||||
<configSetting altId="p915.usbfs0.usbdm" configurationId="p915"/>
|
||||
<configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
|
||||
<configSetting altId="sci1.mode.asynchronous.free" configurationId="sci1.mode"/>
|
||||
<configSetting altId="sci1.rxd.p402" configurationId="sci1.rxd"/>
|
||||
<configSetting altId="sci1.txd.p401" configurationId="sci1.txd"/>
|
||||
<configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/>
|
||||
<configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/>
|
||||
<configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/>
|
||||
<configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/>
|
||||
<configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/>
|
||||
<configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.usbdm.p915" configurationId="usbfs0.usbdm"/>
|
||||
<configSetting altId="usbfs0.usbdp.p914" configurationId="usbfs0.usbdp"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R7FA4M1AB3CFP.pincfg" selected="false" symbol="">
|
||||
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
|
||||
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
|
||||
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
|
||||
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
|
||||
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
@ -49,12 +49,6 @@
|
||||
/* Key code for writing PRCR register. */
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
|
||||
// static const ioport_cfg_t family_pin_cfg = {
|
||||
// .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
|
||||
// .p_pin_cfg_data = board_pin_cfg,
|
||||
// };
|
||||
// static ioport_instance_ctrl_t port_ctrl;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Vector Data
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user