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adding lpcxpresso11u37 board

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This commit is contained in:
hathach 2019-09-06 15:06:04 +07:00
parent 192a95a96e
commit 4ef3946a25
11 changed files with 459 additions and 3 deletions
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3
hw/bsp/ea4088qs/board.mk
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@ -8,6 +8,9 @@ CFLAGS += \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-D__USE_LPCOPEN
# lpc_types.h cause following errors
CFLAGS += -Wno-error=strict-prototypes
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/ea4088qs/lpc4088.ld

46
hw/bsp/lpcxpresso11u37/board.mk Normal file
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@ -0,0 +1,46 @@
CFLAGS += \
-mthumb \
-mabi=aapcs \
-mcpu=cortex-m0 \
-nostdlib \
-DCORE_M0 \
-D__VTOR_PRESENT=0 \
-D__USE_LPCOPEN \
-DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
# startup.c and lpc_types.h cause following errors
CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes
MCU_DIR = hw/mcu/nxp/lpc_driver/lpc11uxx
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/lpcxpresso11u37/lpc11u37.ld
SRC_C += \
$(MCU_DIR)/cr_startup_lpc11xx.c \
$(MCU_DIR)/lpc_chip_11uxx/src/chip_11xx.c \
$(MCU_DIR)/lpc_chip_11uxx/src/clock_11xx.c \
$(MCU_DIR)/lpc_chip_11uxx/src/gpio_11xx_1.c \
$(MCU_DIR)/lpc_chip_11uxx/src/iocon_11xx.c \
$(MCU_DIR)/lpc_chip_11uxx/src/sysctl_11xx.c \
$(MCU_DIR)/lpc_chip_11uxx/src/sysinit_11xx.c
INC += \
$(TOP)/$(MCU_DIR)/lpc_chip_11uxx/inc
# For TinyUSB port source
VENDOR = nxp
CHIP_FAMILY = lpc_ip3511
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0
# For flash-jlink target
JLINK_DEVICE = LPC11U37/401
JLINK_IF = swd
# flash using pyocd
flash: $(BUILD)/$(BOARD)-firmware.hex
pyocd flash -t lpc11u37 $<

195
hw/bsp/lpcxpresso11u37/lpc11u37.ld Normal file
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@ -0,0 +1,195 @@
/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2019
* Generated linker script file for LPC11U37/401
* Created from linkscript.ldt by FMCreateLinkLibraries
* Using Freemarker v2.3.23
* MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Sep 6, 2019 12:16:06 PM
*/
MEMORY
{
/* Define each memory region */
MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */
RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
__base_MFlash128 = 0x0 ; /* MFlash128 */
__base_Flash = 0x0 ; /* Flash */
__top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */
__top_Flash = 0x0 + 0x20000 ; /* 128K bytes */
__base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
__base_RAM = 0x10000000 ; /* RAM */
__top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
__top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
__base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
__base_RAM2 = 0x20004000 ; /* RAM2 */
__top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
__top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
} > MFlash128
.text : ALIGN(4)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > MFlash128
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash128
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash128
__exidx_end = .;
_etext = .;
/* DATA section for RamUsb2 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$RamUsb2)
*(.data.$RAM2)
*(.data.$RamUsb2)
*(.data.$RAM2.*)
*(.data.$RamUsb2.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
} > RamUsb2 AT>MFlash128
/* MAIN DATA SECTION */
.uninit_RESERVED (NOLOAD) :
{
. = ALIGN(4) ;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > RamLoc8
/* Main DATA section (RamLoc8) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > RamLoc8 AT>MFlash128
/* BSS section for RamUsb2 */
.bss_RAM2 :
{
. = ALIGN(4) ;
PROVIDE(__start_bss_RAM2 = .) ;
*(.bss.$RAM2)
*(.bss.$RamUsb2)
*(.bss.$RAM2.*)
*(.bss.$RamUsb2.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
} > RamUsb2
/* MAIN BSS SECTION */
.bss :
{
. = ALIGN(4) ;
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc8
/* NOINIT section for RamUsb2 */
.noinit_RAM2 (NOLOAD) :
{
. = ALIGN(4) ;
*(.noinit.$RAM2)
*(.noinit.$RamUsb2)
*(.noinit.$RAM2.*)
*(.noinit.$RamUsb2.*)
. = ALIGN(4) ;
} > RamUsb2
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD):
{
. = ALIGN(4) ;
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc8
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
/* ## Create checksum value (used in startup) ## */
PROVIDE(__valid_user_code_checksum = 0 -
(_vStackTop
+ (ResetISR + 1)
+ (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+ (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
)
);
/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
}

200
hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c Normal file
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@ -0,0 +1,200 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "chip.h"
#include "../board.h"
#define LED_PORT 1
#define LED_PIN 0
#define LED_STATE_ON 0
// Wake up Switch
#define BUTTON_PORT 0
#define BUTTON_PIN 16
#define BUTTON_STATE_ACTIVE 0
/* System oscillator rate and RTC oscillator rate */
const uint32_t OscRateIn = 12000000;
const uint32_t RTCOscRateIn = 32768;
/* Pin muxing table, only items that need changing from their default pin
state are in this table. Not every pin is mapped. */
/* IOCON pin definitions for pin muxing */
typedef struct {
uint32_t port : 8; /* Pin port */
uint32_t pin : 8; /* Pin number */
uint32_t modefunc : 16; /* Function and mode */
} PINMUX_GRP_T;
static const PINMUX_GRP_T pinmuxing[] =
{
{0, 3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
{0, 6, (IOCON_FUNC1 | IOCON_MODE_INACT)}, /* PIO0_6 used for USB_CONNECT */
{0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
{0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
};
/* Setup system clocking */
static void SystemSetupClocking(void)
{
volatile int i;
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait 200us for OSC to be stablized, no status
indication, dummy wait. */
for (i = 0; i < 0x100; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Set USB PLL input to main oscillator */
Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupUSBPLL(3, 1);
/* Powerup USB PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
}
// Invoked by startup code
void SystemInit(void)
{
SystemSetupClocking();
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
/* Enable IOCON clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++)
{
Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
}
}
void board_init(void)
{
SystemCoreClockUpdate();
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
Chip_GPIO_Init(LPC_GPIO);
// LED
Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
// Button
Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
// USB: Setup PLL clock, and power
/* enable USB main clock */
Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
/* Enable AHB clock to the USB block and USB RAM. */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
/* power UP USB Phy */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
}
uint32_t board_button_read(void)
{
return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf;
(void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
(void) buf;
(void) len;
return 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif

2
hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
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@ -31,7 +31,7 @@
#define LED_PIN 17
#define LED_STATE_ON 0
// Wake up Swtich
// Wake up Switch
#define BUTTON_PORT 0
#define BUTTON_PIN 16
#define BUTTON_STATE_ACTIVE 0

3
hw/bsp/lpcxpresso1347/board.mk
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@ -9,6 +9,9 @@ CFLAGS += \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
# startup.c and lpc_types.h cause following errors
CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/lpcxpresso1347/lpc1347.ld

2
hw/bsp/lpcxpresso1347/cr_startup_lpc13xx.c
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@ -393,7 +393,7 @@ ResetISR(void) {
bss_init ((unsigned int)ExeAddr, SectionLen);
#endif
// extern void SystemInit(void);
extern void SystemInit(void);
SystemInit();
#if defined (__cplusplus)

3
hw/bsp/lpcxpresso1769/board.mk
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@ -8,6 +8,9 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
-DRTC_EV_SUPPORT=0
# lpc_types.h cause following errors
CFLAGS += -Wno-error=strict-prototypes
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/lpcxpresso1769/lpc1769.ld

3
hw/bsp/mbed1768/board.mk
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@ -8,6 +8,9 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
-DRTC_EV_SUPPORT=0
# startup.c and lpc_types.h cause following errors
CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/mbed1768/lpc1768.ld

3
hw/bsp/mcb1800/board.mk
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@ -7,6 +7,9 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_LPC18XX \
-D__USE_LPCOPEN
# lpc_types.h cause following errors
CFLAGS += -Wno-error=strict-prototypes
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/mcb1800/lpc1857.ld

2
hw/mcu/nxp/lpc_driver

@ -1 +1 @@
Subproject commit 42dac0b08d94986bd5423c6327b097fec0c47911
Subproject commit 675b41620db763f89bdbe946cbfb7a9e8f27d42b