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cdc work ok with lpc43xx

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hathach 2018-11-22 17:40:20 +07:00
parent 60d8cde695
commit 569e85a0c0
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GPG Key ID: 2FA891220FBFD581
5 changed files with 51 additions and 44 deletions
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2
examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject
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@ -19,7 +19,7 @@
arm_target_device_name="LPC4357_M4"
arm_target_interface_type="SWD"
build_treat_warnings_as_errors="Yes"
c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4357;CFG_TUSB_MCU=OPT_MCU_LPC43XX"
c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4357;CFG_TUSB_MCU=OPT_MCU_LPC43XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss2")))"
c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/CMSIS_LPC43xx_DriverLib/inc"
debug_register_definition_file="LPC43xx_Registers.xml"
debug_target_connection="J-Link"

18
examples/device/cdc_msc_hid/src/tusb_config.h
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@ -58,16 +58,24 @@
#define CFG_TUSB_DEBUG 2
#define CFG_TUSB_OS OPT_OS_NONE
//--------------------------------------------------------------------
// USB RAM PLACEMENT
//--------------------------------------------------------------------
#define CFG_TUSB_ATTR_USBRAM
/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
* Tinyusb use follows macros to declare transferring memory so that they can be put
* into those specific section.
* e.g
* - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
* - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
*/
#ifndef CFG_TUSB_MEM_SECTION
#define CFG_TUSB_MEM_SECTION
#endif
#ifndef CFG_TUSB_MEM_ALIGN
#define CFG_TUSB_MEM_ALIGN ATTR_ALIGNED(4)
#endif
//--------------------------------------------------------------------
// DEVICE CONFIGURATION
//--------------------------------------------------------------------
#define CFG_TUD_ENDOINT0_SIZE 64
/*------------- Descriptors -------------*/

2
src/common/compiler/tusb_compiler_gcc.h
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@ -66,10 +66,8 @@
/// The packed attribute specifies that a variable or structure field should have the smallest possible alignment—one byte for a variable, and one bit for a field, unless you specify a larger value with the aligned attribute
#define ATTR_PACKED __attribute__ ((packed))
#define ATTR_PREPACKED
#define ATTR_PACKED_STRUCT(x) x __attribute__ ((packed))
/** @} */
/** \defgroup Group_FuncAttr Function Attributes

2
src/common/compiler/tusb_compiler_iar.h
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@ -53,8 +53,6 @@
#endif
#define ALIGN_OF(x) __ALIGNOF__(x)
#define ATTR_PACKED_STRUCT(x) __packed x
#define ATTR_PREPACKED __packed
#define ATTR_PACKED
//#define ATTR_SECTION(section) _Pragma((#section))

71
src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
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@ -237,40 +237,7 @@ static inline uint8_t qtd_find_free(uint8_t rhport)
}
//--------------------------------------------------------------------+
// CONTROL PIPE API
//--------------------------------------------------------------------+
// control transfer does not need to use qtd find function
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length)
{
LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
uint8_t const ep_phy = (dir == TUSB_DIR_IN) ? 1 : 0;
dcd_qhd_t* qhd = &p_dcd->qhd[ep_phy];
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {}
TU_VERIFY( !qhd->qtd_overlay.active );
dcd_qtd_t* qtd = &p_dcd->qtd[0];
qtd_init(qtd, p_buffer, length);
// skip xfer complete for Status
qtd->int_on_complete = (length > 0 ? 1 : 0);
qhd->qtd_overlay.next = (uint32_t) qtd;
lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_phy));
return true;
}
//--------------------------------------------------------------------+
// BULK/INTERRUPT/ISOCHRONOUS PIPE API
// DCD Endpoint Port
//--------------------------------------------------------------------+
static inline volatile uint32_t * get_reg_control_addr(uint8_t rhport, uint8_t physical_endpoint)
{
@ -345,6 +312,36 @@ bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
}
// control transfer does not need to use qtd find function
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length)
{
LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
uint8_t const ep_phy = (dir == TUSB_DIR_IN) ? 1 : 0;
dcd_qhd_t* qhd = &p_dcd->qhd[ep_phy];
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {}
TU_VERIFY( !qhd->qtd_overlay.active );
dcd_qtd_t* qtd = &p_dcd->qtd[0];
qtd_init(qtd, p_buffer, length);
// skip xfer complete for Status
qtd->int_on_complete = (length > 0 ? 1 : 0);
qhd->qtd_overlay.next = (uint32_t) qtd;
lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_phy));
return true;
}
// add only, controller virtually cannot know
// TODO remove and merge to dcd_edpt_xfer
static bool pipe_add_xfer(uint8_t rhport, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
@ -377,6 +374,11 @@ static bool pipe_add_xfer(uint8_t rhport, uint8_t ed_idx, void * buffer, uint16_
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{
if ( edpt_number(ep_addr) == 0 )
{
return dcd_control_xfer(rhport, edpt_dir(ep_addr), buffer, total_bytes);
}
uint8_t ep_idx = edpt_addr2phy(ep_addr);
TU_VERIFY ( pipe_add_xfer(rhport, ep_idx, buffer, total_bytes, true) );
@ -391,6 +393,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
return true;
}
//--------------------------------------------------------------------+
// ISR
//--------------------------------------------------------------------+