mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-24 05:42:57 +08:00
Merge branch 'master' into ncm
This commit is contained in:
commit
57058e33fc
10
.github/ISSUE_TEMPLATE/question.md
vendored
10
.github/ISSUE_TEMPLATE/question.md
vendored
@ -1,10 +0,0 @@
|
|||||||
---
|
|
||||||
name: Question
|
|
||||||
about: Question for this project
|
|
||||||
title: ''
|
|
||||||
labels: Q&A
|
|
||||||
assignees: ''
|
|
||||||
|
|
||||||
---
|
|
||||||
|
|
||||||
**Describe what the question is**
|
|
111
CONTRIBUTORS.md
111
CONTRIBUTORS.md
@ -1,63 +1,82 @@
|
|||||||
# TinyUSB contributors (sorted alphabetically)
|
# TinyUSB contributors (sorted alphabetically)
|
||||||
|
|
||||||
* **[Adafruit Team](https://github.com/adafruit)**
|
- **[Adafruit Team](https://github.com/adafruit)**
|
||||||
* Main supporter and sponsor for hardware boards and kits
|
- Main supporter and sponsor for hardware boards and kits
|
||||||
* Discussion and suggestion for feature and improvement
|
- Discussion and suggestion for feature and improvement
|
||||||
* Design the project logo
|
- Design the project logo
|
||||||
|
|
||||||
* **[arturo182](https://github.com/arturo182)**
|
- **[Ha Thach](https://github.com/hathach)**
|
||||||
* Board support for MiMX RT1010 evaluation kit
|
- *Author and maintainer*
|
||||||
|
- Most features development
|
||||||
|
|
||||||
* **[Ha Thach](https://github.com/hathach)**
|
- **[Hristo Gochkov](https://github.com/me-no-dev)**
|
||||||
* Author and maintainer
|
- Improve ESP32s2 DCD
|
||||||
* Most features development
|
|
||||||
|
|
||||||
* **[Jan Dümpelmann](https://github.com/duempel)**
|
- **[Jan Dümpelmann](https://github.com/duempel)**
|
||||||
* Improvements to Synopsys device controller driver (DCD) for STM32 MCUs
|
- Improve transfer performance for Synopsys DCD for STM32 MCUs
|
||||||
|
|
||||||
* **[Jeff Epler](https://github.com/jepler)**
|
- **[Jeff Epler](https://github.com/jepler)**
|
||||||
* Improvement to MIDI device driver
|
- Improve MIDI class driver
|
||||||
|
|
||||||
* **[Kamil Tomaszewski](https://github.com/kamtom480)**
|
- **[Jerzy Kasenberg](https://github.com/kasjer)**
|
||||||
* Sony CXD56 device driver port for spresnese board
|
- Add new DCD port for **Dialog DA1469x**
|
||||||
|
- Add new class driver for **Bluetooth HCI**
|
||||||
|
- Add ISO transfer for STM32 Synopsys, Nordic nRF, Dialog DA1469x
|
||||||
|
- Improve Audio driver and add uac2_headset example
|
||||||
|
- Improve STM32 Synopsys DCD with various PRs
|
||||||
|
|
||||||
* **[Nathan Conrad](https://github.com/pigrew)**
|
- **[Kamil Tomaszewski](https://github.com/kamtom480)**
|
||||||
* STM32 fsdev Fullspeed device driver port for STM32 L0, F0, F1, F3 etc ...
|
- Add new DCD port for **Sony CXD56** (spresnese board)
|
||||||
* USBTMC class driver support with example
|
|
||||||
* Various improvement e.g Zero-length packet, Lint setup
|
|
||||||
* Board support for STM32F070RB Nucleo, STM32F303 Discovery
|
|
||||||
|
|
||||||
* **[Peter Lawrence](https://github.com/majbthrd)**
|
- **[Kay Sievers](https://github.com/kaysievers)**
|
||||||
* Nuvoton NUC 120, 121, 125, 126, 505 device driver port
|
- Improve MIDI driver with packet API
|
||||||
* USBNET RNDIS, CDC-ECM, CDC-EEM class driver
|
|
||||||
* Added `net_lwip_webserver` example for demonstration of usbnet with lwip
|
|
||||||
* Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
|
|
||||||
* Complete multiple class interfaces & add cdc_dual_ports example
|
|
||||||
|
|
||||||
* **[Scott Shawcroft](https://github.com/tannewt)**
|
- **[Koji KITAYAMA](https://github.com/kkitayam)**
|
||||||
* SAMD21 and SAMD51 device driver port
|
- Add new DCD port for **NXP Kinetis KL25**
|
||||||
* MIDI device class driver support
|
|
||||||
* Improvement to USBD control transfer, MSC, CDC class driver
|
|
||||||
* Board support for Metro M0 & M4 express
|
|
||||||
* Write the execellent porting.md documentation
|
|
||||||
* Introduce inital Makefile
|
|
||||||
|
|
||||||
* **[Sean Cross](https://github.com/xobs)**
|
- **[Nathan Conrad](https://github.com/pigrew)**
|
||||||
* ValentyUSB eptri device driver port
|
- Add new DCD port for **STM32 fsdev** Fullspeed device for STM32 L0, F0, F1, F3 etc ...
|
||||||
* Board support for fomu
|
- Add new class driver for **USB Test and Measurement Class (USBTMC)**
|
||||||
|
- Various improvement e.g Zero-length packet, Lint setup
|
||||||
|
- Board support for STM32F070RB Nucleo, STM32F303 Discovery
|
||||||
|
|
||||||
* **[Sylvain "tnt" Munaut](https://github.com/smunaut)**
|
- **[Peter Lawrence](https://github.com/majbthrd)**
|
||||||
* DFU runtime support with example
|
- Add new DCD port for **Nuvoton NUC 120, 121, 125, 126, 505**
|
||||||
|
- Add new class driver for **USBNET RNDIS, CDC-ECM**
|
||||||
|
- Add *net_lwip_webserver* example for demonstration of usbnet with lwip
|
||||||
|
- Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
|
||||||
|
- Improve multiple cdc interfaces API & add cdc_dual_ports example
|
||||||
|
|
||||||
* **[Timon Skerutsch](https://github.com/PTS93)**
|
- **[Reinhard Panhuber](https://github.com/PanRe)**
|
||||||
* hid_test.js script and extensive test for bi-directional raw HID
|
- Add new class driver for **USB Audio Class 2.0 (UAC2)**
|
||||||
|
- Enhance tu_fifo with unmasked pointer, which better support DMA
|
||||||
|
|
||||||
* **[Tod E. Kurt](https://github.com/todbot)**
|
- **[Scott Shawcroft](https://github.com/tannewt)**
|
||||||
* hid_test.js script and extensive test for bi-directional raw HID
|
- Add new DCD port for **SAMD21 and SAMD51**
|
||||||
|
- Add new class driver for **Musical Instrument Digital Interface (MIDI)**
|
||||||
|
- Improve USBD control transfer, MSC, CDC class driver
|
||||||
|
- Board support for Metro M0 & M4 express
|
||||||
|
- Write the execellent porting.md documentation
|
||||||
|
- Add initial Makefile
|
||||||
|
|
||||||
* **[William D. Jones](https://github.com/cr1901)**
|
- **[Sean Cross](https://github.com/xobs)**
|
||||||
* Synopsys DesignWare device driver port for STM32 L4, F2, F4, F7, H7 etc ...
|
- Add new DCD port for **ValentyUSB eptri** (fomu board)
|
||||||
* TI MSP430 device driver port
|
|
||||||
* Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1, msp_exp430f5529lp etc ...
|
- **[Sylvain "tnt" Munaut](https://github.com/smunaut)**
|
||||||
|
- Add new class driver for DFU Runtime
|
||||||
|
|
||||||
|
- **[Timon Skerutsch](https://github.com/PTS93)**
|
||||||
|
- Add hid_test.js script and extensive test for bi-directional raw HID
|
||||||
|
|
||||||
|
- **[Tod E. Kurt](https://github.com/todbot)**
|
||||||
|
- Add hid_test.js script and extensive test for bi-directional raw HID
|
||||||
|
|
||||||
|
- **[Uwe Bonnes](https://github.com/UweBonnes)**
|
||||||
|
- Improve STM32 Synopsys highspeed DCD
|
||||||
|
|
||||||
|
- **[William D. Jones](https://github.com/cr1901)**
|
||||||
|
- Add new DCD port for **Synopsys DesignWare** for STM32 L4, F2, F4, F7, H7 etc ...
|
||||||
|
- Add new DCD port for **TI MSP430**
|
||||||
|
- Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1, msp_exp430f5529lp etc ...
|
||||||
|
|
||||||
**[Full contributors list](https://github.com/hathach/tinyusb/contributors).**
|
**[Full contributors list](https://github.com/hathach/tinyusb/contributors).**
|
||||||
|
10
README.md
10
README.md
@ -32,12 +32,13 @@ The stack supports the following MCUs:
|
|||||||
|
|
||||||
- **Espressif:** ESP32-S2
|
- **Espressif:** ESP32-S2
|
||||||
- **Dialog:** DA1469x
|
- **Dialog:** DA1469x
|
||||||
- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG (device only)
|
- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55
|
||||||
- **NordicSemi:** nRF52833, nRF52840
|
- **NordicSemi:** nRF52833, nRF52840
|
||||||
- **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
|
- **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
|
||||||
- **NXP:**
|
- **NXP:**
|
||||||
- LPC Series: 11Uxx, 13xx, 175x_6x, 177x_8x, 18xx, 40xx, 43xx, 51Uxx, 54xxx, 55xx
|
|
||||||
- iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
|
- iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
|
||||||
|
- Kinetis: KL25
|
||||||
|
- LPC Series: 11Uxx, 13xx, 175x_6x, 177x_8x, 18xx, 40xx, 43xx, 51Uxx, 54xxx, 55xx
|
||||||
- **Sony:** CXD56
|
- **Sony:** CXD56
|
||||||
- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
|
- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
|
||||||
- **TI:** MSP430
|
- **TI:** MSP430
|
||||||
@ -49,7 +50,10 @@ The stack supports the following MCUs:
|
|||||||
|
|
||||||
Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
|
Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
|
||||||
|
|
||||||
|
- USB Audio Class 2.0 (UAC2) still work in progress
|
||||||
|
- Bluetooth Host Controller Interface (BTH HCI)
|
||||||
- Communication Class (CDC)
|
- Communication Class (CDC)
|
||||||
|
- Device Firmware Update (DFU): only Runtinme
|
||||||
- Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
|
- Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
|
||||||
- Mass Storage Class (MSC): with multiple LUNs
|
- Mass Storage Class (MSC): with multiple LUNs
|
||||||
- Musical Instrument Digital Interface (MIDI)
|
- Musical Instrument Digital Interface (MIDI)
|
||||||
|
124
changelog.md
124
changelog.md
@ -1,46 +1,118 @@
|
|||||||
# TinyUSB Changelog
|
# TinyUSB Changelog
|
||||||
|
|
||||||
## Master branch (WIP)
|
## 0.7.0 - 2020.11.08
|
||||||
|
|
||||||
### Breaking
|
### Device Controller Driver
|
||||||
|
|
||||||
- TinyUSB does not directly implement USB IRQ Handler function anymore. Application must implement IRQ Handler and invoke `tud_int_handler(rhport)`. This is due to:
|
- Added new support for Espressif ESP32-S2
|
||||||
- IRQ Handler name can be different across system depending on the startup
|
- Added new support for Dialog DA1469x
|
||||||
- Some OS need to execute enterISR()/exitISR() to work properly, also tracing tool may need to insert trace ISR enter/exit to record usb event
|
- Enhance STM32 Synopsys
|
||||||
- Give application full control of IRQ handler, can be useful e.g signaling there is new usb event without constant polling
|
- Support bus events disconnection/suspend/resume/wakeup
|
||||||
|
- Improve transfer performance with optimizing xfer and fifo size
|
||||||
|
- Support Highspeed port (OTG_HS) with both internal and external PHY
|
||||||
|
- Support multiple usb ports with rhport=1 is highspeed on selected MCUs e.g H743, F23. It is possible to have OTG_HS to run on Fullspeed PHY (e.g lacking external PHY)
|
||||||
|
- Add ISO transfer, fix odd/even frame
|
||||||
|
- Fix FIFO flush during stall
|
||||||
|
- Implement dcd_edpt_close() API
|
||||||
|
- Support F105, F107
|
||||||
|
- Enhance STM32 fsdev
|
||||||
|
- Improve dcd fifo allocation
|
||||||
|
- Fix ISTR race condition
|
||||||
|
- Support remap USB IRQ on supported MCUs
|
||||||
|
- Implement dcd_edpt_close() API
|
||||||
|
- Enhance NUC 505: enhance set configure behavior
|
||||||
|
- Enhance SAMD
|
||||||
|
- Fix race condition with setup packet
|
||||||
|
- Add SAMD11 option `OPT_MCU_SAMD11`
|
||||||
|
- Add SAME5x option `OPT_MCU_SAME5X`
|
||||||
|
- Fix SAMG control data toggle and stall race condition
|
||||||
|
- Enhance nRF
|
||||||
|
- Fix hanged when tud_task() is called within critical section (disabled interrupt)
|
||||||
|
- Fix disconnect bus event not submitted
|
||||||
|
- Implement ISO transfer and dcd_edpt_close()
|
||||||
|
|
||||||
### MCU
|
### USB Device
|
||||||
|
|
||||||
- Added support for Espressif ESP32-S2 and saola-1 board
|
**USBD**
|
||||||
- All default IRQ Handler is renamed to `dcd_int_handler()`
|
|
||||||
- STM32 Synopsys
|
|
||||||
- Bus events disconnection/suspend/resume are supported
|
|
||||||
- Added `dcd_connect()` and `dcd_disconnect()` to enable/disable internal pullup on D+/D- on supported MCUs.
|
|
||||||
- Added `dcd_edpt_close()` for STM32 FSDev
|
|
||||||
|
|
||||||
### Device Stack
|
- Add new class driver for **Bluetooth HCI** class driver with example can be found in [mynewt-tinyusb-example](https://github.com/hathach/mynewt-tinyusb-example) since it needs mynewt OS to run with.
|
||||||
|
- Fix USBD endpoint usage racing condition with `usbd_edpt_claim()/usbd_edpt_release()`
|
||||||
- tud_cdc_n_write_flush() return number of bytes forced to transfer instead of bool
|
- Added `tud_task_event_ready()` and `osal_queue_empty()`. This API is needed to check before enter low power mode with WFI/WFE
|
||||||
|
- Rename USB IRQ Handler to `dcd_int_handler()`. Application must define IRQ handler in which it calls this API.
|
||||||
|
- Add `dcd_connect()` and `dcd_disconnect()` to enable/disable internal pullup on D+/D- on supported MCUs.
|
||||||
|
- Add `usbd_edpt_open()`
|
||||||
|
- Remove `dcd_set_config()`
|
||||||
|
- Add *OPT_OS_CUMSTOM* as hook for application to overwrite and/or add their own OS implementation
|
||||||
|
- Support SET_INTERFACE, GET_INTERFACE request
|
||||||
|
- Add Logging for debug with optional uart/rtt/swo printf retarget or `CFG_TUSB_DEBUG_PRINTF` hook
|
||||||
|
- Add IAR compiler support
|
||||||
- Support multiple configuration descriptors. `TUD_CONFIG_DESCRIPTOR()` template has extra config_num as 1st argument
|
- Support multiple configuration descriptors. `TUD_CONFIG_DESCRIPTOR()` template has extra config_num as 1st argument
|
||||||
- Improve class driver management
|
- Improve USB Highspeed support with actual link speed detection with `dcd_event_bus_reset()`
|
||||||
- Driver detection is done by open() API
|
- Enhance class driver management
|
||||||
|
- `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
|
||||||
|
- Add application implemented class driver via `usbd_app_driver_get_cb()`
|
||||||
- IAD is handled to assign driver id
|
- IAD is handled to assign driver id
|
||||||
- Improve Alternate Interface request with `SET_INTERFACE()` (not fully supported yet).
|
- Added `tud_descriptor_device_qualifier_cb()` callback
|
||||||
- Fixed CDC ZLP response #260
|
- Optimize `tu_fifo` bulk write/read transfer
|
||||||
- Remove ACM-EEM due to lack of support from host
|
- Forward non-std control request to class driver
|
||||||
|
- Let application handle Microsoft OS 1.0 Descriptors (the 0xEE index string)
|
||||||
|
- Fix OSAL FreeRTOS yield from ISR
|
||||||
|
|
||||||
### Others
|
**Class Drivers**
|
||||||
|
|
||||||
- Added OPT_OS_CUMSTOM as hook for application to overwrite and/or add their own OS implementation
|
- USBNET: remove ACM-EEM due to lack of support from host
|
||||||
- Enhanced `net_lwip_webserver` example with multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
|
- USBTMC: fix descriptors when INT EP is disabled
|
||||||
|
- CDC:
|
||||||
|
- Send zero length packet for end of data when needed
|
||||||
|
- Add `tud_cdc_tx_complete_cb()` callback
|
||||||
|
- Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
|
||||||
|
- MIDI:
|
||||||
|
- Add packet interface
|
||||||
|
- Add multiple jack descriptors
|
||||||
|
- Fix MIDI driver for sysex
|
||||||
|
- DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
|
||||||
|
- Rename some configure macro to make it clear that those are used directly for endpoint transfer
|
||||||
|
- CFG_TUD_HID_BUFSIZE to `CFG_TUD_HID_EP_BUFSIZE
|
||||||
|
- CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
|
||||||
|
- CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
|
||||||
|
- CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
|
||||||
|
- HID:
|
||||||
|
- Fix gamepad template descriptor
|
||||||
|
- Add multiple HID interface API
|
||||||
|
- Add extra comma to HID_REPORT_ID
|
||||||
|
|
||||||
## 0.6.0 - 2019.03.30
|
### USB Host
|
||||||
|
|
||||||
|
- Rework USB host stack (still work in progress)
|
||||||
|
- Fix compile error with pipehandle
|
||||||
|
- Rework usbh control and enumeration as non-blocking
|
||||||
|
- Improve Hub, MSC, HID host driver
|
||||||
|
|
||||||
|
### Examples
|
||||||
|
|
||||||
|
- Add new hid_composite_freertos
|
||||||
|
- Add new dynamic_configuration to demonstrate how to switch configuration descriptors
|
||||||
|
- Add new hid_multiple_interface
|
||||||
|
- Enhance `net_lwip_webserver` example
|
||||||
|
- Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
|
||||||
|
- Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
|
||||||
|
- Added new Audio example: audio_test uac2_headsest
|
||||||
|
|
||||||
|
### New Boards
|
||||||
|
|
||||||
|
- Espressif ESP32-S2: saola_1, kaluga_1
|
||||||
|
- STM32: F746 Nucleo, H743 Eval, H743 Nucleo, F723 discovery, stlink v3 mini, STM32L4r5 Nucleo
|
||||||
|
- Dialog DA1469x dk pro and dk usb
|
||||||
|
- Microchip: Great Scoot Gadgets' LUNA, samd11_xplained, D5035-01, atsamd21 xplained pro
|
||||||
|
- nRF: ItsyBitsy nRF52840
|
||||||
|
|
||||||
|
## 0.6.0 - 2020.03.30
|
||||||
|
|
||||||
Added **CONTRIBUTORS.md** to give proper credit for contributors to the stack. Special thanks to [Nathan Conrad](https://github.com/pigrew), [Peter Lawrence](https://github.com/majbthrd) and [William D. Jones](https://github.com/cr1901) and others for spending their precious time to add lots of features and ports for this release.
|
Added **CONTRIBUTORS.md** to give proper credit for contributors to the stack. Special thanks to [Nathan Conrad](https://github.com/pigrew), [Peter Lawrence](https://github.com/majbthrd) and [William D. Jones](https://github.com/cr1901) and others for spending their precious time to add lots of features and ports for this release.
|
||||||
|
|
||||||
### Added
|
### Added
|
||||||
|
|
||||||
**MCU**
|
**MCUs**
|
||||||
|
|
||||||
- Added support for Microchip SAMG55
|
- Added support for Microchip SAMG55
|
||||||
- Added support for Nordic nRF52833
|
- Added support for Nordic nRF52833
|
||||||
|
@ -68,6 +68,10 @@ This code base already had supported for a handful of following boards (sorted a
|
|||||||
- [MIMX RT1064 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK)
|
- [MIMX RT1064 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK)
|
||||||
- [Teensy 4.0 Development Board](https://www.pjrc.com/store/teensy40.html)
|
- [Teensy 4.0 Development Board](https://www.pjrc.com/store/teensy40.html)
|
||||||
|
|
||||||
|
### NXP Kinetis
|
||||||
|
|
||||||
|
- [FRDM-KL25Z](https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z)
|
||||||
|
|
||||||
### NXP LPC
|
### NXP LPC
|
||||||
|
|
||||||
- [ARM mbed LPC1768](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-cortex-m3/arm-mbed-lpc1768-board:OM11043)
|
- [ARM mbed LPC1768](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-cortex-m3/arm-mbed-lpc1768-board:OM11043)
|
||||||
|
@ -4,14 +4,15 @@
|
|||||||
|
|
||||||
It is relatively simple to incorporate tinyusb to your (existing) project
|
It is relatively simple to incorporate tinyusb to your (existing) project
|
||||||
|
|
||||||
1. Copy or `git submodule` this repo into your project in a subfolder. Let's say it is *your_project/tinyusb*
|
- Copy or `git submodule` this repo into your project in a subfolder. Let's say it is *your_project/tinyusb*
|
||||||
2. Add all the .c in the src folder to your project settings (uvproj, ewp, makefile)
|
- Add all the .c in the `tinyusb/src` folder to your project
|
||||||
3. Add *your_project/tinysb* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h. Or you could simply put the tusb_config.h into the tinyusb folder as well.
|
- Add *your_project/tinyusb/src* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h.
|
||||||
4. Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards).
|
- Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards).
|
||||||
5. If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud_descriptor_** callbacks for that stack to work.
|
- If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud_descriptor_** callbacks for the stack to work.
|
||||||
6. Add tusb_init() call to your reset initialization code.
|
- Add tusb_init() call to your reset initialization code.
|
||||||
7. Implement all enabled classes's callbacks.
|
- Call `tud_int_handler()` (device stack) and/or `tuh_int_handler()` in your USB IRQ Handler
|
||||||
8. If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoke within the call of that task runner.
|
- Implement all enabled classes's callbacks.
|
||||||
|
- If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoke within the call of that task runner.
|
||||||
|
|
||||||
~~~{.c}
|
~~~{.c}
|
||||||
int main(void)
|
int main(void)
|
||||||
@ -23,8 +24,8 @@ int main(void)
|
|||||||
{
|
{
|
||||||
your_application_code();
|
your_application_code();
|
||||||
|
|
||||||
tud_task(); // tinyusb device task
|
tud_task(); // device task
|
||||||
tuh_task(); // tinyusb host task
|
tuh_task(); // host task
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
~~~
|
~~~
|
||||||
|
@ -83,6 +83,8 @@ static void cdc_task(void)
|
|||||||
|
|
||||||
for (itf = 0; itf < CFG_TUD_CDC; itf++)
|
for (itf = 0; itf < CFG_TUD_CDC; itf++)
|
||||||
{
|
{
|
||||||
|
// connected() check for DTR bit
|
||||||
|
// Most but not all terminal client set this when making connection
|
||||||
if ( tud_cdc_n_connected(itf) )
|
if ( tud_cdc_n_connected(itf) )
|
||||||
{
|
{
|
||||||
if ( tud_cdc_n_available(itf) )
|
if ( tud_cdc_n_available(itf) )
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml"
|
linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml"
|
||||||
linker_section_placement_file="flash_placement.xml"
|
linker_section_placement_file="flash_placement.xml"
|
||||||
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
||||||
macros="DeviceFamily=SAMD21;Target=ATSAMD21G18A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/samd/asf4/samd21"
|
macros="DeviceFamily=SAMD21;Target=ATSAMD21G18A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd21"
|
||||||
project_directory=""
|
project_directory=""
|
||||||
project_type="Executable"
|
project_type="Executable"
|
||||||
target_reset_script="Reset();"
|
target_reset_script="Reset();"
|
||||||
@ -54,22 +54,22 @@
|
|||||||
<folder Name="asf4">
|
<folder Name="asf4">
|
||||||
<folder Name="samd21">
|
<folder Name="samd21">
|
||||||
<folder Name="gcc">
|
<folder Name="gcc">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="hpl">
|
<folder Name="hpl">
|
||||||
<folder Name="gclk">
|
<folder Name="gclk">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="pm">
|
<folder Name="pm">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="sysctrl">
|
<folder Name="sysctrl">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c" />
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="hal">
|
<folder Name="hal">
|
||||||
<folder Name="src">
|
<folder Name="src">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c" />
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
|
@ -29,7 +29,7 @@
|
|||||||
linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml"
|
linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml"
|
||||||
linker_section_placement_file="flash_placement.xml"
|
linker_section_placement_file="flash_placement.xml"
|
||||||
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
||||||
macros="DeviceFamily=SAMD51;Target=ATSAMD51J19A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/samd/asf4/samd51"
|
macros="DeviceFamily=SAMD51;Target=ATSAMD51J19A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd51"
|
||||||
project_directory=""
|
project_directory=""
|
||||||
project_type="Executable"
|
project_type="Executable"
|
||||||
target_reset_script="Reset();"
|
target_reset_script="Reset();"
|
||||||
@ -55,25 +55,25 @@
|
|||||||
<folder Name="asf4">
|
<folder Name="asf4">
|
||||||
<folder Name="samd51">
|
<folder Name="samd51">
|
||||||
<folder Name="gcc">
|
<folder Name="gcc">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/gcc/system_samd51.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="hpl">
|
<folder Name="hpl">
|
||||||
<folder Name="osc32kctrl">
|
<folder Name="osc32kctrl">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="oscctrl">
|
<folder Name="oscctrl">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="mclk">
|
<folder Name="mclk">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/mclk/hpl_mclk.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="gclk">
|
<folder Name="gclk">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/gclk/hpl_gclk.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c" />
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="hal">
|
<folder Name="hal">
|
||||||
<folder Name="src">
|
<folder Name="src">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hal/src/hal_atomic.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hal/src/hal_atomic.c" />
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
|
@ -105,7 +105,9 @@ void tud_resume_cb(void)
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void cdc_task(void)
|
void cdc_task(void)
|
||||||
{
|
{
|
||||||
if ( tud_cdc_connected() )
|
// connected() check for DTR bit
|
||||||
|
// Most but not all terminal client set this when making connection
|
||||||
|
// if ( tud_cdc_connected() )
|
||||||
{
|
{
|
||||||
// connected and there are data available
|
// connected and there are data available
|
||||||
if ( tud_cdc_available() )
|
if ( tud_cdc_available() )
|
||||||
@ -131,12 +133,14 @@ void cdc_task(void)
|
|||||||
void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
|
void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
|
||||||
{
|
{
|
||||||
(void) itf;
|
(void) itf;
|
||||||
|
(void) rts;
|
||||||
|
|
||||||
// connected
|
// connected
|
||||||
if ( dtr && rts )
|
if ( dtr )
|
||||||
{
|
{
|
||||||
// print initial message when connected
|
// print initial message when connected
|
||||||
tud_cdc_write_str("\r\nTinyUSB CDC MSC device example\r\n");
|
tud_cdc_write_str("\r\nTinyUSB CDC MSC device example\r\n");
|
||||||
|
tud_cdc_write_flush();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -28,6 +28,9 @@
|
|||||||
|
|
||||||
#if CFG_TUD_MSC
|
#if CFG_TUD_MSC
|
||||||
|
|
||||||
|
// whether host does safe-eject
|
||||||
|
static bool ejected = false;
|
||||||
|
|
||||||
// Some MCU doesn't have enough 8KB SRAM to store the whole disk
|
// Some MCU doesn't have enough 8KB SRAM to store the whole disk
|
||||||
// We will use Flash as read-only disk with board that has
|
// We will use Flash as read-only disk with board that has
|
||||||
// CFG_EXAMPLE_MSC_READONLY defined
|
// CFG_EXAMPLE_MSC_READONLY defined
|
||||||
@ -137,7 +140,13 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun)
|
|||||||
{
|
{
|
||||||
(void) lun;
|
(void) lun;
|
||||||
|
|
||||||
return true; // RAM disk is always ready
|
// RAM disk is ready until ejected
|
||||||
|
if (ejected) {
|
||||||
|
tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
|
// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
|
||||||
@ -166,6 +175,7 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo
|
|||||||
}else
|
}else
|
||||||
{
|
{
|
||||||
// unload disk storage
|
// unload disk storage
|
||||||
|
ejected = true;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
0
examples/device/cdc_msc_freertos/.skip.MCU_MKL25ZXX
Normal file
0
examples/device/cdc_msc_freertos/.skip.MCU_MKL25ZXX
Normal file
@ -27,7 +27,7 @@
|
|||||||
linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml"
|
linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml"
|
||||||
linker_section_placement_file="flash_placement.xml"
|
linker_section_placement_file="flash_placement.xml"
|
||||||
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
||||||
macros="DeviceFamily=SAMD21;Target=ATSAMD21G18A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/samd/asf4/samd21;freertosDir=../../../../../lib/FreeRTOS"
|
macros="DeviceFamily=SAMD21;Target=ATSAMD21G18A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd21;freertosDir=../../../../../lib/FreeRTOS"
|
||||||
project_directory=""
|
project_directory=""
|
||||||
project_type="Executable"
|
project_type="Executable"
|
||||||
target_reset_script="Reset();"
|
target_reset_script="Reset();"
|
||||||
@ -52,20 +52,20 @@
|
|||||||
<folder Name="asf4">
|
<folder Name="asf4">
|
||||||
<folder Name="samd21">
|
<folder Name="samd21">
|
||||||
<folder Name="gcc">
|
<folder Name="gcc">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="hpl">
|
<folder Name="hpl">
|
||||||
<folder Name="core">
|
<folder Name="core">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/core/hpl_init.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/core/hpl_init.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="gclk">
|
<folder Name="gclk">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="pm">
|
<folder Name="pm">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="sysctrl">
|
<folder Name="sysctrl">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c" />
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml"
|
linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml"
|
||||||
linker_section_placement_file="flash_placement.xml"
|
linker_section_placement_file="flash_placement.xml"
|
||||||
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
|
||||||
macros="DeviceFamily=SAMD51;Target=ATSAMD51J19A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/samd/asf4/samd51;freertosDir=../../../../../lib/FreeRTOS"
|
macros="DeviceFamily=SAMD51;Target=ATSAMD51J19A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd51;freertosDir=../../../../../lib/FreeRTOS"
|
||||||
project_directory=""
|
project_directory=""
|
||||||
project_type="Executable"
|
project_type="Executable"
|
||||||
target_reset_script="Reset();"
|
target_reset_script="Reset();"
|
||||||
@ -53,23 +53,23 @@
|
|||||||
<folder Name="asf4">
|
<folder Name="asf4">
|
||||||
<folder Name="samd51">
|
<folder Name="samd51">
|
||||||
<folder Name="gcc">
|
<folder Name="gcc">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/gcc/system_samd51.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="hpl">
|
<folder Name="hpl">
|
||||||
<folder Name="core">
|
<folder Name="core">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/core/hpl_init.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/core/hpl_init.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="osc32kctrl">
|
<folder Name="osc32kctrl">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="oscctrl">
|
<folder Name="oscctrl">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="mclk">
|
<folder Name="mclk">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/mclk/hpl_mclk.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c" />
|
||||||
</folder>
|
</folder>
|
||||||
<folder Name="gclk">
|
<folder Name="gclk">
|
||||||
<file file_name="../../../../../hw/mcu/microchip/samd/asf4/samd51/hpl/gclk/hpl_gclk.c" />
|
<file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c" />
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
</folder>
|
</folder>
|
||||||
|
@ -168,9 +168,11 @@ void cdc_task(void* params)
|
|||||||
// RTOS forever loop
|
// RTOS forever loop
|
||||||
while ( 1 )
|
while ( 1 )
|
||||||
{
|
{
|
||||||
if ( tud_cdc_connected() )
|
// connected() check for DTR bit
|
||||||
|
// Most but not all terminal client set this when making connection
|
||||||
|
// if ( tud_cdc_connected() )
|
||||||
{
|
{
|
||||||
// connected and there are data available
|
// There are data available
|
||||||
if ( tud_cdc_available() )
|
if ( tud_cdc_available() )
|
||||||
{
|
{
|
||||||
uint8_t buf[64];
|
uint8_t buf[64];
|
||||||
@ -198,12 +200,14 @@ void cdc_task(void* params)
|
|||||||
void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
|
void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
|
||||||
{
|
{
|
||||||
(void) itf;
|
(void) itf;
|
||||||
|
(void) rts;
|
||||||
|
|
||||||
// connected
|
// connected
|
||||||
if ( dtr && rts )
|
if ( dtr )
|
||||||
{
|
{
|
||||||
// print initial message when connected
|
// print initial message when connected
|
||||||
tud_cdc_write_str("\r\nTinyUSB CDC MSC device with FreeRTOS example\r\n");
|
tud_cdc_write_str("\r\nTinyUSB CDC MSC device with FreeRTOS example\r\n");
|
||||||
|
tud_cdc_write_flush();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -58,7 +58,12 @@ StaticTimer_t blinky_tmdef;
|
|||||||
TimerHandle_t blinky_tm;
|
TimerHandle_t blinky_tm;
|
||||||
|
|
||||||
// static task for usbd
|
// static task for usbd
|
||||||
#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2)
|
#if CFG_TUSB_DEBUG
|
||||||
|
#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE)
|
||||||
|
#else
|
||||||
|
#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2)
|
||||||
|
#endif
|
||||||
|
|
||||||
StackType_t usb_device_stack[USBD_STACK_SIZE];
|
StackType_t usb_device_stack[USBD_STACK_SIZE];
|
||||||
StaticTask_t usb_device_taskdef;
|
StaticTask_t usb_device_taskdef;
|
||||||
|
|
||||||
|
0
examples/device/msc_dual_lun/.skip.MCU_MKL25ZXX
Normal file
0
examples/device/msc_dual_lun/.skip.MCU_MKL25ZXX
Normal file
@ -143,9 +143,14 @@ void tud_resume_cb(void)
|
|||||||
// WebUSB use vendor class
|
// WebUSB use vendor class
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
// Invoked when received VENDOR control request
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
bool tud_vendor_control_request_cb(uint8_t rhport, tusb_control_request_t const * request)
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
|
bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
|
// nothing to with DATA & ACK stage
|
||||||
|
if (stage != CONTROL_STAGE_SETUP ) return true;
|
||||||
|
|
||||||
switch (request->bRequest)
|
switch (request->bRequest)
|
||||||
{
|
{
|
||||||
case VENDOR_REQUEST_WEBUSB:
|
case VENDOR_REQUEST_WEBUSB:
|
||||||
@ -194,16 +199,6 @@ bool tud_vendor_control_request_cb(uint8_t rhport, tusb_control_request_t const
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when DATA Stage of VENDOR's request is complete
|
|
||||||
bool tud_vendor_control_complete_cb(uint8_t rhport, tusb_control_request_t const * request)
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
(void) request;
|
|
||||||
|
|
||||||
// nothing to do
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
void webserial_task(void)
|
void webserial_task(void)
|
||||||
{
|
{
|
||||||
if ( web_serial_connected )
|
if ( web_serial_connected )
|
||||||
|
@ -16,8 +16,9 @@ SRC_C += \
|
|||||||
src/class/cdc/cdc_host.c \
|
src/class/cdc/cdc_host.c \
|
||||||
src/class/hid/hid_host.c \
|
src/class/hid/hid_host.c \
|
||||||
src/class/msc/msc_host.c \
|
src/class/msc/msc_host.c \
|
||||||
src/host/usbh.c \
|
|
||||||
src/host/hub.c \
|
src/host/hub.c \
|
||||||
|
src/host/usbh.c \
|
||||||
|
src/host/usbh_control.c \
|
||||||
src/host/ehci/ehci.c \
|
src/host/ehci/ehci.c \
|
||||||
src/host/ohci/ohci.c \
|
src/host/ohci/ohci.c \
|
||||||
src/portable/nxp/lpc18_43/hcd_lpc18_43.c \
|
src/portable/nxp/lpc18_43/hcd_lpc18_43.c \
|
||||||
|
@ -23,6 +23,7 @@
|
|||||||
debug_target_connection="J-Link"
|
debug_target_connection="J-Link"
|
||||||
gcc_entry_point="Reset_Handler"
|
gcc_entry_point="Reset_Handler"
|
||||||
linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml"
|
linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml"
|
||||||
|
linker_printf_width_precision_supported="Yes"
|
||||||
linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
|
linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
|
||||||
macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx"
|
macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx"
|
||||||
package_dependencies="LPC1800"
|
package_dependencies="LPC1800"
|
||||||
|
@ -111,6 +111,7 @@ void cdc_task(void)
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
#if CFG_TUH_HID_KEYBOARD
|
#if CFG_TUH_HID_KEYBOARD
|
||||||
|
|
||||||
|
CFG_TUSB_MEM_SECTION static hid_keyboard_report_t usb_keyboard_report;
|
||||||
uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
|
uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
|
||||||
|
|
||||||
// look up new key in previous keys
|
// look up new key in previous keys
|
||||||
@ -153,21 +154,6 @@ static inline void process_kbd_report(hid_keyboard_report_t const *p_new_report)
|
|||||||
prev_report = *p_new_report;
|
prev_report = *p_new_report;
|
||||||
}
|
}
|
||||||
|
|
||||||
CFG_TUSB_MEM_SECTION static hid_keyboard_report_t usb_keyboard_report;
|
|
||||||
|
|
||||||
void hid_task(void)
|
|
||||||
{
|
|
||||||
uint8_t const addr = 1;
|
|
||||||
if ( tuh_hid_keyboard_is_mounted(addr) )
|
|
||||||
{
|
|
||||||
if ( !tuh_hid_keyboard_is_busy(addr) )
|
|
||||||
{
|
|
||||||
process_kbd_report(&usb_keyboard_report);
|
|
||||||
tuh_hid_keyboard_get_report(addr, &usb_keyboard_report);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void tuh_hid_keyboard_mounted_cb(uint8_t dev_addr)
|
void tuh_hid_keyboard_mounted_cb(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
// application set-up
|
// application set-up
|
||||||
@ -192,6 +178,58 @@ void tuh_hid_keyboard_isr(uint8_t dev_addr, xfer_result_t event)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUH_HID_MOUSE
|
#if CFG_TUH_HID_MOUSE
|
||||||
|
|
||||||
|
CFG_TUSB_MEM_SECTION static hid_mouse_report_t usb_mouse_report;
|
||||||
|
|
||||||
|
void cursor_movement(int8_t x, int8_t y, int8_t wheel)
|
||||||
|
{
|
||||||
|
//------------- X -------------//
|
||||||
|
if ( x < 0)
|
||||||
|
{
|
||||||
|
printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left
|
||||||
|
}else if ( x > 0)
|
||||||
|
{
|
||||||
|
printf(ANSI_CURSOR_FORWARD(%d), x); // move right
|
||||||
|
}else { }
|
||||||
|
|
||||||
|
//------------- Y -------------//
|
||||||
|
if ( y < 0)
|
||||||
|
{
|
||||||
|
printf(ANSI_CURSOR_UP(%d), (-y)); // move up
|
||||||
|
}else if ( y > 0)
|
||||||
|
{
|
||||||
|
printf(ANSI_CURSOR_DOWN(%d), y); // move down
|
||||||
|
}else { }
|
||||||
|
|
||||||
|
//------------- wheel -------------//
|
||||||
|
if (wheel < 0)
|
||||||
|
{
|
||||||
|
printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up
|
||||||
|
}else if (wheel > 0)
|
||||||
|
{
|
||||||
|
printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down
|
||||||
|
}else { }
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void process_mouse_report(hid_mouse_report_t const * p_report)
|
||||||
|
{
|
||||||
|
static hid_mouse_report_t prev_report = { 0 };
|
||||||
|
|
||||||
|
//------------- button state -------------//
|
||||||
|
uint8_t button_changed_mask = p_report->buttons ^ prev_report.buttons;
|
||||||
|
if ( button_changed_mask & p_report->buttons)
|
||||||
|
{
|
||||||
|
printf(" %c%c%c ",
|
||||||
|
p_report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-',
|
||||||
|
p_report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-',
|
||||||
|
p_report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-');
|
||||||
|
}
|
||||||
|
|
||||||
|
//------------- cursor movement -------------//
|
||||||
|
cursor_movement(p_report->x, p_report->y, p_report->wheel);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
void tuh_hid_mouse_mounted_cb(uint8_t dev_addr)
|
void tuh_hid_mouse_mounted_cb(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
// application set-up
|
// application set-up
|
||||||
@ -212,6 +250,35 @@ void tuh_hid_mouse_isr(uint8_t dev_addr, xfer_result_t event)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void hid_task(void)
|
||||||
|
{
|
||||||
|
uint8_t const addr = 1;
|
||||||
|
|
||||||
|
#if CFG_TUH_HID_KEYBOARD
|
||||||
|
if ( tuh_hid_keyboard_is_mounted(addr) )
|
||||||
|
{
|
||||||
|
if ( !tuh_hid_keyboard_is_busy(addr) )
|
||||||
|
{
|
||||||
|
process_kbd_report(&usb_keyboard_report);
|
||||||
|
tuh_hid_keyboard_get_report(addr, &usb_mouse_report);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CFG_TUH_HID_MOUSE
|
||||||
|
if ( tuh_hid_mouse_is_mounted(addr) )
|
||||||
|
{
|
||||||
|
if ( !tuh_hid_mouse_is_busy(addr) )
|
||||||
|
{
|
||||||
|
process_mouse_report(&usb_mouse_report);
|
||||||
|
tuh_hid_mouse_get_report(addr, &usb_mouse_report);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// tinyusb callbacks
|
// tinyusb callbacks
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
@ -30,29 +30,59 @@
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
static scsi_inquiry_resp_t inquiry_resp;
|
||||||
|
static scsi_read_capacity10_resp_t capacity_resp;
|
||||||
|
|
||||||
|
uint32_t block_size;
|
||||||
|
uint32_t block_count;
|
||||||
|
|
||||||
|
bool capacity_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
|
||||||
|
{
|
||||||
|
(void) dev_addr;
|
||||||
|
(void) cbw;
|
||||||
|
|
||||||
|
if (csw->status != 0)
|
||||||
|
{
|
||||||
|
printf("Read Capacity (10) failed\r\n");
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Capacity response field: Block size and Last LBA are both Big-Endian
|
||||||
|
block_count = tu_ntohl(capacity_resp.last_lba) + 1;
|
||||||
|
block_size = tu_ntohl(capacity_resp.block_size);
|
||||||
|
|
||||||
|
printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
|
||||||
|
printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
|
||||||
|
{
|
||||||
|
if (csw->status != 0)
|
||||||
|
{
|
||||||
|
printf("Inquiry failed\r\n");
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Print out Vendor ID, Product ID and Rev
|
||||||
|
printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
|
||||||
|
|
||||||
|
// Read capacity of device
|
||||||
|
tuh_msc_read_capacity(dev_addr, cbw->lun, &capacity_resp, capacity_complete_cb);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
//------------- IMPLEMENTATION -------------//
|
//------------- IMPLEMENTATION -------------//
|
||||||
void tuh_msc_mounted_cb(uint8_t dev_addr)
|
void tuh_msc_mounted_cb(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
printf("A MassStorage device is mounted\r\n");
|
printf("A MassStorage device is mounted\r\n");
|
||||||
|
|
||||||
//------------- Disk Information -------------//
|
block_size = block_count = 0;
|
||||||
// SCSI VendorID[8] & ProductID[16] from Inquiry Command
|
|
||||||
uint8_t const* p_vendor = tuh_msc_get_vendor_name(dev_addr);
|
|
||||||
uint8_t const* p_product = tuh_msc_get_product_name(dev_addr);
|
|
||||||
|
|
||||||
for(uint8_t i=0; i<8; i++) putchar(p_vendor[i]);
|
uint8_t const lun = 0;
|
||||||
|
tuh_msc_scsi_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
|
||||||
putchar(' ');
|
|
||||||
for(uint8_t i=0; i<16; i++) putchar(p_product[i]);
|
|
||||||
putchar('\n');
|
|
||||||
|
|
||||||
uint32_t last_lba = 0;
|
|
||||||
uint32_t block_size = 0;
|
|
||||||
tuh_msc_get_capacity(dev_addr, &last_lba, &block_size);
|
|
||||||
printf("Disk Size: %ld MB\r\n", (last_lba+1)/ ((1024*1024)/block_size) );
|
|
||||||
printf("LBA 0-0x%lX Block Size: %ld\r\n", last_lba, block_size);
|
|
||||||
//
|
//
|
||||||
// //------------- file system (only 1 LUN support) -------------//
|
// //------------- file system (only 1 LUN support) -------------//
|
||||||
// uint8_t phy_disk = dev_addr-1;
|
// uint8_t phy_disk = dev_addr-1;
|
||||||
@ -103,12 +133,11 @@ void tuh_msc_unmounted_cb(uint8_t dev_addr)
|
|||||||
// }
|
// }
|
||||||
}
|
}
|
||||||
|
|
||||||
// invoked ISR context
|
//void tuh_msc_scsi_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
|
||||||
void tuh_msc_isr(uint8_t dev_addr, xfer_result_t event, uint32_t xferred_bytes)
|
//{
|
||||||
{
|
// (void) dev_addr;
|
||||||
(void) dev_addr;
|
// (void) cbw;
|
||||||
(void) event;
|
// (void) csw;
|
||||||
(void) xferred_bytes;
|
//}
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -69,7 +69,7 @@
|
|||||||
// CONFIGURATION
|
// CONFIGURATION
|
||||||
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
||||||
|
|
||||||
#define CFG_TUH_HUB 0
|
#define CFG_TUH_HUB 1
|
||||||
#define CFG_TUH_CDC 1
|
#define CFG_TUH_CDC 1
|
||||||
#define CFG_TUH_HID_KEYBOARD 1
|
#define CFG_TUH_HID_KEYBOARD 1
|
||||||
#define CFG_TUH_HID_MOUSE 1
|
#define CFG_TUH_HID_MOUSE 1
|
||||||
|
@ -64,7 +64,7 @@ void tuh_msc_mounted_cb(uint8_t dev_addr)
|
|||||||
putchar('\n');
|
putchar('\n');
|
||||||
|
|
||||||
uint32_t last_lba, block_size;
|
uint32_t last_lba, block_size;
|
||||||
tuh_msc_get_capacity(dev_addr, &last_lba, &block_size);
|
tuh_msc_read_capacity(dev_addr, &last_lba, &block_size);
|
||||||
printf("Disk Size: %d MB\n", (last_lba+1)/ ((1024*1024)/block_size) );
|
printf("Disk Size: %d MB\n", (last_lba+1)/ ((1024*1024)/block_size) );
|
||||||
printf("LBA 0-0x%X Block Size: %d\n", last_lba, block_size);
|
printf("LBA 0-0x%X Block Size: %d\n", last_lba, block_size);
|
||||||
|
|
||||||
|
@ -12,23 +12,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/atsamd21_xpro/samd21j18a_flash.ld
|
LD_FILE = hw/bsp/atsamd21_xpro/samd21j18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -46,7 +46,7 @@
|
|||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
|
|
||||||
#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
|
#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
|
||||||
CFG_TUSB_MCU == OPT_MCU_LPC55XX
|
CFG_TUSB_MCU == OPT_MCU_LPC55XX || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX
|
||||||
#include "fsl_device_registers.h"
|
#include "fsl_device_registers.h"
|
||||||
|
|
||||||
#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
|
#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
|
||||||
|
@ -11,23 +11,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -21,30 +21,30 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/same51/gcc/gcc/startup_same51.c \
|
hw/mcu/microchip/asf4/same51/gcc/gcc/startup_same51.c \
|
||||||
hw/mcu/microchip/samd/asf4/same51/gcc/system_same51.c \
|
hw/mcu/microchip/asf4/same51/gcc/system_same51.c \
|
||||||
|
|
||||||
ifdef SYSCALLS
|
ifdef SYSCALLS
|
||||||
ifneq ($(SYSCALLS),0)
|
ifneq ($(SYSCALLS),0)
|
||||||
SRC_C += hw/mcu/microchip/samd/asf4/same51/hal/utils/src/utils_syscalls.c
|
SRC_C += hw/mcu/microchip/asf4/same51/hal/utils/src/utils_syscalls.c
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifdef LOG
|
ifdef LOG
|
||||||
ifneq ($(LOG),0)
|
ifneq ($(LOG),0)
|
||||||
SRC_C += hw/mcu/microchip/samd/asf4/same51/hal/utils/src/utils_syscalls.c
|
SRC_C += hw/mcu/microchip/asf4/same51/hal/utils/src/utils_syscalls.c
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/ \
|
$(TOP)/hw/mcu/microchip/asf4/same51/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/config \
|
$(TOP)/hw/mcu/microchip/asf4/same51/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/include \
|
$(TOP)/hw/mcu/microchip/asf4/same51/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/same51/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/same51/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/same51/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/hri \
|
$(TOP)/hw/mcu/microchip/asf4/same51/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/same51/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/same51/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -98,6 +98,11 @@ void SystemInit(void)
|
|||||||
|
|
||||||
Chip_IOCON_Init(LPC_IOCON);
|
Chip_IOCON_Init(LPC_IOCON);
|
||||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||||
|
|
||||||
|
/* CPU clock source starts with IRC */
|
||||||
|
/* Enable PBOOST for CPU clock over 100MHz */
|
||||||
|
Chip_SYSCTL_EnableBoost();
|
||||||
|
|
||||||
Chip_SetupXtalClocking();
|
Chip_SetupXtalClocking();
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -130,13 +135,15 @@ void board_init(void)
|
|||||||
Chip_USB_Init();
|
Chip_USB_Init();
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
USBCLK = 0x1B // Host + Device + OTG + AHB
|
USBCLK_DEVCIE = 0x12, // AHB + Device
|
||||||
|
USBCLK_HOST = 0x19 , // AHB + OTG + Host
|
||||||
|
USBCLK_ALL = 0x1B // Host + Device + OTG + AHB
|
||||||
};
|
};
|
||||||
|
|
||||||
LPC_USB->OTGClkCtrl = USBCLK;
|
LPC_USB->OTGClkCtrl = USBCLK_ALL;
|
||||||
while ( (LPC_USB->OTGClkSt & USBCLK) != USBCLK ) {}
|
while ( (LPC_USB->OTGClkSt & USBCLK_ALL) != USBCLK_ALL ) {}
|
||||||
|
|
||||||
// USB1 = host, USB2 = device
|
// set portfunc: USB1 = host, USB2 = device
|
||||||
LPC_USB->StCtrl = 0x3;
|
LPC_USB->StCtrl = 0x3;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -12,23 +12,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -15,23 +15,23 @@ CFLAGS += -Wno-error=undef
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd51g19a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd51g19a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/gcc/gcc/startup_samd51.c \
|
hw/mcu/microchip/asf4/samd51/gcc/gcc/startup_samd51.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/gcc/system_samd51.c \
|
hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/mclk/hpl_mclk.c \
|
hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
|
hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c \
|
hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd51/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd51/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
46
hw/bsp/frdm_kl25z/board.mk
Normal file
46
hw/bsp/frdm_kl25z/board.mk
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
CFLAGS += \
|
||||||
|
-mthumb \
|
||||||
|
-mabi=aapcs \
|
||||||
|
-mcpu=cortex-m0plus \
|
||||||
|
-DCPU_MKL25Z128VLK4 \
|
||||||
|
-DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX
|
||||||
|
|
||||||
|
# mcu driver cause following warnings
|
||||||
|
CFLAGS += -Wno-error=unused-parameter
|
||||||
|
|
||||||
|
MCU_DIR = hw/mcu/nxp/sdk/devices/MKL25Z4
|
||||||
|
|
||||||
|
# All source paths should be relative to the top level.
|
||||||
|
LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
|
||||||
|
|
||||||
|
SRC_C += \
|
||||||
|
$(MCU_DIR)/system_MKL25Z4.c \
|
||||||
|
$(MCU_DIR)/project_template/clock_config.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_clock.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_gpio.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_lpsci.c
|
||||||
|
|
||||||
|
INC += \
|
||||||
|
$(TOP)/hw/bsp/$(BOARD) \
|
||||||
|
$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
|
||||||
|
$(TOP)/$(MCU_DIR) \
|
||||||
|
$(TOP)/$(MCU_DIR)/drivers \
|
||||||
|
$(TOP)/$(MCU_DIR)/project_template \
|
||||||
|
|
||||||
|
SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
|
||||||
|
|
||||||
|
# For TinyUSB port source
|
||||||
|
VENDOR = nxp
|
||||||
|
CHIP_FAMILY = khci
|
||||||
|
|
||||||
|
# For freeRTOS port source
|
||||||
|
FREERTOS_PORT = ARM_CM0
|
||||||
|
|
||||||
|
# For flash-jlink target
|
||||||
|
JLINK_DEVICE = MKL25Z128xxx4
|
||||||
|
|
||||||
|
# For flash-pyocd target
|
||||||
|
PYOCD_TARGET = mkl25zl128
|
||||||
|
|
||||||
|
# flash using pyocd
|
||||||
|
flash: flash-pyocd
|
148
hw/bsp/frdm_kl25z/frdm_kl25z.c
Normal file
148
hw/bsp/frdm_kl25z/frdm_kl25z.c
Normal file
@ -0,0 +1,148 @@
|
|||||||
|
/*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018, hathach (tinyusb.org)
|
||||||
|
* Copyright (c) 2020, Koji Kitayama
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* This file is part of the TinyUSB stack.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../board.h"
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
#include "fsl_gpio.h"
|
||||||
|
#include "fsl_port.h"
|
||||||
|
#include "fsl_clock.h"
|
||||||
|
#include "fsl_lpsci.h"
|
||||||
|
|
||||||
|
#include "clock_config.h"
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
void USB0_IRQHandler(void)
|
||||||
|
{
|
||||||
|
tud_int_handler(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// LED
|
||||||
|
#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
|
||||||
|
#define LED_PORT GPIOB
|
||||||
|
#define LED_PIN_CLOCK kCLOCK_PortB
|
||||||
|
#define LED_PIN_PORT PORTB
|
||||||
|
#define LED_PIN 19U
|
||||||
|
#define LED_PIN_FUNCTION kPORT_MuxAsGpio
|
||||||
|
#define LED_STATE_ON 0
|
||||||
|
|
||||||
|
// UART
|
||||||
|
#define UART_PORT UART0
|
||||||
|
#define UART_PIN_CLOCK kCLOCK_PortA
|
||||||
|
#define UART_PIN_PORT PORTA
|
||||||
|
#define UART_PIN_RX 1u
|
||||||
|
#define UART_PIN_TX 2u
|
||||||
|
#define UART_PIN_FUNCTION kPORT_MuxAlt2
|
||||||
|
#define SOPT5_UART0RXSRC_UART_RX 0x00u /*!< UART0 receive data source select: UART0_RX pin */
|
||||||
|
#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART0 transmit data source select: UART0_TX pin */
|
||||||
|
|
||||||
|
const uint8_t dcd_data[] = { 0x00 };
|
||||||
|
|
||||||
|
void board_init(void)
|
||||||
|
{
|
||||||
|
BOARD_BootClockRUN();
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
|
// 1ms tick timer
|
||||||
|
SysTick_Config(SystemCoreClock / 1000);
|
||||||
|
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||||
|
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||||
|
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// LED
|
||||||
|
CLOCK_EnableClock(LED_PIN_CLOCK);
|
||||||
|
PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION);
|
||||||
|
gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
|
||||||
|
GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
|
||||||
|
board_led_write(true);
|
||||||
|
|
||||||
|
// UART
|
||||||
|
CLOCK_EnableClock(UART_PIN_CLOCK);
|
||||||
|
PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION);
|
||||||
|
PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, UART_PIN_FUNCTION);
|
||||||
|
SIM->SOPT5 = ((SIM->SOPT5 &
|
||||||
|
(~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK)))
|
||||||
|
| SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)
|
||||||
|
| SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX)
|
||||||
|
);
|
||||||
|
|
||||||
|
lpsci_config_t uart_config;
|
||||||
|
CLOCK_SetLpsci0Clock(1);
|
||||||
|
LPSCI_GetDefaultConfig(&uart_config);
|
||||||
|
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
|
||||||
|
uart_config.enableTx = true;
|
||||||
|
uart_config.enableRx = true;
|
||||||
|
LPSCI_Init(UART_PORT, &uart_config, CLOCK_GetPllFllSelClkFreq());
|
||||||
|
|
||||||
|
// USB
|
||||||
|
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Board porting API
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
void board_led_write(bool state)
|
||||||
|
{
|
||||||
|
GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t board_button_read(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_uart_read(uint8_t* buf, int len)
|
||||||
|
{
|
||||||
|
LPSCI_ReadBlocking(UART_PORT, buf, len);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_uart_write(void const * buf, int len)
|
||||||
|
{
|
||||||
|
LPSCI_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
|
volatile uint32_t system_ticks = 0;
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
system_ticks++;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t board_millis(void)
|
||||||
|
{
|
||||||
|
return system_ticks;
|
||||||
|
}
|
||||||
|
#endif
|
@ -12,23 +12,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -15,23 +15,23 @@ CFLAGS += -Wno-error=undef
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd51g19a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd51g19a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/gcc/gcc/startup_samd51.c \
|
hw/mcu/microchip/asf4/samd51/gcc/gcc/startup_samd51.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/gcc/system_samd51.c \
|
hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/mclk/hpl_mclk.c \
|
hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
|
hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c \
|
hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd51/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd51/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -12,23 +12,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -12,23 +12,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -15,23 +15,23 @@ CFLAGS += -Wno-error=undef
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd51g19a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd51g19a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/gcc/gcc/startup_samd51.c \
|
hw/mcu/microchip/asf4/samd51/gcc/gcc/startup_samd51.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/gcc/system_samd51.c \
|
hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/mclk/hpl_mclk.c \
|
hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
|
hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c \
|
hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd51/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd51/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd51/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd51/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd51/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
58
hw/bsp/same70_xplained/board.mk
Normal file
58
hw/bsp/same70_xplained/board.mk
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
CFLAGS += \
|
||||||
|
-mthumb \
|
||||||
|
-mabi=aapcs \
|
||||||
|
-mcpu=cortex-m7 \
|
||||||
|
-mfloat-abi=hard \
|
||||||
|
-mfpu=fpv4-sp-d16 \
|
||||||
|
-nostdlib -nostartfiles \
|
||||||
|
-D__SAME70Q21B__ \
|
||||||
|
-DCFG_TUSB_MCU=OPT_MCU_NONE
|
||||||
|
|
||||||
|
# suppress following warnings from mcu driver
|
||||||
|
CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
|
||||||
|
|
||||||
|
ASF_DIR = hw/mcu/microchip/same70
|
||||||
|
|
||||||
|
# All source paths should be relative to the top level.
|
||||||
|
LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
|
||||||
|
|
||||||
|
SRC_C += \
|
||||||
|
$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
|
||||||
|
$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
|
||||||
|
$(ASF_DIR)/hpl/core/hpl_init.c \
|
||||||
|
$(ASF_DIR)/hpl/usart/hpl_usart.c \
|
||||||
|
$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
|
||||||
|
$(ASF_DIR)/hal/src/hal_usart_async.c \
|
||||||
|
$(ASF_DIR)/hal/src/hal_io.c \
|
||||||
|
$(ASF_DIR)/hal/src/hal_atomic.c \
|
||||||
|
$(ASF_DIR)/hal/utils/src/utils_ringbuffer.c
|
||||||
|
|
||||||
|
INC += \
|
||||||
|
$(TOP)/hw/bsp/$(BOARD) \
|
||||||
|
$(TOP)/$(ASF_DIR) \
|
||||||
|
$(TOP)/$(ASF_DIR)/config \
|
||||||
|
$(TOP)/$(ASF_DIR)/same70b/include \
|
||||||
|
$(TOP)/$(ASF_DIR)/hal/include \
|
||||||
|
$(TOP)/$(ASF_DIR)/hal/utils/include \
|
||||||
|
$(TOP)/$(ASF_DIR)/hpl/core \
|
||||||
|
$(TOP)/$(ASF_DIR)/hpl/pio \
|
||||||
|
$(TOP)/$(ASF_DIR)/hpl/pmc \
|
||||||
|
$(TOP)/$(ASF_DIR)/hri \
|
||||||
|
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
|
||||||
|
|
||||||
|
# For TinyUSB port source
|
||||||
|
#SRC_C += src/portable/template/dcd_template.c
|
||||||
|
VENDOR = .
|
||||||
|
CHIP_FAMILY = template
|
||||||
|
|
||||||
|
# For freeRTOS port source
|
||||||
|
FREERTOS_PORT = ARM_CM7
|
||||||
|
|
||||||
|
# For flash-jlink target
|
||||||
|
JLINK_DEVICE = SAME70Q21B
|
||||||
|
|
||||||
|
# flash using edbg from https://github.com/ataradov/edbg
|
||||||
|
# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
|
||||||
|
# edbg -t same70 -F w0,1,1
|
||||||
|
flash: $(BUILD)/$(BOARD)-firmware.bin
|
||||||
|
edbg --verbose -t same70 -pv -f $<
|
1053
hw/bsp/same70_xplained/hpl_pmc_config.h
Normal file
1053
hw/bsp/same70_xplained/hpl_pmc_config.h
Normal file
File diff suppressed because it is too large
Load Diff
215
hw/bsp/same70_xplained/hpl_usart_config.h
Normal file
215
hw/bsp/same70_xplained/hpl_usart_config.h
Normal file
@ -0,0 +1,215 @@
|
|||||||
|
/* Auto-generated config file hpl_usart_config.h */
|
||||||
|
#ifndef HPL_USART_CONFIG_H
|
||||||
|
#define HPL_USART_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
#include <peripheral_clk_config.h>
|
||||||
|
|
||||||
|
#ifndef CONF_USART_1_ENABLE
|
||||||
|
#define CONF_USART_1_ENABLE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <h> Basic Configuration
|
||||||
|
|
||||||
|
// <o> Frame parity
|
||||||
|
// <0x0=>Even parity
|
||||||
|
// <0x1=>Odd parity
|
||||||
|
// <0x2=>Parity forced to 0
|
||||||
|
// <0x3=>Parity forced to 1
|
||||||
|
// <0x4=>No parity
|
||||||
|
// <i> Parity bit mode for USART frame
|
||||||
|
// <id> usart_parity
|
||||||
|
#ifndef CONF_USART_1_PARITY
|
||||||
|
#define CONF_USART_1_PARITY 0x4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Character Size
|
||||||
|
// <0x0=>5 bits
|
||||||
|
// <0x1=>6 bits
|
||||||
|
// <0x2=>7 bits
|
||||||
|
// <0x3=>8 bits
|
||||||
|
// <i> Data character size in USART frame
|
||||||
|
// <id> usart_character_size
|
||||||
|
#ifndef CONF_USART_1_CHSIZE
|
||||||
|
#define CONF_USART_1_CHSIZE 0x3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Stop Bit
|
||||||
|
// <0=>1 stop bit
|
||||||
|
// <1=>1.5 stop bits
|
||||||
|
// <2=>2 stop bits
|
||||||
|
// <i> Number of stop bits in USART frame
|
||||||
|
// <id> usart_stop_bit
|
||||||
|
#ifndef CONF_USART_1_SBMODE
|
||||||
|
#define CONF_USART_1_SBMODE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Clock Output Select
|
||||||
|
// <0=>The USART does not drive the SCK pin
|
||||||
|
// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
|
||||||
|
// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
|
||||||
|
// <id> usart_clock_output_select
|
||||||
|
#ifndef CONF_USART_1_CLKO
|
||||||
|
#define CONF_USART_1_CLKO 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Baud rate <1-3000000>
|
||||||
|
// <i> USART baud rate setting
|
||||||
|
// <id> usart_baud_rate
|
||||||
|
#ifndef CONF_USART_1_BAUD
|
||||||
|
#define CONF_USART_1_BAUD 9600
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
// <e> Advanced configuration
|
||||||
|
// <id> usart_advanced
|
||||||
|
#ifndef CONF_USART_1_ADVANCED_CONFIG
|
||||||
|
#define CONF_USART_1_ADVANCED_CONFIG 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Channel Mode
|
||||||
|
// <0=>Normal Mode
|
||||||
|
// <1=>Automatic Echo
|
||||||
|
// <2=>Local Loopback
|
||||||
|
// <3=>Remote Loopback
|
||||||
|
// <i> Channel mode in USART frame
|
||||||
|
// <id> usart_channel_mode
|
||||||
|
#ifndef CONF_USART_1_CHMODE
|
||||||
|
#define CONF_USART_1_CHMODE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> 9 bits character enable
|
||||||
|
// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
|
||||||
|
// <id> usart_9bits_enable
|
||||||
|
#ifndef CONF_USART_1_MODE9
|
||||||
|
#define CONF_USART_1_MODE9 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Variable Sync
|
||||||
|
// <0=>User defined configuration
|
||||||
|
// <1=>sync field is updated when a character is written into US_THR
|
||||||
|
// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
|
||||||
|
// <id> variable_sync
|
||||||
|
#ifndef CONF_USART_1_VAR_SYNC
|
||||||
|
#define CONF_USART_1_VAR_SYNC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Oversampling Mode
|
||||||
|
// <0=>16 Oversampling
|
||||||
|
// <1=>8 Oversampling
|
||||||
|
// <i> Oversampling Mode in UART mode
|
||||||
|
// <id> usart__oversampling_mode
|
||||||
|
#ifndef CONF_USART_1_OVER
|
||||||
|
#define CONF_USART_1_OVER 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Inhibit Non Ack
|
||||||
|
// <0=>The NACK is generated
|
||||||
|
// <1=>The NACK is not generated
|
||||||
|
// <i> Inhibit Non Acknowledge
|
||||||
|
// <id> usart__inack
|
||||||
|
#ifndef CONF_USART_1_INACK
|
||||||
|
#define CONF_USART_1_INACK 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Disable Successive NACK
|
||||||
|
// <0=>NACK is sent on the ISO line as soon as a parity error occurs
|
||||||
|
// <1=>Many parity errors generate a NACK on the ISO line
|
||||||
|
// <i> Disable Successive NACK
|
||||||
|
// <id> usart_dsnack
|
||||||
|
#ifndef CONF_USART_1_DSNACK
|
||||||
|
#define CONF_USART_1_DSNACK 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Inverted Data
|
||||||
|
// <0=>Data isn't inverted, nomal mode
|
||||||
|
// <1=>Data is inverted
|
||||||
|
// <i> Inverted Data
|
||||||
|
// <id> usart_invdata
|
||||||
|
#ifndef CONF_USART_1_INVDATA
|
||||||
|
#define CONF_USART_1_INVDATA 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Maximum Number of Automatic Iteration <0-7>
|
||||||
|
// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
|
||||||
|
// <id> usart_max_iteration
|
||||||
|
#ifndef CONF_USART_1_MAX_ITERATION
|
||||||
|
#define CONF_USART_1_MAX_ITERATION 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Receive Line Filter enable
|
||||||
|
// <i> whether the USART filters the receive line using a three-sample filter
|
||||||
|
// <id> usart_receive_filter_enable
|
||||||
|
#ifndef CONF_USART_1_FILTER
|
||||||
|
#define CONF_USART_1_FILTER 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <q> Manchester Encoder/Decoder Enable
|
||||||
|
// <i> whether the USART Manchester Encoder/Decoder
|
||||||
|
// <id> usart_manchester_filter_enable
|
||||||
|
#ifndef CONF_USART_1_MAN
|
||||||
|
#define CONF_USART_1_MAN 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Manchester Synchronization Mode
|
||||||
|
// <0=>The Manchester start bit is a 0 to 1 transition
|
||||||
|
// <1=>The Manchester start bit is a 1 to 0 transition
|
||||||
|
// <i> Manchester Synchronization Mode
|
||||||
|
// <id> usart_manchester_synchronization_mode
|
||||||
|
#ifndef CONF_USART_1_MODSYNC
|
||||||
|
#define CONF_USART_1_MODSYNC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Start Frame Delimiter Selector
|
||||||
|
// <0=>Start frame delimiter is COMMAND or DATA SYNC
|
||||||
|
// <1=>Start frame delimiter is one bit
|
||||||
|
// <i> Start Frame Delimiter Selector
|
||||||
|
// <id> usart_start_frame_delimiter
|
||||||
|
#ifndef CONF_USART_1_ONEBIT
|
||||||
|
#define CONF_USART_1_ONEBIT 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Fractional Part <0-7>
|
||||||
|
// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
|
||||||
|
// <id> usart_arch_fractional
|
||||||
|
#ifndef CONF_USART_1_FRACTIONAL
|
||||||
|
#define CONF_USART_1_FRACTIONAL 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> Data Order
|
||||||
|
// <0=>LSB is transmitted first
|
||||||
|
// <1=>MSB is transmitted first
|
||||||
|
// <i> Data order of the data bits in the frame
|
||||||
|
// <id> usart_arch_msbf
|
||||||
|
#ifndef CONF_USART_1_MSBF
|
||||||
|
#define CONF_USART_1_MSBF 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
#define CONF_USART_1_MODE 0x0
|
||||||
|
|
||||||
|
// Calculate BAUD register value in UART mode
|
||||||
|
#if CONF_USART1_CK_SRC < 3
|
||||||
|
#ifndef CONF_USART_1_BAUD_CD
|
||||||
|
#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
|
||||||
|
#endif
|
||||||
|
#ifndef CONF_USART_1_BAUD_FP
|
||||||
|
#define CONF_USART_1_BAUD_FP \
|
||||||
|
((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
|
||||||
|
#endif
|
||||||
|
#elif CONF_USART1_CK_SRC == 3
|
||||||
|
// No division is active. The value written in US_BRGR has no effect.
|
||||||
|
#ifndef CONF_USART_1_BAUD_CD
|
||||||
|
#define CONF_USART_1_BAUD_CD 1
|
||||||
|
#endif
|
||||||
|
#ifndef CONF_USART_1_BAUD_FP
|
||||||
|
#define CONF_USART_1_BAUD_FP 1
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // HPL_USART_CONFIG_H
|
4400
hw/bsp/same70_xplained/hpl_xdmac_config.h
Normal file
4400
hw/bsp/same70_xplained/hpl_xdmac_config.h
Normal file
File diff suppressed because it is too large
Load Diff
126
hw/bsp/same70_xplained/peripheral_clk_config.h
Normal file
126
hw/bsp/same70_xplained/peripheral_clk_config.h
Normal file
@ -0,0 +1,126 @@
|
|||||||
|
/* Auto-generated config file peripheral_clk_config.h */
|
||||||
|
#ifndef PERIPHERAL_CLK_CONFIG_H
|
||||||
|
#define PERIPHERAL_CLK_CONFIG_H
|
||||||
|
|
||||||
|
// <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_HCLK_FREQUENCY
|
||||||
|
* \brief HCLK's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_HCLK_FREQUENCY
|
||||||
|
#define CONF_HCLK_FREQUENCY 300000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_FCLK_FREQUENCY
|
||||||
|
* \brief FCLK's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_FCLK_FREQUENCY
|
||||||
|
#define CONF_FCLK_FREQUENCY 300000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_CPU_FREQUENCY
|
||||||
|
* \brief CPU's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_CPU_FREQUENCY
|
||||||
|
#define CONF_CPU_FREQUENCY 300000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_SLCK_FREQUENCY
|
||||||
|
* \brief Slow Clock frequency
|
||||||
|
*/
|
||||||
|
#define CONF_SLCK_FREQUENCY 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_MCK_FREQUENCY
|
||||||
|
* \brief Master Clock frequency
|
||||||
|
*/
|
||||||
|
#define CONF_MCK_FREQUENCY 150000000
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_PCK6_FREQUENCY
|
||||||
|
* \brief Programmable Clock Controller 6 frequency
|
||||||
|
*/
|
||||||
|
#define CONF_PCK6_FREQUENCY 1714285
|
||||||
|
|
||||||
|
// <h> USART Clock Settings
|
||||||
|
// <o> USART Clock source
|
||||||
|
|
||||||
|
// <0=> Master Clock (MCK)
|
||||||
|
// <1=> MCK / 8 for USART
|
||||||
|
// <2=> Programmable Clock Controller 4 (PMC_PCK4)
|
||||||
|
// <3=> External Clock
|
||||||
|
// <i> This defines the clock source for the USART
|
||||||
|
// <id> usart_clock_source
|
||||||
|
#ifndef CONF_USART1_CK_SRC
|
||||||
|
#define CONF_USART1_CK_SRC 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <o> USART External Clock Input on SCK <1-4294967295>
|
||||||
|
// <i> Inputs the external clock frequency on SCK
|
||||||
|
// <id> usart_clock_freq
|
||||||
|
#ifndef CONF_USART1_SCK_FREQ
|
||||||
|
#define CONF_USART1_SCK_FREQ 10000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// </h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def USART FREQUENCY
|
||||||
|
* \brief USART's Clock frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_USART1_FREQUENCY
|
||||||
|
#define CONF_USART1_FREQUENCY 150000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONF_SRC_USB_480M
|
||||||
|
#define CONF_SRC_USB_480M 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONF_SRC_USB_48M
|
||||||
|
#define CONF_SRC_USB_48M 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> USB Full/Low Speed Clock
|
||||||
|
// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
|
||||||
|
// <id> usb_fsls_clock_source
|
||||||
|
// <i> 48MHz clock source for low speed and full speed.
|
||||||
|
// <i> It must be available when low speed is supported by host driver.
|
||||||
|
// <i> It must be available when low power mode is selected.
|
||||||
|
#ifndef CONF_USBHS_FSLS_SRC
|
||||||
|
#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <y> USB Clock Source(Normal/Low-power Mode Selection)
|
||||||
|
// <CONF_SRC_USB_480M"> USB High Speed Clock (USB_480M)
|
||||||
|
// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
|
||||||
|
// <id> usb_clock_source
|
||||||
|
// <i> Select the clock source for USB.
|
||||||
|
// <i> In normal mode, use "USB High Speed Clock (USB_480M)".
|
||||||
|
// <i> In low-power mode, use "USB Clock Controller (USB_48M)".
|
||||||
|
#ifndef CONF_USBHS_SRC
|
||||||
|
#define CONF_USBHS_SRC CONF_SRC_USB_480M
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_USBHS_FSLS_FREQUENCY
|
||||||
|
* \brief USBHS's Full/Low Speed Clock Source frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_USBHS_FSLS_FREQUENCY
|
||||||
|
#define CONF_USBHS_FSLS_FREQUENCY 48000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \def CONF_USBHS_FREQUENCY
|
||||||
|
* \brief USBHS's Selected Clock Source frequency
|
||||||
|
*/
|
||||||
|
#ifndef CONF_USBHS_FREQUENCY
|
||||||
|
#define CONF_USBHS_FREQUENCY 480000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// <<< end of configuration section >>>
|
||||||
|
|
||||||
|
#endif // PERIPHERAL_CLK_CONFIG_H
|
167
hw/bsp/same70_xplained/same70_xplained.c
Normal file
167
hw/bsp/same70_xplained/same70_xplained.c
Normal file
@ -0,0 +1,167 @@
|
|||||||
|
/*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2019, hathach (tinyusb.org)
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sam.h"
|
||||||
|
#include "bsp/board.h"
|
||||||
|
|
||||||
|
#include "peripheral_clk_config.h"
|
||||||
|
#include "hpl/usart/hpl_usart_base.h"
|
||||||
|
#include "hpl/pmc/hpl_pmc.h"
|
||||||
|
#include "hal/include/hal_init.h"
|
||||||
|
#include "hal/include/hal_usart_async.h"
|
||||||
|
#include "hal/include/hal_gpio.h"
|
||||||
|
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
#define LED_PIN GPIO(GPIO_PORTC, 8)
|
||||||
|
|
||||||
|
#define BUTTON_PIN GPIO(GPIO_PORTA, 11)
|
||||||
|
#define BUTTON_STATE_ACTIVE 0
|
||||||
|
|
||||||
|
#define UART_TX_PIN GPIO(GPIO_PORTB, 4)
|
||||||
|
#define UART_RX_PIN GPIO(GPIO_PORTA, 21)
|
||||||
|
|
||||||
|
static struct usart_async_descriptor edbg_com;
|
||||||
|
static uint8_t edbg_com_buffer[64];
|
||||||
|
static volatile bool uart_busy = false;
|
||||||
|
|
||||||
|
static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
|
||||||
|
{
|
||||||
|
uart_busy = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
//------------- IMPLEMENTATION -------------//
|
||||||
|
void board_init(void)
|
||||||
|
{
|
||||||
|
init_mcu();
|
||||||
|
|
||||||
|
/* Disable Watchdog */
|
||||||
|
hri_wdt_set_MR_WDDIS_bit(WDT);
|
||||||
|
|
||||||
|
// LED
|
||||||
|
_pmc_enable_periph_clock(ID_PIOC);
|
||||||
|
gpio_set_pin_level(LED_PIN, false);
|
||||||
|
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
|
||||||
|
gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
|
||||||
|
|
||||||
|
// Button
|
||||||
|
_pmc_enable_periph_clock(ID_PIOA);
|
||||||
|
gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
|
||||||
|
gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
|
||||||
|
gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
|
||||||
|
|
||||||
|
// Uart via EDBG Com
|
||||||
|
_pmc_enable_periph_clock(ID_USART1);
|
||||||
|
gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
|
||||||
|
gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
|
||||||
|
|
||||||
|
usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
|
||||||
|
usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
|
||||||
|
usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
|
||||||
|
// usart_async_register_callback(&EDBG_COM, USART_ASYNC_RXC_CB, rx_cb_EDBG_COM);
|
||||||
|
usart_async_enable(&edbg_com);
|
||||||
|
|
||||||
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
|
// 1ms tick timer (samd SystemCoreClock may not correct)
|
||||||
|
SysTick_Config(CONF_CPU_FREQUENCY / 1000);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
// USB Pin, Clock init
|
||||||
|
|
||||||
|
/* Clear SYSIO 10 & 11 for USB DM & DP */
|
||||||
|
hri_matrix_clear_CCFG_SYSIO_reg(MATRIX, CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);
|
||||||
|
|
||||||
|
// Enable clock
|
||||||
|
_pmc_enable_periph_clock(ID_UDP);
|
||||||
|
|
||||||
|
/* USB Device mode & Transceiver active */
|
||||||
|
hri_matrix_write_CCFG_USBMR_reg(MATRIX, CCFG_USBMR_USBMODE);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// USB Interrupt Handler
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
void UDP_Handler(void)
|
||||||
|
{
|
||||||
|
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||||
|
tud_int_handler(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Board porting API
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
void board_led_write(bool state)
|
||||||
|
{
|
||||||
|
gpio_set_pin_level(LED_PIN, state);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t board_button_read(void)
|
||||||
|
{
|
||||||
|
return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_uart_read(uint8_t* buf, int len)
|
||||||
|
{
|
||||||
|
(void) buf; (void) len;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_uart_write(void const * buf, int len)
|
||||||
|
{
|
||||||
|
// while until previous transfer is complete
|
||||||
|
while(uart_busy) {}
|
||||||
|
uart_busy = true;
|
||||||
|
|
||||||
|
io_write(&edbg_com.io, buf, len);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
|
volatile uint32_t system_ticks = 0;
|
||||||
|
|
||||||
|
void SysTick_Handler (void)
|
||||||
|
{
|
||||||
|
system_ticks++;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t board_millis(void)
|
||||||
|
{
|
||||||
|
return system_ticks;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Required by __libc_init_array in startup code if we are compiling using
|
||||||
|
// -nostdlib/-nostartfiles.
|
||||||
|
void _init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
@ -45,7 +45,7 @@
|
|||||||
#define UART_TX_PIN GPIO(GPIO_PORTA, 28)
|
#define UART_TX_PIN GPIO(GPIO_PORTA, 28)
|
||||||
#define UART_RX_PIN GPIO(GPIO_PORTA, 27)
|
#define UART_RX_PIN GPIO(GPIO_PORTA, 27)
|
||||||
|
|
||||||
struct _usart_sync_device _edbg_com;
|
struct _usart_sync_device edbg_com;
|
||||||
|
|
||||||
//------------- IMPLEMENTATION -------------//
|
//------------- IMPLEMENTATION -------------//
|
||||||
void board_init(void)
|
void board_init(void)
|
||||||
@ -72,10 +72,10 @@ void board_init(void)
|
|||||||
gpio_set_pin_function(UART_RX_PIN, MUX_PA27B_FLEXCOM7_RXD);
|
gpio_set_pin_function(UART_RX_PIN, MUX_PA27B_FLEXCOM7_RXD);
|
||||||
gpio_set_pin_function(UART_TX_PIN, MUX_PA28B_FLEXCOM7_TXD);
|
gpio_set_pin_function(UART_TX_PIN, MUX_PA28B_FLEXCOM7_TXD);
|
||||||
|
|
||||||
_usart_sync_init(&_edbg_com, FLEXCOM7);
|
_usart_sync_init(&edbg_com, FLEXCOM7);
|
||||||
_usart_sync_set_baud_rate(&_edbg_com, CFG_BOARD_UART_BAUDRATE);
|
_usart_sync_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
|
||||||
_usart_sync_set_mode(&_edbg_com, USART_MODE_ASYNCHRONOUS);
|
_usart_sync_set_mode(&edbg_com, USART_MODE_ASYNCHRONOUS);
|
||||||
_usart_sync_enable(&_edbg_com);
|
_usart_sync_enable(&edbg_com);
|
||||||
|
|
||||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
// 1ms tick timer (samd SystemCoreClock may not correct)
|
// 1ms tick timer (samd SystemCoreClock may not correct)
|
||||||
@ -129,8 +129,8 @@ int board_uart_write(void const * buf, int len)
|
|||||||
uint8_t const * buf8 = (uint8_t const *) buf;
|
uint8_t const * buf8 = (uint8_t const *) buf;
|
||||||
for(int i=0; i<len; i++)
|
for(int i=0; i<len; i++)
|
||||||
{
|
{
|
||||||
while ( !_usart_sync_is_ready_to_send(&_edbg_com) ) {}
|
while ( !_usart_sync_is_ready_to_send(&edbg_com) ) {}
|
||||||
_usart_sync_write_byte(&_edbg_com, buf8[i]);
|
_usart_sync_write_byte(&edbg_com, buf8[i]);
|
||||||
}
|
}
|
||||||
return len;
|
return len;
|
||||||
}
|
}
|
||||||
|
@ -12,23 +12,23 @@ CFLAGS += \
|
|||||||
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
LD_FILE = hw/bsp/$(BOARD)/samd21g18a_flash.ld
|
||||||
|
|
||||||
SRC_C += \
|
SRC_C += \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/gcc/startup_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
|
hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
|
hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
|
||||||
hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
|
hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c
|
||||||
|
|
||||||
INC += \
|
INC += \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/config \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hal/utils/include \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/pm/ \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/pm/ \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hpl/port \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
|
$(TOP)/hw/mcu/microchip/asf4/samd21/hri \
|
||||||
$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
|
$(TOP)/hw/mcu/microchip/asf4/samd21/CMSIS/Include
|
||||||
|
|
||||||
# For TinyUSB port source
|
# For TinyUSB port source
|
||||||
VENDOR = microchip
|
VENDOR = microchip
|
||||||
|
@ -1 +1 @@
|
|||||||
Subproject commit 434e384e8f1c6a05377f82e1f0796467a2267ad5
|
Subproject commit 6fd71727de19733a96766fb93990d7d3ab24ce8a
|
@ -1 +1 @@
|
|||||||
Subproject commit b618cb1d521cc9e133bdcd0fca154dee2d925dfe
|
Subproject commit 587c65766538a5e1cfb6188ac611ded61f2eb859
|
@ -989,7 +989,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
|
|||||||
|
|
||||||
// Invoked when class request DATA stage is finished.
|
// Invoked when class request DATA stage is finished.
|
||||||
// return false to stall control EP (e.g Host send non-sense DATA)
|
// return false to stall control EP (e.g Host send non-sense DATA)
|
||||||
bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const * p_request)
|
static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const * p_request)
|
||||||
{
|
{
|
||||||
// Handle audio class specific set requests
|
// Handle audio class specific set requests
|
||||||
if(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.direction == TUSB_DIR_OUT)
|
if(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.direction == TUSB_DIR_OUT)
|
||||||
@ -1065,7 +1065,7 @@ bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const * p_re
|
|||||||
|
|
||||||
// Handle class control request
|
// Handle class control request
|
||||||
// return false to stall control endpoint (e.g unsupported request)
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
bool audiod_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
|
static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
|
||||||
{
|
{
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
|
|
||||||
@ -1175,6 +1175,20 @@ bool audiod_control_request(uint8_t rhport, tusb_control_request_t const * p_req
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
|
{
|
||||||
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
|
{
|
||||||
|
return audiod_control_request(rhport, request);
|
||||||
|
}
|
||||||
|
else if ( stage == CONTROL_STAGE_DATA )
|
||||||
|
{
|
||||||
|
return audiod_control_complete(rhport, request);
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
(void) result;
|
(void) result;
|
||||||
|
@ -384,11 +384,10 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t b
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Internal Class Driver API
|
// Internal Class Driver API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void audiod_init (void);
|
void audiod_init (void);
|
||||||
void audiod_reset (uint8_t rhport);
|
void audiod_reset (uint8_t rhport);
|
||||||
uint16_t audiod_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t audiod_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool audiod_control_request (uint8_t rhport, tusb_control_request_t const * request);
|
bool audiod_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool audiod_control_complete (uint8_t rhport, tusb_control_request_t const * request);
|
|
||||||
bool audiod_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
|
bool audiod_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -186,45 +186,48 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool btd_control_complete(uint8_t rhport, tusb_control_request_t const *request)
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
|
bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request)
|
||||||
{
|
{
|
||||||
(void)rhport;
|
(void)rhport;
|
||||||
|
|
||||||
// Handle class request only
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
{
|
||||||
|
if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS &&
|
||||||
|
request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE)
|
||||||
|
{
|
||||||
|
// HCI command packet addressing for single function Primary Controllers
|
||||||
|
TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0);
|
||||||
|
}
|
||||||
|
else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
|
||||||
|
{
|
||||||
|
if (request->bRequest == TUSB_REQ_SET_INTERFACE && _btd_itf.itf_num + 1 == request->wIndex)
|
||||||
|
{
|
||||||
|
// TODO: Set interface it would involve changing size of endpoint size
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
// HCI command packet for Primary Controller function in a composite device
|
||||||
|
TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == _btd_itf.itf_num);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else return false;
|
||||||
|
|
||||||
if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, request->wLength);
|
return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, request->wLength);
|
||||||
|
}
|
||||||
|
else if ( stage == CONTROL_STAGE_DATA )
|
||||||
|
{
|
||||||
|
// Handle class request only
|
||||||
|
TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
||||||
|
|
||||||
|
if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, request->wLength);
|
||||||
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool btd_control_request(uint8_t rhport, tusb_control_request_t const *request)
|
|
||||||
{
|
|
||||||
(void)rhport;
|
|
||||||
|
|
||||||
if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS &&
|
|
||||||
request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE)
|
|
||||||
{
|
|
||||||
// HCI command packet addressing for single function Primary Controllers
|
|
||||||
TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0);
|
|
||||||
}
|
|
||||||
else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
|
|
||||||
{
|
|
||||||
if (request->bRequest == TUSB_REQ_SET_INTERFACE && _btd_itf.itf_num + 1 == request->wIndex)
|
|
||||||
{
|
|
||||||
// TODO: Set interface it would involve changing size of endpoint size
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
// HCI command packet for Primary Controller function in a composite device
|
|
||||||
TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == _btd_itf.itf_num);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else return false;
|
|
||||||
|
|
||||||
return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, request->wLength);
|
|
||||||
}
|
|
||||||
|
|
||||||
bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
(void)result;
|
(void)result;
|
||||||
@ -246,7 +249,7 @@ bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t
|
|||||||
if (tud_bt_acl_data_sent_cb) tud_bt_acl_data_sent_cb((uint16_t)xferred_bytes);
|
if (tud_bt_acl_data_sent_cb) tud_bt_acl_data_sent_cb((uint16_t)xferred_bytes);
|
||||||
}
|
}
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -96,12 +96,11 @@ bool tud_bt_acl_data_send(void *acl_data, uint16_t data_len);
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Internal Class Driver API
|
// Internal Class Driver API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void btd_init (void);
|
void btd_init (void);
|
||||||
void btd_reset (uint8_t rhport);
|
void btd_reset (uint8_t rhport);
|
||||||
uint16_t btd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t btd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool btd_control_request (uint8_t rhport, tusb_control_request_t const * request);
|
bool btd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const *request);
|
||||||
bool btd_control_complete (uint8_t rhport, tusb_control_request_t const * request);
|
bool btd_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
bool btd_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -178,6 +178,9 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf)
|
|||||||
{
|
{
|
||||||
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
|
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
|
||||||
|
|
||||||
|
// Skip if usb is not ready yet
|
||||||
|
TU_VERIFY( tud_ready(), 0 );
|
||||||
|
|
||||||
// No data to send
|
// No data to send
|
||||||
if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
|
if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
|
||||||
|
|
||||||
@ -189,7 +192,7 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf)
|
|||||||
// Pull data from FIFO
|
// Pull data from FIFO
|
||||||
uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf));
|
uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf));
|
||||||
|
|
||||||
if ( count && tud_cdc_n_connected(itf) )
|
if ( count )
|
||||||
{
|
{
|
||||||
TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
|
TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
|
||||||
return count;
|
return count;
|
||||||
@ -207,6 +210,10 @@ uint32_t tud_cdc_n_write_available (uint8_t itf)
|
|||||||
return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff);
|
return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool tud_cdc_n_write_clear (uint8_t itf)
|
||||||
|
{
|
||||||
|
return tu_fifo_clear(&_cdcd_itf[itf].tx_ff);
|
||||||
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// USBD Driver API
|
// USBD Driver API
|
||||||
@ -227,9 +234,13 @@ void cdcd_init(void)
|
|||||||
p_cdc->line_coding.parity = 0;
|
p_cdc->line_coding.parity = 0;
|
||||||
p_cdc->line_coding.data_bits = 8;
|
p_cdc->line_coding.data_bits = 8;
|
||||||
|
|
||||||
// config fifo
|
// Config RX fifo
|
||||||
tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false);
|
tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false);
|
||||||
tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, false);
|
|
||||||
|
// Config TX fifo as overwritable at initialization and will be changed to non-overwritable
|
||||||
|
// if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal.
|
||||||
|
// In this way, the most current data is prioritized.
|
||||||
|
tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
|
||||||
|
|
||||||
#if CFG_FIFO_MUTEX
|
#if CFG_FIFO_MUTEX
|
||||||
tu_fifo_config_mutex(&p_cdc->rx_ff, osal_mutex_create(&p_cdc->rx_ff_mutex));
|
tu_fifo_config_mutex(&p_cdc->rx_ff, osal_mutex_create(&p_cdc->rx_ff_mutex));
|
||||||
@ -244,9 +255,12 @@ void cdcd_reset(uint8_t rhport)
|
|||||||
|
|
||||||
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
|
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
|
||||||
{
|
{
|
||||||
tu_memclr(&_cdcd_itf[i], ITF_MEM_RESET_SIZE);
|
cdcd_interface_t* p_cdc = &_cdcd_itf[i];
|
||||||
tu_fifo_clear(&_cdcd_itf[i].rx_ff);
|
|
||||||
tu_fifo_clear(&_cdcd_itf[i].tx_ff);
|
tu_memclr(p_cdc, ITF_MEM_RESET_SIZE);
|
||||||
|
tu_fifo_clear(&p_cdc->rx_ff);
|
||||||
|
tu_fifo_clear(&p_cdc->tx_ff);
|
||||||
|
tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -315,38 +329,10 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when class request DATA stage is finished.
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
// return false to stall control endpoint (e.g Host send non-sense DATA)
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
bool cdcd_control_complete(uint8_t rhport, tusb_control_request_t const * request)
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
|
|
||||||
//------------- Class Specific Request -------------//
|
|
||||||
TU_VERIFY (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
|
||||||
|
|
||||||
uint8_t itf = 0;
|
|
||||||
cdcd_interface_t* p_cdc = _cdcd_itf;
|
|
||||||
|
|
||||||
// Identify which interface to use
|
|
||||||
for ( ; ; itf++, p_cdc++)
|
|
||||||
{
|
|
||||||
if (itf >= TU_ARRAY_SIZE(_cdcd_itf)) return false;
|
|
||||||
|
|
||||||
if ( p_cdc->itf_num == request->wIndex ) break;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Invoke callback
|
|
||||||
if ( CDC_REQUEST_SET_LINE_CODING == request->bRequest )
|
|
||||||
{
|
|
||||||
if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
|
|
||||||
}
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Handle class control request
|
|
||||||
// return false to stall control endpoint (e.g unsupported request)
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
bool cdcd_control_request(uint8_t rhport, tusb_control_request_t const * request)
|
bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
// Handle class request only
|
// Handle class request only
|
||||||
TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
||||||
@ -365,34 +351,50 @@ bool cdcd_control_request(uint8_t rhport, tusb_control_request_t const * request
|
|||||||
switch ( request->bRequest )
|
switch ( request->bRequest )
|
||||||
{
|
{
|
||||||
case CDC_REQUEST_SET_LINE_CODING:
|
case CDC_REQUEST_SET_LINE_CODING:
|
||||||
TU_LOG2(" Set Line Coding\r\n");
|
if (stage == CONTROL_STAGE_SETUP)
|
||||||
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
|
{
|
||||||
|
TU_LOG2(" Set Line Coding\r\n");
|
||||||
|
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
|
||||||
|
}
|
||||||
|
else if ( stage == CONTROL_STAGE_ACK)
|
||||||
|
{
|
||||||
|
if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case CDC_REQUEST_GET_LINE_CODING:
|
case CDC_REQUEST_GET_LINE_CODING:
|
||||||
TU_LOG2(" Get Line Coding\r\n");
|
if (stage == CONTROL_STAGE_SETUP)
|
||||||
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
|
{
|
||||||
|
TU_LOG2(" Get Line Coding\r\n");
|
||||||
|
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case CDC_REQUEST_SET_CONTROL_LINE_STATE:
|
case CDC_REQUEST_SET_CONTROL_LINE_STATE:
|
||||||
{
|
if (stage == CONTROL_STAGE_SETUP)
|
||||||
// CDC PSTN v1.2 section 6.3.12
|
{
|
||||||
// Bit 0: Indicates if DTE is present or not.
|
tud_control_status(rhport, request);
|
||||||
// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
|
}
|
||||||
// Bit 1: Carrier control for half-duplex modems.
|
else if (stage == CONTROL_STAGE_ACK)
|
||||||
// This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
|
{
|
||||||
bool const dtr = tu_bit_test(request->wValue, 0);
|
// CDC PSTN v1.2 section 6.3.12
|
||||||
bool const rts = tu_bit_test(request->wValue, 1);
|
// Bit 0: Indicates if DTE is present or not.
|
||||||
|
// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
|
||||||
|
// Bit 1: Carrier control for half-duplex modems.
|
||||||
|
// This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
|
||||||
|
bool const dtr = tu_bit_test(request->wValue, 0);
|
||||||
|
bool const rts = tu_bit_test(request->wValue, 1);
|
||||||
|
|
||||||
p_cdc->line_state = (uint8_t) request->wValue;
|
p_cdc->line_state = (uint8_t) request->wValue;
|
||||||
|
|
||||||
|
// Disable fifo overwriting if DTR bit is set
|
||||||
|
tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
|
||||||
|
|
||||||
TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
|
TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
|
||||||
|
|
||||||
tud_control_status(rhport, request);
|
// Invoke callback
|
||||||
|
if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
|
||||||
// Invoke callback
|
}
|
||||||
if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
|
|
||||||
}
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default: return false; // stall unsupported request
|
default: return false; // stall unsupported request
|
||||||
|
@ -102,6 +102,9 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf);
|
|||||||
// Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation.
|
// Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation.
|
||||||
uint32_t tud_cdc_n_write_available (uint8_t itf);
|
uint32_t tud_cdc_n_write_available (uint8_t itf);
|
||||||
|
|
||||||
|
// Clear the transmit FIFO
|
||||||
|
bool tud_cdc_n_write_clear (uint8_t itf);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Application API (Single Port)
|
// Application API (Single Port)
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -121,6 +124,7 @@ static inline uint32_t tud_cdc_write (void const* buffer, uint32_t buf
|
|||||||
static inline uint32_t tud_cdc_write_str (char const* str);
|
static inline uint32_t tud_cdc_write_str (char const* str);
|
||||||
static inline uint32_t tud_cdc_write_flush (void);
|
static inline uint32_t tud_cdc_write_flush (void);
|
||||||
static inline uint32_t tud_cdc_write_available (void);
|
static inline uint32_t tud_cdc_write_available (void);
|
||||||
|
static inline bool tud_cdc_write_clear (void);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Application Callback API (weak is optional)
|
// Application Callback API (weak is optional)
|
||||||
@ -230,18 +234,22 @@ static inline uint32_t tud_cdc_write_available(void)
|
|||||||
return tud_cdc_n_write_available(0);
|
return tud_cdc_n_write_available(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline bool tud_cdc_write_clear(void)
|
||||||
|
{
|
||||||
|
return tud_cdc_n_write_clear(0);
|
||||||
|
}
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// INTERNAL USBD-CLASS DRIVER API
|
// INTERNAL USBD-CLASS DRIVER API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void cdcd_init (void);
|
void cdcd_init (void);
|
||||||
void cdcd_reset (uint8_t rhport);
|
void cdcd_reset (uint8_t rhport);
|
||||||
uint16_t cdcd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t cdcd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool cdcd_control_request (uint8_t rhport, tusb_control_request_t const * request);
|
bool cdcd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool cdcd_control_complete (uint8_t rhport, tusb_control_request_t const * request);
|
bool cdcd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
bool cdcd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -51,9 +51,14 @@ typedef struct {
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
static cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX];
|
static cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX];
|
||||||
|
|
||||||
|
static inline cdch_data_t* get_itf(uint8_t dev_addr)
|
||||||
|
{
|
||||||
|
return &cdch_data[dev_addr-1];
|
||||||
|
}
|
||||||
|
|
||||||
bool tuh_cdc_mounted(uint8_t dev_addr)
|
bool tuh_cdc_mounted(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
cdch_data_t* cdc = &cdch_data[dev_addr-1];
|
cdch_data_t* cdc = get_itf(dev_addr);
|
||||||
return cdc->ep_in && cdc->ep_out;
|
return cdc->ep_in && cdc->ep_out;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -61,7 +66,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
|
|||||||
{
|
{
|
||||||
if ( !tuh_cdc_mounted(dev_addr) ) return false;
|
if ( !tuh_cdc_mounted(dev_addr) ) return false;
|
||||||
|
|
||||||
cdch_data_t const * p_cdc = &cdch_data[dev_addr-1];
|
cdch_data_t const * p_cdc = get_itf(dev_addr);
|
||||||
|
|
||||||
switch (pipeid)
|
switch (pipeid)
|
||||||
{
|
{
|
||||||
@ -111,6 +116,27 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
|
|||||||
return hcd_pipe_xfer(dev_addr, ep_in, p_buffer, length, is_notify);
|
return hcd_pipe_xfer(dev_addr, ep_in, p_buffer, length, is_notify);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
cdch_data_t const * p_cdc = get_itf(dev_addr);
|
||||||
|
tusb_control_request_t const request =
|
||||||
|
{
|
||||||
|
.bmRequestType_bit =
|
||||||
|
{
|
||||||
|
.recipient = TUSB_REQ_RCPT_INTERFACE,
|
||||||
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
|
.direction = TUSB_DIR_OUT
|
||||||
|
},
|
||||||
|
.bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
|
||||||
|
.wValue = (rts ? 2 : 0) | (dtr ? 1 : 0),
|
||||||
|
.wIndex = p_cdc->itf_num,
|
||||||
|
.wLength = 0
|
||||||
|
};
|
||||||
|
|
||||||
|
TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, complete_cb) );
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// USBH-CLASS DRIVER API
|
// USBH-CLASS DRIVER API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -132,7 +158,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
|
|||||||
cdch_data_t * p_cdc;
|
cdch_data_t * p_cdc;
|
||||||
|
|
||||||
p_desc = tu_desc_next(itf_desc);
|
p_desc = tu_desc_next(itf_desc);
|
||||||
p_cdc = &cdch_data[dev_addr-1];
|
p_cdc = get_itf(dev_addr);
|
||||||
|
|
||||||
p_cdc->itf_num = itf_desc->bInterfaceNumber;
|
p_cdc->itf_num = itf_desc->bInterfaceNumber;
|
||||||
p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com
|
p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com
|
||||||
@ -194,30 +220,25 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// FIXME move to seperate API : connect
|
|
||||||
tusb_control_request_t request =
|
|
||||||
{
|
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
|
|
||||||
.bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
|
|
||||||
.wValue = 0x03, // dtr on, cst on
|
|
||||||
.wIndex = p_cdc->itf_num,
|
|
||||||
.wLength = 0
|
|
||||||
};
|
|
||||||
|
|
||||||
TU_ASSERT( usbh_control_xfer(dev_addr, &request, NULL) );
|
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void cdch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
|
||||||
|
{
|
||||||
|
(void) dev_addr; (void) itf_num;
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
(void) ep_addr;
|
(void) ep_addr;
|
||||||
tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
|
tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void cdch_close(uint8_t dev_addr)
|
void cdch_close(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
cdch_data_t * p_cdc = &cdch_data[dev_addr-1];
|
cdch_data_t * p_cdc = get_itf(dev_addr);
|
||||||
tu_memclr(p_cdc, sizeof(cdch_data_t));
|
tu_memclr(p_cdc, sizeof(cdch_data_t));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -44,6 +44,18 @@
|
|||||||
* \defgroup CDC_Serial_Host Host
|
* \defgroup CDC_Serial_Host Host
|
||||||
* @{ */
|
* @{ */
|
||||||
|
|
||||||
|
bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb);
|
||||||
|
|
||||||
|
static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
|
||||||
|
}
|
||||||
|
|
||||||
/** \brief Check if device support CDC Serial interface or not
|
/** \brief Check if device support CDC Serial interface or not
|
||||||
* \param[in] dev_addr device address
|
* \param[in] dev_addr device address
|
||||||
* \retval true if device supports
|
* \retval true if device supports
|
||||||
@ -113,7 +125,8 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void cdch_init(void);
|
void cdch_init(void);
|
||||||
bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
|
bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
|
||||||
void cdch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num);
|
||||||
|
bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
void cdch_close(uint8_t dev_addr);
|
void cdch_close(uint8_t dev_addr);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -85,17 +85,14 @@ uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, ui
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool dfu_rtd_control_complete(uint8_t rhport, tusb_control_request_t const * request)
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
|
bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
(void) rhport;
|
// nothing to do with DATA and ACK stage
|
||||||
(void) request;
|
if ( stage != CONTROL_STAGE_SETUP ) return true;
|
||||||
|
|
||||||
// nothing to do
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool dfu_rtd_control_request(uint8_t rhport, tusb_control_request_t const * request)
|
|
||||||
{
|
|
||||||
TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
|
TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
|
||||||
|
|
||||||
// dfu-util will try to claim the interface with SET_INTERFACE request before sending DFU request
|
// dfu-util will try to claim the interface with SET_INTERFACE request before sending DFU request
|
||||||
|
@ -66,8 +66,7 @@ TU_ATTR_WEAK void tud_dfu_rt_reboot_to_dfu(void); // TODO rename to _cb conventi
|
|||||||
void dfu_rtd_init(void);
|
void dfu_rtd_init(void);
|
||||||
void dfu_rtd_reset(uint8_t rhport);
|
void dfu_rtd_reset(uint8_t rhport);
|
||||||
uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool dfu_rtd_control_request(uint8_t rhport, tusb_control_request_t const * request);
|
bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool dfu_rtd_control_complete(uint8_t rhport, tusb_control_request_t const * request);
|
|
||||||
bool dfu_rtd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool dfu_rtd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -211,9 +211,10 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Handle class control request
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
// return false to stall control endpoint (e.g unsupported request)
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
bool hidd_control_request(uint8_t rhport, tusb_control_request_t const * request)
|
bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
|
TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
|
||||||
|
|
||||||
@ -225,27 +226,29 @@ bool hidd_control_request(uint8_t rhport, tusb_control_request_t const * request
|
|||||||
if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD)
|
if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD)
|
||||||
{
|
{
|
||||||
//------------- STD Request -------------//
|
//------------- STD Request -------------//
|
||||||
uint8_t const desc_type = tu_u16_high(request->wValue);
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
uint8_t const desc_index = tu_u16_low (request->wValue);
|
{
|
||||||
(void) desc_index;
|
uint8_t const desc_type = tu_u16_high(request->wValue);
|
||||||
|
//uint8_t const desc_index = tu_u16_low (request->wValue);
|
||||||
|
|
||||||
if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID)
|
if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID)
|
||||||
{
|
{
|
||||||
TU_VERIFY(p_hid->hid_descriptor != NULL);
|
TU_VERIFY(p_hid->hid_descriptor != NULL);
|
||||||
TU_VERIFY(tud_control_xfer(rhport, request, (void*) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
|
TU_VERIFY(tud_control_xfer(rhport, request, (void*) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
|
||||||
}
|
}
|
||||||
else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT)
|
else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT)
|
||||||
{
|
{
|
||||||
uint8_t const * desc_report = tud_hid_descriptor_report_cb(
|
uint8_t const * desc_report = tud_hid_descriptor_report_cb(
|
||||||
#if CFG_TUD_HID > 1
|
#if CFG_TUD_HID > 1
|
||||||
hid_itf // TODO for backward compatible callback, remove later when appropriate
|
hid_itf // TODO for backward compatible callback, remove later when appropriate
|
||||||
#endif
|
#endif
|
||||||
);
|
);
|
||||||
tud_control_xfer(rhport, request, (void*) desc_report, p_hid->report_desc_len);
|
tud_control_xfer(rhport, request, (void*) desc_report, p_hid->report_desc_len);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return false; // stall unsupported request
|
return false; // stall unsupported request
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
|
else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
|
||||||
@ -254,70 +257,98 @@ bool hidd_control_request(uint8_t rhport, tusb_control_request_t const * request
|
|||||||
switch( request->bRequest )
|
switch( request->bRequest )
|
||||||
{
|
{
|
||||||
case HID_REQ_CONTROL_GET_REPORT:
|
case HID_REQ_CONTROL_GET_REPORT:
|
||||||
{
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
// wValue = Report Type | Report ID
|
|
||||||
uint8_t const report_type = tu_u16_high(request->wValue);
|
|
||||||
uint8_t const report_id = tu_u16_low(request->wValue);
|
|
||||||
|
|
||||||
uint16_t xferlen = tud_hid_get_report_cb(
|
|
||||||
#if CFG_TUD_HID > 1
|
|
||||||
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
|
||||||
#endif
|
|
||||||
report_id, (hid_report_type_t) report_type, p_hid->epin_buf, request->wLength
|
|
||||||
);
|
|
||||||
TU_ASSERT( xferlen > 0 );
|
|
||||||
|
|
||||||
tud_control_xfer(rhport, request, p_hid->epin_buf, xferlen);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case HID_REQ_CONTROL_SET_REPORT:
|
|
||||||
TU_VERIFY(request->wLength <= sizeof(p_hid->epout_buf));
|
|
||||||
tud_control_xfer(rhport, request, p_hid->epout_buf, request->wLength);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case HID_REQ_CONTROL_SET_IDLE:
|
|
||||||
p_hid->idle_rate = tu_u16_high(request->wValue);
|
|
||||||
if ( tud_hid_set_idle_cb )
|
|
||||||
{
|
{
|
||||||
// stall request if callback return false
|
uint8_t const report_type = tu_u16_high(request->wValue);
|
||||||
TU_VERIFY( tud_hid_set_idle_cb(
|
uint8_t const report_id = tu_u16_low(request->wValue);
|
||||||
#if CFG_TUD_HID > 1
|
|
||||||
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
|
||||||
#endif
|
|
||||||
p_hid->idle_rate)
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
tud_control_status(rhport, request);
|
uint16_t xferlen = tud_hid_get_report_cb(
|
||||||
break;
|
|
||||||
|
|
||||||
case HID_REQ_CONTROL_GET_IDLE:
|
|
||||||
// TODO idle rate of report
|
|
||||||
tud_control_xfer(rhport, request, &p_hid->idle_rate, 1);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case HID_REQ_CONTROL_GET_PROTOCOL:
|
|
||||||
{
|
|
||||||
uint8_t protocol = (uint8_t)(1-p_hid->boot_mode); // 0 is Boot, 1 is Report protocol
|
|
||||||
tud_control_xfer(rhport, request, &protocol, 1);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case HID_REQ_CONTROL_SET_PROTOCOL:
|
|
||||||
p_hid->boot_mode = 1 - request->wValue; // 0 is Boot, 1 is Report protocol
|
|
||||||
|
|
||||||
if (tud_hid_boot_mode_cb)
|
|
||||||
{
|
|
||||||
tud_hid_boot_mode_cb(
|
|
||||||
#if CFG_TUD_HID > 1
|
#if CFG_TUD_HID > 1
|
||||||
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
||||||
#endif
|
#endif
|
||||||
p_hid->boot_mode
|
report_id, (hid_report_type_t) report_type, p_hid->epin_buf, request->wLength
|
||||||
|
);
|
||||||
|
TU_ASSERT( xferlen > 0 );
|
||||||
|
|
||||||
|
tud_control_xfer(rhport, request, p_hid->epin_buf, xferlen);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case HID_REQ_CONTROL_SET_REPORT:
|
||||||
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
|
{
|
||||||
|
TU_VERIFY(request->wLength <= sizeof(p_hid->epout_buf));
|
||||||
|
tud_control_xfer(rhport, request, p_hid->epout_buf, request->wLength);
|
||||||
|
}
|
||||||
|
else if ( stage == CONTROL_STAGE_ACK )
|
||||||
|
{
|
||||||
|
uint8_t const report_type = tu_u16_high(request->wValue);
|
||||||
|
uint8_t const report_id = tu_u16_low(request->wValue);
|
||||||
|
|
||||||
|
tud_hid_set_report_cb(
|
||||||
|
#if CFG_TUD_HID > 1
|
||||||
|
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
||||||
|
#endif
|
||||||
|
report_id, (hid_report_type_t) report_type, p_hid->epout_buf, request->wLength
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
tud_control_status(rhport, request);
|
case HID_REQ_CONTROL_SET_IDLE:
|
||||||
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
|
{
|
||||||
|
p_hid->idle_rate = tu_u16_high(request->wValue);
|
||||||
|
if ( tud_hid_set_idle_cb )
|
||||||
|
{
|
||||||
|
// stall request if callback return false
|
||||||
|
TU_VERIFY( tud_hid_set_idle_cb(
|
||||||
|
#if CFG_TUD_HID > 1
|
||||||
|
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
||||||
|
#endif
|
||||||
|
p_hid->idle_rate)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
tud_control_status(rhport, request);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case HID_REQ_CONTROL_GET_IDLE:
|
||||||
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
|
{
|
||||||
|
// TODO idle rate of report
|
||||||
|
tud_control_xfer(rhport, request, &p_hid->idle_rate, 1);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case HID_REQ_CONTROL_GET_PROTOCOL:
|
||||||
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
|
{
|
||||||
|
// 0 is Boot, 1 is Report protocol
|
||||||
|
uint8_t protocol = (uint8_t)(1-p_hid->boot_mode);
|
||||||
|
tud_control_xfer(rhport, request, &protocol, 1);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case HID_REQ_CONTROL_SET_PROTOCOL:
|
||||||
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
|
{
|
||||||
|
// 0 is Boot, 1 is Report protocol
|
||||||
|
p_hid->boot_mode = 1 - request->wValue;
|
||||||
|
tud_control_status(rhport, request);
|
||||||
|
}
|
||||||
|
else if ( stage == CONTROL_STAGE_ACK )
|
||||||
|
{
|
||||||
|
if (tud_hid_boot_mode_cb)
|
||||||
|
{
|
||||||
|
tud_hid_boot_mode_cb(
|
||||||
|
#if CFG_TUD_HID > 1
|
||||||
|
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
||||||
|
#endif
|
||||||
|
p_hid->boot_mode
|
||||||
|
);
|
||||||
|
}
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default: return false; // stall unsupported request
|
default: return false; // stall unsupported request
|
||||||
@ -330,35 +361,6 @@ bool hidd_control_request(uint8_t rhport, tusb_control_request_t const * request
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when class request DATA stage is finished.
|
|
||||||
// return false to stall control endpoint (e.g Host send non-sense DATA)
|
|
||||||
bool hidd_control_complete(uint8_t rhport, tusb_control_request_t const * p_request)
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
|
|
||||||
uint8_t const hid_itf = get_index_by_itfnum((uint8_t) p_request->wIndex);
|
|
||||||
TU_VERIFY(hid_itf < CFG_TUD_HID);
|
|
||||||
|
|
||||||
hidd_interface_t* p_hid = &_hidd_itf[hid_itf];
|
|
||||||
|
|
||||||
if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS &&
|
|
||||||
p_request->bRequest == HID_REQ_CONTROL_SET_REPORT)
|
|
||||||
{
|
|
||||||
// wValue = Report Type | Report ID
|
|
||||||
uint8_t const report_type = tu_u16_high(p_request->wValue);
|
|
||||||
uint8_t const report_id = tu_u16_low(p_request->wValue);
|
|
||||||
|
|
||||||
tud_hid_set_report_cb(
|
|
||||||
#if CFG_TUD_HID > 1
|
|
||||||
hid_itf, // TODO for backward compatible callback, remove later when appropriate
|
|
||||||
#endif
|
|
||||||
report_id, (hid_report_type_t) report_type, p_hid->epout_buf, p_request->wLength
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
(void) result;
|
(void) result;
|
||||||
|
@ -359,12 +359,11 @@ static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Internal Class Driver API
|
// Internal Class Driver API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void hidd_init (void);
|
void hidd_init (void);
|
||||||
void hidd_reset (uint8_t rhport);
|
void hidd_reset (uint8_t rhport);
|
||||||
uint16_t hidd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t hidd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool hidd_control_request (uint8_t rhport, tusb_control_request_t const * request);
|
bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool hidd_control_complete (uint8_t rhport, tusb_control_request_t const * request);
|
bool hidd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
bool hidd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -71,7 +71,7 @@ tusb_error_t hidh_interface_get_report(uint8_t dev_addr, void * report, hidh_int
|
|||||||
TU_VERIFY(report, TUSB_ERROR_INVALID_PARA);
|
TU_VERIFY(report, TUSB_ERROR_INVALID_PARA);
|
||||||
TU_ASSERT(!hcd_edpt_busy(dev_addr, p_hid->ep_in), TUSB_ERROR_INTERFACE_IS_BUSY);
|
TU_ASSERT(!hcd_edpt_busy(dev_addr, p_hid->ep_in), TUSB_ERROR_INTERFACE_IS_BUSY);
|
||||||
|
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, p_hid->ep_in, report, p_hid->report_size, true) ) ;
|
TU_ASSERT( usbh_edpt_xfer(dev_addr, p_hid->ep_in, report, p_hid->report_size) ) ;
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
return TUSB_ERROR_NONE;
|
||||||
}
|
}
|
||||||
@ -173,30 +173,6 @@ bool hidh_open_subtask(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t c
|
|||||||
tusb_desc_endpoint_t const * p_endpoint_desc = (tusb_desc_endpoint_t const *) p_desc;
|
tusb_desc_endpoint_t const * p_endpoint_desc = (tusb_desc_endpoint_t const *) p_desc;
|
||||||
TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint_desc->bDescriptorType, TUSB_ERROR_INVALID_PARA);
|
TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint_desc->bDescriptorType, TUSB_ERROR_INVALID_PARA);
|
||||||
|
|
||||||
//------------- SET IDLE (0) request -------------//
|
|
||||||
tusb_control_request_t request = {
|
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
|
|
||||||
.bRequest = HID_REQ_CONTROL_SET_IDLE,
|
|
||||||
.wValue = 0, // idle_rate = 0
|
|
||||||
.wIndex = p_interface_desc->bInterfaceNumber,
|
|
||||||
.wLength = 0
|
|
||||||
};
|
|
||||||
TU_ASSERT( usbh_control_xfer( dev_addr, &request, NULL ) );
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
//------------- Get Report Descriptor TODO HID parser -------------//
|
|
||||||
if ( p_desc_hid->bNumDescriptors )
|
|
||||||
{
|
|
||||||
STASK_INVOKE(
|
|
||||||
usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_INTERFACE),
|
|
||||||
TUSB_REQ_GET_DESCRIPTOR, (p_desc_hid->bReportType << 8), 0,
|
|
||||||
p_desc_hid->wReportLength, report_descriptor ),
|
|
||||||
error
|
|
||||||
);
|
|
||||||
(void) error; // if error in getting report descriptor --> treating like there is none
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if ( HID_SUBCLASS_BOOT == p_interface_desc->bInterfaceSubClass )
|
if ( HID_SUBCLASS_BOOT == p_interface_desc->bInterfaceSubClass )
|
||||||
{
|
{
|
||||||
#if CFG_TUH_HID_KEYBOARD
|
#if CFG_TUH_HID_KEYBOARD
|
||||||
@ -204,7 +180,6 @@ bool hidh_open_subtask(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t c
|
|||||||
{
|
{
|
||||||
TU_ASSERT( hidh_interface_open(rhport, dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &keyboardh_data[dev_addr-1]) );
|
TU_ASSERT( hidh_interface_open(rhport, dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &keyboardh_data[dev_addr-1]) );
|
||||||
TU_LOG2_HEX(keyboardh_data[dev_addr-1].ep_in);
|
TU_LOG2_HEX(keyboardh_data[dev_addr-1].ep_in);
|
||||||
tuh_hid_keyboard_mounted_cb(dev_addr);
|
|
||||||
} else
|
} else
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -213,7 +188,6 @@ bool hidh_open_subtask(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t c
|
|||||||
{
|
{
|
||||||
TU_ASSERT ( hidh_interface_open(rhport, dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &mouseh_data[dev_addr-1]) );
|
TU_ASSERT ( hidh_interface_open(rhport, dev_addr, p_interface_desc->bInterfaceNumber, p_endpoint_desc, &mouseh_data[dev_addr-1]) );
|
||||||
TU_LOG2_HEX(mouseh_data[dev_addr-1].ep_in);
|
TU_LOG2_HEX(mouseh_data[dev_addr-1].ep_in);
|
||||||
tuh_hid_mouse_mounted_cb(dev_addr);
|
|
||||||
} else
|
} else
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -232,7 +206,63 @@ bool hidh_open_subtask(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t c
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void hidh_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
|
||||||
|
{
|
||||||
|
#if 0
|
||||||
|
//------------- Get Report Descriptor TODO HID parser -------------//
|
||||||
|
if ( p_desc_hid->bNumDescriptors )
|
||||||
|
{
|
||||||
|
STASK_INVOKE(
|
||||||
|
usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_INTERFACE),
|
||||||
|
TUSB_REQ_GET_DESCRIPTOR, (p_desc_hid->bReportType << 8), 0,
|
||||||
|
p_desc_hid->wReportLength, report_descriptor ),
|
||||||
|
error
|
||||||
|
);
|
||||||
|
(void) error; // if error in getting report descriptor --> treating like there is none
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
// SET IDLE = 0 request
|
||||||
|
// Device can stall if not support this request
|
||||||
|
tusb_control_request_t const request =
|
||||||
|
{
|
||||||
|
.bmRequestType_bit =
|
||||||
|
{
|
||||||
|
.recipient = TUSB_REQ_RCPT_INTERFACE,
|
||||||
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
|
.direction = TUSB_DIR_OUT
|
||||||
|
},
|
||||||
|
.bRequest = HID_REQ_CONTROL_SET_IDLE,
|
||||||
|
.wValue = 0, // idle_rate = 0
|
||||||
|
.wIndex = p_interface_desc->bInterfaceNumber,
|
||||||
|
.wLength = 0
|
||||||
|
};
|
||||||
|
|
||||||
|
// stall is a valid response for SET_IDLE, therefore we could ignore result of this request
|
||||||
|
tuh_control_xfer(dev_addr, &request, NULL, NULL);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
usbh_driver_set_config_complete(dev_addr, itf_num);
|
||||||
|
|
||||||
|
#if CFG_TUH_HID_KEYBOARD
|
||||||
|
if ( keyboardh_data[dev_addr-1].itf_num == itf_num)
|
||||||
|
{
|
||||||
|
tuh_hid_keyboard_mounted_cb(dev_addr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CFG_TUH_HID_MOUSE
|
||||||
|
if ( mouseh_data[dev_addr-1].ep_in == itf_num )
|
||||||
|
{
|
||||||
|
tuh_hid_mouse_mounted_cb(dev_addr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
(void) xferred_bytes; // TODO may need to use this para later
|
(void) xferred_bytes; // TODO may need to use this para later
|
||||||
|
|
||||||
@ -240,7 +270,7 @@ void hidh_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t x
|
|||||||
if ( ep_addr == keyboardh_data[dev_addr-1].ep_in )
|
if ( ep_addr == keyboardh_data[dev_addr-1].ep_in )
|
||||||
{
|
{
|
||||||
tuh_hid_keyboard_isr(dev_addr, event);
|
tuh_hid_keyboard_isr(dev_addr, event);
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -248,13 +278,15 @@ void hidh_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t x
|
|||||||
if ( ep_addr == mouseh_data[dev_addr-1].ep_in )
|
if ( ep_addr == mouseh_data[dev_addr-1].ep_in )
|
||||||
{
|
{
|
||||||
tuh_hid_mouse_isr(dev_addr, event);
|
tuh_hid_mouse_isr(dev_addr, event);
|
||||||
return;
|
return true;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUSB_HOST_HID_GENERIC
|
#if CFG_TUSB_HOST_HID_GENERIC
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void hidh_close(uint8_t dev_addr)
|
void hidh_close(uint8_t dev_addr)
|
||||||
|
@ -197,7 +197,8 @@ void tuh_hid_generic_isr(uint8_t dev_addr, xfer_result_t event);
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void hidh_init(void);
|
void hidh_init(void);
|
||||||
bool hidh_open_subtask(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length);
|
bool hidh_open_subtask(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length);
|
||||||
void hidh_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num);
|
||||||
|
bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
void hidh_close(uint8_t dev_addr);
|
void hidh_close(uint8_t dev_addr);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -375,17 +375,14 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool midid_control_complete(uint8_t rhport, tusb_control_request_t const * p_request)
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
|
bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
(void) p_request;
|
(void) stage;
|
||||||
return true;
|
(void) request;
|
||||||
}
|
|
||||||
|
|
||||||
bool midid_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
(void) p_request;
|
|
||||||
|
|
||||||
// driver doesn't support any request yet
|
// driver doesn't support any request yet
|
||||||
return false;
|
return false;
|
||||||
|
@ -142,12 +142,11 @@ static inline bool tud_midi_send (uint8_t const packet[4])
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Internal Class Driver API
|
// Internal Class Driver API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void midid_init (void);
|
void midid_init (void);
|
||||||
void midid_reset (uint8_t rhport);
|
void midid_reset (uint8_t rhport);
|
||||||
uint16_t midid_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t midid_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool midid_control_request (uint8_t rhport, tusb_control_request_t const * request);
|
bool midid_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool midid_control_complete (uint8_t rhport, tusb_control_request_t const * request);
|
bool midid_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
bool midid_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -255,7 +255,7 @@ typedef struct TU_ATTR_PACKED
|
|||||||
|
|
||||||
uint8_t : 3;
|
uint8_t : 3;
|
||||||
uint8_t disable_block_descriptor : 1;
|
uint8_t disable_block_descriptor : 1;
|
||||||
uint8_t : 0;
|
uint8_t : 4;
|
||||||
|
|
||||||
uint8_t page_code : 6;
|
uint8_t page_code : 6;
|
||||||
uint8_t page_control : 2;
|
uint8_t page_control : 2;
|
||||||
|
@ -71,6 +71,7 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _mscd_buf[CFG_TUD_MSC_EP_
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize);
|
||||||
static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
|
static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
|
||||||
static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
|
static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
|
||||||
|
|
||||||
@ -186,10 +187,14 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Handle class control request
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
// return false to stall control endpoint (e.g unsupported request)
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
bool mscd_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
|
bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * p_request)
|
||||||
{
|
{
|
||||||
|
// nothing to do with DATA & ACK stage
|
||||||
|
if (stage != CONTROL_STAGE_SETUP) return true;
|
||||||
|
|
||||||
// Handle class request only
|
// Handle class request only
|
||||||
TU_VERIFY(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
TU_VERIFY(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
||||||
|
|
||||||
@ -219,190 +224,6 @@ bool mscd_control_request(uint8_t rhport, tusb_control_request_t const * p_reque
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when class request DATA stage is finished.
|
|
||||||
// return false to stall control endpoint (e.g Host send non-sense DATA)
|
|
||||||
bool mscd_control_complete(uint8_t rhport, tusb_control_request_t const * request)
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
(void) request;
|
|
||||||
|
|
||||||
// nothing to do
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
// return response's length (copied to buffer). Negative if it is not an built-in command or indicate Failed status (CSW)
|
|
||||||
// In case of a failed status, sense key must be set for reason of failure
|
|
||||||
int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize)
|
|
||||||
{
|
|
||||||
(void) bufsize; // TODO refractor later
|
|
||||||
int32_t resplen;
|
|
||||||
|
|
||||||
switch ( scsi_cmd[0] )
|
|
||||||
{
|
|
||||||
case SCSI_CMD_TEST_UNIT_READY:
|
|
||||||
resplen = 0;
|
|
||||||
if ( !tud_msc_test_unit_ready_cb(lun) )
|
|
||||||
{
|
|
||||||
// Failed status response
|
|
||||||
resplen = - 1;
|
|
||||||
|
|
||||||
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
|
||||||
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_START_STOP_UNIT:
|
|
||||||
resplen = 0;
|
|
||||||
|
|
||||||
if (tud_msc_start_stop_cb)
|
|
||||||
{
|
|
||||||
scsi_start_stop_unit_t const * start_stop = (scsi_start_stop_unit_t const *) scsi_cmd;
|
|
||||||
if ( !tud_msc_start_stop_cb(lun, start_stop->power_condition, start_stop->start, start_stop->load_eject) )
|
|
||||||
{
|
|
||||||
// Failed status response
|
|
||||||
resplen = - 1;
|
|
||||||
|
|
||||||
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
|
||||||
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_READ_CAPACITY_10:
|
|
||||||
{
|
|
||||||
uint32_t block_count;
|
|
||||||
uint32_t block_size;
|
|
||||||
uint16_t block_size_u16;
|
|
||||||
|
|
||||||
tud_msc_capacity_cb(lun, &block_count, &block_size_u16);
|
|
||||||
block_size = (uint32_t) block_size_u16;
|
|
||||||
|
|
||||||
// Invalid block size/count from callback, possibly unit is not ready
|
|
||||||
// stall this request, set sense key to NOT READY
|
|
||||||
if (block_count == 0 || block_size == 0)
|
|
||||||
{
|
|
||||||
resplen = -1;
|
|
||||||
|
|
||||||
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
|
||||||
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
|
||||||
}else
|
|
||||||
{
|
|
||||||
scsi_read_capacity10_resp_t read_capa10;
|
|
||||||
|
|
||||||
read_capa10.last_lba = tu_htonl(block_count-1);
|
|
||||||
read_capa10.block_size = tu_htonl(block_size);
|
|
||||||
|
|
||||||
resplen = sizeof(read_capa10);
|
|
||||||
memcpy(buffer, &read_capa10, resplen);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_READ_FORMAT_CAPACITY:
|
|
||||||
{
|
|
||||||
scsi_read_format_capacity_data_t read_fmt_capa =
|
|
||||||
{
|
|
||||||
.list_length = 8,
|
|
||||||
.block_num = 0,
|
|
||||||
.descriptor_type = 2, // formatted media
|
|
||||||
.block_size_u16 = 0
|
|
||||||
};
|
|
||||||
|
|
||||||
uint32_t block_count;
|
|
||||||
uint16_t block_size;
|
|
||||||
|
|
||||||
tud_msc_capacity_cb(lun, &block_count, &block_size);
|
|
||||||
|
|
||||||
// Invalid block size/count from callback, possibly unit is not ready
|
|
||||||
// stall this request, set sense key to NOT READY
|
|
||||||
if (block_count == 0 || block_size == 0)
|
|
||||||
{
|
|
||||||
resplen = -1;
|
|
||||||
|
|
||||||
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
|
||||||
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
|
||||||
}else
|
|
||||||
{
|
|
||||||
read_fmt_capa.block_num = tu_htonl(block_count);
|
|
||||||
read_fmt_capa.block_size_u16 = tu_htons(block_size);
|
|
||||||
|
|
||||||
resplen = sizeof(read_fmt_capa);
|
|
||||||
memcpy(buffer, &read_fmt_capa, resplen);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_INQUIRY:
|
|
||||||
{
|
|
||||||
scsi_inquiry_resp_t inquiry_rsp =
|
|
||||||
{
|
|
||||||
.is_removable = 1,
|
|
||||||
.version = 2,
|
|
||||||
.response_data_format = 2,
|
|
||||||
};
|
|
||||||
|
|
||||||
// vendor_id, product_id, product_rev is space padded string
|
|
||||||
memset(inquiry_rsp.vendor_id , ' ', sizeof(inquiry_rsp.vendor_id));
|
|
||||||
memset(inquiry_rsp.product_id , ' ', sizeof(inquiry_rsp.product_id));
|
|
||||||
memset(inquiry_rsp.product_rev, ' ', sizeof(inquiry_rsp.product_rev));
|
|
||||||
|
|
||||||
tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev);
|
|
||||||
|
|
||||||
resplen = sizeof(inquiry_rsp);
|
|
||||||
memcpy(buffer, &inquiry_rsp, resplen);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_MODE_SENSE_6:
|
|
||||||
{
|
|
||||||
scsi_mode_sense6_resp_t mode_resp =
|
|
||||||
{
|
|
||||||
.data_len = 3,
|
|
||||||
.medium_type = 0,
|
|
||||||
.write_protected = false,
|
|
||||||
.reserved = 0,
|
|
||||||
.block_descriptor_len = 0 // no block descriptor are included
|
|
||||||
};
|
|
||||||
|
|
||||||
bool writable = true;
|
|
||||||
if (tud_msc_is_writable_cb) {
|
|
||||||
writable = tud_msc_is_writable_cb(lun);
|
|
||||||
}
|
|
||||||
mode_resp.write_protected = !writable;
|
|
||||||
|
|
||||||
resplen = sizeof(mode_resp);
|
|
||||||
memcpy(buffer, &mode_resp, resplen);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_REQUEST_SENSE:
|
|
||||||
{
|
|
||||||
scsi_sense_fixed_resp_t sense_rsp =
|
|
||||||
{
|
|
||||||
.response_code = 0x70,
|
|
||||||
.valid = 1
|
|
||||||
};
|
|
||||||
|
|
||||||
sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8;
|
|
||||||
|
|
||||||
sense_rsp.sense_key = _mscd_itf.sense_key;
|
|
||||||
sense_rsp.add_sense_code = _mscd_itf.add_sense_code;
|
|
||||||
sense_rsp.add_sense_qualifier = _mscd_itf.add_sense_qualifier;
|
|
||||||
|
|
||||||
resplen = sizeof(sense_rsp);
|
|
||||||
memcpy(buffer, &sense_rsp, resplen);
|
|
||||||
|
|
||||||
// Clear sense data after copy
|
|
||||||
tud_msc_set_sense(lun, 0, 0, 0);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default: resplen = -1; break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return resplen;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
mscd_interface_t* p_msc = &_mscd_itf;
|
mscd_interface_t* p_msc = &_mscd_itf;
|
||||||
@ -592,6 +413,24 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
|
|||||||
TU_LOG2(" SCSI Status: %u\r\n", p_csw->status);
|
TU_LOG2(" SCSI Status: %u\r\n", p_csw->status);
|
||||||
// TU_LOG2_MEM(p_csw, xferred_bytes, 2);
|
// TU_LOG2_MEM(p_csw, xferred_bytes, 2);
|
||||||
|
|
||||||
|
// Invoke complete callback if defined
|
||||||
|
// Note: There is racing issue with samd51 + qspi flash testing with arduino
|
||||||
|
// if complete_cb() is invoked after queuing the status.
|
||||||
|
switch(p_cbw->command[0])
|
||||||
|
{
|
||||||
|
case SCSI_CMD_READ_10:
|
||||||
|
if ( tud_msc_read10_complete_cb ) tud_msc_read10_complete_cb(p_cbw->lun);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_WRITE_10:
|
||||||
|
if ( tud_msc_write10_complete_cb ) tud_msc_write10_complete_cb(p_cbw->lun);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
if ( tud_msc_scsi_complete_cb ) tud_msc_scsi_complete_cb(p_cbw->lun, p_cbw->command);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
// Move to default CMD stage
|
// Move to default CMD stage
|
||||||
p_msc->stage = MSC_STAGE_CMD;
|
p_msc->stage = MSC_STAGE_CMD;
|
||||||
|
|
||||||
@ -615,24 +454,6 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
// Invoke complete callback if defined
|
|
||||||
// Note: There is racing issue with samd51 + qspi flash testing with arduino
|
|
||||||
// if complete_cb() is invoked after queuing the status.
|
|
||||||
switch(p_cbw->command[0])
|
|
||||||
{
|
|
||||||
case SCSI_CMD_READ_10:
|
|
||||||
if ( tud_msc_read10_complete_cb ) tud_msc_read10_complete_cb(p_cbw->lun);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SCSI_CMD_WRITE_10:
|
|
||||||
if ( tud_msc_write10_complete_cb ) tud_msc_write10_complete_cb(p_cbw->lun);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
if ( tud_msc_scsi_complete_cb ) tud_msc_scsi_complete_cb(p_cbw->lun, p_cbw->command);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Move to Status Sent stage
|
// Move to Status Sent stage
|
||||||
p_msc->stage = MSC_STAGE_STATUS_SENT;
|
p_msc->stage = MSC_STAGE_STATUS_SENT;
|
||||||
|
|
||||||
@ -647,6 +468,180 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
|
|||||||
/*------------------------------------------------------------------*/
|
/*------------------------------------------------------------------*/
|
||||||
/* SCSI Command Process
|
/* SCSI Command Process
|
||||||
*------------------------------------------------------------------*/
|
*------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
// return response's length (copied to buffer). Negative if it is not an built-in command or indicate Failed status (CSW)
|
||||||
|
// In case of a failed status, sense key must be set for reason of failure
|
||||||
|
static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize)
|
||||||
|
{
|
||||||
|
(void) bufsize; // TODO refractor later
|
||||||
|
int32_t resplen;
|
||||||
|
|
||||||
|
switch ( scsi_cmd[0] )
|
||||||
|
{
|
||||||
|
case SCSI_CMD_TEST_UNIT_READY:
|
||||||
|
resplen = 0;
|
||||||
|
if ( !tud_msc_test_unit_ready_cb(lun) )
|
||||||
|
{
|
||||||
|
// Failed status response
|
||||||
|
resplen = - 1;
|
||||||
|
|
||||||
|
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
||||||
|
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_START_STOP_UNIT:
|
||||||
|
resplen = 0;
|
||||||
|
|
||||||
|
if (tud_msc_start_stop_cb)
|
||||||
|
{
|
||||||
|
scsi_start_stop_unit_t const * start_stop = (scsi_start_stop_unit_t const *) scsi_cmd;
|
||||||
|
if ( !tud_msc_start_stop_cb(lun, start_stop->power_condition, start_stop->start, start_stop->load_eject) )
|
||||||
|
{
|
||||||
|
// Failed status response
|
||||||
|
resplen = - 1;
|
||||||
|
|
||||||
|
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
||||||
|
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_READ_CAPACITY_10:
|
||||||
|
{
|
||||||
|
uint32_t block_count;
|
||||||
|
uint32_t block_size;
|
||||||
|
uint16_t block_size_u16;
|
||||||
|
|
||||||
|
tud_msc_capacity_cb(lun, &block_count, &block_size_u16);
|
||||||
|
block_size = (uint32_t) block_size_u16;
|
||||||
|
|
||||||
|
// Invalid block size/count from callback, possibly unit is not ready
|
||||||
|
// stall this request, set sense key to NOT READY
|
||||||
|
if (block_count == 0 || block_size == 0)
|
||||||
|
{
|
||||||
|
resplen = -1;
|
||||||
|
|
||||||
|
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
||||||
|
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
scsi_read_capacity10_resp_t read_capa10;
|
||||||
|
|
||||||
|
read_capa10.last_lba = tu_htonl(block_count-1);
|
||||||
|
read_capa10.block_size = tu_htonl(block_size);
|
||||||
|
|
||||||
|
resplen = sizeof(read_capa10);
|
||||||
|
memcpy(buffer, &read_capa10, resplen);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_READ_FORMAT_CAPACITY:
|
||||||
|
{
|
||||||
|
scsi_read_format_capacity_data_t read_fmt_capa =
|
||||||
|
{
|
||||||
|
.list_length = 8,
|
||||||
|
.block_num = 0,
|
||||||
|
.descriptor_type = 2, // formatted media
|
||||||
|
.block_size_u16 = 0
|
||||||
|
};
|
||||||
|
|
||||||
|
uint32_t block_count;
|
||||||
|
uint16_t block_size;
|
||||||
|
|
||||||
|
tud_msc_capacity_cb(lun, &block_count, &block_size);
|
||||||
|
|
||||||
|
// Invalid block size/count from callback, possibly unit is not ready
|
||||||
|
// stall this request, set sense key to NOT READY
|
||||||
|
if (block_count == 0 || block_size == 0)
|
||||||
|
{
|
||||||
|
resplen = -1;
|
||||||
|
|
||||||
|
// If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
|
||||||
|
if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
read_fmt_capa.block_num = tu_htonl(block_count);
|
||||||
|
read_fmt_capa.block_size_u16 = tu_htons(block_size);
|
||||||
|
|
||||||
|
resplen = sizeof(read_fmt_capa);
|
||||||
|
memcpy(buffer, &read_fmt_capa, resplen);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_INQUIRY:
|
||||||
|
{
|
||||||
|
scsi_inquiry_resp_t inquiry_rsp =
|
||||||
|
{
|
||||||
|
.is_removable = 1,
|
||||||
|
.version = 2,
|
||||||
|
.response_data_format = 2,
|
||||||
|
};
|
||||||
|
|
||||||
|
// vendor_id, product_id, product_rev is space padded string
|
||||||
|
memset(inquiry_rsp.vendor_id , ' ', sizeof(inquiry_rsp.vendor_id));
|
||||||
|
memset(inquiry_rsp.product_id , ' ', sizeof(inquiry_rsp.product_id));
|
||||||
|
memset(inquiry_rsp.product_rev, ' ', sizeof(inquiry_rsp.product_rev));
|
||||||
|
|
||||||
|
tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev);
|
||||||
|
|
||||||
|
resplen = sizeof(inquiry_rsp);
|
||||||
|
memcpy(buffer, &inquiry_rsp, resplen);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_MODE_SENSE_6:
|
||||||
|
{
|
||||||
|
scsi_mode_sense6_resp_t mode_resp =
|
||||||
|
{
|
||||||
|
.data_len = 3,
|
||||||
|
.medium_type = 0,
|
||||||
|
.write_protected = false,
|
||||||
|
.reserved = 0,
|
||||||
|
.block_descriptor_len = 0 // no block descriptor are included
|
||||||
|
};
|
||||||
|
|
||||||
|
bool writable = true;
|
||||||
|
if (tud_msc_is_writable_cb) {
|
||||||
|
writable = tud_msc_is_writable_cb(lun);
|
||||||
|
}
|
||||||
|
mode_resp.write_protected = !writable;
|
||||||
|
|
||||||
|
resplen = sizeof(mode_resp);
|
||||||
|
memcpy(buffer, &mode_resp, resplen);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SCSI_CMD_REQUEST_SENSE:
|
||||||
|
{
|
||||||
|
scsi_sense_fixed_resp_t sense_rsp =
|
||||||
|
{
|
||||||
|
.response_code = 0x70,
|
||||||
|
.valid = 1
|
||||||
|
};
|
||||||
|
|
||||||
|
sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8;
|
||||||
|
|
||||||
|
sense_rsp.sense_key = _mscd_itf.sense_key;
|
||||||
|
sense_rsp.add_sense_code = _mscd_itf.add_sense_code;
|
||||||
|
sense_rsp.add_sense_qualifier = _mscd_itf.add_sense_qualifier;
|
||||||
|
|
||||||
|
resplen = sizeof(sense_rsp);
|
||||||
|
memcpy(buffer, &sense_rsp, resplen);
|
||||||
|
|
||||||
|
// Clear sense data after copy
|
||||||
|
tud_msc_set_sense(lun, 0, 0, 0);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default: resplen = -1; break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return resplen;
|
||||||
|
}
|
||||||
|
|
||||||
static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
|
static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
|
||||||
{
|
{
|
||||||
msc_cbw_t const * p_cbw = &p_msc->cbw;
|
msc_cbw_t const * p_cbw = &p_msc->cbw;
|
||||||
|
@ -158,12 +158,11 @@ TU_ATTR_WEAK bool tud_msc_is_writable_cb(uint8_t lun);
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Internal Class Driver API
|
// Internal Class Driver API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void mscd_init (void);
|
void mscd_init (void);
|
||||||
void mscd_reset (uint8_t rhport);
|
void mscd_reset (uint8_t rhport);
|
||||||
uint16_t mscd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t mscd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool mscd_control_request (uint8_t rhport, tusb_control_request_t const * p_request);
|
bool mscd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * p_request);
|
||||||
bool mscd_control_complete (uint8_t rhport, tusb_control_request_t const * p_request);
|
bool mscd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
bool mscd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -37,53 +37,63 @@
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// MACRO CONSTANT TYPEDEF
|
// MACRO CONSTANT TYPEDEF
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
CFG_TUSB_MEM_SECTION static msch_interface_t msch_data[CFG_TUSB_HOST_DEVICE_MAX];
|
enum
|
||||||
|
{
|
||||||
|
MSC_STAGE_IDLE = 0,
|
||||||
|
MSC_STAGE_CMD,
|
||||||
|
MSC_STAGE_DATA,
|
||||||
|
MSC_STAGE_STATUS,
|
||||||
|
};
|
||||||
|
|
||||||
//------------- Initalization Data -------------//
|
typedef struct
|
||||||
static osal_semaphore_def_t msch_sem_def;
|
{
|
||||||
static osal_semaphore_t msch_sem_hdl;
|
uint8_t itf_num;
|
||||||
|
uint8_t ep_in;
|
||||||
|
uint8_t ep_out;
|
||||||
|
|
||||||
|
uint8_t max_lun;
|
||||||
|
|
||||||
|
volatile bool mounted;
|
||||||
|
|
||||||
|
uint8_t stage;
|
||||||
|
void* buffer;
|
||||||
|
tuh_msc_complete_cb_t complete_cb;
|
||||||
|
|
||||||
|
msc_cbw_t cbw;
|
||||||
|
msc_csw_t csw;
|
||||||
|
}msch_interface_t;
|
||||||
|
|
||||||
|
CFG_TUSB_MEM_SECTION static msch_interface_t msch_data[CFG_TUSB_HOST_DEVICE_MAX];
|
||||||
|
|
||||||
// buffer used to read scsi information when mounted, largest response data currently is inquiry
|
// buffer used to read scsi information when mounted, largest response data currently is inquiry
|
||||||
CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msch_buffer[sizeof(scsi_inquiry_resp_t)];
|
CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msch_buffer[sizeof(scsi_inquiry_resp_t)];
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
static inline msch_interface_t* get_itf(uint8_t dev_addr)
|
||||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
{
|
||||||
//--------------------------------------------------------------------+
|
return &msch_data[dev_addr-1];
|
||||||
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// PUBLIC API
|
// PUBLIC API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
bool tuh_msc_is_mounted(uint8_t dev_addr)
|
uint8_t tuh_msc_get_maxlun(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
return tuh_device_is_configured(dev_addr) && // is configured can be omitted
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
msch_data[dev_addr-1].is_initialized;
|
return p_msc->max_lun;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool tuh_msc_mounted(uint8_t dev_addr)
|
||||||
|
{
|
||||||
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
|
||||||
|
// is configured can be omitted
|
||||||
|
return tuh_device_is_configured(dev_addr) && p_msc->mounted;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool tuh_msc_is_busy(uint8_t dev_addr)
|
bool tuh_msc_is_busy(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
return msch_data[dev_addr-1].is_initialized &&
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
hcd_edpt_busy(dev_addr, msch_data[dev_addr-1].ep_in);
|
return p_msc->mounted && hcd_edpt_busy(dev_addr, p_msc->ep_in);
|
||||||
}
|
|
||||||
|
|
||||||
uint8_t const* tuh_msc_get_vendor_name(uint8_t dev_addr)
|
|
||||||
{
|
|
||||||
return msch_data[dev_addr-1].is_initialized ? msch_data[dev_addr-1].vendor_id : NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8_t const* tuh_msc_get_product_name(uint8_t dev_addr)
|
|
||||||
{
|
|
||||||
return msch_data[dev_addr-1].is_initialized ? msch_data[dev_addr-1].product_id : NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
tusb_error_t tuh_msc_get_capacity(uint8_t dev_addr, uint32_t* p_last_lba, uint32_t* p_block_size)
|
|
||||||
{
|
|
||||||
if ( !msch_data[dev_addr-1].is_initialized ) return TUSB_ERROR_MSCH_DEVICE_NOT_MOUNTED;
|
|
||||||
TU_ASSERT(p_last_lba != NULL && p_block_size != NULL, TUSB_ERROR_INVALID_PARA);
|
|
||||||
|
|
||||||
(*p_last_lba) = msch_data[dev_addr-1].last_lba;
|
|
||||||
(*p_block_size) = (uint32_t) msch_data[dev_addr-1].block_size;
|
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -92,130 +102,97 @@ tusb_error_t tuh_msc_get_capacity(uint8_t dev_addr, uint32_t* p_last_lba, uint32
|
|||||||
static inline void msc_cbw_add_signature(msc_cbw_t *p_cbw, uint8_t lun)
|
static inline void msc_cbw_add_signature(msc_cbw_t *p_cbw, uint8_t lun)
|
||||||
{
|
{
|
||||||
p_cbw->signature = MSC_CBW_SIGNATURE;
|
p_cbw->signature = MSC_CBW_SIGNATURE;
|
||||||
p_cbw->tag = 0xCAFECAFE;
|
p_cbw->tag = 0x54555342; // TUSB
|
||||||
p_cbw->lun = lun;
|
p_cbw->lun = lun;
|
||||||
}
|
}
|
||||||
|
|
||||||
static tusb_error_t msch_command_xfer(uint8_t dev_addr, msch_interface_t * p_msch, void* p_buffer)
|
bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb)
|
||||||
{
|
{
|
||||||
if ( NULL != p_buffer)
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
{ // there is data phase
|
// TU_VERIFY(p_msc->mounted); // TODO part of the enumeration also use scsi command
|
||||||
if (p_msch->cbw.dir & TUSB_DIR_IN_MASK)
|
|
||||||
{
|
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t), false), TUSB_ERROR_FAILED );
|
|
||||||
TU_ASSERT( hcd_pipe_queue_xfer(dev_addr, p_msch->ep_in , p_buffer, p_msch->cbw.total_bytes), TUSB_ERROR_FAILED );
|
|
||||||
}else
|
|
||||||
{
|
|
||||||
TU_ASSERT( hcd_pipe_queue_xfer(dev_addr, p_msch->ep_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_FAILED );
|
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_out , p_buffer, p_msch->cbw.total_bytes, false), TUSB_ERROR_FAILED );
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_in , (uint8_t*) &p_msch->csw, sizeof(msc_csw_t), true), TUSB_ERROR_FAILED);
|
// TODO claim endpoint
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
p_msc->cbw = *cbw;
|
||||||
|
p_msc->stage = MSC_STAGE_CMD;
|
||||||
|
p_msc->buffer = data;
|
||||||
|
p_msc->complete_cb = complete_cb;
|
||||||
|
|
||||||
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)));
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
tusb_error_t tusbh_msc_inquiry(uint8_t dev_addr, uint8_t lun, uint8_t *p_data)
|
bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb)
|
||||||
{
|
{
|
||||||
msch_interface_t* p_msch = &msch_data[dev_addr-1];
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
if ( !p_msc->mounted ) return false;
|
||||||
|
|
||||||
//------------- Command Block Wrapper -------------//
|
msc_cbw_t cbw = { 0 };
|
||||||
msc_cbw_add_signature(&p_msch->cbw, lun);
|
|
||||||
p_msch->cbw.total_bytes = sizeof(scsi_inquiry_resp_t);
|
|
||||||
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
|
|
||||||
p_msch->cbw.cmd_len = sizeof(scsi_inquiry_t);
|
|
||||||
|
|
||||||
//------------- SCSI command -------------//
|
msc_cbw_add_signature(&cbw, lun);
|
||||||
scsi_inquiry_t cmd_inquiry =
|
cbw.total_bytes = sizeof(scsi_read_capacity10_resp_t);
|
||||||
|
cbw.dir = TUSB_DIR_IN_MASK;
|
||||||
|
cbw.cmd_len = sizeof(scsi_read_capacity10_t);
|
||||||
|
cbw.command[0] = SCSI_CMD_READ_CAPACITY_10;
|
||||||
|
|
||||||
|
return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool tuh_msc_scsi_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
msc_cbw_t cbw = { 0 };
|
||||||
|
|
||||||
|
msc_cbw_add_signature(&cbw, lun);
|
||||||
|
cbw.total_bytes = sizeof(scsi_inquiry_resp_t);
|
||||||
|
cbw.dir = TUSB_DIR_IN_MASK;
|
||||||
|
cbw.cmd_len = sizeof(scsi_inquiry_t);
|
||||||
|
|
||||||
|
scsi_inquiry_t const cmd_inquiry =
|
||||||
{
|
{
|
||||||
.cmd_code = SCSI_CMD_INQUIRY,
|
.cmd_code = SCSI_CMD_INQUIRY,
|
||||||
.alloc_length = sizeof(scsi_inquiry_resp_t)
|
.alloc_length = sizeof(scsi_inquiry_resp_t)
|
||||||
|
};
|
||||||
|
memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len);
|
||||||
|
|
||||||
|
return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
msc_cbw_t cbw = { 0 };
|
||||||
|
msc_cbw_add_signature(&cbw, lun);
|
||||||
|
|
||||||
|
cbw.total_bytes = 0; // Number of bytes
|
||||||
|
cbw.dir = TUSB_DIR_OUT;
|
||||||
|
cbw.cmd_len = sizeof(scsi_test_unit_ready_t);
|
||||||
|
cbw.command[0] = SCSI_CMD_TEST_UNIT_READY;
|
||||||
|
cbw.command[1] = lun; // according to wiki TODO need verification
|
||||||
|
|
||||||
|
return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
msc_cbw_t cbw = { 0 };
|
||||||
|
msc_cbw_add_signature(&cbw, lun);
|
||||||
|
|
||||||
|
cbw.total_bytes = 18; // TODO sense response
|
||||||
|
cbw.dir = TUSB_DIR_IN_MASK;
|
||||||
|
cbw.cmd_len = sizeof(scsi_request_sense_t);
|
||||||
|
|
||||||
|
scsi_request_sense_t const cmd_request_sense =
|
||||||
|
{
|
||||||
|
.cmd_code = SCSI_CMD_REQUEST_SENSE,
|
||||||
|
.alloc_length = 18
|
||||||
};
|
};
|
||||||
|
|
||||||
memcpy(p_msch->cbw.command, &cmd_inquiry, p_msch->cbw.cmd_len);
|
memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
|
||||||
|
|
||||||
TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_data) );
|
return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb);
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
tusb_error_t tusbh_msc_read_capacity10(uint8_t dev_addr, uint8_t lun, uint8_t *p_data)
|
#if 0
|
||||||
{
|
|
||||||
msch_interface_t* p_msch = &msch_data[dev_addr-1];
|
|
||||||
|
|
||||||
//------------- Command Block Wrapper -------------//
|
|
||||||
msc_cbw_add_signature(&p_msch->cbw, lun);
|
|
||||||
p_msch->cbw.total_bytes = sizeof(scsi_read_capacity10_resp_t);
|
|
||||||
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
|
|
||||||
p_msch->cbw.cmd_len = sizeof(scsi_read_capacity10_t);
|
|
||||||
|
|
||||||
//------------- SCSI command -------------//
|
|
||||||
scsi_read_capacity10_t cmd_read_capacity10 =
|
|
||||||
{
|
|
||||||
.cmd_code = SCSI_CMD_READ_CAPACITY_10,
|
|
||||||
.lba = 0,
|
|
||||||
.partial_medium_indicator = 0
|
|
||||||
};
|
|
||||||
|
|
||||||
memcpy(p_msch->cbw.command, &cmd_read_capacity10, p_msch->cbw.cmd_len);
|
|
||||||
|
|
||||||
TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_data) );
|
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
tusb_error_t tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, uint8_t *p_data)
|
|
||||||
{
|
|
||||||
(void) lun; // TODO [MSCH] multiple lun support
|
|
||||||
|
|
||||||
msch_interface_t* p_msch = &msch_data[dev_addr-1];
|
|
||||||
|
|
||||||
//------------- Command Block Wrapper -------------//
|
|
||||||
p_msch->cbw.total_bytes = 18;
|
|
||||||
p_msch->cbw.dir = TUSB_DIR_IN_MASK;
|
|
||||||
p_msch->cbw.cmd_len = sizeof(scsi_request_sense_t);
|
|
||||||
|
|
||||||
//------------- SCSI command -------------//
|
|
||||||
scsi_request_sense_t cmd_request_sense =
|
|
||||||
{
|
|
||||||
.cmd_code = SCSI_CMD_REQUEST_SENSE,
|
|
||||||
.alloc_length = 18
|
|
||||||
};
|
|
||||||
|
|
||||||
memcpy(p_msch->cbw.command, &cmd_request_sense, p_msch->cbw.cmd_len);
|
|
||||||
|
|
||||||
TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_data) );
|
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
tusb_error_t tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, msc_csw_t * p_csw)
|
|
||||||
{
|
|
||||||
msch_interface_t* p_msch = &msch_data[dev_addr-1];
|
|
||||||
|
|
||||||
//------------- Command Block Wrapper -------------//
|
|
||||||
msc_cbw_add_signature(&p_msch->cbw, lun);
|
|
||||||
|
|
||||||
p_msch->cbw.total_bytes = 0; // Number of bytes
|
|
||||||
p_msch->cbw.dir = TUSB_DIR_OUT;
|
|
||||||
p_msch->cbw.cmd_len = sizeof(scsi_test_unit_ready_t);
|
|
||||||
|
|
||||||
//------------- SCSI command -------------//
|
|
||||||
scsi_test_unit_ready_t cmd_test_unit_ready =
|
|
||||||
{
|
|
||||||
.cmd_code = SCSI_CMD_TEST_UNIT_READY,
|
|
||||||
.lun = lun // according to wiki
|
|
||||||
};
|
|
||||||
|
|
||||||
memcpy(p_msch->cbw.command, &cmd_test_unit_ready, p_msch->cbw.cmd_len);
|
|
||||||
|
|
||||||
// TODO MSCH refractor test uinit ready
|
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_out, (uint8_t*) &p_msch->cbw, sizeof(msc_cbw_t), false), TUSB_ERROR_FAILED );
|
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, p_msch->ep_in , (uint8_t*) p_csw, sizeof(msc_csw_t), true), TUSB_ERROR_FAILED );
|
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
tusb_error_t tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * p_buffer, uint32_t lba, uint16_t block_count)
|
tusb_error_t tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * p_buffer, uint32_t lba, uint16_t block_count)
|
||||||
{
|
{
|
||||||
@ -229,7 +206,7 @@ tusb_error_t tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * p_buffer, uin
|
|||||||
p_msch->cbw.cmd_len = sizeof(scsi_read10_t);
|
p_msch->cbw.cmd_len = sizeof(scsi_read10_t);
|
||||||
|
|
||||||
//------------- SCSI command -------------//
|
//------------- SCSI command -------------//
|
||||||
scsi_read10_t cmd_read10 =
|
scsi_read10_t cmd_read10 =msch_sem_hdl
|
||||||
{
|
{
|
||||||
.cmd_code = SCSI_CMD_READ_10,
|
.cmd_code = SCSI_CMD_READ_10,
|
||||||
.lba = tu_htonl(lba),
|
.lba = tu_htonl(lba),
|
||||||
@ -238,7 +215,7 @@ tusb_error_t tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * p_buffer, uin
|
|||||||
|
|
||||||
memcpy(p_msch->cbw.command, &cmd_read10, p_msch->cbw.cmd_len);
|
memcpy(p_msch->cbw.command, &cmd_read10, p_msch->cbw.cmd_len);
|
||||||
|
|
||||||
TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, p_buffer));
|
TU_ASSERT_ERR ( send_cbw(dev_addr, p_msch, p_buffer));
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
return TUSB_ERROR_NONE;
|
||||||
}
|
}
|
||||||
@ -264,10 +241,32 @@ tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffe
|
|||||||
|
|
||||||
memcpy(p_msch->cbw.command, &cmd_write10, p_msch->cbw.cmd_len);
|
memcpy(p_msch->cbw.command, &cmd_write10, p_msch->cbw.cmd_len);
|
||||||
|
|
||||||
TU_ASSERT_ERR ( msch_command_xfer(dev_addr, p_msch, (void*) p_buffer));
|
TU_ASSERT_ERR ( send_cbw(dev_addr, p_msch, (void*) p_buffer));
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
return TUSB_ERROR_NONE;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
// MSC interface Reset (not used now)
|
||||||
|
bool tuh_msc_reset(uint8_t dev_addr)
|
||||||
|
{
|
||||||
|
tusb_control_request_t const new_request =
|
||||||
|
{
|
||||||
|
.bmRequestType_bit =
|
||||||
|
{
|
||||||
|
.recipient = TUSB_REQ_RCPT_INTERFACE,
|
||||||
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
|
.direction = TUSB_DIR_OUT
|
||||||
|
},
|
||||||
|
.bRequest = MSC_REQ_RESET,
|
||||||
|
.wValue = 0,
|
||||||
|
.wIndex = p_msc->itf_num,
|
||||||
|
.wLength = 0
|
||||||
|
};
|
||||||
|
TU_ASSERT( usbh_control_xfer( dev_addr, &new_request, NULL ) );
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// CLASS-USBH API (don't require to verify parameters)
|
// CLASS-USBH API (don't require to verify parameters)
|
||||||
@ -275,24 +274,83 @@ tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffe
|
|||||||
void msch_init(void)
|
void msch_init(void)
|
||||||
{
|
{
|
||||||
tu_memclr(msch_data, sizeof(msch_interface_t)*CFG_TUSB_HOST_DEVICE_MAX);
|
tu_memclr(msch_data, sizeof(msch_interface_t)*CFG_TUSB_HOST_DEVICE_MAX);
|
||||||
msch_sem_hdl = osal_semaphore_create(&msch_sem_def);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void msch_close(uint8_t dev_addr)
|
||||||
|
{
|
||||||
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
tu_memclr(p_msc, sizeof(msch_interface_t));
|
||||||
|
tuh_msc_unmounted_cb(dev_addr); // invoke Application Callback
|
||||||
|
}
|
||||||
|
|
||||||
|
bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
||||||
|
{
|
||||||
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
msc_cbw_t const * cbw = &p_msc->cbw;
|
||||||
|
msc_csw_t * csw = &p_msc->csw;
|
||||||
|
|
||||||
|
switch (p_msc->stage)
|
||||||
|
{
|
||||||
|
case MSC_STAGE_CMD:
|
||||||
|
// Must be Command Block
|
||||||
|
TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
|
||||||
|
|
||||||
|
if ( cbw->total_bytes && p_msc->buffer )
|
||||||
|
{
|
||||||
|
// Data stage if any
|
||||||
|
p_msc->stage = MSC_STAGE_DATA;
|
||||||
|
|
||||||
|
uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
|
||||||
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, cbw->total_bytes));
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
// Status stage
|
||||||
|
p_msc->stage = MSC_STAGE_STATUS;
|
||||||
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)));
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case MSC_STAGE_DATA:
|
||||||
|
// Status stage
|
||||||
|
p_msc->stage = MSC_STAGE_STATUS;
|
||||||
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)));
|
||||||
|
break;
|
||||||
|
|
||||||
|
case MSC_STAGE_STATUS:
|
||||||
|
// SCSI op is complete
|
||||||
|
p_msc->stage = MSC_STAGE_IDLE;
|
||||||
|
|
||||||
|
if (p_msc->complete_cb) p_msc->complete_cb(dev_addr, cbw, csw);
|
||||||
|
break;
|
||||||
|
|
||||||
|
// unknown state
|
||||||
|
default: break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// MSC Enumeration
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
static bool config_get_maxlun_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
|
||||||
|
static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
|
||||||
|
|
||||||
bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length)
|
bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length)
|
||||||
{
|
{
|
||||||
TU_VERIFY (MSC_SUBCLASS_SCSI == itf_desc->bInterfaceSubClass &&
|
TU_VERIFY (MSC_SUBCLASS_SCSI == itf_desc->bInterfaceSubClass &&
|
||||||
MSC_PROTOCOL_BOT == itf_desc->bInterfaceProtocol);
|
MSC_PROTOCOL_BOT == itf_desc->bInterfaceProtocol);
|
||||||
|
|
||||||
msch_interface_t* p_msc = &msch_data[dev_addr-1];
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
|
||||||
//------------- Open Data Pipe -------------//
|
//------------- Open Data Pipe -------------//
|
||||||
tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
|
tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
|
||||||
|
|
||||||
for(uint32_t i=0; i<2; i++)
|
for(uint32_t i=0; i<2; i++)
|
||||||
{
|
{
|
||||||
TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType);
|
TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
|
||||||
TU_ASSERT(TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
|
|
||||||
|
|
||||||
TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
|
TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
|
||||||
|
|
||||||
if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
|
if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
|
||||||
@ -309,106 +367,78 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
|
|||||||
p_msc->itf_num = itf_desc->bInterfaceNumber;
|
p_msc->itf_num = itf_desc->bInterfaceNumber;
|
||||||
(*p_length) += sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
|
(*p_length) += sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
|
||||||
|
{
|
||||||
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
TU_ASSERT(p_msc->itf_num == itf_num);
|
||||||
|
|
||||||
//------------- Get Max Lun -------------//
|
//------------- Get Max Lun -------------//
|
||||||
TU_LOG2("MSC Get Max Lun\r\n");
|
TU_LOG2("MSC Get Max Lun\r\n");
|
||||||
tusb_control_request_t request = {
|
tusb_control_request_t request =
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
|
|
||||||
.bRequest = MSC_REQ_GET_MAX_LUN,
|
|
||||||
.wValue = 0,
|
|
||||||
.wIndex = p_msc->itf_num,
|
|
||||||
.wLength = 1
|
|
||||||
};
|
|
||||||
// TODO STALL means zero
|
|
||||||
TU_ASSERT( usbh_control_xfer( dev_addr, &request, msch_buffer ) );
|
|
||||||
p_msc->max_lun = msch_buffer[0];
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
//------------- Reset -------------//
|
|
||||||
request = (tusb_control_request_t) {
|
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
|
|
||||||
.bRequest = MSC_REQ_RESET,
|
|
||||||
.wValue = 0,
|
|
||||||
.wIndex = p_msc->itf_num,
|
|
||||||
.wLength = 0
|
|
||||||
};
|
|
||||||
TU_ASSERT( usbh_control_xfer( dev_addr, &request, NULL ) );
|
|
||||||
#endif
|
|
||||||
|
|
||||||
enum { SCSI_XFER_TIMEOUT = 2000 };
|
|
||||||
//------------- SCSI Inquiry -------------//
|
|
||||||
tusbh_msc_inquiry(dev_addr, 0, msch_buffer);
|
|
||||||
TU_ASSERT( osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT) );
|
|
||||||
|
|
||||||
memcpy(p_msc->vendor_id , ((scsi_inquiry_resp_t*) msch_buffer)->vendor_id , 8);
|
|
||||||
memcpy(p_msc->product_id, ((scsi_inquiry_resp_t*) msch_buffer)->product_id, 16);
|
|
||||||
|
|
||||||
//------------- SCSI Read Capacity 10 -------------//
|
|
||||||
tusbh_msc_read_capacity10(dev_addr, 0, msch_buffer);
|
|
||||||
TU_ASSERT( osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT));
|
|
||||||
|
|
||||||
// NOTE: my toshiba thumb-drive stall the first Read Capacity and require the sequence
|
|
||||||
// Read Capacity --> Stalled --> Clear Stall --> Request Sense --> Read Capacity (2) to work
|
|
||||||
if ( hcd_edpt_stalled(dev_addr, p_msc->ep_in) )
|
|
||||||
{
|
{
|
||||||
// clear stall TODO abstract clear stall function
|
.bmRequestType_bit =
|
||||||
request = (tusb_control_request_t) {
|
{
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_ENDPOINT, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_OUT },
|
.recipient = TUSB_REQ_RCPT_INTERFACE,
|
||||||
.bRequest = TUSB_REQ_CLEAR_FEATURE,
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
.wValue = 0,
|
.direction = TUSB_DIR_IN
|
||||||
.wIndex = p_msc->ep_in,
|
},
|
||||||
.wLength = 0
|
.bRequest = MSC_REQ_GET_MAX_LUN,
|
||||||
};
|
.wValue = 0,
|
||||||
|
.wIndex = itf_num,
|
||||||
TU_ASSERT(usbh_control_xfer( dev_addr, &request, NULL ));
|
.wLength = 1
|
||||||
|
};
|
||||||
hcd_edpt_clear_stall(dev_addr, p_msc->ep_in);
|
TU_ASSERT(tuh_control_xfer(dev_addr, &request, &p_msc->max_lun, config_get_maxlun_complete));
|
||||||
TU_ASSERT( osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT) ); // wait for SCSI status
|
|
||||||
|
|
||||||
//------------- SCSI Request Sense -------------//
|
|
||||||
(void) tuh_msc_request_sense(dev_addr, 0, msch_buffer);
|
|
||||||
TU_ASSERT(osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT));
|
|
||||||
|
|
||||||
//------------- Re-read SCSI Read Capactity -------------//
|
|
||||||
tusbh_msc_read_capacity10(dev_addr, 0, msch_buffer);
|
|
||||||
TU_ASSERT(osal_semaphore_wait(msch_sem_hdl, SCSI_XFER_TIMEOUT));
|
|
||||||
}
|
|
||||||
|
|
||||||
p_msc->last_lba = tu_ntohl( ((scsi_read_capacity10_resp_t*)msch_buffer)->last_lba );
|
|
||||||
p_msc->block_size = (uint16_t) tu_ntohl( ((scsi_read_capacity10_resp_t*)msch_buffer)->block_size );
|
|
||||||
|
|
||||||
p_msc->is_initialized = true;
|
|
||||||
|
|
||||||
tuh_msc_mounted_cb(dev_addr);
|
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void msch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
static bool config_get_maxlun_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
|
||||||
{
|
{
|
||||||
msch_interface_t* p_msc = &msch_data[dev_addr-1];
|
(void) request;
|
||||||
if ( ep_addr == p_msc->ep_in )
|
|
||||||
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
|
|
||||||
|
// STALL means zero
|
||||||
|
p_msc->max_lun = (XFER_RESULT_SUCCESS == result) ? msch_buffer[0] : 0;
|
||||||
|
p_msc->max_lun++; // MAX LUN is minus 1 by specs
|
||||||
|
|
||||||
|
// TODO multiple LUN support
|
||||||
|
TU_LOG2("SCSI Test Unit Ready\r\n");
|
||||||
|
tuh_msc_test_unit_ready(dev_addr, 0, config_test_unit_ready_complete);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
|
||||||
|
{
|
||||||
|
if (csw->status == 0)
|
||||||
{
|
{
|
||||||
if (p_msc->is_initialized)
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
||||||
{
|
|
||||||
tuh_msc_isr(dev_addr, event, xferred_bytes);
|
usbh_driver_set_config_complete(dev_addr, p_msc->itf_num);
|
||||||
}else
|
|
||||||
{ // still initializing under open subtask
|
// Unit is ready, Enumeration is complete
|
||||||
osal_semaphore_post(msch_sem_hdl, true);
|
p_msc->mounted = true;
|
||||||
}
|
tuh_msc_mounted_cb(dev_addr);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
// Note: During enumeration, some device fails Test Unit Ready and require a few retries
|
||||||
|
// with Request Sense to start working !!
|
||||||
|
// TODO limit number of retries
|
||||||
|
TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, msch_buffer, config_request_sense_complete));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void msch_close(uint8_t dev_addr)
|
static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
|
||||||
{
|
{
|
||||||
tu_memclr(&msch_data[dev_addr-1], sizeof(msch_interface_t));
|
TU_ASSERT(csw->status == 0);
|
||||||
osal_semaphore_reset(msch_sem_hdl);
|
TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete));
|
||||||
|
return true;
|
||||||
tuh_msc_unmounted_cb(dev_addr); // invoke Application Callback
|
|
||||||
}
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
|
||||||
// INTERNAL & HELPER
|
|
||||||
//--------------------------------------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -40,15 +40,16 @@
|
|||||||
* \defgroup MSC_Host Host
|
* \defgroup MSC_Host Host
|
||||||
* The interface API includes status checking function, data transferring function and callback functions
|
* The interface API includes status checking function, data transferring function and callback functions
|
||||||
* @{ */
|
* @{ */
|
||||||
|
|
||||||
|
typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// MASS STORAGE Application API
|
// Application API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
/** \brief Check if device supports MassStorage interface or not
|
|
||||||
* \param[in] dev_addr device address
|
// Check if device supports MassStorage interface.
|
||||||
* \retval true if device supports
|
// This function true after tuh_msc_mounted_cb() and false after tuh_msc_unmounted_cb()
|
||||||
* \retval false if device does not support or is not mounted
|
bool tuh_msc_mounted(uint8_t dev_addr);
|
||||||
*/
|
|
||||||
bool tuh_msc_is_mounted(uint8_t dev_addr);
|
|
||||||
|
|
||||||
/** \brief Check if the interface is currently busy or not
|
/** \brief Check if the interface is currently busy or not
|
||||||
* \param[in] dev_addr device address
|
* \param[in] dev_addr device address
|
||||||
@ -60,35 +61,27 @@ bool tuh_msc_is_mounted(uint8_t dev_addr);
|
|||||||
*/
|
*/
|
||||||
bool tuh_msc_is_busy(uint8_t dev_addr);
|
bool tuh_msc_is_busy(uint8_t dev_addr);
|
||||||
|
|
||||||
/** \brief Get SCSI vendor's name of MassStorage device
|
// Get Max Lun
|
||||||
* \param[in] dev_addr device address
|
uint8_t tuh_msc_get_maxlun(uint8_t dev_addr);
|
||||||
* \return pointer to vendor's name or NULL if specified device does not support MassStorage
|
|
||||||
* \note SCSI vendor's name is 8-byte length field in \ref scsi_inquiry_data_t. During enumeration, the stack has already
|
|
||||||
* retrieved (via SCSI INQUIRY) and store this information internally. There is no need for application to re-send SCSI INQUIRY
|
|
||||||
* command or allocate buffer for this.
|
|
||||||
*/
|
|
||||||
uint8_t const* tuh_msc_get_vendor_name(uint8_t dev_addr);
|
|
||||||
|
|
||||||
/** \brief Get SCSI product's name of MassStorage device
|
// Carry out a full SCSI command (cbw, data, csw) in non-blocking manner.
|
||||||
* \param[in] dev_addr device address
|
// `complete_cb` callback is invoked when SCSI op is complete.
|
||||||
* \return pointer to product's name or NULL if specified device does not support MassStorage
|
// return true if success, false if there is already pending operation.
|
||||||
* \note SCSI product's name is 16-byte length field in \ref scsi_inquiry_data_t. During enumeration, the stack has already
|
bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb);
|
||||||
* retrieved (via SCSI INQUIRY) and store this information internally. There is no need for application to re-send SCSI INQUIRY
|
|
||||||
* command or allocate buffer for this.
|
|
||||||
*/
|
|
||||||
uint8_t const* tuh_msc_get_product_name(uint8_t dev_addr);
|
|
||||||
|
|
||||||
/** \brief Get SCSI Capacity of MassStorage device
|
// Carry out SCSI INQUIRY command in non-blocking manner.
|
||||||
* \param[in] dev_addr device address
|
bool tuh_msc_scsi_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb);
|
||||||
* \param[out] p_last_lba Last Logical Block Address of device
|
|
||||||
* \param[out] p_block_size Block Size of device in bytes
|
|
||||||
* \retval pointer to product's name or NULL if specified device does not support MassStorage
|
|
||||||
* \note MassStorage's capacity can be computed by last LBA x block size (in bytes). During enumeration, the stack has already
|
|
||||||
* retrieved (via SCSI READ CAPACITY 10) and store this information internally. There is no need for application
|
|
||||||
* to re-send SCSI READ CAPACITY 10 command
|
|
||||||
*/
|
|
||||||
tusb_error_t tuh_msc_get_capacity(uint8_t dev_addr, uint32_t* p_last_lba, uint32_t* p_block_size);
|
|
||||||
|
|
||||||
|
// Carry out SCSI REQUEST SENSE (10) command in non-blocking manner.
|
||||||
|
bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb);
|
||||||
|
|
||||||
|
// Carry out SCSI REQUEST SENSE (10) command in non-blocking manner.
|
||||||
|
bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb);
|
||||||
|
|
||||||
|
// Carry out SCSI READ CAPACITY (10) command in non-blocking manner.
|
||||||
|
bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb);
|
||||||
|
|
||||||
|
#if 0
|
||||||
/** \brief Perform SCSI READ 10 command to read data from MassStorage device
|
/** \brief Perform SCSI READ 10 command to read data from MassStorage device
|
||||||
* \param[in] dev_addr device address
|
* \param[in] dev_addr device address
|
||||||
* \param[in] lun Targeted Logical Unit
|
* \param[in] lun Targeted Logical Unit
|
||||||
@ -116,84 +109,24 @@ tusb_error_t tuh_msc_read10 (uint8_t dev_addr, uint8_t lun, void * p_buffer, uin
|
|||||||
* \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the interface's callback function
|
* \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the interface's callback function
|
||||||
*/
|
*/
|
||||||
tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffer, uint32_t lba, uint16_t block_count);
|
tusb_error_t tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * p_buffer, uint32_t lba, uint16_t block_count);
|
||||||
|
#endif
|
||||||
/** \brief Perform SCSI REQUEST SENSE command, used to retrieve sense data from MassStorage device
|
|
||||||
* \param[in] dev_addr device address
|
|
||||||
* \param[in] lun Targeted Logical Unit
|
|
||||||
* \param[in] p_data Buffer to store response's data from device. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
|
|
||||||
* \retval TUSB_ERROR_NONE on success
|
|
||||||
* \retval TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
|
|
||||||
* \retval TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
|
|
||||||
* \retval TUSB_ERROR_INVALID_PARA if input parameters are not correct
|
|
||||||
* \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the interface's callback function
|
|
||||||
*/
|
|
||||||
tusb_error_t tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, uint8_t *p_data);
|
|
||||||
|
|
||||||
/** \brief Perform SCSI TEST UNIT READY command to test if MassStorage device is ready
|
|
||||||
* \param[in] dev_addr device address
|
|
||||||
* \param[in] lun Targeted Logical Unit
|
|
||||||
* \retval TUSB_ERROR_NONE on success
|
|
||||||
* \retval TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
|
|
||||||
* \retval TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
|
|
||||||
* \retval TUSB_ERROR_INVALID_PARA if input parameters are not correct
|
|
||||||
* \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the interface's callback function
|
|
||||||
*/
|
|
||||||
tusb_error_t tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, msc_csw_t * p_csw); // TODO to be refractor
|
|
||||||
|
|
||||||
//tusb_error_t tusbh_msc_scsi_send(uint8_t dev_addr, uint8_t lun, bool is_direction_in,
|
|
||||||
// uint8_t const * p_command, uint8_t cmd_len,
|
|
||||||
// uint8_t * p_response, uint32_t resp_len);
|
|
||||||
|
|
||||||
//------------- Application Callback -------------//
|
//------------- Application Callback -------------//
|
||||||
/** \brief Callback function that will be invoked when a device with MassStorage interface is mounted
|
|
||||||
* \param[in] dev_addr Address of newly mounted device
|
// Invoked when a device with MassStorage interface is mounted
|
||||||
* \note This callback should be used by Application to set-up interface-related data
|
|
||||||
*/
|
|
||||||
void tuh_msc_mounted_cb(uint8_t dev_addr);
|
void tuh_msc_mounted_cb(uint8_t dev_addr);
|
||||||
|
|
||||||
/** \brief Callback function that will be invoked when a device with MassStorage interface is unmounted
|
// Invoked when a device with MassStorage interface is unmounted
|
||||||
* \param[in] dev_addr Address of newly unmounted device
|
|
||||||
* \note This callback should be used by Application to tear-down interface-related data
|
|
||||||
*/
|
|
||||||
void tuh_msc_unmounted_cb(uint8_t dev_addr);
|
void tuh_msc_unmounted_cb(uint8_t dev_addr);
|
||||||
|
|
||||||
/** \brief Callback function that is invoked when an transferring event occurred
|
|
||||||
* \param[in] dev_addr Address of device
|
|
||||||
* \param[in] event an value from \ref xfer_result_t
|
|
||||||
* \param[in] xferred_bytes Number of bytes transferred via USB bus
|
|
||||||
* \note event can be one of following
|
|
||||||
* - XFER_RESULT_SUCCESS : previously scheduled transfer completes successfully.
|
|
||||||
* - XFER_RESULT_FAILED : previously scheduled transfer encountered a transaction error.
|
|
||||||
* - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device.
|
|
||||||
* \note
|
|
||||||
*/
|
|
||||||
void tuh_msc_isr(uint8_t dev_addr, xfer_result_t event, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Internal Class Driver API
|
// Internal Class Driver API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t itf_num;
|
|
||||||
uint8_t ep_in;
|
|
||||||
uint8_t ep_out;
|
|
||||||
|
|
||||||
uint8_t max_lun;
|
|
||||||
uint16_t block_size;
|
|
||||||
uint32_t last_lba; // last logical block address
|
|
||||||
|
|
||||||
volatile bool is_initialized;
|
|
||||||
uint8_t vendor_id[8];
|
|
||||||
uint8_t product_id[16];
|
|
||||||
|
|
||||||
msc_cbw_t cbw;
|
|
||||||
msc_csw_t csw;
|
|
||||||
}msch_interface_t;
|
|
||||||
|
|
||||||
void msch_init(void);
|
void msch_init(void);
|
||||||
bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
|
bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
|
||||||
void msch_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool msch_set_config(uint8_t dev_addr, uint8_t itf_num);
|
||||||
|
bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
void msch_close(uint8_t dev_addr);
|
void msch_close(uint8_t dev_addr);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -220,26 +220,6 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
|
|||||||
return drv_len;
|
return drv_len;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when class request DATA stage is finished.
|
|
||||||
// return false to stall control endpoint (e.g Host send nonsense DATA)
|
|
||||||
bool netd_control_complete(uint8_t rhport, tusb_control_request_t const * request)
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
|
|
||||||
// Handle RNDIS class control OUT only
|
|
||||||
if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS &&
|
|
||||||
request->bmRequestType_bit.direction == TUSB_DIR_OUT &&
|
|
||||||
_netd_itf.itf_num == request->wIndex)
|
|
||||||
{
|
|
||||||
if ( !_netd_itf.ecm_mode )
|
|
||||||
{
|
|
||||||
rndis_class_set_handler(notify.rndis_buf, request->wLength);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ecm_report(bool nc)
|
static void ecm_report(bool nc)
|
||||||
{
|
{
|
||||||
notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc;
|
notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc;
|
||||||
@ -247,99 +227,116 @@ static void ecm_report(bool nc)
|
|||||||
netd_report((uint8_t *)¬ify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf));
|
netd_report((uint8_t *)¬ify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf));
|
||||||
}
|
}
|
||||||
|
|
||||||
// Handle class control request
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
// return false to stall control endpoint (e.g unsupported request)
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
bool netd_control_request(uint8_t rhport, tusb_control_request_t const * request)
|
bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
switch ( request->bmRequestType_bit.type )
|
if ( stage == CONTROL_STAGE_SETUP )
|
||||||
{
|
{
|
||||||
case TUSB_REQ_TYPE_STANDARD:
|
switch ( request->bmRequestType_bit.type )
|
||||||
switch ( request->bRequest )
|
{
|
||||||
{
|
case TUSB_REQ_TYPE_STANDARD:
|
||||||
case TUSB_REQ_GET_INTERFACE:
|
switch ( request->bRequest )
|
||||||
{
|
{
|
||||||
uint8_t const req_itfnum = (uint8_t) request->wIndex;
|
case TUSB_REQ_GET_INTERFACE:
|
||||||
TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum);
|
|
||||||
|
|
||||||
tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case TUSB_REQ_SET_INTERFACE:
|
|
||||||
{
|
|
||||||
uint8_t const req_itfnum = (uint8_t) request->wIndex;
|
|
||||||
uint8_t const req_alt = (uint8_t) request->wValue;
|
|
||||||
|
|
||||||
// Only valid for Data Interface with Alternate is either 0 or 1
|
|
||||||
TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2);
|
|
||||||
|
|
||||||
// ACM-ECM only: qequest to enable/disable network activities
|
|
||||||
TU_VERIFY(_netd_itf.ecm_mode);
|
|
||||||
|
|
||||||
_netd_itf.itf_data_alt = req_alt;
|
|
||||||
|
|
||||||
if ( _netd_itf.itf_data_alt )
|
|
||||||
{
|
{
|
||||||
// TODO since we don't actually close endpoint
|
uint8_t const req_itfnum = (uint8_t) request->wIndex;
|
||||||
// hack here to not re-open it
|
TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum);
|
||||||
if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 )
|
|
||||||
{
|
|
||||||
TU_ASSERT(_netd_itf.ecm_desc_epdata);
|
|
||||||
TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) );
|
|
||||||
|
|
||||||
// TODO should be merge with RNDIS's after endpoint opened
|
tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1);
|
||||||
// Also should have opposite callback for application to disable network !!
|
|
||||||
tud_network_init_cb();
|
|
||||||
can_xmit = true; // we are ready to transmit a packet
|
|
||||||
tud_network_recv_renew(); // prepare for incoming packets
|
|
||||||
}
|
|
||||||
}else
|
|
||||||
{
|
|
||||||
// TODO close the endpoint pair
|
|
||||||
// For now pretend that we did, this should have no harm since host won't try to
|
|
||||||
// communicate with the endpoints again
|
|
||||||
// _netd_itf.ep_in = _netd_itf.ep_out = 0
|
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
tud_control_status(rhport, request);
|
case TUSB_REQ_SET_INTERFACE:
|
||||||
|
{
|
||||||
|
uint8_t const req_itfnum = (uint8_t) request->wIndex;
|
||||||
|
uint8_t const req_alt = (uint8_t) request->wValue;
|
||||||
|
|
||||||
|
// Only valid for Data Interface with Alternate is either 0 or 1
|
||||||
|
TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2);
|
||||||
|
|
||||||
|
// ACM-ECM only: qequest to enable/disable network activities
|
||||||
|
TU_VERIFY(_netd_itf.ecm_mode);
|
||||||
|
|
||||||
|
_netd_itf.itf_data_alt = req_alt;
|
||||||
|
|
||||||
|
if ( _netd_itf.itf_data_alt )
|
||||||
|
{
|
||||||
|
// TODO since we don't actually close endpoint
|
||||||
|
// hack here to not re-open it
|
||||||
|
if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 )
|
||||||
|
{
|
||||||
|
TU_ASSERT(_netd_itf.ecm_desc_epdata);
|
||||||
|
TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) );
|
||||||
|
|
||||||
|
// TODO should be merge with RNDIS's after endpoint opened
|
||||||
|
// Also should have opposite callback for application to disable network !!
|
||||||
|
tud_network_init_cb();
|
||||||
|
can_xmit = true; // we are ready to transmit a packet
|
||||||
|
tud_network_recv_renew(); // prepare for incoming packets
|
||||||
|
}
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
// TODO close the endpoint pair
|
||||||
|
// For now pretend that we did, this should have no harm since host won't try to
|
||||||
|
// communicate with the endpoints again
|
||||||
|
// _netd_itf.ep_in = _netd_itf.ep_out = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
tud_control_status(rhport, request);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
// unsupported request
|
||||||
|
default: return false;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
// unsupported request
|
case TUSB_REQ_TYPE_CLASS:
|
||||||
default: return false;
|
TU_VERIFY (_netd_itf.itf_num == request->wIndex);
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case TUSB_REQ_TYPE_CLASS:
|
if (_netd_itf.ecm_mode)
|
||||||
TU_VERIFY (_netd_itf.itf_num == request->wIndex);
|
|
||||||
|
|
||||||
if (_netd_itf.ecm_mode)
|
|
||||||
{
|
|
||||||
/* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */
|
|
||||||
if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest)
|
|
||||||
{
|
{
|
||||||
tud_control_xfer(rhport, request, NULL, 0);
|
/* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */
|
||||||
ecm_report(true);
|
if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest)
|
||||||
}
|
{
|
||||||
}
|
tud_control_xfer(rhport, request, NULL, 0);
|
||||||
else
|
ecm_report(true);
|
||||||
{
|
}
|
||||||
if (request->bmRequestType_bit.direction == TUSB_DIR_IN)
|
|
||||||
{
|
|
||||||
rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf);
|
|
||||||
uint32_t msglen = tu_le32toh(rndis_msg->MessageLength);
|
|
||||||
TU_ASSERT(msglen <= sizeof(notify.rndis_buf));
|
|
||||||
tud_control_xfer(rhport, request, notify.rndis_buf, msglen);
|
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf));
|
if (request->bmRequestType_bit.direction == TUSB_DIR_IN)
|
||||||
|
{
|
||||||
|
rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf);
|
||||||
|
uint32_t msglen = tu_le32toh(rndis_msg->MessageLength);
|
||||||
|
TU_ASSERT(msglen <= sizeof(notify.rndis_buf));
|
||||||
|
tud_control_xfer(rhport, request, notify.rndis_buf, msglen);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
break;
|
||||||
break;
|
|
||||||
|
|
||||||
// unsupported request
|
// unsupported request
|
||||||
default: return false;
|
default: return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if ( stage == CONTROL_STAGE_DATA )
|
||||||
|
{
|
||||||
|
// Handle RNDIS class control OUT only
|
||||||
|
if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS &&
|
||||||
|
request->bmRequestType_bit.direction == TUSB_DIR_OUT &&
|
||||||
|
_netd_itf.itf_num == request->wIndex)
|
||||||
|
{
|
||||||
|
if ( !_netd_itf.ecm_mode )
|
||||||
|
{
|
||||||
|
rndis_class_set_handler(notify.rndis_buf, request->wLength);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
|
@ -73,13 +73,12 @@ void tud_network_xmit(void *ref, uint16_t arg);
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// INTERNAL USBD-CLASS DRIVER API
|
// INTERNAL USBD-CLASS DRIVER API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void netd_init (void);
|
void netd_init (void);
|
||||||
void netd_reset (uint8_t rhport);
|
void netd_reset (uint8_t rhport);
|
||||||
uint16_t netd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t netd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
bool netd_control_request (uint8_t rhport, tusb_control_request_t const * request);
|
bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool netd_control_complete (uint8_t rhport, tusb_control_request_t const * request);
|
bool netd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
bool netd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
void netd_report (uint8_t *buf, uint16_t len);
|
||||||
void netd_report (uint8_t *buf, uint16_t len);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -575,7 +575,13 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool usbtmcd_control_request_cb(uint8_t rhport, tusb_control_request_t const * request) {
|
// Invoked when a control transfer occurred on an interface of this class
|
||||||
|
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
|
||||||
|
// return false to stall control endpoint (e.g unsupported request)
|
||||||
|
bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
|
||||||
|
{
|
||||||
|
// nothing to do with DATA and ACK stage
|
||||||
|
if ( stage != CONTROL_STAGE_SETUP ) return true;
|
||||||
|
|
||||||
uint8_t tmcStatusCode = USBTMC_STATUS_FAILED;
|
uint8_t tmcStatusCode = USBTMC_STATUS_FAILED;
|
||||||
#if (CFG_TUD_USBTMC_ENABLE_488)
|
#if (CFG_TUD_USBTMC_ENABLE_488)
|
||||||
@ -855,13 +861,4 @@ bool usbtmcd_control_request_cb(uint8_t rhport, tusb_control_request_t const * r
|
|||||||
TU_VERIFY(false);
|
TU_VERIFY(false);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool usbtmcd_control_complete_cb(uint8_t rhport, tusb_control_request_t const * request)
|
|
||||||
{
|
|
||||||
(void)rhport;
|
|
||||||
//------------- Class Specific Request -------------//
|
|
||||||
TU_ASSERT (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CFG_TUD_TSMC */
|
#endif /* CFG_TUD_TSMC */
|
||||||
|
@ -111,8 +111,7 @@ bool tud_usbtmc_start_bus_read(void);
|
|||||||
uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
|
||||||
void usbtmcd_reset_cb(uint8_t rhport);
|
void usbtmcd_reset_cb(uint8_t rhport);
|
||||||
bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
bool usbtmcd_control_request_cb(uint8_t rhport, tusb_control_request_t const * request);
|
bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool usbtmcd_control_complete_cb(uint8_t rhport, tusb_control_request_t const * request);
|
|
||||||
void usbtmcd_init_cb(void);
|
void usbtmcd_init_cb(void);
|
||||||
|
|
||||||
/************************************************************
|
/************************************************************
|
||||||
|
@ -1,871 +0,0 @@
|
|||||||
/*-
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*
|
|
||||||
* Copyright (c) 1991, 1993
|
|
||||||
* The Regents of the University of California. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of the University nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
||||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
||||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
||||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
||||||
* SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* @(#)queue.h 8.5 (Berkeley) 8/20/94
|
|
||||||
* $FreeBSD$
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _SYS_QUEUE_H_
|
|
||||||
#define _SYS_QUEUE_H_
|
|
||||||
|
|
||||||
#include <sys/cdefs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This file defines four types of data structures: singly-linked lists,
|
|
||||||
* singly-linked tail queues, lists and tail queues.
|
|
||||||
*
|
|
||||||
* A singly-linked list is headed by a single forward pointer. The elements
|
|
||||||
* are singly linked for minimum space and pointer manipulation overhead at
|
|
||||||
* the expense of O(n) removal for arbitrary elements. New elements can be
|
|
||||||
* added to the list after an existing element or at the head of the list.
|
|
||||||
* Elements being removed from the head of the list should use the explicit
|
|
||||||
* macro for this purpose for optimum efficiency. A singly-linked list may
|
|
||||||
* only be traversed in the forward direction. Singly-linked lists are ideal
|
|
||||||
* for applications with large datasets and few or no removals or for
|
|
||||||
* implementing a LIFO queue.
|
|
||||||
*
|
|
||||||
* A singly-linked tail queue is headed by a pair of pointers, one to the
|
|
||||||
* head of the list and the other to the tail of the list. The elements are
|
|
||||||
* singly linked for minimum space and pointer manipulation overhead at the
|
|
||||||
* expense of O(n) removal for arbitrary elements. New elements can be added
|
|
||||||
* to the list after an existing element, at the head of the list, or at the
|
|
||||||
* end of the list. Elements being removed from the head of the tail queue
|
|
||||||
* should use the explicit macro for this purpose for optimum efficiency.
|
|
||||||
* A singly-linked tail queue may only be traversed in the forward direction.
|
|
||||||
* Singly-linked tail queues are ideal for applications with large datasets
|
|
||||||
* and few or no removals or for implementing a FIFO queue.
|
|
||||||
*
|
|
||||||
* A list is headed by a single forward pointer (or an array of forward
|
|
||||||
* pointers for a hash table header). The elements are doubly linked
|
|
||||||
* so that an arbitrary element can be removed without a need to
|
|
||||||
* traverse the list. New elements can be added to the list before
|
|
||||||
* or after an existing element or at the head of the list. A list
|
|
||||||
* may be traversed in either direction.
|
|
||||||
*
|
|
||||||
* A tail queue is headed by a pair of pointers, one to the head of the
|
|
||||||
* list and the other to the tail of the list. The elements are doubly
|
|
||||||
* linked so that an arbitrary element can be removed without a need to
|
|
||||||
* traverse the list. New elements can be added to the list before or
|
|
||||||
* after an existing element, at the head of the list, or at the end of
|
|
||||||
* the list. A tail queue may be traversed in either direction.
|
|
||||||
*
|
|
||||||
* For details on the use of these macros, see the queue(3) manual page.
|
|
||||||
*
|
|
||||||
* Below is a summary of implemented functions where:
|
|
||||||
* + means the macro is available
|
|
||||||
* - means the macro is not available
|
|
||||||
* s means the macro is available but is slow (runs in O(n) time)
|
|
||||||
*
|
|
||||||
* SLIST LIST STAILQ TAILQ
|
|
||||||
* _HEAD + + + +
|
|
||||||
* _CLASS_HEAD + + + +
|
|
||||||
* _HEAD_INITIALIZER + + + +
|
|
||||||
* _ENTRY + + + +
|
|
||||||
* _CLASS_ENTRY + + + +
|
|
||||||
* _INIT + + + +
|
|
||||||
* _EMPTY + + + +
|
|
||||||
* _FIRST + + + +
|
|
||||||
* _NEXT + + + +
|
|
||||||
* _PREV - + - +
|
|
||||||
* _LAST - - + +
|
|
||||||
* _LAST_FAST - - - +
|
|
||||||
* _FOREACH + + + +
|
|
||||||
* _FOREACH_FROM + + + +
|
|
||||||
* _FOREACH_SAFE + + + +
|
|
||||||
* _FOREACH_FROM_SAFE + + + +
|
|
||||||
* _FOREACH_REVERSE - - - +
|
|
||||||
* _FOREACH_REVERSE_FROM - - - +
|
|
||||||
* _FOREACH_REVERSE_SAFE - - - +
|
|
||||||
* _FOREACH_REVERSE_FROM_SAFE - - - +
|
|
||||||
* _INSERT_HEAD + + + +
|
|
||||||
* _INSERT_BEFORE - + - +
|
|
||||||
* _INSERT_AFTER + + + +
|
|
||||||
* _INSERT_TAIL - - + +
|
|
||||||
* _CONCAT s s + +
|
|
||||||
* _REMOVE_AFTER + - + -
|
|
||||||
* _REMOVE_HEAD + - + -
|
|
||||||
* _REMOVE s + s +
|
|
||||||
* _SWAP + + + +
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#ifdef QUEUE_MACRO_DEBUG
|
|
||||||
#warn Use QUEUE_MACRO_DEBUG_TRACE and/or QUEUE_MACRO_DEBUG_TRASH
|
|
||||||
#define QUEUE_MACRO_DEBUG_TRACE
|
|
||||||
#define QUEUE_MACRO_DEBUG_TRASH
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef QUEUE_MACRO_DEBUG_TRACE
|
|
||||||
/* Store the last 2 places the queue element or head was altered */
|
|
||||||
struct qm_trace {
|
|
||||||
unsigned long lastline;
|
|
||||||
unsigned long prevline;
|
|
||||||
const char *lastfile;
|
|
||||||
const char *prevfile;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define TRACEBUF struct qm_trace trace;
|
|
||||||
#define TRACEBUF_INITIALIZER { __LINE__, 0, __FILE__, NULL } ,
|
|
||||||
|
|
||||||
#define QMD_TRACE_HEAD(head) do { \
|
|
||||||
(head)->trace.prevline = (head)->trace.lastline; \
|
|
||||||
(head)->trace.prevfile = (head)->trace.lastfile; \
|
|
||||||
(head)->trace.lastline = __LINE__; \
|
|
||||||
(head)->trace.lastfile = __FILE__; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define QMD_TRACE_ELEM(elem) do { \
|
|
||||||
(elem)->trace.prevline = (elem)->trace.lastline; \
|
|
||||||
(elem)->trace.prevfile = (elem)->trace.lastfile; \
|
|
||||||
(elem)->trace.lastline = __LINE__; \
|
|
||||||
(elem)->trace.lastfile = __FILE__; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#else /* !QUEUE_MACRO_DEBUG_TRACE */
|
|
||||||
#define QMD_TRACE_ELEM(elem)
|
|
||||||
#define QMD_TRACE_HEAD(head)
|
|
||||||
#define TRACEBUF
|
|
||||||
#define TRACEBUF_INITIALIZER
|
|
||||||
#endif /* QUEUE_MACRO_DEBUG_TRACE */
|
|
||||||
|
|
||||||
#ifdef QUEUE_MACRO_DEBUG_TRASH
|
|
||||||
#define TRASHIT(x) do {(x) = (void *)-1;} while (0)
|
|
||||||
#define QMD_IS_TRASHED(x) ((x) == (void *)(intptr_t)-1)
|
|
||||||
#else /* !QUEUE_MACRO_DEBUG_TRASH */
|
|
||||||
#define TRASHIT(x)
|
|
||||||
#define QMD_IS_TRASHED(x) 0
|
|
||||||
#endif /* QUEUE_MACRO_DEBUG_TRASH */
|
|
||||||
|
|
||||||
#if defined(QUEUE_MACRO_DEBUG_TRACE) || defined(QUEUE_MACRO_DEBUG_TRASH)
|
|
||||||
#define QMD_SAVELINK(name, link) void **name = (void *)&(link)
|
|
||||||
#else /* !QUEUE_MACRO_DEBUG_TRACE && !QUEUE_MACRO_DEBUG_TRASH */
|
|
||||||
#define QMD_SAVELINK(name, link)
|
|
||||||
#endif /* QUEUE_MACRO_DEBUG_TRACE || QUEUE_MACRO_DEBUG_TRASH */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
/*
|
|
||||||
* In C++ there can be structure lists and class lists:
|
|
||||||
*/
|
|
||||||
#define QUEUE_TYPEOF(type) type
|
|
||||||
#else
|
|
||||||
#define QUEUE_TYPEOF(type) struct type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Singly-linked List declarations.
|
|
||||||
*/
|
|
||||||
#define SLIST_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
struct type *slh_first; /* first element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define SLIST_CLASS_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
class type *slh_first; /* first element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define SLIST_HEAD_INITIALIZER(head) \
|
|
||||||
{ NULL }
|
|
||||||
|
|
||||||
#define SLIST_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
struct type *sle_next; /* next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define SLIST_CLASS_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
class type *sle_next; /* next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Singly-linked List functions.
|
|
||||||
*/
|
|
||||||
#if (defined(_KERNEL) && defined(INVARIANTS))
|
|
||||||
#define QMD_SLIST_CHECK_PREVPTR(prevp, elm) do { \
|
|
||||||
if (*(prevp) != (elm)) \
|
|
||||||
panic("Bad prevptr *(%p) == %p != %p", \
|
|
||||||
(prevp), *(prevp), (elm)); \
|
|
||||||
} while (0)
|
|
||||||
#else
|
|
||||||
#define QMD_SLIST_CHECK_PREVPTR(prevp, elm)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define SLIST_CONCAT(head1, head2, type, field) do { \
|
|
||||||
QUEUE_TYPEOF(type) *curelm = SLIST_FIRST(head1); \
|
|
||||||
if (curelm == NULL) { \
|
|
||||||
if ((SLIST_FIRST(head1) = SLIST_FIRST(head2)) != NULL) \
|
|
||||||
SLIST_INIT(head2); \
|
|
||||||
} else if (SLIST_FIRST(head2) != NULL) { \
|
|
||||||
while (SLIST_NEXT(curelm, field) != NULL) \
|
|
||||||
curelm = SLIST_NEXT(curelm, field); \
|
|
||||||
SLIST_NEXT(curelm, field) = SLIST_FIRST(head2); \
|
|
||||||
SLIST_INIT(head2); \
|
|
||||||
} \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
|
|
||||||
|
|
||||||
#define SLIST_FIRST(head) ((head)->slh_first)
|
|
||||||
|
|
||||||
#define SLIST_FOREACH(var, head, field) \
|
|
||||||
for ((var) = SLIST_FIRST((head)); \
|
|
||||||
(var); \
|
|
||||||
(var) = SLIST_NEXT((var), field))
|
|
||||||
|
|
||||||
#define SLIST_FOREACH_FROM(var, head, field) \
|
|
||||||
for ((var) = ((var) ? (var) : SLIST_FIRST((head))); \
|
|
||||||
(var); \
|
|
||||||
(var) = SLIST_NEXT((var), field))
|
|
||||||
|
|
||||||
#define SLIST_FOREACH_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = SLIST_FIRST((head)); \
|
|
||||||
(var) && ((tvar) = SLIST_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define SLIST_FOREACH_FROM_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = ((var) ? (var) : SLIST_FIRST((head))); \
|
|
||||||
(var) && ((tvar) = SLIST_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \
|
|
||||||
for ((varp) = &SLIST_FIRST((head)); \
|
|
||||||
((var) = *(varp)) != NULL; \
|
|
||||||
(varp) = &SLIST_NEXT((var), field))
|
|
||||||
|
|
||||||
#define SLIST_INIT(head) do { \
|
|
||||||
SLIST_FIRST((head)) = NULL; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
|
|
||||||
SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
|
|
||||||
SLIST_NEXT((slistelm), field) = (elm); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_INSERT_HEAD(head, elm, field) do { \
|
|
||||||
SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
|
|
||||||
SLIST_FIRST((head)) = (elm); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
|
|
||||||
|
|
||||||
#define SLIST_REMOVE(head, elm, type, field) do { \
|
|
||||||
QMD_SAVELINK(oldnext, (elm)->field.sle_next); \
|
|
||||||
if (SLIST_FIRST((head)) == (elm)) { \
|
|
||||||
SLIST_REMOVE_HEAD((head), field); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
QUEUE_TYPEOF(type) *curelm = SLIST_FIRST(head); \
|
|
||||||
while (SLIST_NEXT(curelm, field) != (elm)) \
|
|
||||||
curelm = SLIST_NEXT(curelm, field); \
|
|
||||||
SLIST_REMOVE_AFTER(curelm, field); \
|
|
||||||
} \
|
|
||||||
TRASHIT(*oldnext); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_REMOVE_AFTER(elm, field) do { \
|
|
||||||
SLIST_NEXT(elm, field) = \
|
|
||||||
SLIST_NEXT(SLIST_NEXT(elm, field), field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_REMOVE_HEAD(head, field) do { \
|
|
||||||
SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_REMOVE_PREVPTR(prevp, elm, field) do { \
|
|
||||||
QMD_SLIST_CHECK_PREVPTR(prevp, elm); \
|
|
||||||
*(prevp) = SLIST_NEXT(elm, field); \
|
|
||||||
TRASHIT((elm)->field.sle_next); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define SLIST_SWAP(head1, head2, type) do { \
|
|
||||||
QUEUE_TYPEOF(type) *swap_first = SLIST_FIRST(head1); \
|
|
||||||
SLIST_FIRST(head1) = SLIST_FIRST(head2); \
|
|
||||||
SLIST_FIRST(head2) = swap_first; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Singly-linked Tail queue declarations.
|
|
||||||
*/
|
|
||||||
#define STAILQ_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
struct type *stqh_first;/* first element */ \
|
|
||||||
struct type **stqh_last;/* addr of last next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define STAILQ_CLASS_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
class type *stqh_first; /* first element */ \
|
|
||||||
class type **stqh_last; /* addr of last next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define STAILQ_HEAD_INITIALIZER(head) \
|
|
||||||
{ NULL, &(head).stqh_first }
|
|
||||||
|
|
||||||
#define STAILQ_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
struct type *stqe_next; /* next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define STAILQ_CLASS_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
class type *stqe_next; /* next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Singly-linked Tail queue functions.
|
|
||||||
*/
|
|
||||||
#define STAILQ_CONCAT(head1, head2) do { \
|
|
||||||
if (!STAILQ_EMPTY((head2))) { \
|
|
||||||
*(head1)->stqh_last = (head2)->stqh_first; \
|
|
||||||
(head1)->stqh_last = (head2)->stqh_last; \
|
|
||||||
STAILQ_INIT((head2)); \
|
|
||||||
} \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
|
|
||||||
|
|
||||||
#define STAILQ_FIRST(head) ((head)->stqh_first)
|
|
||||||
|
|
||||||
#define STAILQ_FOREACH(var, head, field) \
|
|
||||||
for((var) = STAILQ_FIRST((head)); \
|
|
||||||
(var); \
|
|
||||||
(var) = STAILQ_NEXT((var), field))
|
|
||||||
|
|
||||||
#define STAILQ_FOREACH_FROM(var, head, field) \
|
|
||||||
for ((var) = ((var) ? (var) : STAILQ_FIRST((head))); \
|
|
||||||
(var); \
|
|
||||||
(var) = STAILQ_NEXT((var), field))
|
|
||||||
|
|
||||||
#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = STAILQ_FIRST((head)); \
|
|
||||||
(var) && ((tvar) = STAILQ_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define STAILQ_FOREACH_FROM_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = ((var) ? (var) : STAILQ_FIRST((head))); \
|
|
||||||
(var) && ((tvar) = STAILQ_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define STAILQ_INIT(head) do { \
|
|
||||||
STAILQ_FIRST((head)) = NULL; \
|
|
||||||
(head)->stqh_last = &STAILQ_FIRST((head)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
|
|
||||||
if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
|
|
||||||
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
|
|
||||||
STAILQ_NEXT((tqelm), field) = (elm); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_INSERT_HEAD(head, elm, field) do { \
|
|
||||||
if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
|
|
||||||
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
|
|
||||||
STAILQ_FIRST((head)) = (elm); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_INSERT_TAIL(head, elm, field) do { \
|
|
||||||
STAILQ_NEXT((elm), field) = NULL; \
|
|
||||||
*(head)->stqh_last = (elm); \
|
|
||||||
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_LAST(head, type, field) \
|
|
||||||
(STAILQ_EMPTY((head)) ? NULL : \
|
|
||||||
__containerof((head)->stqh_last, \
|
|
||||||
QUEUE_TYPEOF(type), field.stqe_next))
|
|
||||||
|
|
||||||
#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
|
|
||||||
|
|
||||||
#define STAILQ_REMOVE(head, elm, type, field) do { \
|
|
||||||
QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \
|
|
||||||
if (STAILQ_FIRST((head)) == (elm)) { \
|
|
||||||
STAILQ_REMOVE_HEAD((head), field); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
QUEUE_TYPEOF(type) *curelm = STAILQ_FIRST(head); \
|
|
||||||
while (STAILQ_NEXT(curelm, field) != (elm)) \
|
|
||||||
curelm = STAILQ_NEXT(curelm, field); \
|
|
||||||
STAILQ_REMOVE_AFTER(head, curelm, field); \
|
|
||||||
} \
|
|
||||||
TRASHIT(*oldnext); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_REMOVE_AFTER(head, elm, field) do { \
|
|
||||||
if ((STAILQ_NEXT(elm, field) = \
|
|
||||||
STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \
|
|
||||||
(head)->stqh_last = &STAILQ_NEXT((elm), field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_REMOVE_HEAD(head, field) do { \
|
|
||||||
if ((STAILQ_FIRST((head)) = \
|
|
||||||
STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
|
|
||||||
(head)->stqh_last = &STAILQ_FIRST((head)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define STAILQ_SWAP(head1, head2, type) do { \
|
|
||||||
QUEUE_TYPEOF(type) *swap_first = STAILQ_FIRST(head1); \
|
|
||||||
QUEUE_TYPEOF(type) **swap_last = (head1)->stqh_last; \
|
|
||||||
STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \
|
|
||||||
(head1)->stqh_last = (head2)->stqh_last; \
|
|
||||||
STAILQ_FIRST(head2) = swap_first; \
|
|
||||||
(head2)->stqh_last = swap_last; \
|
|
||||||
if (STAILQ_EMPTY(head1)) \
|
|
||||||
(head1)->stqh_last = &STAILQ_FIRST(head1); \
|
|
||||||
if (STAILQ_EMPTY(head2)) \
|
|
||||||
(head2)->stqh_last = &STAILQ_FIRST(head2); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* List declarations.
|
|
||||||
*/
|
|
||||||
#define LIST_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
struct type *lh_first; /* first element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define LIST_CLASS_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
class type *lh_first; /* first element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define LIST_HEAD_INITIALIZER(head) \
|
|
||||||
{ NULL }
|
|
||||||
|
|
||||||
#define LIST_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
struct type *le_next; /* next element */ \
|
|
||||||
struct type **le_prev; /* address of previous next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define LIST_CLASS_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
class type *le_next; /* next element */ \
|
|
||||||
class type **le_prev; /* address of previous next element */ \
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* List functions.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (defined(_KERNEL) && defined(INVARIANTS))
|
|
||||||
/*
|
|
||||||
* QMD_LIST_CHECK_HEAD(LIST_HEAD *head, LIST_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* If the list is non-empty, validates that the first element of the list
|
|
||||||
* points back at 'head.'
|
|
||||||
*/
|
|
||||||
#define QMD_LIST_CHECK_HEAD(head, field) do { \
|
|
||||||
if (LIST_FIRST((head)) != NULL && \
|
|
||||||
LIST_FIRST((head))->field.le_prev != \
|
|
||||||
&LIST_FIRST((head))) \
|
|
||||||
panic("Bad list head %p first->prev != head", (head)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* QMD_LIST_CHECK_NEXT(TYPE *elm, LIST_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* If an element follows 'elm' in the list, validates that the next element
|
|
||||||
* points back at 'elm.'
|
|
||||||
*/
|
|
||||||
#define QMD_LIST_CHECK_NEXT(elm, field) do { \
|
|
||||||
if (LIST_NEXT((elm), field) != NULL && \
|
|
||||||
LIST_NEXT((elm), field)->field.le_prev != \
|
|
||||||
&((elm)->field.le_next)) \
|
|
||||||
panic("Bad link elm %p next->prev != elm", (elm)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* QMD_LIST_CHECK_PREV(TYPE *elm, LIST_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* Validates that the previous element (or head of the list) points to 'elm.'
|
|
||||||
*/
|
|
||||||
#define QMD_LIST_CHECK_PREV(elm, field) do { \
|
|
||||||
if (*(elm)->field.le_prev != (elm)) \
|
|
||||||
panic("Bad link elm %p prev->next != elm", (elm)); \
|
|
||||||
} while (0)
|
|
||||||
#else
|
|
||||||
#define QMD_LIST_CHECK_HEAD(head, field)
|
|
||||||
#define QMD_LIST_CHECK_NEXT(elm, field)
|
|
||||||
#define QMD_LIST_CHECK_PREV(elm, field)
|
|
||||||
#endif /* (_KERNEL && INVARIANTS) */
|
|
||||||
|
|
||||||
#define LIST_CONCAT(head1, head2, type, field) do { \
|
|
||||||
QUEUE_TYPEOF(type) *curelm = LIST_FIRST(head1); \
|
|
||||||
if (curelm == NULL) { \
|
|
||||||
if ((LIST_FIRST(head1) = LIST_FIRST(head2)) != NULL) { \
|
|
||||||
LIST_FIRST(head2)->field.le_prev = \
|
|
||||||
&LIST_FIRST((head1)); \
|
|
||||||
LIST_INIT(head2); \
|
|
||||||
} \
|
|
||||||
} else if (LIST_FIRST(head2) != NULL) { \
|
|
||||||
while (LIST_NEXT(curelm, field) != NULL) \
|
|
||||||
curelm = LIST_NEXT(curelm, field); \
|
|
||||||
LIST_NEXT(curelm, field) = LIST_FIRST(head2); \
|
|
||||||
LIST_FIRST(head2)->field.le_prev = &LIST_NEXT(curelm, field); \
|
|
||||||
LIST_INIT(head2); \
|
|
||||||
} \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define LIST_EMPTY(head) ((head)->lh_first == NULL)
|
|
||||||
|
|
||||||
#define LIST_FIRST(head) ((head)->lh_first)
|
|
||||||
|
|
||||||
#define LIST_FOREACH(var, head, field) \
|
|
||||||
for ((var) = LIST_FIRST((head)); \
|
|
||||||
(var); \
|
|
||||||
(var) = LIST_NEXT((var), field))
|
|
||||||
|
|
||||||
#define LIST_FOREACH_FROM(var, head, field) \
|
|
||||||
for ((var) = ((var) ? (var) : LIST_FIRST((head))); \
|
|
||||||
(var); \
|
|
||||||
(var) = LIST_NEXT((var), field))
|
|
||||||
|
|
||||||
#define LIST_FOREACH_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = LIST_FIRST((head)); \
|
|
||||||
(var) && ((tvar) = LIST_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define LIST_FOREACH_FROM_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = ((var) ? (var) : LIST_FIRST((head))); \
|
|
||||||
(var) && ((tvar) = LIST_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define LIST_INIT(head) do { \
|
|
||||||
LIST_FIRST((head)) = NULL; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define LIST_INSERT_AFTER(listelm, elm, field) do { \
|
|
||||||
QMD_LIST_CHECK_NEXT(listelm, field); \
|
|
||||||
if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
|
|
||||||
LIST_NEXT((listelm), field)->field.le_prev = \
|
|
||||||
&LIST_NEXT((elm), field); \
|
|
||||||
LIST_NEXT((listelm), field) = (elm); \
|
|
||||||
(elm)->field.le_prev = &LIST_NEXT((listelm), field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
|
|
||||||
QMD_LIST_CHECK_PREV(listelm, field); \
|
|
||||||
(elm)->field.le_prev = (listelm)->field.le_prev; \
|
|
||||||
LIST_NEXT((elm), field) = (listelm); \
|
|
||||||
*(listelm)->field.le_prev = (elm); \
|
|
||||||
(listelm)->field.le_prev = &LIST_NEXT((elm), field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define LIST_INSERT_HEAD(head, elm, field) do { \
|
|
||||||
QMD_LIST_CHECK_HEAD((head), field); \
|
|
||||||
if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
|
|
||||||
LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
|
|
||||||
LIST_FIRST((head)) = (elm); \
|
|
||||||
(elm)->field.le_prev = &LIST_FIRST((head)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define LIST_NEXT(elm, field) ((elm)->field.le_next)
|
|
||||||
|
|
||||||
#define LIST_PREV(elm, head, type, field) \
|
|
||||||
((elm)->field.le_prev == &LIST_FIRST((head)) ? NULL : \
|
|
||||||
__containerof((elm)->field.le_prev, \
|
|
||||||
QUEUE_TYPEOF(type), field.le_next))
|
|
||||||
|
|
||||||
#define LIST_REMOVE(elm, field) do { \
|
|
||||||
QMD_SAVELINK(oldnext, (elm)->field.le_next); \
|
|
||||||
QMD_SAVELINK(oldprev, (elm)->field.le_prev); \
|
|
||||||
QMD_LIST_CHECK_NEXT(elm, field); \
|
|
||||||
QMD_LIST_CHECK_PREV(elm, field); \
|
|
||||||
if (LIST_NEXT((elm), field) != NULL) \
|
|
||||||
LIST_NEXT((elm), field)->field.le_prev = \
|
|
||||||
(elm)->field.le_prev; \
|
|
||||||
*(elm)->field.le_prev = LIST_NEXT((elm), field); \
|
|
||||||
TRASHIT(*oldnext); \
|
|
||||||
TRASHIT(*oldprev); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define LIST_SWAP(head1, head2, type, field) do { \
|
|
||||||
QUEUE_TYPEOF(type) *swap_tmp = LIST_FIRST(head1); \
|
|
||||||
LIST_FIRST((head1)) = LIST_FIRST((head2)); \
|
|
||||||
LIST_FIRST((head2)) = swap_tmp; \
|
|
||||||
if ((swap_tmp = LIST_FIRST((head1))) != NULL) \
|
|
||||||
swap_tmp->field.le_prev = &LIST_FIRST((head1)); \
|
|
||||||
if ((swap_tmp = LIST_FIRST((head2))) != NULL) \
|
|
||||||
swap_tmp->field.le_prev = &LIST_FIRST((head2)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Tail queue declarations.
|
|
||||||
*/
|
|
||||||
#define TAILQ_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
struct type *tqh_first; /* first element */ \
|
|
||||||
struct type **tqh_last; /* addr of last next element */ \
|
|
||||||
TRACEBUF \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define TAILQ_CLASS_HEAD(name, type) \
|
|
||||||
struct name { \
|
|
||||||
class type *tqh_first; /* first element */ \
|
|
||||||
class type **tqh_last; /* addr of last next element */ \
|
|
||||||
TRACEBUF \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define TAILQ_HEAD_INITIALIZER(head) \
|
|
||||||
{ NULL, &(head).tqh_first, TRACEBUF_INITIALIZER }
|
|
||||||
|
|
||||||
#define TAILQ_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
struct type *tqe_next; /* next element */ \
|
|
||||||
struct type **tqe_prev; /* address of previous next element */ \
|
|
||||||
TRACEBUF \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define TAILQ_CLASS_ENTRY(type) \
|
|
||||||
struct { \
|
|
||||||
class type *tqe_next; /* next element */ \
|
|
||||||
class type **tqe_prev; /* address of previous next element */ \
|
|
||||||
TRACEBUF \
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Tail queue functions.
|
|
||||||
*/
|
|
||||||
#if (defined(_KERNEL) && defined(INVARIANTS))
|
|
||||||
/*
|
|
||||||
* QMD_TAILQ_CHECK_HEAD(TAILQ_HEAD *head, TAILQ_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* If the tailq is non-empty, validates that the first element of the tailq
|
|
||||||
* points back at 'head.'
|
|
||||||
*/
|
|
||||||
#define QMD_TAILQ_CHECK_HEAD(head, field) do { \
|
|
||||||
if (!TAILQ_EMPTY(head) && \
|
|
||||||
TAILQ_FIRST((head))->field.tqe_prev != \
|
|
||||||
&TAILQ_FIRST((head))) \
|
|
||||||
panic("Bad tailq head %p first->prev != head", (head)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* QMD_TAILQ_CHECK_TAIL(TAILQ_HEAD *head, TAILQ_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* Validates that the tail of the tailq is a pointer to pointer to NULL.
|
|
||||||
*/
|
|
||||||
#define QMD_TAILQ_CHECK_TAIL(head, field) do { \
|
|
||||||
if (*(head)->tqh_last != NULL) \
|
|
||||||
panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* QMD_TAILQ_CHECK_NEXT(TYPE *elm, TAILQ_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* If an element follows 'elm' in the tailq, validates that the next element
|
|
||||||
* points back at 'elm.'
|
|
||||||
*/
|
|
||||||
#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \
|
|
||||||
if (TAILQ_NEXT((elm), field) != NULL && \
|
|
||||||
TAILQ_NEXT((elm), field)->field.tqe_prev != \
|
|
||||||
&((elm)->field.tqe_next)) \
|
|
||||||
panic("Bad link elm %p next->prev != elm", (elm)); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* QMD_TAILQ_CHECK_PREV(TYPE *elm, TAILQ_ENTRY NAME)
|
|
||||||
*
|
|
||||||
* Validates that the previous element (or head of the tailq) points to 'elm.'
|
|
||||||
*/
|
|
||||||
#define QMD_TAILQ_CHECK_PREV(elm, field) do { \
|
|
||||||
if (*(elm)->field.tqe_prev != (elm)) \
|
|
||||||
panic("Bad link elm %p prev->next != elm", (elm)); \
|
|
||||||
} while (0)
|
|
||||||
#else
|
|
||||||
#define QMD_TAILQ_CHECK_HEAD(head, field)
|
|
||||||
#define QMD_TAILQ_CHECK_TAIL(head, headname)
|
|
||||||
#define QMD_TAILQ_CHECK_NEXT(elm, field)
|
|
||||||
#define QMD_TAILQ_CHECK_PREV(elm, field)
|
|
||||||
#endif /* (_KERNEL && INVARIANTS) */
|
|
||||||
|
|
||||||
#define TAILQ_CONCAT(head1, head2, field) do { \
|
|
||||||
if (!TAILQ_EMPTY(head2)) { \
|
|
||||||
*(head1)->tqh_last = (head2)->tqh_first; \
|
|
||||||
(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
|
|
||||||
(head1)->tqh_last = (head2)->tqh_last; \
|
|
||||||
TAILQ_INIT((head2)); \
|
|
||||||
QMD_TRACE_HEAD(head1); \
|
|
||||||
QMD_TRACE_HEAD(head2); \
|
|
||||||
} \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
|
|
||||||
|
|
||||||
#define TAILQ_FIRST(head) ((head)->tqh_first)
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH(var, head, field) \
|
|
||||||
for ((var) = TAILQ_FIRST((head)); \
|
|
||||||
(var); \
|
|
||||||
(var) = TAILQ_NEXT((var), field))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_FROM(var, head, field) \
|
|
||||||
for ((var) = ((var) ? (var) : TAILQ_FIRST((head))); \
|
|
||||||
(var); \
|
|
||||||
(var) = TAILQ_NEXT((var), field))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = TAILQ_FIRST((head)); \
|
|
||||||
(var) && ((tvar) = TAILQ_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_FROM_SAFE(var, head, field, tvar) \
|
|
||||||
for ((var) = ((var) ? (var) : TAILQ_FIRST((head))); \
|
|
||||||
(var) && ((tvar) = TAILQ_NEXT((var), field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
|
|
||||||
for ((var) = TAILQ_LAST((head), headname); \
|
|
||||||
(var); \
|
|
||||||
(var) = TAILQ_PREV((var), headname, field))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_REVERSE_FROM(var, head, headname, field) \
|
|
||||||
for ((var) = ((var) ? (var) : TAILQ_LAST((head), headname)); \
|
|
||||||
(var); \
|
|
||||||
(var) = TAILQ_PREV((var), headname, field))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \
|
|
||||||
for ((var) = TAILQ_LAST((head), headname); \
|
|
||||||
(var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define TAILQ_FOREACH_REVERSE_FROM_SAFE(var, head, headname, field, tvar) \
|
|
||||||
for ((var) = ((var) ? (var) : TAILQ_LAST((head), headname)); \
|
|
||||||
(var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \
|
|
||||||
(var) = (tvar))
|
|
||||||
|
|
||||||
#define TAILQ_INIT(head) do { \
|
|
||||||
TAILQ_FIRST((head)) = NULL; \
|
|
||||||
(head)->tqh_last = &TAILQ_FIRST((head)); \
|
|
||||||
QMD_TRACE_HEAD(head); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
|
|
||||||
QMD_TAILQ_CHECK_NEXT(listelm, field); \
|
|
||||||
if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
|
|
||||||
TAILQ_NEXT((elm), field)->field.tqe_prev = \
|
|
||||||
&TAILQ_NEXT((elm), field); \
|
|
||||||
else { \
|
|
||||||
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
|
|
||||||
QMD_TRACE_HEAD(head); \
|
|
||||||
} \
|
|
||||||
TAILQ_NEXT((listelm), field) = (elm); \
|
|
||||||
(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
|
|
||||||
QMD_TRACE_ELEM(&(elm)->field); \
|
|
||||||
QMD_TRACE_ELEM(&(listelm)->field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
|
|
||||||
QMD_TAILQ_CHECK_PREV(listelm, field); \
|
|
||||||
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
|
|
||||||
TAILQ_NEXT((elm), field) = (listelm); \
|
|
||||||
*(listelm)->field.tqe_prev = (elm); \
|
|
||||||
(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
|
|
||||||
QMD_TRACE_ELEM(&(elm)->field); \
|
|
||||||
QMD_TRACE_ELEM(&(listelm)->field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_INSERT_HEAD(head, elm, field) do { \
|
|
||||||
QMD_TAILQ_CHECK_HEAD(head, field); \
|
|
||||||
if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
|
|
||||||
TAILQ_FIRST((head))->field.tqe_prev = \
|
|
||||||
&TAILQ_NEXT((elm), field); \
|
|
||||||
else \
|
|
||||||
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
|
|
||||||
TAILQ_FIRST((head)) = (elm); \
|
|
||||||
(elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
|
|
||||||
QMD_TRACE_HEAD(head); \
|
|
||||||
QMD_TRACE_ELEM(&(elm)->field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_INSERT_TAIL(head, elm, field) do { \
|
|
||||||
QMD_TAILQ_CHECK_TAIL(head, field); \
|
|
||||||
TAILQ_NEXT((elm), field) = NULL; \
|
|
||||||
(elm)->field.tqe_prev = (head)->tqh_last; \
|
|
||||||
*(head)->tqh_last = (elm); \
|
|
||||||
(head)->tqh_last = &TAILQ_NEXT((elm), field); \
|
|
||||||
QMD_TRACE_HEAD(head); \
|
|
||||||
QMD_TRACE_ELEM(&(elm)->field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_LAST(head, headname) \
|
|
||||||
(*(((struct headname *)((head)->tqh_last))->tqh_last))
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The FAST function is fast in that it causes no data access other
|
|
||||||
* then the access to the head. The standard LAST function above
|
|
||||||
* will cause a data access of both the element you want and
|
|
||||||
* the previous element. FAST is very useful for instances when
|
|
||||||
* you may want to prefetch the last data element.
|
|
||||||
*/
|
|
||||||
#define TAILQ_LAST_FAST(head, type, field) \
|
|
||||||
(TAILQ_EMPTY(head) ? NULL : __containerof((head)->tqh_last, QUEUE_TYPEOF(type), field.tqe_next))
|
|
||||||
|
|
||||||
#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
|
|
||||||
|
|
||||||
#define TAILQ_PREV(elm, headname, field) \
|
|
||||||
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
|
|
||||||
|
|
||||||
#define TAILQ_REMOVE(head, elm, field) do { \
|
|
||||||
QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \
|
|
||||||
QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \
|
|
||||||
QMD_TAILQ_CHECK_NEXT(elm, field); \
|
|
||||||
QMD_TAILQ_CHECK_PREV(elm, field); \
|
|
||||||
if ((TAILQ_NEXT((elm), field)) != NULL) \
|
|
||||||
TAILQ_NEXT((elm), field)->field.tqe_prev = \
|
|
||||||
(elm)->field.tqe_prev; \
|
|
||||||
else { \
|
|
||||||
(head)->tqh_last = (elm)->field.tqe_prev; \
|
|
||||||
QMD_TRACE_HEAD(head); \
|
|
||||||
} \
|
|
||||||
*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
|
|
||||||
TRASHIT(*oldnext); \
|
|
||||||
TRASHIT(*oldprev); \
|
|
||||||
QMD_TRACE_ELEM(&(elm)->field); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define TAILQ_SWAP(head1, head2, type, field) do { \
|
|
||||||
QUEUE_TYPEOF(type) *swap_first = (head1)->tqh_first; \
|
|
||||||
QUEUE_TYPEOF(type) **swap_last = (head1)->tqh_last; \
|
|
||||||
(head1)->tqh_first = (head2)->tqh_first; \
|
|
||||||
(head1)->tqh_last = (head2)->tqh_last; \
|
|
||||||
(head2)->tqh_first = swap_first; \
|
|
||||||
(head2)->tqh_last = swap_last; \
|
|
||||||
if ((swap_first = (head1)->tqh_first) != NULL) \
|
|
||||||
swap_first->field.tqe_prev = &(head1)->tqh_first; \
|
|
||||||
else \
|
|
||||||
(head1)->tqh_last = &(head1)->tqh_first; \
|
|
||||||
if ((swap_first = (head2)->tqh_first) != NULL) \
|
|
||||||
swap_first->field.tqe_prev = &(head2)->tqh_first; \
|
|
||||||
else \
|
|
||||||
(head2)->tqh_last = &(head2)->tqh_first; \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#endif /* !_SYS_QUEUE_H_ */
|
|
@ -102,6 +102,7 @@
|
|||||||
#define TU_BSWAP32(u32) (__builtin_bswap32(u32))
|
#define TU_BSWAP32(u32) (__builtin_bswap32(u32))
|
||||||
|
|
||||||
#elif defined(__ICCARM__)
|
#elif defined(__ICCARM__)
|
||||||
|
#include <intrinsics.h>
|
||||||
#define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
|
#define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
|
||||||
#define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
|
#define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
|
||||||
#define TU_ATTR_PACKED __attribute__ ((packed))
|
#define TU_ATTR_PACKED __attribute__ ((packed))
|
||||||
|
@ -54,6 +54,7 @@
|
|||||||
ENTRY(TUSB_ERROR_FAILED )\
|
ENTRY(TUSB_ERROR_FAILED )\
|
||||||
|
|
||||||
/// \brief Error Code returned
|
/// \brief Error Code returned
|
||||||
|
/// TODO obsolete and to be remove
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
ERROR_TABLE(ERROR_ENUM)
|
ERROR_TABLE(ERROR_ENUM)
|
||||||
|
@ -30,6 +30,12 @@
|
|||||||
#include "osal/osal.h"
|
#include "osal/osal.h"
|
||||||
#include "tusb_fifo.h"
|
#include "tusb_fifo.h"
|
||||||
|
|
||||||
|
// Supress IAR warning
|
||||||
|
// Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
|
||||||
|
#if defined(__ICCARM__)
|
||||||
|
#pragma diag_suppress = Pa082
|
||||||
|
#endif
|
||||||
|
|
||||||
// implement mutex lock and unlock
|
// implement mutex lock and unlock
|
||||||
#if CFG_FIFO_MUTEX
|
#if CFG_FIFO_MUTEX
|
||||||
|
|
||||||
@ -106,7 +112,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * data, uint16_t n, uint16_t wRe
|
|||||||
memcpy(f->buffer + (wRel * f->item_size), data, nLin*f->item_size);
|
memcpy(f->buffer + (wRel * f->item_size), data, nLin*f->item_size);
|
||||||
|
|
||||||
// Write data wrapped around
|
// Write data wrapped around
|
||||||
memcpy(f->buffer, data + nLin*f->item_size, (n - nLin) * f->item_size);
|
memcpy(f->buffer, ((uint8_t const*) data) + nLin*f->item_size, (n - nLin) * f->item_size);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -131,7 +137,7 @@ static void _ff_pull_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t rRel)
|
|||||||
memcpy(p_buffer, f->buffer + (rRel * f->item_size), nLin*f->item_size);
|
memcpy(p_buffer, f->buffer + (rRel * f->item_size), nLin*f->item_size);
|
||||||
|
|
||||||
// Read data wrapped part
|
// Read data wrapped part
|
||||||
memcpy(p_buffer + nLin*f->item_size, f->buffer, (n - nLin) * f->item_size);
|
memcpy((uint8_t*)p_buffer + nLin*f->item_size, f->buffer, (n - nLin) * f->item_size);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -597,6 +603,27 @@ bool tu_fifo_clear(tu_fifo_t *f)
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/*!
|
||||||
|
@brief Change the fifo mode to overwritable or not overwritable
|
||||||
|
|
||||||
|
@param[in] f
|
||||||
|
Pointer to the FIFO buffer to manipulate
|
||||||
|
@param[in] overwritable
|
||||||
|
Overwritable mode the fifo is set to
|
||||||
|
*/
|
||||||
|
/******************************************************************************/
|
||||||
|
bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
|
||||||
|
{
|
||||||
|
tu_fifo_lock(f);
|
||||||
|
|
||||||
|
f->overwritable = overwritable;
|
||||||
|
|
||||||
|
tu_fifo_unlock(f);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
/*!
|
/*!
|
||||||
@brief Advance write pointer - intended to be used in combination with DMA.
|
@brief Advance write pointer - intended to be used in combination with DMA.
|
||||||
|
@ -89,6 +89,7 @@ typedef struct
|
|||||||
.non_used_index_space = 0xFFFF - 2*_depth-1, \
|
.non_used_index_space = 0xFFFF - 2*_depth-1, \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable);
|
||||||
bool tu_fifo_clear(tu_fifo_t *f);
|
bool tu_fifo_clear(tu_fifo_t *f);
|
||||||
bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
|
bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
|
||||||
|
|
||||||
|
@ -250,6 +250,13 @@ typedef enum
|
|||||||
MS_OS_20_FEATURE_VENDOR_REVISION = 0x08
|
MS_OS_20_FEATURE_VENDOR_REVISION = 0x08
|
||||||
} microsoft_os_20_type_t;
|
} microsoft_os_20_type_t;
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
CONTROL_STAGE_SETUP,
|
||||||
|
CONTROL_STAGE_DATA,
|
||||||
|
CONTROL_STAGE_ACK
|
||||||
|
};
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// USB Descriptors
|
// USB Descriptors
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -276,6 +283,8 @@ typedef struct TU_ATTR_PACKED
|
|||||||
uint8_t bNumConfigurations ; ///< Number of possible configurations.
|
uint8_t bNumConfigurations ; ///< Number of possible configurations.
|
||||||
} tusb_desc_device_t;
|
} tusb_desc_device_t;
|
||||||
|
|
||||||
|
TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
|
||||||
|
|
||||||
// USB Binary Device Object Store (BOS) Descriptor
|
// USB Binary Device Object Store (BOS) Descriptor
|
||||||
typedef struct TU_ATTR_PACKED
|
typedef struct TU_ATTR_PACKED
|
||||||
{
|
{
|
||||||
@ -431,7 +440,7 @@ typedef struct TU_ATTR_PACKED{
|
|||||||
uint16_t wLength;
|
uint16_t wLength;
|
||||||
} tusb_control_request_t;
|
} tusb_control_request_t;
|
||||||
|
|
||||||
TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "mostly compiler option issue");
|
TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
|
||||||
|
|
||||||
// TODO move to somewhere suitable
|
// TODO move to somewhere suitable
|
||||||
static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient)
|
static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient)
|
||||||
|
@ -77,7 +77,7 @@ typedef struct TU_ATTR_ALIGNED(4)
|
|||||||
uint32_t len;
|
uint32_t len;
|
||||||
}xfer_complete;
|
}xfer_complete;
|
||||||
|
|
||||||
// USBD_EVENT_FUNC_CALL
|
// FUNC_CALL
|
||||||
struct {
|
struct {
|
||||||
void (*func) (void*);
|
void (*func) (void*);
|
||||||
void* param;
|
void* param;
|
||||||
@ -140,7 +140,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
|
|||||||
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
|
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Event API (Implemented by device stack)
|
// Event API (implemented by stack)
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
// Called by DCD to notify device stack
|
// Called by DCD to notify device stack
|
||||||
|
@ -93,131 +93,121 @@ static usbd_class_driver_t const _usbd_driver[] =
|
|||||||
{
|
{
|
||||||
#if CFG_TUD_CDC
|
#if CFG_TUD_CDC
|
||||||
{
|
{
|
||||||
DRIVER_NAME("CDC")
|
DRIVER_NAME("CDC")
|
||||||
.init = cdcd_init,
|
.init = cdcd_init,
|
||||||
.reset = cdcd_reset,
|
.reset = cdcd_reset,
|
||||||
.open = cdcd_open,
|
.open = cdcd_open,
|
||||||
.control_request = cdcd_control_request,
|
.control_xfer_cb = cdcd_control_xfer_cb,
|
||||||
.control_complete = cdcd_control_complete,
|
.xfer_cb = cdcd_xfer_cb,
|
||||||
.xfer_cb = cdcd_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_MSC
|
#if CFG_TUD_MSC
|
||||||
{
|
{
|
||||||
DRIVER_NAME("MSC")
|
DRIVER_NAME("MSC")
|
||||||
.init = mscd_init,
|
.init = mscd_init,
|
||||||
.reset = mscd_reset,
|
.reset = mscd_reset,
|
||||||
.open = mscd_open,
|
.open = mscd_open,
|
||||||
.control_request = mscd_control_request,
|
.control_xfer_cb = mscd_control_xfer_cb,
|
||||||
.control_complete = mscd_control_complete,
|
.xfer_cb = mscd_xfer_cb,
|
||||||
.xfer_cb = mscd_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_HID
|
#if CFG_TUD_HID
|
||||||
{
|
{
|
||||||
DRIVER_NAME("HID")
|
DRIVER_NAME("HID")
|
||||||
.init = hidd_init,
|
.init = hidd_init,
|
||||||
.reset = hidd_reset,
|
.reset = hidd_reset,
|
||||||
.open = hidd_open,
|
.open = hidd_open,
|
||||||
.control_request = hidd_control_request,
|
.control_xfer_cb = hidd_control_xfer_cb,
|
||||||
.control_complete = hidd_control_complete,
|
.xfer_cb = hidd_xfer_cb,
|
||||||
.xfer_cb = hidd_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_AUDIO
|
#if CFG_TUD_AUDIO
|
||||||
{
|
{
|
||||||
DRIVER_NAME("AUDIO")
|
DRIVER_NAME("AUDIO")
|
||||||
.init = audiod_init,
|
.init = audiod_init,
|
||||||
.reset = audiod_reset,
|
.reset = audiod_reset,
|
||||||
.open = audiod_open,
|
.open = audiod_open,
|
||||||
.control_request = audiod_control_request,
|
.control_xfer_cb = audiod_control_xfer_cb,
|
||||||
.control_complete = audiod_control_complete,
|
|
||||||
.xfer_cb = audiod_xfer_cb,
|
.xfer_cb = audiod_xfer_cb,
|
||||||
.sof = NULL
|
.sof = NULL
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_MIDI
|
#if CFG_TUD_MIDI
|
||||||
{
|
{
|
||||||
DRIVER_NAME("MIDI")
|
DRIVER_NAME("MIDI")
|
||||||
.init = midid_init,
|
.init = midid_init,
|
||||||
.open = midid_open,
|
.open = midid_open,
|
||||||
.reset = midid_reset,
|
.reset = midid_reset,
|
||||||
.control_request = midid_control_request,
|
.control_xfer_cb = midid_control_xfer_cb,
|
||||||
.control_complete = midid_control_complete,
|
.xfer_cb = midid_xfer_cb,
|
||||||
.xfer_cb = midid_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_VENDOR
|
#if CFG_TUD_VENDOR
|
||||||
{
|
{
|
||||||
DRIVER_NAME("VENDOR")
|
DRIVER_NAME("VENDOR")
|
||||||
.init = vendord_init,
|
.init = vendord_init,
|
||||||
.reset = vendord_reset,
|
.reset = vendord_reset,
|
||||||
.open = vendord_open,
|
.open = vendord_open,
|
||||||
.control_request = tud_vendor_control_request_cb,
|
.control_xfer_cb = tud_vendor_control_xfer_cb,
|
||||||
.control_complete = tud_vendor_control_complete_cb,
|
.xfer_cb = vendord_xfer_cb,
|
||||||
.xfer_cb = vendord_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_USBTMC
|
#if CFG_TUD_USBTMC
|
||||||
{
|
{
|
||||||
DRIVER_NAME("TMC")
|
DRIVER_NAME("TMC")
|
||||||
.init = usbtmcd_init_cb,
|
.init = usbtmcd_init_cb,
|
||||||
.reset = usbtmcd_reset_cb,
|
.reset = usbtmcd_reset_cb,
|
||||||
.open = usbtmcd_open_cb,
|
.open = usbtmcd_open_cb,
|
||||||
.control_request = usbtmcd_control_request_cb,
|
.control_xfer_cb = usbtmcd_control_xfer_cb,
|
||||||
.control_complete = usbtmcd_control_complete_cb,
|
.xfer_cb = usbtmcd_xfer_cb,
|
||||||
.xfer_cb = usbtmcd_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_DFU_RT
|
#if CFG_TUD_DFU_RT
|
||||||
{
|
{
|
||||||
DRIVER_NAME("DFU-RT")
|
DRIVER_NAME("DFU-RT")
|
||||||
.init = dfu_rtd_init,
|
.init = dfu_rtd_init,
|
||||||
.reset = dfu_rtd_reset,
|
.reset = dfu_rtd_reset,
|
||||||
.open = dfu_rtd_open,
|
.open = dfu_rtd_open,
|
||||||
.control_request = dfu_rtd_control_request,
|
.control_xfer_cb = dfu_rtd_control_xfer_cb,
|
||||||
.control_complete = dfu_rtd_control_complete,
|
.xfer_cb = dfu_rtd_xfer_cb,
|
||||||
.xfer_cb = dfu_rtd_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_NET
|
#if CFG_TUD_NET
|
||||||
{
|
{
|
||||||
DRIVER_NAME("NET")
|
DRIVER_NAME("NET")
|
||||||
.init = netd_init,
|
.init = netd_init,
|
||||||
.reset = netd_reset,
|
.reset = netd_reset,
|
||||||
.open = netd_open,
|
.open = netd_open,
|
||||||
.control_request = netd_control_request,
|
.control_xfer_cb = netd_control_xfer_cb,
|
||||||
.control_complete = netd_control_complete,
|
.xfer_cb = netd_xfer_cb,
|
||||||
.xfer_cb = netd_xfer_cb,
|
.sof = NULL,
|
||||||
.sof = NULL,
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CFG_TUD_BTH
|
#if CFG_TUD_BTH
|
||||||
{
|
{
|
||||||
DRIVER_NAME("BTH")
|
DRIVER_NAME("BTH")
|
||||||
.init = btd_init,
|
.init = btd_init,
|
||||||
.reset = btd_reset,
|
.reset = btd_reset,
|
||||||
.open = btd_open,
|
.open = btd_open,
|
||||||
.control_request = btd_control_request,
|
.control_xfer_cb = btd_control_xfer_cb,
|
||||||
.control_complete = btd_control_complete,
|
.xfer_cb = btd_xfer_cb,
|
||||||
.xfer_cb = btd_xfer_cb,
|
.sof = NULL
|
||||||
.sof = NULL
|
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -287,7 +277,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
|
|||||||
// from usbd_control.c
|
// from usbd_control.c
|
||||||
void usbd_control_reset(void);
|
void usbd_control_reset(void);
|
||||||
void usbd_control_set_request(tusb_control_request_t const *request);
|
void usbd_control_set_request(tusb_control_request_t const *request);
|
||||||
void usbd_control_set_complete_callback( bool (*fp) (uint8_t, tusb_control_request_t const * ) );
|
void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
|
||||||
bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
|
|
||||||
|
|
||||||
@ -326,12 +316,12 @@ static char const* const _tusb_std_request_str[] =
|
|||||||
};
|
};
|
||||||
|
|
||||||
// for usbd_control to print the name of control complete driver
|
// for usbd_control to print the name of control complete driver
|
||||||
void usbd_driver_print_control_complete_name(bool (*control_complete) (uint8_t, tusb_control_request_t const * ))
|
void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
|
||||||
{
|
{
|
||||||
for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
|
for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
|
||||||
{
|
{
|
||||||
usbd_class_driver_t const * driver = get_driver(i);
|
usbd_class_driver_t const * driver = get_driver(i);
|
||||||
if ( driver->control_complete == control_complete )
|
if ( driver->control_xfer_cb == callback )
|
||||||
{
|
{
|
||||||
TU_LOG2(" %s control complete\r\n", driver->name);
|
TU_LOG2(" %s control complete\r\n", driver->name);
|
||||||
return;
|
return;
|
||||||
@ -349,9 +339,14 @@ tusb_speed_t tud_speed_get(void)
|
|||||||
return (tusb_speed_t) _usbd_dev.speed;
|
return (tusb_speed_t) _usbd_dev.speed;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool tud_connected(void)
|
||||||
|
{
|
||||||
|
return _usbd_dev.connected;
|
||||||
|
}
|
||||||
|
|
||||||
bool tud_mounted(void)
|
bool tud_mounted(void)
|
||||||
{
|
{
|
||||||
return _usbd_dev.cfg_num ? 1 : 0;
|
return _usbd_dev.cfg_num ? true : false;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool tud_suspended(void)
|
bool tud_suspended(void)
|
||||||
@ -535,7 +530,7 @@ void tud_task (void)
|
|||||||
TU_ASSERT(driver, );
|
TU_ASSERT(driver, );
|
||||||
|
|
||||||
TU_LOG2(" %s xfer callback\r\n", driver->name);
|
TU_LOG2(" %s xfer callback\r\n", driver->name);
|
||||||
driver->xfer_cb(event.rhport, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
|
driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
@ -578,9 +573,9 @@ void tud_task (void)
|
|||||||
// Helper to invoke class driver control request handler
|
// Helper to invoke class driver control request handler
|
||||||
static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
|
static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
|
||||||
{
|
{
|
||||||
usbd_control_set_complete_callback(driver->control_complete);
|
usbd_control_set_complete_callback(driver->control_xfer_cb);
|
||||||
TU_LOG2(" %s control request\r\n", driver->name);
|
TU_LOG2(" %s control request\r\n", driver->name);
|
||||||
return driver->control_request(rhport, request);
|
return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
|
||||||
}
|
}
|
||||||
|
|
||||||
// This handles the actual request and its response.
|
// This handles the actual request and its response.
|
||||||
@ -594,10 +589,10 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
|
|||||||
// Vendor request
|
// Vendor request
|
||||||
if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
|
if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
|
||||||
{
|
{
|
||||||
TU_VERIFY(tud_vendor_control_request_cb);
|
TU_VERIFY(tud_vendor_control_xfer_cb);
|
||||||
|
|
||||||
if (tud_vendor_control_complete_cb) usbd_control_set_complete_callback(tud_vendor_control_complete_cb);
|
usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
|
||||||
return tud_vendor_control_request_cb(rhport, p_request);
|
return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if CFG_TUSB_DEBUG >= 2
|
#if CFG_TUSB_DEBUG >= 2
|
||||||
@ -951,6 +946,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case TUSB_DESC_STRING:
|
case TUSB_DESC_STRING:
|
||||||
|
{
|
||||||
TU_LOG2(" String[%u]\r\n", desc_index);
|
TU_LOG2(" String[%u]\r\n", desc_index);
|
||||||
|
|
||||||
// String Descriptor always uses the desc set from user
|
// String Descriptor always uses the desc set from user
|
||||||
@ -959,6 +955,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
|
|||||||
|
|
||||||
// first byte of descriptor is its size
|
// first byte of descriptor is its size
|
||||||
return tud_control_xfer(rhport, p_request, (void*) desc_str, desc_str[0]);
|
return tud_control_xfer(rhport, p_request, (void*) desc_str, desc_str[0]);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case TUSB_DESC_DEVICE_QUALIFIER:
|
case TUSB_DESC_DEVICE_QUALIFIER:
|
||||||
|
@ -41,8 +41,6 @@ extern "C" {
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
// Init device stack
|
// Init device stack
|
||||||
// Note: when using with RTOS, this should be called after scheduler/kernel is started.
|
|
||||||
// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
|
|
||||||
bool tud_init (void);
|
bool tud_init (void);
|
||||||
|
|
||||||
// Task function should be called in main/rtos loop
|
// Task function should be called in main/rtos loop
|
||||||
@ -58,6 +56,9 @@ extern void dcd_int_handler(uint8_t rhport);
|
|||||||
// Get current bus speed
|
// Get current bus speed
|
||||||
tusb_speed_t tud_speed_get(void);
|
tusb_speed_t tud_speed_get(void);
|
||||||
|
|
||||||
|
// Check if device is connected (may not mounted/configured yet)
|
||||||
|
bool tud_connected(void);
|
||||||
|
|
||||||
// Check if device is connected and configured
|
// Check if device is connected and configured
|
||||||
bool tud_mounted(void);
|
bool tud_mounted(void);
|
||||||
|
|
||||||
@ -127,11 +128,7 @@ TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en);
|
|||||||
TU_ATTR_WEAK void tud_resume_cb(void);
|
TU_ATTR_WEAK void tud_resume_cb(void);
|
||||||
|
|
||||||
// Invoked when received control request with VENDOR TYPE
|
// Invoked when received control request with VENDOR TYPE
|
||||||
TU_ATTR_WEAK bool tud_vendor_control_request_cb(uint8_t rhport, tusb_control_request_t const * request);
|
TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
|
|
||||||
// Invoked when vendor control request is complete
|
|
||||||
TU_ATTR_WEAK bool tud_vendor_control_complete_cb(uint8_t rhport, tusb_control_request_t const * request);
|
|
||||||
|
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Binary Device Object Store (BOS) Descriptor Templates
|
// Binary Device Object Store (BOS) Descriptor Templates
|
||||||
|
@ -33,7 +33,7 @@
|
|||||||
#include "dcd.h"
|
#include "dcd.h"
|
||||||
|
|
||||||
#if CFG_TUSB_DEBUG >= 2
|
#if CFG_TUSB_DEBUG >= 2
|
||||||
extern void usbd_driver_print_control_complete_name(bool (*control_complete) (uint8_t, tusb_control_request_t const *));
|
extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
enum
|
enum
|
||||||
@ -50,7 +50,7 @@ typedef struct
|
|||||||
uint16_t data_len;
|
uint16_t data_len;
|
||||||
uint16_t total_xferred;
|
uint16_t total_xferred;
|
||||||
|
|
||||||
bool (*complete_cb) (uint8_t, tusb_control_request_t const *);
|
usbd_control_xfer_cb_t complete_cb;
|
||||||
} usbd_control_xfer_t;
|
} usbd_control_xfer_t;
|
||||||
|
|
||||||
static usbd_control_xfer_t _ctrl_xfer;
|
static usbd_control_xfer_t _ctrl_xfer;
|
||||||
@ -140,13 +140,21 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
|
|||||||
// USBD API
|
// USBD API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Prototypes
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
void usbd_control_reset(void);
|
||||||
|
void usbd_control_set_request(tusb_control_request_t const *request);
|
||||||
|
void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
|
||||||
|
bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
|
|
||||||
void usbd_control_reset(void)
|
void usbd_control_reset(void)
|
||||||
{
|
{
|
||||||
tu_varclr(&_ctrl_xfer);
|
tu_varclr(&_ctrl_xfer);
|
||||||
}
|
}
|
||||||
|
|
||||||
// TODO may find a better way
|
// TODO may find a better way
|
||||||
void usbd_control_set_complete_callback( bool (*fp) (uint8_t, tusb_control_request_t const * ) )
|
void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp )
|
||||||
{
|
{
|
||||||
_ctrl_xfer.complete_cb = fp;
|
_ctrl_xfer.complete_cb = fp;
|
||||||
}
|
}
|
||||||
@ -171,7 +179,16 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
|
|||||||
if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
|
if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
|
||||||
{
|
{
|
||||||
TU_ASSERT(0 == xferred_bytes);
|
TU_ASSERT(0 == xferred_bytes);
|
||||||
|
|
||||||
|
// invoke optional dcd hook if available
|
||||||
if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
|
if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
|
||||||
|
|
||||||
|
if (_ctrl_xfer.complete_cb)
|
||||||
|
{
|
||||||
|
// TODO refactor with usbd_driver_print_control_complete_name
|
||||||
|
_ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request);
|
||||||
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -199,7 +216,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
|
|||||||
usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
|
usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
is_ok = _ctrl_xfer.complete_cb(rhport, &_ctrl_xfer.request);
|
is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request);
|
||||||
}
|
}
|
||||||
|
|
||||||
if ( is_ok )
|
if ( is_ok )
|
||||||
|
@ -46,8 +46,7 @@ typedef struct
|
|||||||
void (* init ) (void);
|
void (* init ) (void);
|
||||||
void (* reset ) (uint8_t rhport);
|
void (* reset ) (uint8_t rhport);
|
||||||
uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
|
uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
|
||||||
bool (* control_request ) (uint8_t rhport, tusb_control_request_t const * request);
|
bool (* control_xfer_cb ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
bool (* control_complete ) (uint8_t rhport, tusb_control_request_t const * request);
|
|
||||||
bool (* xfer_cb ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool (* xfer_cb ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
void (* sof ) (uint8_t rhport); /* optional */
|
void (* sof ) (uint8_t rhport); /* optional */
|
||||||
} usbd_class_driver_t;
|
} usbd_class_driver_t;
|
||||||
@ -57,6 +56,9 @@ typedef struct
|
|||||||
// Note: The drivers array must be accessible at all time when stack is active
|
// Note: The drivers array must be accessible at all time when stack is active
|
||||||
usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
|
usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
|
||||||
|
|
||||||
|
|
||||||
|
typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// USBD Endpoint API
|
// USBD Endpoint API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
@ -326,6 +326,22 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
|
|||||||
|
|
||||||
// attach TD
|
// attach TD
|
||||||
qhd->qtd_overlay.next.address = (uint32_t) qtd;
|
qhd->qtd_overlay.next.address = (uint32_t) qtd;
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
|
||||||
|
ehci_qtd_t *p_qtd = qtd_find_free();
|
||||||
|
TU_ASSERT(p_qtd);
|
||||||
|
|
||||||
|
qtd_init(p_qtd, buffer, buflen);
|
||||||
|
p_qtd->pid = p_qhd->pid;
|
||||||
|
|
||||||
|
// Insert TD to QH
|
||||||
|
qtd_insert_to_qhd(p_qhd, p_qtd);
|
||||||
|
|
||||||
|
p_qhd->p_qtd_list_tail->int_on_complete = 1;
|
||||||
|
|
||||||
|
// attach head QTD to QHD start transferring
|
||||||
|
p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head;
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
@ -489,10 +505,10 @@ static void port_connect_status_change_isr(uint8_t hostid)
|
|||||||
if (ehci_data.regs->portsc_bm.current_connect_status)
|
if (ehci_data.regs->portsc_bm.current_connect_status)
|
||||||
{
|
{
|
||||||
hcd_port_reset(hostid);
|
hcd_port_reset(hostid);
|
||||||
hcd_event_device_attach(hostid);
|
hcd_event_device_attach(hostid, true);
|
||||||
}else // device unplugged
|
}else // device unplugged
|
||||||
{
|
{
|
||||||
hcd_event_device_remove(hostid);
|
hcd_event_device_remove(hostid, true);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -512,7 +528,7 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
|
|||||||
{
|
{
|
||||||
// end of request
|
// end of request
|
||||||
// call USBH callback
|
// call USBH callback
|
||||||
hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), XFER_RESULT_SUCCESS, p_qhd->total_xferred_bytes);
|
hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), p_qhd->total_xferred_bytes, XFER_RESULT_SUCCESS, true);
|
||||||
p_qhd->total_xferred_bytes = 0;
|
p_qhd->total_xferred_bytes = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -533,7 +549,7 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
|
|||||||
|
|
||||||
static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
|
static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
|
||||||
{
|
{
|
||||||
uint8_t max_loop = 0;
|
uint16_t max_loop = 0;
|
||||||
uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
|
uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
|
||||||
ehci_link_t next_item = * get_period_head(hostid, interval_ms);
|
ehci_link_t next_item = * get_period_head(hostid, interval_ms);
|
||||||
|
|
||||||
@ -599,7 +615,7 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
|
|||||||
}
|
}
|
||||||
|
|
||||||
// call USBH callback
|
// call USBH callback
|
||||||
hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), error_event, p_qhd->total_xferred_bytes);
|
hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), p_qhd->total_xferred_bytes, error_event, true);
|
||||||
|
|
||||||
p_qhd->total_xferred_bytes = 0;
|
p_qhd->total_xferred_bytes = 0;
|
||||||
}
|
}
|
||||||
|
@ -45,27 +45,39 @@ typedef enum
|
|||||||
HCD_EVENT_DEVICE_ATTACH,
|
HCD_EVENT_DEVICE_ATTACH,
|
||||||
HCD_EVENT_DEVICE_REMOVE,
|
HCD_EVENT_DEVICE_REMOVE,
|
||||||
HCD_EVENT_XFER_COMPLETE,
|
HCD_EVENT_XFER_COMPLETE,
|
||||||
|
|
||||||
|
// Not an HCD event, just a convenient way to defer ISR function
|
||||||
|
USBH_EVENT_FUNC_CALL,
|
||||||
|
|
||||||
|
HCD_EVENT_COUNT
|
||||||
} hcd_eventid_t;
|
} hcd_eventid_t;
|
||||||
|
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint8_t rhport;
|
uint8_t rhport;
|
||||||
uint8_t event_id;
|
uint8_t event_id;
|
||||||
|
uint8_t dev_addr;
|
||||||
|
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
struct
|
// Attach, Remove
|
||||||
{
|
struct {
|
||||||
uint8_t hub_addr;
|
uint8_t hub_addr;
|
||||||
uint8_t hub_port;
|
uint8_t hub_port;
|
||||||
} attach, remove;
|
} connection;
|
||||||
|
|
||||||
struct
|
// XFER_COMPLETE
|
||||||
{
|
struct {
|
||||||
uint8_t ep_addr;
|
uint8_t ep_addr;
|
||||||
uint8_t result;
|
uint8_t result;
|
||||||
uint32_t len;
|
uint32_t len;
|
||||||
} xfer_complete;
|
} xfer_complete;
|
||||||
|
|
||||||
|
// FUNC_CALL
|
||||||
|
struct {
|
||||||
|
void (*func) (void*);
|
||||||
|
void* param;
|
||||||
|
}func_call;
|
||||||
};
|
};
|
||||||
|
|
||||||
} hcd_event_t;
|
} hcd_event_t;
|
||||||
@ -109,20 +121,6 @@ tusb_speed_t hcd_port_speed_get(uint8_t hostid);
|
|||||||
// HCD closes all opened endpoints belong to this device
|
// HCD closes all opened endpoints belong to this device
|
||||||
void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
|
void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
|
||||||
// Event function
|
|
||||||
//--------------------------------------------------------------------+
|
|
||||||
void hcd_event_handler(hcd_event_t const* event, bool in_isr);
|
|
||||||
|
|
||||||
// Helper to send device attach event
|
|
||||||
void hcd_event_device_attach(uint8_t rhport);
|
|
||||||
|
|
||||||
// Helper to send device removal event
|
|
||||||
void hcd_event_device_remove(uint8_t rhport);
|
|
||||||
|
|
||||||
// Helper to send USB transfer event
|
|
||||||
void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Endpoints API
|
// Endpoints API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -145,6 +143,22 @@ bool hcd_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t
|
|||||||
|
|
||||||
// tusb_error_t hcd_pipe_cancel();
|
// tusb_error_t hcd_pipe_cancel();
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Event API (implemented by stack)
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
// Called by HCD to notify stack
|
||||||
|
extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
|
||||||
|
|
||||||
|
// Helper to send device attach event
|
||||||
|
extern void hcd_event_device_attach(uint8_t rhport, bool in_isr);
|
||||||
|
|
||||||
|
// Helper to send device removal event
|
||||||
|
extern void hcd_event_device_remove(uint8_t rhport, bool in_isr);
|
||||||
|
|
||||||
|
// Helper to send USB transfer event
|
||||||
|
extern void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
349
src/host/hub.c
349
src/host/hub.c
@ -39,13 +39,15 @@
|
|||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint8_t itf_num;
|
uint8_t itf_num;
|
||||||
uint8_t ep_status;
|
uint8_t ep_in;
|
||||||
uint8_t port_number;
|
uint8_t port_count;
|
||||||
uint8_t status_change; // data from status change interrupt endpoint
|
uint8_t status_change; // data from status change interrupt endpoint
|
||||||
|
|
||||||
|
hub_port_status_response_t port_status;
|
||||||
}usbh_hub_t;
|
}usbh_hub_t;
|
||||||
|
|
||||||
CFG_TUSB_MEM_SECTION static usbh_hub_t hub_data[CFG_TUSB_HOST_DEVICE_MAX];
|
CFG_TUSB_MEM_SECTION static usbh_hub_t hub_data[CFG_TUSB_HOST_DEVICE_MAX];
|
||||||
TU_ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION static uint8_t hub_enum_buffer[sizeof(descriptor_hub_desc_t)];
|
TU_ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
|
||||||
|
|
||||||
//OSAL_SEM_DEF(hub_enum_semaphore);
|
//OSAL_SEM_DEF(hub_enum_semaphore);
|
||||||
//static osal_semaphore_handle_t hub_enum_sem_hdl;
|
//static osal_semaphore_handle_t hub_enum_sem_hdl;
|
||||||
@ -53,84 +55,67 @@ TU_ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION static uint8_t hub_enum_buffer[sizeof(de
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// HUB
|
// HUB
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
bool hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature)
|
bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb)
|
||||||
{
|
{
|
||||||
TU_ASSERT(HUB_FEATURE_PORT_CONNECTION_CHANGE <= feature && feature <= HUB_FEATURE_PORT_RESET_CHANGE);
|
tusb_control_request_t const request =
|
||||||
|
{
|
||||||
tusb_control_request_t request = {
|
.bmRequestType_bit =
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
|
{
|
||||||
.bRequest = HUB_REQUEST_CLEAR_FEATURE,
|
.recipient = TUSB_REQ_RCPT_OTHER,
|
||||||
.wValue = feature,
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
.wIndex = hub_port,
|
.direction = TUSB_DIR_OUT
|
||||||
.wLength = 0
|
},
|
||||||
|
.bRequest = HUB_REQUEST_CLEAR_FEATURE,
|
||||||
|
.wValue = feature,
|
||||||
|
.wIndex = hub_port,
|
||||||
|
.wLength = 0
|
||||||
};
|
};
|
||||||
|
|
||||||
//------------- Clear Port Feature request -------------//
|
TU_LOG2("HUB Clear Port Feature: addr = %u port = %u, feature = %u\r\n", hub_addr, hub_port, feature);
|
||||||
TU_ASSERT( usbh_control_xfer( hub_addr, &request, NULL ) );
|
TU_ASSERT( tuh_control_xfer(hub_addr, &request, NULL, complete_cb) );
|
||||||
|
|
||||||
//------------- Get Port Status to check if feature is cleared -------------//
|
|
||||||
request = (tusb_control_request_t ) {
|
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
|
|
||||||
.bRequest = HUB_REQUEST_GET_STATUS,
|
|
||||||
.wValue = 0,
|
|
||||||
.wIndex = hub_port,
|
|
||||||
.wLength = 4
|
|
||||||
};
|
|
||||||
|
|
||||||
TU_ASSERT( usbh_control_xfer( hub_addr, &request, hub_enum_buffer ) );
|
|
||||||
|
|
||||||
//------------- Check if feature is cleared -------------//
|
|
||||||
hub_port_status_response_t * p_port_status;
|
|
||||||
p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
|
|
||||||
|
|
||||||
TU_ASSERT( !tu_bit_test(p_port_status->status_change.value, feature-16) );
|
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port)
|
bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb)
|
||||||
{
|
{
|
||||||
enum { RESET_DELAY = 200 }; // USB specs say only 50ms but many devices require much longer
|
tusb_control_request_t const request =
|
||||||
|
{
|
||||||
//------------- Set Port Reset -------------//
|
.bmRequestType_bit =
|
||||||
tusb_control_request_t request = {
|
{
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
|
.recipient = TUSB_REQ_RCPT_OTHER,
|
||||||
.bRequest = HUB_REQUEST_SET_FEATURE,
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
.wValue = HUB_FEATURE_PORT_RESET,
|
.direction = TUSB_DIR_IN
|
||||||
.wIndex = hub_port,
|
},
|
||||||
.wLength = 0
|
.bRequest = HUB_REQUEST_GET_STATUS,
|
||||||
|
.wValue = 0,
|
||||||
|
.wIndex = hub_port,
|
||||||
|
.wLength = 4
|
||||||
};
|
};
|
||||||
|
|
||||||
TU_ASSERT( usbh_control_xfer( hub_addr, &request, NULL ) );
|
TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
|
||||||
|
TU_ASSERT( tuh_control_xfer( hub_addr, &request, resp, complete_cb) );
|
||||||
osal_task_delay(RESET_DELAY); // TODO Hub wait for Status Endpoint on Reset Change
|
|
||||||
|
|
||||||
//------------- Get Port Status to check if port is enabled, powered and reset_change -------------//
|
|
||||||
request = (tusb_control_request_t ) {
|
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
|
|
||||||
.bRequest = HUB_REQUEST_GET_STATUS,
|
|
||||||
.wValue = 0,
|
|
||||||
.wIndex = hub_port,
|
|
||||||
.wLength = 4
|
|
||||||
};
|
|
||||||
|
|
||||||
TU_ASSERT( usbh_control_xfer( hub_addr, &request, hub_enum_buffer ) );
|
|
||||||
|
|
||||||
hub_port_status_response_t * p_port_status;
|
|
||||||
p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
|
|
||||||
|
|
||||||
TU_ASSERT ( p_port_status->status_change.reset && p_port_status->status_current.connect_status &&
|
|
||||||
p_port_status->status_current.port_power && p_port_status->status_current.port_enable);
|
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// can only get the speed RIGHT AFTER hub_port_reset_subtask call
|
bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb)
|
||||||
tusb_speed_t hub_port_get_speed(void)
|
|
||||||
{
|
{
|
||||||
hub_port_status_response_t * p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
|
tusb_control_request_t const request =
|
||||||
return (p_port_status->status_current.high_speed_device_attached) ? TUSB_SPEED_HIGH :
|
{
|
||||||
(p_port_status->status_current.low_speed_device_attached ) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
|
.bmRequestType_bit =
|
||||||
|
{
|
||||||
|
.recipient = TUSB_REQ_RCPT_OTHER,
|
||||||
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
|
.direction = TUSB_DIR_OUT
|
||||||
|
},
|
||||||
|
.bRequest = HUB_REQUEST_SET_FEATURE,
|
||||||
|
.wValue = HUB_FEATURE_PORT_RESET,
|
||||||
|
.wIndex = hub_port,
|
||||||
|
.wLength = 0
|
||||||
|
};
|
||||||
|
|
||||||
|
TU_LOG2("HUB Reset Port: addr = %u port = %u\r\n", hub_addr, hub_port);
|
||||||
|
TU_ASSERT( tuh_control_xfer(hub_addr, &request, NULL, complete_cb) );
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -157,82 +142,207 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf
|
|||||||
TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
|
TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
|
||||||
|
|
||||||
hub_data[dev_addr-1].itf_num = itf_desc->bInterfaceNumber;
|
hub_data[dev_addr-1].itf_num = itf_desc->bInterfaceNumber;
|
||||||
hub_data[dev_addr-1].ep_status = ep_desc->bEndpointAddress;
|
hub_data[dev_addr-1].ep_in = ep_desc->bEndpointAddress;
|
||||||
|
|
||||||
(*p_length) = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
|
(*p_length) = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
|
||||||
|
|
||||||
//------------- Get Hub Descriptor -------------//
|
return true;
|
||||||
tusb_control_request_t request = {
|
}
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_IN },
|
|
||||||
.bRequest = HUB_REQUEST_GET_DESCRIPTOR,
|
|
||||||
.wValue = 0,
|
|
||||||
.wIndex = 0,
|
|
||||||
.wLength = sizeof(descriptor_hub_desc_t)
|
|
||||||
};
|
|
||||||
|
|
||||||
TU_ASSERT( usbh_control_xfer( dev_addr, &request, hub_enum_buffer ) );
|
static bool config_get_hub_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
|
||||||
// only care about this field in hub descriptor
|
static bool config_get_hub_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
|
||||||
hub_data[dev_addr-1].port_number = ((descriptor_hub_desc_t*) hub_enum_buffer)->bNbrPorts;
|
{
|
||||||
|
(void) request;
|
||||||
|
TU_ASSERT(XFER_RESULT_SUCCESS == result);
|
||||||
|
|
||||||
//------------- Set Port_Power on all ports -------------//
|
usbh_hub_t* p_hub = &hub_data[dev_addr-1];
|
||||||
// TODO may only power port with attached
|
|
||||||
request = (tusb_control_request_t ) {
|
|
||||||
.bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_OTHER, .type = TUSB_REQ_TYPE_CLASS, .direction = TUSB_DIR_OUT },
|
|
||||||
.bRequest = HUB_REQUEST_SET_FEATURE,
|
|
||||||
.wValue = HUB_FEATURE_PORT_POWER,
|
|
||||||
.wIndex = 0,
|
|
||||||
.wLength = 0
|
|
||||||
};
|
|
||||||
|
|
||||||
for(uint8_t i=1; i <= hub_data[dev_addr-1].port_number; i++)
|
// only use number of ports in hub descriptor
|
||||||
|
descriptor_hub_desc_t const* desc_hub = (descriptor_hub_desc_t const*) _hub_buffer;
|
||||||
|
p_hub->port_count = desc_hub->bNbrPorts;
|
||||||
|
|
||||||
|
// May need to GET_STATUS
|
||||||
|
|
||||||
|
// Ports must be powered on to be able to detect connection
|
||||||
|
tusb_control_request_t const new_request =
|
||||||
{
|
{
|
||||||
request.wIndex = i;
|
.bmRequestType_bit =
|
||||||
TU_ASSERT( usbh_control_xfer( dev_addr, &request, NULL ) );
|
{
|
||||||
|
.recipient = TUSB_REQ_RCPT_OTHER,
|
||||||
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
|
.direction = TUSB_DIR_OUT
|
||||||
|
},
|
||||||
|
.bRequest = HUB_REQUEST_SET_FEATURE,
|
||||||
|
.wValue = HUB_FEATURE_PORT_POWER,
|
||||||
|
.wIndex = 1, // starting with port 1
|
||||||
|
.wLength = 0
|
||||||
|
};
|
||||||
|
|
||||||
|
TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, config_port_power_complete) );
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
|
||||||
|
{
|
||||||
|
TU_ASSERT(XFER_RESULT_SUCCESS == result);
|
||||||
|
usbh_hub_t* p_hub = &hub_data[dev_addr-1];
|
||||||
|
|
||||||
|
if (request->wIndex == p_hub->port_count)
|
||||||
|
{
|
||||||
|
// All ports are power -> queue notification status endpoint and
|
||||||
|
// complete the SET CONFIGURATION
|
||||||
|
TU_ASSERT( usbh_edpt_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1) );
|
||||||
|
|
||||||
|
usbh_driver_set_config_complete(dev_addr, p_hub->itf_num);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
tusb_control_request_t new_request = *request;
|
||||||
|
new_request.wIndex++; // power next port
|
||||||
|
|
||||||
|
TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, config_port_power_complete) );
|
||||||
}
|
}
|
||||||
|
|
||||||
//------------- Queue the initial Status endpoint transfer -------------//
|
return true;
|
||||||
TU_ASSERT( hcd_pipe_xfer(dev_addr, hub_data[dev_addr-1].ep_status, &hub_data[dev_addr-1].status_change, 1, true) );
|
}
|
||||||
|
|
||||||
|
bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
|
||||||
|
{
|
||||||
|
usbh_hub_t* p_hub = &hub_data[dev_addr-1];
|
||||||
|
TU_ASSERT(itf_num == p_hub->itf_num);
|
||||||
|
|
||||||
|
//------------- Get Hub Descriptor -------------//
|
||||||
|
tusb_control_request_t request =
|
||||||
|
{
|
||||||
|
.bmRequestType_bit =
|
||||||
|
{
|
||||||
|
.recipient = TUSB_REQ_RCPT_DEVICE,
|
||||||
|
.type = TUSB_REQ_TYPE_CLASS,
|
||||||
|
.direction = TUSB_DIR_IN
|
||||||
|
},
|
||||||
|
.bRequest = HUB_REQUEST_GET_DESCRIPTOR,
|
||||||
|
.wValue = 0,
|
||||||
|
.wIndex = 0,
|
||||||
|
.wLength = sizeof(descriptor_hub_desc_t)
|
||||||
|
};
|
||||||
|
|
||||||
|
TU_ASSERT( tuh_control_xfer(dev_addr, &request, _hub_buffer, config_get_hub_desc_complete) );
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
|
||||||
|
static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
|
||||||
|
{
|
||||||
|
TU_ASSERT(result == XFER_RESULT_SUCCESS);
|
||||||
|
|
||||||
|
// usbh_hub_t * p_hub = &hub_data[dev_addr-1];
|
||||||
|
uint8_t const port_num = (uint8_t) request->wIndex;
|
||||||
|
|
||||||
|
// submit attach event
|
||||||
|
hcd_event_t event =
|
||||||
|
{
|
||||||
|
.rhport = usbh_get_rhport(dev_addr),
|
||||||
|
.event_id = HCD_EVENT_DEVICE_ATTACH,
|
||||||
|
.connection =
|
||||||
|
{
|
||||||
|
.hub_addr = dev_addr,
|
||||||
|
.hub_port = port_num
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
hcd_event_handler(&event, false);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
|
||||||
|
{
|
||||||
|
TU_ASSERT(result == XFER_RESULT_SUCCESS);
|
||||||
|
|
||||||
|
usbh_hub_t * p_hub = &hub_data[dev_addr-1];
|
||||||
|
uint8_t const port_num = (uint8_t) request->wIndex;
|
||||||
|
|
||||||
|
if ( p_hub->port_status.status.connection )
|
||||||
|
{
|
||||||
|
// Reset port if attach event
|
||||||
|
hub_port_reset(dev_addr, port_num, connection_port_reset_complete);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
// submit detach event
|
||||||
|
hcd_event_t event =
|
||||||
|
{
|
||||||
|
.rhport = usbh_get_rhport(dev_addr),
|
||||||
|
.event_id = HCD_EVENT_DEVICE_REMOVE,
|
||||||
|
.connection =
|
||||||
|
{
|
||||||
|
.hub_addr = dev_addr,
|
||||||
|
.hub_port = port_num
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
hcd_event_handler(&event, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
|
||||||
|
{
|
||||||
|
TU_ASSERT(result == XFER_RESULT_SUCCESS);
|
||||||
|
usbh_hub_t * p_hub = &hub_data[dev_addr-1];
|
||||||
|
uint8_t const port_num = (uint8_t) request->wIndex;
|
||||||
|
|
||||||
|
// Connection change
|
||||||
|
if (p_hub->port_status.change.connection)
|
||||||
|
{
|
||||||
|
// Port is powered and enabled
|
||||||
|
//TU_VERIFY(port_status.status_current.port_power && port_status.status_current.port_enable, );
|
||||||
|
|
||||||
|
// Acknowledge Port Connection Change
|
||||||
|
hub_port_clear_feature(dev_addr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
// Other changes are: Enable, Suspend, Over Current, Reset, L1 state
|
||||||
|
// TODO clear change
|
||||||
|
|
||||||
|
// prepare for next hub status
|
||||||
|
// TODO continue with status_change, or maybe we can do it again with status
|
||||||
|
hub_status_pipe_queue(dev_addr);
|
||||||
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// is the response of interrupt endpoint polling
|
// is the response of interrupt endpoint polling
|
||||||
#include "usbh_hcd.h" // FIXME remove
|
#include "usbh_hcd.h" // FIXME remove
|
||||||
void hub_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
||||||
{
|
{
|
||||||
(void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
|
(void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
|
||||||
(void) ep_addr;
|
(void) ep_addr;
|
||||||
|
TU_ASSERT( result == XFER_RESULT_SUCCESS);
|
||||||
|
|
||||||
usbh_hub_t * p_hub = &hub_data[dev_addr-1];
|
usbh_hub_t * p_hub = &hub_data[dev_addr-1];
|
||||||
|
|
||||||
if ( event == XFER_RESULT_SUCCESS )
|
TU_LOG2("Port Status Change = 0x%02X\r\n", p_hub->status_change);
|
||||||
|
for (uint8_t port=1; port <= p_hub->port_count; port++)
|
||||||
{
|
{
|
||||||
for (uint8_t port=1; port <= p_hub->port_number; port++)
|
// TODO HUB ignore bit0 hub_status_change
|
||||||
|
if ( tu_bit_test(p_hub->status_change, port) )
|
||||||
{
|
{
|
||||||
// TODO HUB ignore bit0 hub_status_change
|
hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete);
|
||||||
if ( tu_bit_test(p_hub->status_change, port) )
|
break;
|
||||||
{
|
|
||||||
hcd_event_t event =
|
|
||||||
{
|
|
||||||
.rhport = _usbh_devices[dev_addr].rhport,
|
|
||||||
.event_id = HCD_EVENT_DEVICE_ATTACH
|
|
||||||
};
|
|
||||||
|
|
||||||
event.attach.hub_addr = dev_addr;
|
|
||||||
event.attach.hub_port = port;
|
|
||||||
|
|
||||||
hcd_event_handler(&event, true);
|
|
||||||
break; // handle one port at a time, next port if any will be handled in the next cycle
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
// NOTE: next status transfer is queued by usbh.c after handling this request
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
// TODO [HUB] check if hub is still plugged before polling status endpoint since failed usually mean hub unplugged
|
|
||||||
// TU_ASSERT ( hub_status_pipe_queue(dev_addr) );
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// NOTE: next status transfer is queued by usbh.c after handling this request
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void hub_close(uint8_t dev_addr)
|
void hub_close(uint8_t dev_addr)
|
||||||
@ -243,7 +353,8 @@ void hub_close(uint8_t dev_addr)
|
|||||||
|
|
||||||
bool hub_status_pipe_queue(uint8_t dev_addr)
|
bool hub_status_pipe_queue(uint8_t dev_addr)
|
||||||
{
|
{
|
||||||
return hcd_pipe_xfer(dev_addr, hub_data[dev_addr-1].ep_status, &hub_data[dev_addr-1].status_change, 1, true);
|
usbh_hub_t * p_hub = &hub_data[dev_addr-1];
|
||||||
|
return hcd_pipe_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -36,7 +36,7 @@
|
|||||||
#ifndef _TUSB_HUB_H_
|
#ifndef _TUSB_HUB_H_
|
||||||
#define _TUSB_HUB_H_
|
#define _TUSB_HUB_H_
|
||||||
|
|
||||||
#include <common/tusb_common.h>
|
#include "common/tusb_common.h"
|
||||||
#include "usbh.h"
|
#include "usbh.h"
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
@ -142,7 +142,7 @@ typedef struct {
|
|||||||
};
|
};
|
||||||
|
|
||||||
uint16_t value;
|
uint16_t value;
|
||||||
} status, status_change;
|
} status, change;
|
||||||
} hub_status_response_t;
|
} hub_status_response_t;
|
||||||
|
|
||||||
TU_VERIFY_STATIC( sizeof(hub_status_response_t) == 4, "size is not correct");
|
TU_VERIFY_STATIC( sizeof(hub_status_response_t) == 4, "size is not correct");
|
||||||
@ -151,30 +151,30 @@ TU_VERIFY_STATIC( sizeof(hub_status_response_t) == 4, "size is not correct");
|
|||||||
typedef struct {
|
typedef struct {
|
||||||
union {
|
union {
|
||||||
struct TU_ATTR_PACKED {
|
struct TU_ATTR_PACKED {
|
||||||
uint16_t connect_status : 1;
|
uint16_t connection : 1;
|
||||||
uint16_t port_enable : 1;
|
uint16_t port_enable : 1;
|
||||||
uint16_t suspend : 1;
|
uint16_t suspend : 1;
|
||||||
uint16_t over_current : 1;
|
uint16_t over_current : 1;
|
||||||
uint16_t reset : 1;
|
uint16_t reset : 1;
|
||||||
|
|
||||||
uint16_t : 3;
|
uint16_t : 3;
|
||||||
uint16_t port_power : 1;
|
uint16_t port_power : 1;
|
||||||
uint16_t low_speed_device_attached : 1;
|
uint16_t low_speed : 1;
|
||||||
uint16_t high_speed_device_attached : 1;
|
uint16_t high_speed : 1;
|
||||||
uint16_t port_test_mode : 1;
|
uint16_t port_test_mode : 1;
|
||||||
uint16_t port_indicator_control : 1;
|
uint16_t port_indicator_control : 1;
|
||||||
uint16_t : 0;
|
uint16_t : 0;
|
||||||
};
|
};
|
||||||
|
|
||||||
uint16_t value;
|
uint16_t value;
|
||||||
} status_current, status_change;
|
} status, change;
|
||||||
} hub_port_status_response_t;
|
} hub_port_status_response_t;
|
||||||
|
|
||||||
TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
|
TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
|
||||||
|
|
||||||
bool hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port);
|
bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb);
|
||||||
bool hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature);
|
bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb);
|
||||||
tusb_speed_t hub_port_get_speed(void);
|
bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
|
||||||
bool hub_status_pipe_queue(uint8_t dev_addr);
|
bool hub_status_pipe_queue(uint8_t dev_addr);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -182,7 +182,8 @@ bool hub_status_pipe_queue(uint8_t dev_addr);
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
void hub_init(void);
|
void hub_init(void);
|
||||||
bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
|
bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
|
||||||
void hub_isr(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
bool hub_set_config(uint8_t dev_addr, uint8_t itf_num);
|
||||||
|
bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
|
||||||
void hub_close(uint8_t dev_addr);
|
void hub_close(uint8_t dev_addr);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -306,6 +306,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// TODO move around
|
||||||
|
static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr);
|
||||||
|
static ohci_gtd_t * gtd_find_free(void);
|
||||||
|
static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd);
|
||||||
|
|
||||||
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
|
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
|
||||||
{
|
{
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
@ -329,6 +334,21 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
|
|||||||
p_ed->td_head.address = (uint32_t) p_data;
|
p_ed->td_head.address = (uint32_t) p_data;
|
||||||
|
|
||||||
OHCI_REG->command_status_bit.control_list_filled = 1;
|
OHCI_REG->command_status_bit.control_list_filled = 1;
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
ohci_ed_t * p_ed = ed_from_addr(dev_addr, ep_addr);
|
||||||
|
ohci_gtd_t* p_gtd = gtd_find_free();
|
||||||
|
|
||||||
|
TU_ASSERT(p_gtd);
|
||||||
|
|
||||||
|
gtd_init(p_gtd, buffer, buflen);
|
||||||
|
p_gtd->index = p_ed-ohci_data.ed_pool;
|
||||||
|
p_gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
|
||||||
|
|
||||||
|
td_insert_to_ed(p_ed, p_gtd);
|
||||||
|
|
||||||
|
tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_addr(dev_addr, ep_addr) );
|
||||||
|
if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
@ -337,7 +357,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// BULK/INT/ISO PIPE API
|
// BULK/INT/ISO PIPE API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
static inline ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
|
static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
|
||||||
{
|
{
|
||||||
if ( tu_edpt_number(ep_addr) == 0 ) return &ohci_data.control[dev_addr].ed;
|
if ( tu_edpt_number(ep_addr) == 0 ) return &ohci_data.control[dev_addr].ed;
|
||||||
|
|
||||||
@ -355,7 +375,7 @@ static inline ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
|
|||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline ohci_ed_t * ed_find_free(void)
|
static ohci_ed_t * ed_find_free(void)
|
||||||
{
|
{
|
||||||
ohci_ed_t* ed_pool = ohci_data.ed_pool;
|
ohci_ed_t* ed_pool = ohci_data.ed_pool;
|
||||||
|
|
||||||
@ -599,7 +619,7 @@ static void done_queue_isr(uint8_t hostid)
|
|||||||
|
|
||||||
hcd_event_xfer_complete(p_ed->dev_addr,
|
hcd_event_xfer_complete(p_ed->dev_addr,
|
||||||
tu_edpt_addr(p_ed->ep_number, p_ed->pid == OHCI_PID_IN),
|
tu_edpt_addr(p_ed->ep_number, p_ed->pid == OHCI_PID_IN),
|
||||||
event, xferred_bytes);
|
xferred_bytes, event, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
td_head = (ohci_td_item_t*) td_head->next;
|
td_head = (ohci_td_item_t*) td_head->next;
|
||||||
@ -632,10 +652,10 @@ void hcd_int_handler(uint8_t hostid)
|
|||||||
{
|
{
|
||||||
// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
|
// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
|
||||||
OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
|
OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
|
||||||
hcd_event_device_attach(0);
|
hcd_event_device_attach(hostid, true);
|
||||||
}else
|
}else
|
||||||
{
|
{
|
||||||
hcd_event_device_remove(0);
|
hcd_event_device_remove(hostid, true);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
1014
src/host/usbh.c
1014
src/host/usbh.c
File diff suppressed because it is too large
Load Diff
@ -58,11 +58,15 @@ typedef struct {
|
|||||||
|
|
||||||
uint8_t class_code;
|
uint8_t class_code;
|
||||||
|
|
||||||
void (* const init) (void);
|
void (* const init )(void);
|
||||||
bool (* const open)(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t* outlen);
|
bool (* const open )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t* outlen);
|
||||||
void (* const isr) (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t len);
|
bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
|
||||||
void (* const close) (uint8_t);
|
bool (* const xfer_cb )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
|
||||||
} host_class_driver_t;
|
void (* const close )(uint8_t dev_addr);
|
||||||
|
} usbh_class_driver_t;
|
||||||
|
|
||||||
|
typedef bool (*tuh_control_complete_cb_t)(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@ -70,6 +74,11 @@ typedef struct {
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// APPLICATION API
|
// APPLICATION API
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
// Init host stack
|
||||||
|
bool tuh_init(void);
|
||||||
|
|
||||||
|
// Task function should be called in main/rtos loop
|
||||||
void tuh_task(void);
|
void tuh_task(void);
|
||||||
|
|
||||||
// Interrupt handler, name alias to HCD
|
// Interrupt handler, name alias to HCD
|
||||||
@ -82,10 +91,12 @@ static inline bool tuh_device_is_configured(uint8_t dev_addr)
|
|||||||
return tuh_device_get_state(dev_addr) == TUSB_DEVICE_STATE_CONFIGURED;
|
return tuh_device_get_state(dev_addr) == TUSB_DEVICE_STATE_CONFIGURED;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// APPLICATION CALLBACK
|
// APPLICATION CALLBACK
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
TU_ATTR_WEAK uint8_t tuh_device_attached_cb (tusb_desc_device_t const *p_desc_device);
|
//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
|
||||||
|
|
||||||
/** Callback invoked when device is mounted (configured) */
|
/** Callback invoked when device is mounted (configured) */
|
||||||
TU_ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr);
|
TU_ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr);
|
||||||
@ -95,14 +106,19 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr);
|
|||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// CLASS-USBH & INTERNAL API
|
// CLASS-USBH & INTERNAL API
|
||||||
|
// TODO move to usbh_pvt.h
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
// Note: when using with RTOS, this should be called after scheduler/kernel is started.
|
|
||||||
// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
|
|
||||||
bool usbh_init(void);
|
|
||||||
bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data);
|
|
||||||
|
|
||||||
bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
|
bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
|
||||||
|
bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
|
||||||
|
|
||||||
|
// Claim an endpoint before submitting a transfer.
|
||||||
|
// If caller does not make any transfer, it must release endpoint for others.
|
||||||
|
bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
|
||||||
|
|
||||||
|
void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
|
||||||
|
|
||||||
|
uint8_t usbh_get_rhport(uint8_t dev_addr);
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
140
src/host/usbh_control.c
Normal file
140
src/host/usbh_control.c
Normal file
@ -0,0 +1,140 @@
|
|||||||
|
/*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020, Ha Thach (tinyusb.org)
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* This file is part of the TinyUSB stack.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "tusb_option.h"
|
||||||
|
|
||||||
|
#if TUSB_OPT_HOST_ENABLED
|
||||||
|
|
||||||
|
#include "tusb.h"
|
||||||
|
#include "usbh_hcd.h"
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
STAGE_SETUP,
|
||||||
|
STAGE_DATA,
|
||||||
|
STAGE_ACK
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
tusb_control_request_t request TU_ATTR_ALIGNED(4);
|
||||||
|
|
||||||
|
uint8_t stage;
|
||||||
|
uint8_t* buffer;
|
||||||
|
tuh_control_complete_cb_t complete_cb;
|
||||||
|
} usbh_control_xfer_t;
|
||||||
|
|
||||||
|
static usbh_control_xfer_t _ctrl_xfer;
|
||||||
|
|
||||||
|
//CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
|
||||||
|
//static uint8_t _tuh_ctrl_buf[CFG_TUSB_HOST_ENUM_BUFFER_SIZE];
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
|
||||||
|
{
|
||||||
|
// TODO need to claim the endpoint first
|
||||||
|
|
||||||
|
usbh_device_t* dev = &_usbh_devices[dev_addr];
|
||||||
|
const uint8_t rhport = dev->rhport;
|
||||||
|
|
||||||
|
_ctrl_xfer.request = (*request);
|
||||||
|
_ctrl_xfer.buffer = buffer;
|
||||||
|
_ctrl_xfer.stage = STAGE_SETUP;
|
||||||
|
_ctrl_xfer.complete_cb = complete_cb;
|
||||||
|
|
||||||
|
TU_LOG2("Control Setup: ");
|
||||||
|
TU_LOG2_VAR(request);
|
||||||
|
TU_LOG2("\r\n");
|
||||||
|
|
||||||
|
// Send setup packet
|
||||||
|
TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request) );
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
|
||||||
|
{
|
||||||
|
if (_ctrl_xfer.complete_cb) _ctrl_xfer.complete_cb(dev_addr, &_ctrl_xfer.request, result);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
|
||||||
|
{
|
||||||
|
(void) ep_addr;
|
||||||
|
(void) xferred_bytes;
|
||||||
|
|
||||||
|
usbh_device_t* dev = &_usbh_devices[dev_addr];
|
||||||
|
const uint8_t rhport = dev->rhport;
|
||||||
|
|
||||||
|
tusb_control_request_t const * request = &_ctrl_xfer.request;
|
||||||
|
|
||||||
|
if (XFER_RESULT_SUCCESS != result)
|
||||||
|
{
|
||||||
|
TU_LOG2("Control failed: result = %d\r\n", result);
|
||||||
|
|
||||||
|
// terminate transfer if any stage failed
|
||||||
|
_xfer_complete(dev_addr, result);
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
switch(_ctrl_xfer.stage)
|
||||||
|
{
|
||||||
|
case STAGE_SETUP:
|
||||||
|
_ctrl_xfer.stage = STAGE_DATA;
|
||||||
|
if (request->wLength)
|
||||||
|
{
|
||||||
|
// Note: initial data toggle is always 1
|
||||||
|
hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
__attribute__((fallthrough));
|
||||||
|
|
||||||
|
case STAGE_DATA:
|
||||||
|
_ctrl_xfer.stage = STAGE_ACK;
|
||||||
|
|
||||||
|
if (request->wLength)
|
||||||
|
{
|
||||||
|
TU_LOG2("Control data:\r\n");
|
||||||
|
TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
// data toggle is always 1
|
||||||
|
hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case STAGE_ACK:
|
||||||
|
_xfer_complete(dev_addr, result);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default: return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
@ -40,9 +40,15 @@
|
|||||||
#include "common/tusb_common.h"
|
#include "common/tusb_common.h"
|
||||||
#include "osal/osal.h"
|
#include "osal/osal.h"
|
||||||
|
|
||||||
|
#ifndef CFG_TUH_EP_MAX
|
||||||
|
#define CFG_TUH_EP_MAX 9
|
||||||
|
#endif
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// USBH-HCD common data structure
|
// USBH-HCD common data structure
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
// TODO move to usbh.c
|
||||||
typedef struct {
|
typedef struct {
|
||||||
//------------- port -------------//
|
//------------- port -------------//
|
||||||
uint8_t rhport;
|
uint8_t rhport;
|
||||||
@ -53,29 +59,40 @@ typedef struct {
|
|||||||
//------------- device descriptor -------------//
|
//------------- device descriptor -------------//
|
||||||
uint16_t vendor_id;
|
uint16_t vendor_id;
|
||||||
uint16_t product_id;
|
uint16_t product_id;
|
||||||
uint8_t configure_count; // bNumConfigurations alias
|
uint8_t ep0_packet_size;
|
||||||
|
|
||||||
//------------- configuration descriptor -------------//
|
//------------- configuration descriptor -------------//
|
||||||
uint8_t interface_count; // bNumInterfaces alias
|
// uint8_t interface_count; // bNumInterfaces alias
|
||||||
|
|
||||||
//------------- device -------------//
|
//------------- device -------------//
|
||||||
|
struct TU_ATTR_PACKED
|
||||||
|
{
|
||||||
|
uint8_t connected : 1;
|
||||||
|
uint8_t addressed : 1;
|
||||||
|
uint8_t configured : 1;
|
||||||
|
uint8_t suspended : 1;
|
||||||
|
};
|
||||||
|
|
||||||
volatile uint8_t state; // device state, value from enum tusbh_device_state_t
|
volatile uint8_t state; // device state, value from enum tusbh_device_state_t
|
||||||
|
|
||||||
//------------- control pipe -------------//
|
|
||||||
struct {
|
|
||||||
volatile uint8_t pipe_status;
|
|
||||||
// uint8_t xferred_bytes; TODO not yet necessary
|
|
||||||
tusb_control_request_t request;
|
|
||||||
|
|
||||||
osal_semaphore_def_t sem_def;
|
|
||||||
osal_semaphore_t sem_hdl; // used to synchronize with HCD when control xfer complete
|
|
||||||
|
|
||||||
osal_mutex_def_t mutex_def;
|
|
||||||
osal_mutex_t mutex_hdl; // used to exclusively occupy control pipe
|
|
||||||
} control;
|
|
||||||
|
|
||||||
uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
|
uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
|
||||||
uint8_t ep2drv[8][2]; // map endpoint to driver ( 0xff is invalid )
|
uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
|
||||||
|
|
||||||
|
struct TU_ATTR_PACKED
|
||||||
|
{
|
||||||
|
volatile bool busy : 1;
|
||||||
|
volatile bool stalled : 1;
|
||||||
|
volatile bool claimed : 1;
|
||||||
|
|
||||||
|
// TODO merge ep2drv here, 4-bit should be sufficient
|
||||||
|
}ep_status[CFG_TUH_EP_MAX][2];
|
||||||
|
|
||||||
|
// Mutex for claiming endpoint, only needed when using with preempted RTOS
|
||||||
|
#if CFG_TUSB_OS != OPT_OS_NONE
|
||||||
|
osal_mutex_def_t mutexdef;
|
||||||
|
osal_mutex_t mutex;
|
||||||
|
#endif
|
||||||
|
|
||||||
} usbh_device_t;
|
} usbh_device_t;
|
||||||
|
|
||||||
extern usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
|
extern usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
|
||||||
|
@ -218,6 +218,9 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
|||||||
void dcd_remote_wakeup(uint8_t rhport)
|
void dcd_remote_wakeup(uint8_t rhport)
|
||||||
{
|
{
|
||||||
(void)rhport;
|
(void)rhport;
|
||||||
|
|
||||||
|
// TODO must manually clear this bit after 1-15 ms
|
||||||
|
// USB0.DCTL |= USB_RMTWKUPSIG_M;
|
||||||
}
|
}
|
||||||
|
|
||||||
// connect by enabling internal pull-up resistor on D+/D-
|
// connect by enabling internal pull-up resistor on D+/D-
|
||||||
@ -670,6 +673,7 @@ static void handle_epin_ints(void)
|
|||||||
static void _dcd_int_handler(void* arg)
|
static void _dcd_int_handler(void* arg)
|
||||||
{
|
{
|
||||||
(void) arg;
|
(void) arg;
|
||||||
|
uint8_t const rhport = 0;
|
||||||
|
|
||||||
const uint32_t int_status = USB0.gintsts;
|
const uint32_t int_status = USB0.gintsts;
|
||||||
//const uint32_t int_msk = USB0.gintmsk;
|
//const uint32_t int_msk = USB0.gintmsk;
|
||||||
@ -695,7 +699,19 @@ static void _dcd_int_handler(void* arg)
|
|||||||
// the end of reset.
|
// the end of reset.
|
||||||
USB0.gintsts = USB_ENUMDONE_M;
|
USB0.gintsts = USB_ENUMDONE_M;
|
||||||
enum_done_processing();
|
enum_done_processing();
|
||||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(int_status & USB_USBSUSP_M)
|
||||||
|
{
|
||||||
|
USB0.gintsts = USB_USBSUSP_M;
|
||||||
|
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(int_status & USB_WKUPINT_M)
|
||||||
|
{
|
||||||
|
USB0.gintsts = USB_WKUPINT_M;
|
||||||
|
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (int_status & USB_OTGINT_M)
|
if (int_status & USB_OTGINT_M)
|
||||||
@ -707,7 +723,7 @@ static void _dcd_int_handler(void* arg)
|
|||||||
|
|
||||||
if (otg_int & USB_SESENDDET_M)
|
if (otg_int & USB_SESENDDET_M)
|
||||||
{
|
{
|
||||||
dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
|
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
USB0.gotgint = otg_int;
|
USB0.gotgint = otg_int;
|
||||||
@ -716,7 +732,7 @@ static void _dcd_int_handler(void* arg)
|
|||||||
#if USE_SOF
|
#if USE_SOF
|
||||||
if (int_status & USB_SOF_M) {
|
if (int_status & USB_SOF_M) {
|
||||||
USB0.gintsts = USB_SOF_M;
|
USB0.gintsts = USB_SOF_M;
|
||||||
dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually
|
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); // do nothing actually
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
477
src/portable/nxp/khci/dcd_khci.c
Normal file
477
src/portable/nxp/khci/dcd_khci.c
Normal file
@ -0,0 +1,477 @@
|
|||||||
|
/*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020 Koji Kitayama
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* This file is part of the TinyUSB stack.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "tusb_option.h"
|
||||||
|
|
||||||
|
#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX )
|
||||||
|
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
#define KHCI USB0
|
||||||
|
|
||||||
|
#include "device/dcd.h"
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
enum {
|
||||||
|
TOK_PID_OUT = 0x1u,
|
||||||
|
TOK_PID_IN = 0x9u,
|
||||||
|
TOK_PID_SETUP = 0xDu,
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct TU_ATTR_PACKED
|
||||||
|
{
|
||||||
|
union {
|
||||||
|
uint32_t head;
|
||||||
|
struct {
|
||||||
|
union {
|
||||||
|
struct {
|
||||||
|
uint16_t : 2;
|
||||||
|
uint16_t tok_pid : 4;
|
||||||
|
uint16_t data : 1;
|
||||||
|
uint16_t own : 1;
|
||||||
|
uint16_t : 8;
|
||||||
|
};
|
||||||
|
struct {
|
||||||
|
uint16_t : 2;
|
||||||
|
uint16_t bdt_stall: 1;
|
||||||
|
uint16_t dts : 1;
|
||||||
|
uint16_t ninc : 1;
|
||||||
|
uint16_t keep : 1;
|
||||||
|
uint16_t : 10;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uint16_t bc : 10;
|
||||||
|
uint16_t : 6;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uint8_t *addr;
|
||||||
|
}buffer_descriptor_t;
|
||||||
|
|
||||||
|
TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
|
||||||
|
|
||||||
|
typedef struct TU_ATTR_PACKED
|
||||||
|
{
|
||||||
|
union {
|
||||||
|
uint32_t state;
|
||||||
|
struct {
|
||||||
|
uint32_t max_packet_size :11;
|
||||||
|
uint32_t : 5;
|
||||||
|
uint32_t odd : 1;
|
||||||
|
uint32_t :15;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uint16_t length;
|
||||||
|
uint16_t remaining;
|
||||||
|
}endpoint_state_t;
|
||||||
|
|
||||||
|
TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
union {
|
||||||
|
/* [#EP][OUT,IN][EVEN,ODD] */
|
||||||
|
buffer_descriptor_t bdt[16][2][2];
|
||||||
|
uint16_t bda[512];
|
||||||
|
};
|
||||||
|
TU_ATTR_ALIGNED(4) union {
|
||||||
|
endpoint_state_t endpoint[16][2];
|
||||||
|
endpoint_state_t endpoint_unified[16 * 2];
|
||||||
|
};
|
||||||
|
uint8_t setup_packet[8];
|
||||||
|
uint8_t addr;
|
||||||
|
}dcd_data_t;
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// BDT(Buffer Descriptor Table) must be 256-byte aligned
|
||||||
|
CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
|
||||||
|
|
||||||
|
TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
|
||||||
|
|
||||||
|
static void prepare_next_setup_packet(uint8_t rhport)
|
||||||
|
{
|
||||||
|
const unsigned out_odd = _dcd.endpoint[0][0].odd;
|
||||||
|
const unsigned in_odd = _dcd.endpoint[0][1].odd;
|
||||||
|
if (_dcd.bdt[0][0][out_odd].own) {
|
||||||
|
TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
_dcd.bdt[0][0][out_odd].data = 0;
|
||||||
|
_dcd.bdt[0][0][out_odd ^ 1].data = 1;
|
||||||
|
_dcd.bdt[0][1][in_odd].data = 1;
|
||||||
|
_dcd.bdt[0][1][in_odd ^ 1].data = 0;
|
||||||
|
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||||
|
_dcd.setup_packet, sizeof(_dcd.setup_packet));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void process_stall(uint8_t rhport)
|
||||||
|
{
|
||||||
|
if (KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) {
|
||||||
|
/* clear stall condition of the control pipe */
|
||||||
|
prepare_next_setup_packet(rhport);
|
||||||
|
KHCI->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void process_tokdne(uint8_t rhport)
|
||||||
|
{
|
||||||
|
const unsigned s = KHCI->STAT;
|
||||||
|
KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
|
||||||
|
buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
|
||||||
|
endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3];
|
||||||
|
unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
|
||||||
|
|
||||||
|
/* fetch pid before discarded by the next steps */
|
||||||
|
const unsigned pid = bd->tok_pid;
|
||||||
|
/* reset values for a next transfer */
|
||||||
|
bd->bdt_stall = 0;
|
||||||
|
bd->dts = 1;
|
||||||
|
bd->ninc = 0;
|
||||||
|
bd->keep = 0;
|
||||||
|
/* update the odd variable to prepare for the next transfer */
|
||||||
|
ep->odd = odd ^ 1;
|
||||||
|
if (pid == TOK_PID_SETUP) {
|
||||||
|
dcd_event_setup_received(rhport, bd->addr, true);
|
||||||
|
KHCI->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (s >> 4) {
|
||||||
|
TU_LOG1("TKDNE %x\r\n", s);
|
||||||
|
}
|
||||||
|
|
||||||
|
const unsigned bc = bd->bc;
|
||||||
|
const unsigned remaining = ep->remaining - bc;
|
||||||
|
if (remaining && bc == ep->max_packet_size) {
|
||||||
|
/* continue the transferring consecutive data */
|
||||||
|
ep->remaining = remaining;
|
||||||
|
const int next_remaining = remaining - ep->max_packet_size;
|
||||||
|
if (next_remaining > 0) {
|
||||||
|
/* prepare to the after next transfer */
|
||||||
|
bd->addr += ep->max_packet_size * 2;
|
||||||
|
bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
|
||||||
|
__DSB();
|
||||||
|
bd->own = 1; /* the own bit must set after addr */
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
const unsigned length = ep->length;
|
||||||
|
dcd_event_xfer_complete(rhport,
|
||||||
|
((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
|
||||||
|
length - remaining, XFER_RESULT_SUCCESS, true);
|
||||||
|
if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
|
||||||
|
/* After completion a ZLP of control transfer,
|
||||||
|
* it prepares for the next steup transfer. */
|
||||||
|
if (_dcd.addr) {
|
||||||
|
/* When the transfer was the SetAddress,
|
||||||
|
* the device address should be updated here. */
|
||||||
|
KHCI->ADDR = _dcd.addr;
|
||||||
|
_dcd.addr = 0;
|
||||||
|
}
|
||||||
|
prepare_next_setup_packet(rhport);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void process_bus_reset(uint8_t rhport)
|
||||||
|
{
|
||||||
|
KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
|
||||||
|
KHCI->CTL |= USB_CTL_ODDRST_MASK;
|
||||||
|
KHCI->ADDR = 0;
|
||||||
|
KHCI->INTEN = (KHCI->INTEN & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
|
||||||
|
|
||||||
|
KHCI->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
|
||||||
|
for (unsigned i = 1; i < 16; ++i) {
|
||||||
|
KHCI->ENDPOINT[i].ENDPT = 0;
|
||||||
|
}
|
||||||
|
buffer_descriptor_t *bd = _dcd.bdt[0][0];
|
||||||
|
for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
|
||||||
|
bd->head = 0;
|
||||||
|
}
|
||||||
|
const endpoint_state_t ep0 = {
|
||||||
|
.max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
|
||||||
|
.odd = 0,
|
||||||
|
.length = 0,
|
||||||
|
.remaining = 0,
|
||||||
|
};
|
||||||
|
_dcd.endpoint[0][0] = ep0;
|
||||||
|
_dcd.endpoint[0][1] = ep0;
|
||||||
|
tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
|
||||||
|
_dcd.addr = 0;
|
||||||
|
prepare_next_setup_packet(rhport);
|
||||||
|
KHCI->CTL &= ~USB_CTL_ODDRST_MASK;
|
||||||
|
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void process_bus_inactive(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
const unsigned inten = KHCI->INTEN;
|
||||||
|
KHCI->INTEN = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
|
||||||
|
KHCI->USBCTRL |= USB_USBCTRL_SUSP_MASK;
|
||||||
|
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void process_bus_active(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
|
||||||
|
const unsigned inten = KHCI->INTEN;
|
||||||
|
KHCI->INTEN = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
|
||||||
|
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------*/
|
||||||
|
/* Device API
|
||||||
|
*------------------------------------------------------------------*/
|
||||||
|
void dcd_init(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
|
||||||
|
KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
|
||||||
|
while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
|
||||||
|
tu_memclr(&_dcd, sizeof(_dcd));
|
||||||
|
KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
|
||||||
|
KHCI->BDTPAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
|
||||||
|
KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
|
||||||
|
KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
|
||||||
|
|
||||||
|
dcd_connect(rhport);
|
||||||
|
NVIC_ClearPendingIRQ(USB0_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_int_enable(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
|
||||||
|
USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
|
||||||
|
NVIC_EnableIRQ(USB0_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_int_disable(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
NVIC_DisableIRQ(USB0_IRQn);
|
||||||
|
KHCI->INTEN = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
_dcd.addr = dev_addr & 0x7F;
|
||||||
|
/* Response with status first before changing device address */
|
||||||
|
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_remote_wakeup(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
unsigned cnt = SystemCoreClock / 100;
|
||||||
|
KHCI->CTL |= USB_CTL_RESUME_MASK;
|
||||||
|
while (cnt--) __NOP();
|
||||||
|
KHCI->CTL &= ~USB_CTL_RESUME_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_connect(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
KHCI->USBCTRL = 0;
|
||||||
|
KHCI->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
|
||||||
|
KHCI->CTL |= USB_CTL_USBENSOFEN_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_disconnect(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
KHCI->CTL = 0;
|
||||||
|
KHCI->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Endpoint API
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
|
||||||
|
const unsigned ep_addr = ep_desc->bEndpointAddress;
|
||||||
|
const unsigned epn = ep_addr & 0xFu;
|
||||||
|
const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
|
||||||
|
const unsigned xfer = ep_desc->bmAttributes.xfer;
|
||||||
|
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||||
|
const unsigned odd = ep->odd;
|
||||||
|
buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
|
||||||
|
|
||||||
|
/* No support for control transfer */
|
||||||
|
TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
|
||||||
|
|
||||||
|
ep->max_packet_size = ep_desc->wMaxPacketSize.size;
|
||||||
|
unsigned val = USB_ENDPT_EPCTLDIS_MASK;
|
||||||
|
val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
|
||||||
|
val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
|
||||||
|
KHCI->ENDPOINT[epn].ENDPT |= val;
|
||||||
|
|
||||||
|
if (xfer != TUSB_XFER_ISOCHRONOUS) {
|
||||||
|
bd[odd].dts = 1;
|
||||||
|
bd[odd].data = 0;
|
||||||
|
bd[odd ^ 1].dts = 1;
|
||||||
|
bd[odd ^ 1].data = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
|
||||||
|
const unsigned epn = ep_addr & 0xFu;
|
||||||
|
const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
|
||||||
|
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||||
|
buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
|
||||||
|
const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
|
||||||
|
KHCI->ENDPOINT[epn].ENDPT &= ~msk;
|
||||||
|
ep->max_packet_size = 0;
|
||||||
|
ep->length = 0;
|
||||||
|
ep->remaining = 0;
|
||||||
|
bd->head = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
NVIC_DisableIRQ(USB0_IRQn);
|
||||||
|
const unsigned epn = ep_addr & 0xFu;
|
||||||
|
const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
|
||||||
|
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||||
|
buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
|
||||||
|
|
||||||
|
if (bd->own) {
|
||||||
|
TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
|
||||||
|
return false; /* The last transfer has not completed */
|
||||||
|
}
|
||||||
|
ep->length = total_bytes;
|
||||||
|
ep->remaining = total_bytes;
|
||||||
|
|
||||||
|
const unsigned mps = ep->max_packet_size;
|
||||||
|
if (total_bytes > mps) {
|
||||||
|
buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
|
||||||
|
/* When total_bytes is greater than the max packet size,
|
||||||
|
* it prepares to the next transfer to avoid NAK in advance. */
|
||||||
|
next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps;
|
||||||
|
next->addr = buffer + mps;
|
||||||
|
next->own = 1;
|
||||||
|
}
|
||||||
|
bd->bc = total_bytes >= mps ? mps: total_bytes;
|
||||||
|
bd->addr = buffer;
|
||||||
|
__DSB();
|
||||||
|
bd->own = 1; /* the own bit must set after addr */
|
||||||
|
NVIC_EnableIRQ(USB0_IRQn);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
const unsigned epn = ep_addr & 0xFu;
|
||||||
|
if (0 == epn) {
|
||||||
|
KHCI->ENDPOINT[epn].ENDPT |= USB_ENDPT_EPSTALL_MASK;
|
||||||
|
} else {
|
||||||
|
const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
|
||||||
|
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||||
|
bd[0].bdt_stall = 1;
|
||||||
|
bd[1].bdt_stall = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
const unsigned epn = ep_addr & 0xFu;
|
||||||
|
const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
|
||||||
|
const unsigned odd = _dcd.endpoint[epn][dir].odd;
|
||||||
|
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||||
|
|
||||||
|
bd[odd ^ 1].own = 0;
|
||||||
|
bd[odd ^ 1].data = 1;
|
||||||
|
bd[odd ^ 1].bdt_stall = 0;
|
||||||
|
bd[odd].own = 0;
|
||||||
|
bd[odd].data = 0;
|
||||||
|
bd[odd].bdt_stall = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// ISR
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
void dcd_int_handler(uint8_t rhport)
|
||||||
|
{
|
||||||
|
(void) rhport;
|
||||||
|
|
||||||
|
uint32_t is = KHCI->ISTAT;
|
||||||
|
uint32_t msk = KHCI->INTEN;
|
||||||
|
KHCI->ISTAT = is & ~msk;
|
||||||
|
is &= msk;
|
||||||
|
if (is & USB_ISTAT_ERROR_MASK) {
|
||||||
|
/* TODO: */
|
||||||
|
uint32_t es = KHCI->ERRSTAT;
|
||||||
|
KHCI->ERRSTAT = es;
|
||||||
|
KHCI->ISTAT = is; /* discard any pending events */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (is & USB_ISTAT_USBRST_MASK) {
|
||||||
|
KHCI->ISTAT = is; /* discard any pending events */
|
||||||
|
process_bus_reset(rhport);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (is & USB_ISTAT_SLEEP_MASK) {
|
||||||
|
KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
|
||||||
|
process_bus_inactive(rhport);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (is & USB_ISTAT_RESUME_MASK) {
|
||||||
|
KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
|
||||||
|
process_bus_active(rhport);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (is & USB_ISTAT_SOFTOK_MASK) {
|
||||||
|
KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK;
|
||||||
|
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (is & USB_ISTAT_STALL_MASK) {
|
||||||
|
KHCI->ISTAT = USB_ISTAT_STALL_MASK;
|
||||||
|
process_stall(rhport);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (is & USB_ISTAT_TOKDNE_MASK) {
|
||||||
|
process_tokdne(rhport);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
@ -507,13 +507,16 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
|
|||||||
void dcd_remote_wakeup(uint8_t rhport)
|
void dcd_remote_wakeup(uint8_t rhport)
|
||||||
{
|
{
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
|
|
||||||
|
// TODO must manually clear this bit after 1-15 ms
|
||||||
|
// USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
|
||||||
|
// dev->DCTL |= USB_OTG_DCTL_RWUSIG;
|
||||||
}
|
}
|
||||||
|
|
||||||
void dcd_connect(uint8_t rhport)
|
void dcd_connect(uint8_t rhport)
|
||||||
{
|
{
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
|
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
|
||||||
|
|
||||||
dev->DCTL &= ~USB_OTG_DCTL_SDIS;
|
dev->DCTL &= ~USB_OTG_DCTL_SDIS;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -521,7 +524,6 @@ void dcd_disconnect(uint8_t rhport)
|
|||||||
{
|
{
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
|
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
|
||||||
|
|
||||||
dev->DCTL |= USB_OTG_DCTL_SDIS;
|
dev->DCTL |= USB_OTG_DCTL_SDIS;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -45,20 +45,6 @@ void dcd_init (uint8_t rhport)
|
|||||||
(void) rhport;
|
(void) rhport;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if HAS_INTERNAL_PULLUP
|
|
||||||
// Enable internal D+/D- pullup
|
|
||||||
void dcd_connect(uint8_t rhport) TU_ATTR_WEAK
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Disable internal D+/D- pullup
|
|
||||||
void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK
|
|
||||||
{
|
|
||||||
(void) rhport;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// Enable device interrupt
|
// Enable device interrupt
|
||||||
void dcd_int_enable (uint8_t rhport)
|
void dcd_int_enable (uint8_t rhport)
|
||||||
{
|
{
|
||||||
|
@ -43,7 +43,7 @@ bool tusb_init(void)
|
|||||||
if (_initialized) return true;
|
if (_initialized) return true;
|
||||||
|
|
||||||
#if TUSB_OPT_HOST_ENABLED
|
#if TUSB_OPT_HOST_ENABLED
|
||||||
TU_ASSERT( usbh_init() ); // init host stack
|
TU_ASSERT( tuh_init() ); // init host stack
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if TUSB_OPT_DEVICE_ENABLED
|
#if TUSB_OPT_DEVICE_ENABLED
|
||||||
@ -52,7 +52,7 @@ bool tusb_init(void)
|
|||||||
|
|
||||||
_initialized = true;
|
_initialized = true;
|
||||||
|
|
||||||
return TUSB_ERROR_NONE;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool tusb_inited(void)
|
bool tusb_inited(void)
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
#define _TUSB_OPTION_H_
|
#define _TUSB_OPTION_H_
|
||||||
|
|
||||||
#define TUSB_VERSION_MAJOR 0
|
#define TUSB_VERSION_MAJOR 0
|
||||||
#define TUSB_VERSION_MINOR 5
|
#define TUSB_VERSION_MINOR 7
|
||||||
#define TUSB_VERSION_REVISION 0
|
#define TUSB_VERSION_REVISION 0
|
||||||
#define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
|
#define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
|
||||||
|
|
||||||
@ -97,6 +97,10 @@
|
|||||||
// Dialog
|
// Dialog
|
||||||
#define OPT_MCU_DA1469X 1000 ///< Dialog Semiconductor DA1469x
|
#define OPT_MCU_DA1469X 1000 ///< Dialog Semiconductor DA1469x
|
||||||
|
|
||||||
|
// NXP Kinetis
|
||||||
|
#define OPT_MCU_MKL25ZXX 1100 ///< NXP MKL25Zxx
|
||||||
|
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/** \defgroup group_supported_os Supported RTOS
|
/** \defgroup group_supported_os Supported RTOS
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user