Embedded/tinyusb
1
0
Fork 0
mirror of https://github.com/hathach/tinyusb.git synced 2025-01-31 05:52:55 +08:00
Code Issues Packages Projects Releases Wiki Activity

moving lpc17xx to use lpcopen

Browse Source
This commit is contained in:
hathach 2018-12-03 17:28:38 +07:00
parent f898f8f7a4
commit 5f10584983
No known key found for this signature in database
GPG Key ID: 2FA891220FBFD581
97 changed files with 31929 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
examples/device/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject
View File

@ -19,8 +19,8 @@
arm_target_device_name="LPC1769"
arm_target_interface_type="SWD"
build_treat_warnings_as_errors="No"
c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;BOARD_LPCXPRESSO1769;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X"
c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/CMSIS_CORE_LPC17xx/inc;$(lpcDir)/LPC17xx_DriverLib/include"
c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1769;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X"
c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc"
debug_register_definition_file="LPC176x5x_Registers.xml"
debug_target_connection="J-Link"
gcc_enable_all_warnings="Yes"
@ -29,7 +29,7 @@
linker_memory_map_file="LPC1769_MemoryMap.xml"
linker_section_placement_file="flash_placement.xml"
linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000"
macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc175x_6x"
macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_175x_6x"
project_directory=""
project_type="Executable"
target_reset_script="Reset();"
@ -52,22 +52,34 @@
</folder>
<folder Name="mcu">
<folder Name="nxp">
<folder Name="lpc175x_6x">
<folder Name="CMSIS_CORE_LPC17xx">
<folder Name="inc">
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h" />
</folder>
<folder Name="src">
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c" />
</folder>
<folder Name="lpc_chip_175x_6x">
<folder Name="inc">
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/clock_17xx_40xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis_175x_6x.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cm3.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmFunc.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmInstr.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/lpc_types.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/sys_config.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/inc/uart_17xx_40xx.h" />
</folder>
<folder Name="LPC17xx_DriverLib">
<folder Name="include" />
<folder Name="source">
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_gpio.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_pinsel.c" />
</folder>
<folder Name="src">
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/chip_17xx_40xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/clock_17xx_40xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc_chip_175x_6x/src/uart_17xx_40xx.c" />
</folder>
</folder>
</folder>

82
hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
View File

@ -36,19 +36,12 @@
*/
/**************************************************************************/
#include "bsp/board.h"
#ifdef BOARD_LPCXPRESSO1769
#include "LPC17xx.h"
#include "lpc17xx_clkpwr.h"
#include "lpc17xx_gpio.h"
#include "lpc17xx_uart.h"
#include "lpc17xx_pinsel.h"
#include "bsp/board.h"
#include "tusb.h"
#define BOARD_LED0_PORT (0)
#define LED_PORT 0
static const struct {
uint8_t port;
@ -70,22 +63,69 @@ enum {
#define BOARD_UART_PORT LPC_UART3
/* Pin muxing configuration */
static const PINMUX_GRP_T pinmuxing[] = {
{0, 0, IOCON_MODE_INACT | IOCON_FUNC2}, /* TXD3 */
{0, 1, IOCON_MODE_INACT | IOCON_FUNC2}, /* RXD3 */
{0, 4, IOCON_MODE_INACT | IOCON_FUNC2}, /* CAN-RD2 */
{0, 5, IOCON_MODE_INACT | IOCON_FUNC2}, /* CAN-TD2 */
{0, 22, IOCON_MODE_INACT | IOCON_FUNC0}, /* Led 0 */
{0, 23, IOCON_MODE_INACT | IOCON_FUNC1}, /* ADC 0 */
{0, 26, IOCON_MODE_INACT | IOCON_FUNC2}, /* DAC */
/* ENET */
{0x1, 0, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_TXD0 */
{0x1, 1, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_TXD1 */
{0x1, 4, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_TX_EN */
{0x1, 8, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_CRS */
{0x1, 9, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_RXD0 */
{0x1, 10, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_RXD1 */
{0x1, 14, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_RX_ER */
{0x1, 15, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_REF_CLK */
{0x1, 16, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_MDC */
{0x1, 17, IOCON_MODE_INACT | IOCON_FUNC1}, /* ENET_MDIO */
{0x1, 27, IOCON_MODE_INACT | IOCON_FUNC1}, /* CLKOUT */
/* Joystick buttons. */
{2, 3, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_UP */
{0, 15, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_DOWN */
{2, 4, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_LEFT */
{0, 16, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_RIGHT */
{0, 17, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_PRESS */
};
/* System oscillator rate and RTC oscillator rate */
const uint32_t OscRateIn = 12000000;
const uint32_t RTCOscRateIn = 32768;
// Invoked by startup code
void SystemInit(void)
{
/* Enable IOCON clock */
Chip_IOCON_Init(LPC_IOCON);
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
Chip_SetupXtalClocking();
}
void board_init(void)
{
SystemInit();
SystemCoreClockUpdate();
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
#if CFG_TUSB_OS == OPT_OS_NONE
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
Chip_GPIO_Init(LPC_GPIO);
//------------- LED -------------//
GPIO_SetDir(BOARD_LED0_PORT, BIT_(BOARD_LED0), 1);
Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, BOARD_LED0);
//------------- BUTTON -------------//
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
#if TUSB_OPT_DEVICE_ENABLED
//------------- USB Device -------------//
@ -149,14 +189,7 @@ uint32_t tusb_hal_millis(void)
void board_led_control(uint32_t id, bool state)
{
(void) id;
if (state)
{
GPIO_SetValue(BOARD_LED0_PORT, BIT_(BOARD_LED0));
}else
{
GPIO_ClearValue(BOARD_LED0_PORT, BIT_(BOARD_LED0));
}
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, BOARD_LED0, state);
}
//--------------------------------------------------------------------+
@ -164,14 +197,15 @@ void board_led_control(uint32_t id, bool state)
//--------------------------------------------------------------------+
static bool button_read(uint8_t id)
{
return !BIT_TEST_( GPIO_ReadValue(buttons[id].port), buttons[id].pin ); // button is active low
// return !BIT_TEST_( GPIO_ReadValue(buttons[id].port), buttons[id].pin ); // button is active low
return false;
}
uint32_t board_buttons(void)
{
uint32_t result = 0;
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
return result;
}

4
hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h
View File

@ -39,12 +39,12 @@
#ifndef _TUSB_BOARD_LPCXPRESSO1769_H_
#define _TUSB_BOARD_LPCXPRESSO1769_H_
#include "LPC17xx.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "chip.h"
#define BOARD_LED_NUM 1
#define BOARD_LED0 22

263
hw/mcu/nxp/lpc_chip_175x_6x/inc/adc_17xx_40xx.h Normal file
View File

@ -0,0 +1,263 @@
/*
* @brief LPC17xx/40xx A/D conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ADC_17XX_40XX_H_
#define __ADC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ADC_17XX_40XX CHIP: LPC17xx/40xx A/D conversion driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#define ADC_ACC_12BITS
#define ADC_TRIM_SUPPORT
#if defined(CHIP_LPC175X_6X)
#define ADC_MAX_SAMPLE_RATE 200000
#else
#define ADC_MAX_SAMPLE_RATE 400000
#endif
/**
* @brief 10 or 12-bit ADC register block structure
*/
typedef struct { /*!< ADCn Structure */
__IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
__I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__I uint32_t RESERVED0;
__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
__I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
__I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
#if defined(ADC_TRIM_SUPPORT)
__IO uint32_t ADTRM;
#endif
} LPC_ADC_T;
/**
* @brief ADC register support bitfields and mask
*/
#if defined(ADC_ACC_12BITS)
#define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Mask for getting the 12 bits ADC data read value */
#else
#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
#endif
#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */
#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */
#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */
#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
#if defined(ADC_ACC_12BITS)
#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF))
#else
#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
#endif
/**
* @brief ADC status register used for IP drivers
*/
typedef enum IP_ADC_STATUS {
ADC_DR_DONE_STAT, /*!< ADC data register staus */
ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
ADC_DR_ADINT_STAT /*!< ADC interrupt status */
} ADC_STATUS_T;
/** The channels on one ADC peripheral*/
typedef enum CHIP_ADC_CHANNEL {
ADC_CH0 = 0, /**< ADC channel 0 */
ADC_CH1, /**< ADC channel 1 */
ADC_CH2, /**< ADC channel 2 */
ADC_CH3, /**< ADC channel 3 */
ADC_CH4, /**< ADC channel 4 */
ADC_CH5, /**< ADC channel 5 */
ADC_CH6, /**< ADC channel 6 */
ADC_CH7, /**< ADC channel 7 */
} ADC_CHANNEL_T;
/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
typedef enum CHIP_ADC_EDGE_CFG {
ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */
ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */
} ADC_EDGE_CFG_T;
/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
typedef enum CHIP_ADC_START_MODE {
ADC_NO_START = 0,
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
} ADC_START_MODE_T;
/** Clock setup structure for ADC controller passed to the initialize function */
typedef struct {
uint32_t adcRate; /*!< ADC rate */
uint8_t bitsAccuracy; /*!< ADC bit accuracy */
bool burstMode; /*!< ADC Burt Mode */
} ADC_CLOCK_SETUP_T;
/**
* @brief Initialize the ADC peripheral and the ADC setup structure to default value
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be set
* @return Nothing
* @note Default setting for ADC is 400kHz - 10bits
*/
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
/**
* @brief Shutdown ADC
* @param pADC : The base of ADC peripheral on the chip
* @return Nothing
*/
void Chip_ADC_DeInit(LPC_ADC_T *pADC);
/**
* @brief Read the ADC value from a channel
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param data : Pointer to where to put data
* @return SUCCESS or ERROR if no conversion is ready
*/
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
/**
* @brief Read the ADC value and convert it to 8bits value
* @param pADC : The base of ADC peripheral on the chip
* @param channel: selected channel
* @param data : Storage for data
* @return Status : ERROR or SUCCESS
*/
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
/**
* @brief Read the ADC channel status
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param StatusType : Status type of ADC_DR_*
* @return SET or RESET
*/
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
/**
* @brief Enable/Disable interrupt for ADC channel
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param NewState : New state, ENABLE or DISABLE
* @return SET or RESET
*/
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
/**
* @brief Enable/Disable global interrupt for ADC channel
* @param pADC : The base of ADC peripheral on the chip
* @param NewState : New state, ENABLE or DISABLE
* @return Nothing
*/
STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
}
/**
* @brief Select the mode starting the AD conversion
* @param pADC : The base of ADC peripheral on the chip
* @param mode : Stating mode, should be :
* - ADC_NO_START : Must be set for Burst mode
* - ADC_START_NOW : Start conversion now
* - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
* - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
* - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
* - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
* - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
* @param EdgeOption : Stating Edge Condition, should be :
* - ADC_TRIGGERMODE_RISING : Trigger event on rising edge
* - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge
* @return Nothing
*/
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
/**
* @brief Set the ADC Sample rate
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be modified
* @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
* @return Nothing
*/
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
/**
* @brief Enable or disable the ADC channel on ADC peripheral
* @param pADC : The base of ADC peripheral on the chip
* @param channel : Channel to be enable or disable
* @param NewState : New state, should be:
* - ENABLE
* - DISABLE
* @return Nothing
*/
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
/**
* @brief Enable burst mode
* @param pADC : The base of ADC peripheral on the chip
* @param NewState : New state, should be:
* - ENABLE
* - DISABLE
* @return Nothing
*/
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ADC_17XX_40XX_H_ */

1130
hw/mcu/nxp/lpc_chip_175x_6x/inc/can_17xx_40xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

152
hw/mcu/nxp/lpc_chip_175x_6x/inc/chip.h Normal file
View File

@ -0,0 +1,152 @@
/*
* @brief LPC17xx/LPC40xx basic chip inclusion file
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CHIP_H_
#define __CHIP_H_
#include "lpc_types.h"
#include "sys_config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @ingroup CHIP_17XX_40XX_DRIVER_OPTIONS
* @{
*/
/**
* @brief System oscillator rate
* This value is defined externally to the chip layer and contains
* the value in Hz for the external oscillator for the board. If using the
* internal oscillator, this rate can be 0.
*/
extern const uint32_t OscRateIn;
/**
* @brief RTC oscillator rate
* This value is defined externally to the chip layer and contains
* the value in Hz for the RTC oscillator for the board. This is
* usually 32KHz (32768). If not using the RTC, this rate can be 0.
*/
extern const uint32_t RTCOscRateIn;
/**
* @}
*/
/** @defgroup SUPPORT_17XX_40XX_FUNC CHIP: LPC17xx/40xx support functions
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief Current system clock rate, mainly used for sysTick
*/
extern uint32_t SystemCoreClock;
/**
* @brief Update system core clock rate, should be called if the
* system has a clock rate change
* @return None
*/
void SystemCoreClockUpdate(void);
/**
* @brief Set up and initialize hardware prior to call to main()
* @return None
* @note Chip_SystemInit() is called prior to the application and sets up
* system clocking prior to the application starting.
*/
void Chip_SystemInit(void);
/**
* @brief USB Pin and clock initialization
* Calling this function will initialize the USB pins and the clock
* @return None
* @note This function will assume that the chip is clocked by an
* external crystal oscillator of frequency 12MHz and the Oscillator
* is running.
*/
void Chip_USB_Init(void);
/**
* @brief Clock and PLL initialization based on the external oscillator
* @return None
* @note This function assumes an external crystal oscillator
* frequency of 12MHz.
*/
void Chip_SetupXtalClocking(void);
/**
* @brief Clock and PLL initialization based on the internal oscillator
* @return None
*/
void Chip_SetupIrcClocking(void);
/**
* @}
*/
#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X)
#ifndef CORE_M3
#error CORE_M3 is not defined for the LPC17xx architecture
#error CORE_M3 should be defined as part of your compiler define list
#endif
#elif defined(CHIP_LPC40XX)
#ifndef CORE_M4
#error CORE_M4 is not defined for the LPC40xx architecture
#error CORE_M4 should be defined as part of your compiler define list
#endif
#elif defined(CHIP_LPC40XX)
#error CHIP_LPC175X_6X/CHIP_LPC177X_8X/CHIP_LPC40XX is not defined!
#endif
#if defined(CHIP_LPC175X_6X)
#include "chip_lpc175x_6x.h"
#elif defined(CHIP_LPC177X_8X)
#include "chip_lpc177x_8x.h"
#elif defined(CHIP_LPC40XX)
#include "chip_lpc407x_8x.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CHIP_H_ */

190
hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h Normal file
View File

@ -0,0 +1,190 @@
/*
* @brief LPC175x/6x basic chip inclusion file
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CHIP_LPC175X_6X_H_
#define __CHIP_LPC175X_6X_H_
#include "lpc_types.h"
#include "sys_config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(CORE_M3)
#error CORE_M3 is not defined for the LPC175x/6x architecture
#error CORE_M3 should be defined as part of your compiler define list
#endif
#ifndef CHIP_LPC175X_6X
#error CHIP_LPC175X_6X is not defined!
#endif
/** @defgroup PERIPH_175X_6X_BASE CHIP: LPC175x/6x Peripheral addresses and register set declarations
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#define LPC_GPIO0_BASE 0x2009C000
#define LPC_GPIO1_BASE 0x2009C020
#define LPC_GPIO2_BASE 0x2009C040
#define LPC_GPIO3_BASE 0x2009C060
#define LPC_GPIO4_BASE 0x2009C080
/* APB0 peripheral */
#define LPC_WWDT_BASE 0x40000000
#define LPC_TIMER0_BASE 0x40004000
#define LPC_TIMER1_BASE 0x40008000
#define LPC_UART0_BASE 0x4000C000
#define LPC_UART1_BASE 0x40010000
#define LPC_PWM1_BASE 0x40018000
#define LPC_I2C0_BASE 0x4001C000
#define LPC_SPI_BASE 0x40020000
#define LPC_RTC_BASE 0x40024000
#define LPC_REGFILE_BASE 0x40024044
#define LPC_GPIOINT_BASE 0x40028080
#define LPC_IOCON_BASE 0x4002C000
#define LPC_SSP1_BASE 0x40030000
#define LPC_ADC_BASE 0x40034000
#define LPC_CANAF_RAM_BASE 0x40038000
#define LPC_CANAF_BASE 0x4003C000
#define LPC_CANCR_BASE 0x40040000
#define LPC_CAN1_BASE 0x40044000
#define LPC_CAN2_BASE 0x40048000
#define LPC_I2C1_BASE 0x4005C000
/* APB1 peripheral */
#define LPC_FMC_BASE 0x40084000
#define LPC_SSP0_BASE 0x40088000
#define LPC_DAC_BASE 0x4008C000
#define LPC_TIMER2_BASE 0x40090000
#define LPC_TIMER3_BASE 0x40094000
#define LPC_UART2_BASE 0x40098000
#define LPC_UART3_BASE 0x4009C000
#define LPC_I2C2_BASE 0x400A0000
#define LPC_I2S_BASE 0x400A8000
#define LPC_RITIMER_BASE 0x400B0000
#define LPC_MCPWM_BASE 0x400B8000
#define LPC_QEI_BASE 0x400BC000
#define LPC_SYSCTL_BASE 0x400FC000
#define LPC_PMU_BASE 0x400FC0C0
/* AHB peripheral */
#define LPC_ENET_BASE 0x50000000
#define LPC_GPDMA_BASE 0x50004000
#define LPC_USB_BASE 0x5000C000
/* Assign LPC_* names to structures mapped to addresses */
#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
#define LPC_USB ((LPC_USB_T *) LPC_USB_BASE)
#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ENET_BASE)
#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO0_BASE)
#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
#define LPC_GPIOINT ((LPC_GPIOINT_T *) LPC_GPIOINT_BASE)
#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
#define LPC_UART0 ((LPC_USART_T *) LPC_UART0_BASE)
#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
#define LPC_UART2 ((LPC_USART_T *) LPC_UART2_BASE)
#define LPC_UART3 ((LPC_USART_T *) LPC_UART3_BASE)
#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE)
#define LPC_I2S ((LPC_I2S_T *) LPC_I2S_BASE)
#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
#define LPC_SYSCON ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_T *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF ((LPC_CANAF_T *) LPC_CANAF_BASE)
#define LPC_CANCR ((LPC_CANCR_T *) LPC_CANCR_BASE)
#define LPC_CAN1 ((LPC_CAN_T *) LPC_CAN1_BASE)
#define LPC_CAN2 ((LPC_CAN_T *) LPC_CAN2_BASE)
#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
#define LPC_FMC ((LPC_FMC_T *) LPC_FMC_BASE)
/* IRQ Handler Alias list */
#define UART_IRQHandler UART0_IRQHandler
#define I2C_IRQHandler I2C0_IRQHandler
#define SSP_IRQHandler SSP0_IRQHandler
/**
* @}
*/
#include "sysctl_17xx_40xx.h"
#include "clock_17xx_40xx.h"
#include "iocon_17xx_40xx.h"
#include "adc_17xx_40xx.h"
#include "can_17xx_40xx.h"
#include "dac_17xx_40xx.h"
#include "enet_17xx_40xx.h"
#include "gpdma_17xx_40xx.h"
#include "gpio_17xx_40xx.h"
#include "gpioint_17xx_40xx.h"
#include "i2c_17xx_40xx.h"
#include "i2s_17xx_40xx.h"
#include "mcpwm_17xx_40xx.h"
#include "pmu_17xx_40xx.h"
#include "qei_17xx_40xx.h"
#include "ritimer_17xx_40xx.h"
#include "rtc_17xx_40xx.h"
#include "spi_17xx_40xx.h"
#include "ssp_17xx_40xx.h"
#include "timer_17xx_40xx.h"
#include "uart_17xx_40xx.h"
#include "usb_17xx_40xx.h"
#include "wwdt_17xx_40xx.h"
#include "fmc_17xx_40xx.h"
#include "romapi_17xx_40xx.h"
/* FIXME : PWM drivers */
#ifdef __cplusplus
}
#endif
#endif /* __CHIP_LPC175X_6X_H_ */

203
hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h Normal file
View File

@ -0,0 +1,203 @@
/*
* @brief LPC177x/8x basic chip inclusion file
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CHIP_LPC177X_8X_H_
#define __CHIP_LPC177X_8X_H_
#include "lpc_types.h"
#include "sys_config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(CORE_M3)
#error CORE_M3 is not defined for the LPC177x/8x architecture
#error CORE_M3 should be defined as part of your compiler define list
#endif
#ifndef CHIP_LPC177X_8X
#error CHIP_LPC177X_8X is not defined!
#endif
/** @defgroup PERIPH_177X_8X_BASE CHIP: LPC177x/8x Peripheral addresses and register set declarations
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#define LPC_FMC_BASE 0x00200000
#define LPC_EEPROM_BASE 0x00200080
#define LPC_GPDMA_BASE 0x20080000
#define LPC_ENET_BASE 0x20084000
#define LPC_LCD_BASE 0x20088000
#define LPC_USB_BASE 0x2008C000
#define LPC_CRC_BASE 0x20090000
#define LPC_SPIFI_BASE 0x20094000
#define LPC_GPIO0_BASE 0x20098000
#define LPC_GPIO1_BASE 0x20098020
#define LPC_GPIO2_BASE 0x20098040
#define LPC_GPIO3_BASE 0x20098060
#define LPC_GPIO4_BASE 0x20098080
#define LPC_GPIO5_BASE 0x200980A0
#define LPC_EMC_BASE 0x2009C000
#define LPC_RTC_BASE 0x40024000
#define LPC_REGFILE_BASE 0x40024044
#define LPC_WWDT_BASE 0x40000000
#define LPC_UART0_BASE 0x4000C000
#define LPC_UART1_BASE 0x40010000
#define LPC_UART2_BASE 0x40098000
#define LPC_UART3_BASE 0x4009C000
#define LPC_UART4_BASE 0x400A4000
#define LPC_SSP0_BASE 0x40088000
#define LPC_SSP1_BASE 0x40030000
#define LPC_SSP2_BASE 0x400AC000
#define LPC_TIMER0_BASE 0x40004000
#define LPC_TIMER1_BASE 0x40008000
#define LPC_TIMER2_BASE 0x40090000
#define LPC_TIMER3_BASE 0x40094000
#define LPC_MCPWM_BASE 0x400B8000
#define LPC_PWM0_BASE 0x40014000
#define LPC_PWM1_BASE 0x40018000
#define LPC_I2C0_BASE 0x4001C000
#define LPC_I2C1_BASE 0x4005C000
#define LPC_I2C2_BASE 0x400A0000
#define LPC_I2S_BASE 0x400A8000
#define LPC_CANAF_RAM_BASE 0x40038000
#define LPC_CANAF_BASE 0x4003C000
#define LPC_CANCR_BASE 0x40040000
#define LPC_CAN1_BASE 0x40044000
#define LPC_CAN2_BASE 0x40048000
#define LPC_QEI_BASE 0x400BC000
#define LPC_DAC_BASE 0x4008C000
#define LPC_ADC_BASE 0x40034000
#define LPC_GPIOINT_BASE 0x40028080
#define LPC_IOCON_BASE 0x4002C000
#define LPC_SDC_BASE 0x400C0000
#define LPC_SYSCTL_BASE 0x400FC000
#define LPC_PMU_BASE 0x400FC0C0
/* Assign LPC_* names to structures mapped to addresses */
#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
#define LPC_USB ((LPC_USB_T *) LPC_USB_BASE)
#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ENET_BASE)
#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO0_BASE)
#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
#define LPC_GPIOINT ((LPC_GPIOINT_T *) LPC_GPIOINT_BASE)
#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
#define LPC_UART0 ((LPC_USART_T *) LPC_UART0_BASE)
#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
#define LPC_UART2 ((LPC_USART_T *) LPC_UART2_BASE)
#define LPC_UART3 ((LPC_USART_T *) LPC_UART3_BASE)
#define LPC_UART4 ((LPC_USART_T *) LPC_UART4_BASE)
#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
#define LPC_SSP2 ((LPC_SSP_T *) LPC_SSP2_BASE)
#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE)
#define LPC_I2S ((LPC_I2S_T *) LPC_I2S_BASE)
#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
#define LPC_SDC ((LPC_SDC_T *) LPC_SDC_BASE)
#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
#define LPC_SYSCON ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_T *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF ((LPC_CANAF_T *) LPC_CANAF_BASE)
#define LPC_CANCR ((LPC_CANCR_T *) LPC_CANCR_BASE)
#define LPC_CAN1 ((LPC_CAN_T *) LPC_CAN1_BASE)
#define LPC_CAN2 ((LPC_CAN_T *) LPC_CAN2_BASE)
#define LPC_CRC ((LPC_CRC_T *) LPC_CRC_BASE)
#define LPC_FMC ((LPC_FMC_T *) LPC_FMC_BASE)
/* IRQ Handler Alias list */
#define UART_IRQHandler UART0_IRQHandler
#define I2C_IRQHandler I2C0_IRQHandler
#define SSP_IRQHandler SSP0_IRQHandler
/**
* @}
*/
#include "sysctl_17xx_40xx.h"
#include "clock_17xx_40xx.h"
#include "iocon_17xx_40xx.h"
#include "adc_17xx_40xx.h"
#include "can_17xx_40xx.h"
#include "crc_17xx_40xx.h"
#include "dac_17xx_40xx.h"
#include "eeprom_17xx_40xx.h"
#include "emc_17xx_40xx.h"
#include "enet_17xx_40xx.h"
#include "gpdma_17xx_40xx.h"
#include "gpio_17xx_40xx.h"
#include "gpioint_17xx_40xx.h"
#include "i2c_17xx_40xx.h"
#include "i2s_17xx_40xx.h"
#include "lcd_17xx_40xx.h"
#include "mcpwm_17xx_40xx.h"
#include "pmu_17xx_40xx.h"
#include "qei_17xx_40xx.h"
#include "rtc_17xx_40xx.h"
#include "sdc_17xx_40xx.h"
#include "sdmmc_17xx_40xx.h"
#include "ssp_17xx_40xx.h"
#include "timer_17xx_40xx.h"
#include "uart_17xx_40xx.h"
#include "usb_17xx_40xx.h"
#include "wwdt_17xx_40xx.h"
#include "fmc_17xx_40xx.h"
#include "romapi_17xx_40xx.h"
/* FIXME - missing PWM and possibly CREG drivers */
#ifdef __cplusplus
}
#endif
#endif /* __CHIP_LPC177X_8X_H_ */

206
hw/mcu/nxp/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h Normal file
View File

@ -0,0 +1,206 @@
/*
* @brief LPC407x/8x basic chip inclusion file
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CHIP_LPC40XX_H_
#define __CHIP_LPC40XX_H_
#include "lpc_types.h"
#include "sys_config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(CORE_M4)
#error CORE_M4 is not defined for the LPC407x/8x architecture
#error CORE_M4 should be defined as part of your compiler define list
#endif
#ifndef CHIP_LPC40XX
#error CHIP_LPC40XX is not defined!
#endif
/** @defgroup PERIPH_407X_8X_BASE CHIP: LPC407x/8x Peripheral addresses and register set declarations
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#define LPC_FMC_BASE 0x00200000
#define LPC_EEPROM_BASE 0x00200080
#define LPC_GPDMA_BASE 0x20080000
#define LPC_ENET_BASE 0x20084000
#define LPC_LCD_BASE 0x20088000
#define LPC_USB_BASE 0x2008C000
#define LPC_CRC_BASE 0x20090000
#define LPC_SPIFI_BASE 0x20094000
#define LPC_GPIO0_BASE 0x20098000
#define LPC_GPIO1_BASE 0x20098020
#define LPC_GPIO2_BASE 0x20098040
#define LPC_GPIO3_BASE 0x20098060
#define LPC_GPIO4_BASE 0x20098080
#define LPC_GPIO5_BASE 0x200980A0
#define LPC_EMC_BASE 0x2009C000
#define LPC_RTC_BASE 0x40024000
#define LPC_REGFILE_BASE 0x40024044
#define LPC_WWDT_BASE 0x40000000
#define LPC_UART0_BASE 0x4000C000
#define LPC_UART1_BASE 0x40010000
#define LPC_UART2_BASE 0x40098000
#define LPC_UART3_BASE 0x4009C000
#define LPC_UART4_BASE 0x400A4000
#define LPC_SSP0_BASE 0x40088000
#define LPC_SSP1_BASE 0x40030000
#define LPC_SSP2_BASE 0x400AC000
#define LPC_TIMER0_BASE 0x40004000
#define LPC_TIMER1_BASE 0x40008000
#define LPC_TIMER2_BASE 0x40090000
#define LPC_TIMER3_BASE 0x40094000
#define LPC_MCPWM_BASE 0x400B8000
#define LPC_PWM0_BASE 0x40014000
#define LPC_PWM1_BASE 0x40018000
#define LPC_I2C0_BASE 0x4001C000
#define LPC_I2C1_BASE 0x4005C000
#define LPC_I2C2_BASE 0x400A0000
#define LPC_I2S_BASE 0x400A8000
#define LPC_CANAF_RAM_BASE 0x40038000
#define LPC_CANAF_BASE 0x4003C000
#define LPC_CANCR_BASE 0x40040000
#define LPC_CAN1_BASE 0x40044000
#define LPC_CAN2_BASE 0x40048000
#define LPC_QEI_BASE 0x400BC000
#define LPC_DAC_BASE 0x4008C000
#define LPC_ADC_BASE 0x40034000
#define LPC_GPIOINT_BASE 0x40028080
#define LPC_IOCON_BASE 0x4002C000
#define LPC_SDC_BASE 0x400C0000
#define LPC_SYSCTL_BASE 0x400FC000
#define LPC_CMP_BASE 0x40020000
#define LPC_PMU_BASE 0x400FC0C0
/* Assign LPC_* names to structures mapped to addresses */
#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
#define LPC_USB ((LPC_USB_T *) LPC_USB_BASE)
#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ENET_BASE)
#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO0_BASE)
#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
#define LPC_GPIOINT ((LPC_GPIOINT_T *) LPC_GPIOINT_BASE)
#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
#define LPC_UART0 ((LPC_USART_T *) LPC_UART0_BASE)
#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
#define LPC_UART2 ((LPC_USART_T *) LPC_UART2_BASE)
#define LPC_UART3 ((LPC_USART_T *) LPC_UART3_BASE)
#define LPC_UART4 ((LPC_USART_T *) LPC_UART4_BASE)
#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
#define LPC_SSP2 ((LPC_SSP_T *) LPC_SSP2_BASE)
#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
#define LPC_I2C2 ((LPC_I2C_T *) LPC_I2C2_BASE)
#define LPC_I2S ((LPC_I2S_T *) LPC_I2S_BASE)
#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
#define LPC_SDC ((LPC_SDC_T *) LPC_SDC_BASE)
#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
#define LPC_SYSCON ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
#define LPC_CMP ((LPC_CMP_T *) LPC_CMP_BASE)
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_T *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF ((LPC_CANAF_T *) LPC_CANAF_BASE)
#define LPC_CANCR ((LPC_CANCR_T *) LPC_CANCR_BASE)
#define LPC_CAN1 ((LPC_CAN_T *) LPC_CAN1_BASE)
#define LPC_CAN2 ((LPC_CAN_T *) LPC_CAN2_BASE)
#define LPC_CRC ((LPC_CRC_T *) LPC_CRC_BASE)
#define LPC_FMC ((LPC_FMC_T *) LPC_FMC_BASE)
/* IRQ Handler Alias list */
#define UART_IRQHandler UART0_IRQHandler
#define I2C_IRQHandler I2C0_IRQHandler
#define SSP_IRQHandler SSP0_IRQHandler
/**
* @}
*/
#include "sysctl_17xx_40xx.h"
#include "clock_17xx_40xx.h"
#include "iocon_17xx_40xx.h"
#include "adc_17xx_40xx.h"
#include "can_17xx_40xx.h"
#include "cmp_17xx_40xx.h"
#include "crc_17xx_40xx.h"
#include "dac_17xx_40xx.h"
#include "eeprom_17xx_40xx.h"
#include "emc_17xx_40xx.h"
#include "enet_17xx_40xx.h"
#include "gpdma_17xx_40xx.h"
#include "gpio_17xx_40xx.h"
#include "gpioint_17xx_40xx.h"
#include "i2c_17xx_40xx.h"
#include "i2s_17xx_40xx.h"
#include "lcd_17xx_40xx.h"
#include "pmu_17xx_40xx.h"
#include "mcpwm_17xx_40xx.h"
#include "qei_17xx_40xx.h"
#include "rtc_17xx_40xx.h"
#include "sdc_17xx_40xx.h"
#include "sdmmc_17xx_40xx.h"
#include "spifi_17xx_40xx.h"
#include "ssp_17xx_40xx.h"
#include "timer_17xx_40xx.h"
#include "uart_17xx_40xx.h"
#include "usb_17xx_40xx.h"
#include "wwdt_17xx_40xx.h"
#include "fmc_17xx_40xx.h"
#include "romapi_17xx_40xx.h"
#include "fpu_init.h"
/* FIXME - missing PWM and possibly CREG drivers */
#ifdef __cplusplus
}
#endif
#endif /* __CHIP_LPC40XX_H_ */

896
hw/mcu/nxp/lpc_chip_175x_6x/inc/clock_17xx_40xx.h Normal file
View File

@ -0,0 +1,896 @@
/*
* @brief LPC17XX/40XX Clock control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CLOCK_17XX_40XX_H_
#define __CLOCK_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CLOCK_17XX_40XX CHIP: LPC17xx/40xx Clock Driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#define SYSCTL_OSCRANGE_15_25 (1 << 4) /*!< SCS register - main oscillator range 15 to 25MHz */
#define SYSCTL_OSCEC (1 << 5) /*!< SCS register - main oscillator enable */
#define SYSCTL_OSCSTAT (1 << 6) /*!< SCS register - main oscillator is ready status */
/*!< Internal oscillator frequency */
#if defined(CHIP_LPC175X_6X)
#define SYSCTL_IRC_FREQ (4000000)
#else
#define SYSCTL_IRC_FREQ (12000000)
#endif
#define SYSCTL_PLL_ENABLE (1 << 0)/*!< PLL enable flag */
#if defined(CHIP_LPC175X_6X)
#define SYSCTL_PLL_CONNECT (1 << 1) /*!< PLL connect flag only applies to 175x/6x */
#endif
/**
* @brief Enables or connects a PLL
* @param PLLNum: PLL number
* @param flags: SYSCTL_PLL_ENABLE or SYSCTL_PLL_CONNECT
* @return Nothing
* @note This will also perform a PLL feed sequence. Connect only applies to the
* LPC175x/6x devices.
*/
void Chip_Clock_EnablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags);
/**
* @brief Disables or disconnects a PLL
* @param PLLNum: PLL number
* @param flags: SYSCTL_PLL_ENABLE or SYSCTL_PLL_CONNECT
* @return Nothing
* @note This will also perform a PLL feed sequence. Connect only applies to the
* LPC175x/6x devices.
*/
void Chip_Clock_DisablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags);
/**
* @brief Sets up a PLL
* @param PLLNum: PLL number
* @param msel: PLL Multiplier value (Must be pre-decremented)
* @param psel: PLL Divider value (Must be pre-decremented)
* @note See the User Manual for limitations on these values for stable PLL
* operation. Be careful with these values - they must be safe values for the
* msl, nsel, and psel registers so must be already decremented by 1 or the
* the correct value for psel (0 = div by 1, 1 = div by 2, etc.).
* @return Nothing
*/
void Chip_Clock_SetupPLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t msel, uint32_t psel);
#if defined(CHIP_LPC175X_6X)
#define SYSCTL_PLL0STS_ENABLED (1 << 24) /*!< PLL0 enable flag */
#define SYSCTL_PLL0STS_CONNECTED (1 << 25) /*!< PLL0 connect flag */
#define SYSCTL_PLL0STS_LOCKED (1 << 26) /*!< PLL0 connect flag */
#define SYSCTL_PLL1STS_ENABLED (1 << 8) /*!< PLL1 enable flag */
#define SYSCTL_PLL1STS_CONNECTED (1 << 9) /*!< PLL1 connect flag */
#define SYSCTL_PLL1STS_LOCKED (1 << 10) /*!< PLL1 connect flag */
#else
#define SYSCTL_PLLSTS_ENABLED (1 << 8) /*!< PLL enable flag */
#define SYSCTL_PLLSTS_LOCKED (1 << 10) /*!< PLL connect flag */
#endif
/**
* @brief Returns PLL status
* @param PLLNum: PLL number
* @return Current enabled flags, Or'ed SYSCTL_PLLSTS_* states
* @note Note flag positions for PLL0 and PLL1 differ on the LPC175x/6x devices.
*/
STATIC INLINE uint32_t Chip_Clock_GetPLLStatus(CHIP_SYSCTL_PLL_T PLLNum)
{
return LPC_SYSCTL->PLL[PLLNum].PLLSTAT;
}
/**
* @brief Read PLL0 enable status
* @return true of the PLL0 is enabled. false if not enabled
*/
STATIC INLINE bool Chip_Clock_IsMainPLLEnabled(void)
{
#if defined(CHIP_LPC175X_6X)
return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_ENABLED) != 0);
#else
return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLLSTS_ENABLED) != 0);
#endif
}
/**
* @brief Read PLL1 enable status
* @return true of the PLL1 is enabled. false if not enabled
*/
STATIC INLINE bool Chip_Clock_IsUSBPLLEnabled(void)
{
#if defined(CHIP_LPC175X_6X)
return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_ENABLED) != 0);
#else
return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLLSTS_ENABLED) != 0);
#endif
}
/**
* @brief Read PLL0 lock status
* @return true of the PLL0 is locked. false if not locked
*/
STATIC INLINE bool Chip_Clock_IsMainPLLLocked(void)
{
#if defined(CHIP_LPC175X_6X)
return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_LOCKED) != 0);
#else
return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLLSTS_LOCKED) != 0);
#endif
}
/**
* @brief Read PLL1 lock status
* @return true of the PLL1 is locked. false if not locked
*/
STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
{
#if defined(CHIP_LPC175X_6X)
return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_LOCKED) != 0);
#else
return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLLSTS_LOCKED) != 0);
#endif
}
#if defined(CHIP_LPC175X_6X)
/**
* @brief Read PLL0 connect status
* @return true of the PLL0 is connected. false if not connected
*/
STATIC INLINE bool Chip_Clock_IsMainPLLConnected(void)
{
return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_CONNECTED) != 0);
}
/**
* @brief Read PLL1 lock status
* @return true of the PLL1 is connected. false if not connected
*/
STATIC INLINE bool Chip_Clock_IsUSBPLLConnected(void)
{
return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_CONNECTED) != 0);
}
#endif
/**
* @brief Enables the external Crystal oscillator
* @return Nothing
*/
STATIC INLINE void Chip_Clock_EnableCrystal(void)
{
LPC_SYSCTL->SCS |= SYSCTL_OSCEC;
}
/**
* @brief Checks if the external Crystal oscillator is enabled
* @return true if enabled, false otherwise
*/
STATIC INLINE bool Chip_Clock_IsCrystalEnabled(void)
{
return (LPC_SYSCTL->SCS & SYSCTL_OSCSTAT) != 0;
}
/**
* @brief Sets the external crystal oscillator range to 15Mhz - 25MHz
* @return Nothing
*/
STATIC INLINE void Chip_Clock_SetCrystalRangeHi(void)
{
LPC_SYSCTL->SCS |= SYSCTL_OSCRANGE_15_25;
}
/**
* @brief Sets the external crystal oscillator range to 1Mhz - 20MHz
* @return Nothing
*/
STATIC INLINE void Chip_Clock_SetCrystalRangeLo(void)
{
LPC_SYSCTL->SCS &= ~SYSCTL_OSCRANGE_15_25;
}
/**
* @brief Feeds a PLL
* @param PLLNum: PLL number
* @return Nothing
*/
STATIC INLINE void Chip_Clock_FeedPLL(CHIP_SYSCTL_PLL_T PLLNum)
{
LPC_SYSCTL->PLL[PLLNum].PLLFEED = 0xAA;
LPC_SYSCTL->PLL[PLLNum].PLLFEED = 0x55;
}
/**
* Power control for peripherals
*/
typedef enum CHIP_SYSCTL_CLOCK {
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_RSVD0,
#else
SYSCTL_CLOCK_LCD, /*!< LCD clock */
#endif
SYSCTL_CLOCK_TIMER0, /*!< Timer 0 clock */
SYSCTL_CLOCK_TIMER1, /*!< Timer 1 clock */
SYSCTL_CLOCK_UART0, /*!< UART 0 clock */
SYSCTL_CLOCK_UART1, /*!< UART 1 clock */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_RSVD5,
#else
SYSCTL_CLOCK_PWM0, /*!< PWM0 clock */
#endif
SYSCTL_CLOCK_PWM1, /*!< PWM1 clock */
SYSCTL_CLOCK_I2C0, /*!< I2C0 clock */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_SPI, /*!< SPI clock */
#else
SYSCTL_CLOCK_UART4, /*!< UART 4 clock */
#endif
SYSCTL_CLOCK_RTC, /*!< RTC clock */
SYSCTL_CLOCK_SSP1, /*!< SSP1 clock */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_RSVD11,
#else
SYSCTL_CLOCK_EMC, /*!< EMC clock */
#endif
SYSCTL_CLOCK_ADC, /*!< ADC clock */
SYSCTL_CLOCK_CAN1, /*!< CAN1 clock */
SYSCTL_CLOCK_CAN2, /*!< CAN2 clock */
SYSCTL_CLOCK_GPIO, /*!< GPIO clock */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_RIT, /*!< RIT clock */
#else
SYSCTL_CLOCK_SPIFI, /*!< SPIFI clock */
#endif
SYSCTL_CLOCK_MCPWM, /*!< MCPWM clock */
SYSCTL_CLOCK_QEI, /*!< QEI clock */
SYSCTL_CLOCK_I2C1, /*!< I2C1 clock */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_RSVD20,
#else
SYSCTL_CLOCK_SSP2, /*!< SSP2 clock */
#endif
SYSCTL_CLOCK_SSP0, /*!< SSP0 clock */
SYSCTL_CLOCK_TIMER2, /*!< Timer 2 clock */
SYSCTL_CLOCK_TIMER3, /*!< Timer 3 clock */
SYSCTL_CLOCK_UART2, /*!< UART 2 clock */
SYSCTL_CLOCK_UART3, /*!< UART 3 clock */
SYSCTL_CLOCK_I2C2, /*!< I2C2 clock */
SYSCTL_CLOCK_I2S, /*!< I2S clock */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLOCK_RSVD28,
#else
SYSCTL_CLOCK_SDC, /*!< SD Card interface clock */
#endif
SYSCTL_CLOCK_GPDMA, /*!< GP DMA clock */
SYSCTL_CLOCK_ENET, /*!< EMAC/Ethernet clock */
SYSCTL_CLOCK_USB, /*!< USB clock */
SYSCTL_CLOCK_RSVD32,
SYSCTL_CLOCK_RSVD33,
SYSCTL_CLOCK_RSVD34,
#if defined(CHIP_LPC40XX)
SYSCTL_CLOCK_CMP, /*!< Comparator clock (PCONP1) */
#else
SYSCTL_CLOCK_RSVD35,
#endif
} CHIP_SYSCTL_CLOCK_T;
/**
* @brief Enables power and clocking for a peripheral
* @param clk: Clock to enable
* @return Nothing
* @note Only peripheral clocks that are defined in the PCONP registers of the clock
* and power controller can be enabled and disabled with this function.
* Some clocks need to be enabled elsewhere (ie, USB) and will return
* false to indicate it can't be enabled with this function.
*/
void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
/**
* @brief Disables power and clocking for a peripheral
* @param clk: Clock to disable
* @return Nothing
* @note Only peripheral clocks that are defined in the PCONP registers of the clock
* and power controller can be enabled and disabled with this function.
* Some clocks need to be disabled elsewhere (ie, USB) and will return
* false to indicate it can't be disabled with this function.
*/
void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
/**
* @brief Returns power enables state for a peripheral
* @param clk: Clock to check
* @return true if the clock is enabled, false if disabled
*/
bool Chip_Clock_IsPeripheralClockEnabled(CHIP_SYSCTL_CLOCK_T clk);
#if !defined(CHIP_LPC175X_6X)
/**
* EMC clock divider values
*/
typedef enum CHIP_SYSCTL_EMC_DIV {
SYSCTL_EMC_DIV1 = 0,
SYSCTL_EMC_DIV2 = 1,
} CHIP_SYSCTL_EMC_DIV_T;
/**
* @brief Selects a EMC divider rate
* @param emcDiv: Source clock for PLL
* @return Nothing
* @note This function controls division of the clock before it is used by the EMC.
* The EMC uses the same base clock as the CPU and the APB peripherals. The
* EMC clock can tun at half or the same as the CPU clock. This is intended to
* be used primarily when the CPU is running faster than the external bus can
* support.
*/
STATIC INLINE void Chip_Clock_SetEMCClockDiv(CHIP_SYSCTL_EMC_DIV_T emcDiv)
{
LPC_SYSCTL->EMCCLKSEL = (uint32_t) emcDiv;
}
/**
* @brief Get EMC divider rate
* @return divider value
*/
STATIC INLINE uint32_t Chip_Clock_GetEMCClockDiv(void)
{
return ((uint32_t) LPC_SYSCTL->EMCCLKSEL) + 1;
}
#endif
/**
* Selectable CPU clock sources
*/
typedef enum CHIP_SYSCTL_CCLKSRC {
SYSCTL_CCLKSRC_SYSCLK, /*!< Select Sysclk as the input to the CPU clock divider. */
SYSCTL_CCLKSRC_MAINPLL, /*!< Select the output of the Main PLL as the input to the CPU clock divider. */
} CHIP_SYSCTL_CCLKSRC_T;
/**
* @brief Sets the current CPU clock source
* @param src Source selected
* @return Nothing
* @note When setting the clock source to the PLL, it should
* be enabled and locked.
*/
void Chip_Clock_SetCPUClockSource(CHIP_SYSCTL_CCLKSRC_T src);
/**
* @brief Returns the current CPU clock source
* @return CPU clock source
* @note On 177x/8x and 407x/8x devices, this is also the peripheral
* clock source.
*/
CHIP_SYSCTL_CCLKSRC_T Chip_Clock_GetCPUClockSource(void);
/**
* @brief Sets the CPU clock divider
* @param div: CPU clock divider, between 1 and divider max
* @return Nothing
* @note The maximum divider for the 175x/6x is 256. The maximum divider for
* the 177x/8x and 407x/8x is 32. Note on 175x/6x devices, the divided CPU
* clock rate is used as the input to the peripheral clock dividers,
* while 177x/8x and 407x/8x devices use the undivided CPU clock rate.
*/
void Chip_Clock_SetCPUClockDiv(uint32_t div);
/**
* @brief Gets the CPU clock divider
* @return CPU clock divider, between 1 and divider max
* @note The maximum divider for the 175x/6x is 256. The maximum divider for
* the 177x/8x and 407x/8x is 32. Note on 175x/6x devices, the divided CPU
* clock rate is used as the input to the peripheral clock dividers,
* while 177x/8x and 407x/8x devices use the undivided CPU clock rate.
*/
uint32_t Chip_Clock_GetCPUClockDiv(void);
#if !defined(CHIP_LPC175X_6X)
/**
* Clock sources for the USB divider. On 175x/6x devices, only the USB
* PLL1 can be used as an input for the USB divider
*/
typedef enum CHIP_SYSCTL_USBCLKSRC {
SYSCTL_USBCLKSRC_SYSCLK, /*!< SYSCLK clock as USB divider source */
SYSCTL_USBCLKSRC_MAINPLL, /*!< PLL0 clock as USB divider source */
SYSCTL_USBCLKSRC_USBPLL, /*!< PLL1 clock as USB divider source */
SYSCTL_USBCLKSRC_RESERVED
} CHIP_SYSCTL_USBCLKSRC_T;
/**
* @brief Sets the USB clock divider source
* @param src: USB clock divider source clock
* @return Nothing
* @note This function doesn't apply for LPC175x/6x devices. The divider must be
* be selected with the selected source to give a valid USB clock with a
* rate of 48MHz.
*/
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src);
/**
* @brief Gets the USB clock divider source
* @return USB clock divider source clock
*/
STATIC INLINE CHIP_SYSCTL_USBCLKSRC_T Chip_Clock_GetUSBClockSource(void)
{
return (CHIP_SYSCTL_USBCLKSRC_T) ((LPC_SYSCTL->USBCLKSEL >> 8) & 0x3);
}
#endif /* !defined(CHIP_LPC175X_6X)*/
/**
* @brief Sets the USB clock divider
* @param div: USB clock divider to generate 48MHz from USB source clock
* @return Nothing
* @note Divider values are between 1 and 32 (16 max for 175x/6x)
*/
void Chip_Clock_SetUSBClockDiv(uint32_t div);
/**
* @brief Gets the USB clock divider
* @return USB clock divider
* @note Divider values are between 1 and 32 (16 max for 175x/6x)
*/
uint32_t Chip_Clock_GetUSBClockDiv(void);
/**
* PLL source clocks
*/
typedef enum CHIP_SYSCTL_PLLCLKSRC {
SYSCTL_PLLCLKSRC_IRC, /*!< PLL is sourced from the internal oscillator (IRC) */
SYSCTL_PLLCLKSRC_MAINOSC, /*!< PLL is sourced from the main oscillator */
#if defined(CHIP_LPC175X_6X)
SYSCTL_PLLCLKSRC_RTC, /*!< PLL is sourced from the RTC oscillator */
#else
SYSCTL_PLLCLKSRC_RESERVED1,
#endif
SYSCTL_PLLCLKSRC_RESERVED2
} CHIP_SYSCTL_PLLCLKSRC_T;
/**
* @brief Selects a input clock source for SYSCLK
* @param src: input clock source for SYSCLK
* @return Nothing
* @note SYSCLK is used for sourcing PLL0, SPIFI FLASH, the USB clock
* divider, and the CPU clock divider.
*/
STATIC INLINE void Chip_Clock_SetMainPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
{
LPC_SYSCTL->CLKSRCSEL = src;
}
/**
* @brief Returns the input clock source for SYSCLK
* @return input clock source for SYSCLK
*/
STATIC INLINE CHIP_SYSCTL_PLLCLKSRC_T Chip_Clock_GetMainPLLSource(void)
{
return (CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->CLKSRCSEL & 0x3);
}
#if defined(CHIP_LPC175X_6X)
/**
* Clock and power peripheral clock divider rates used with the
* Clock_CLKDIVSEL_T clock types (devices only)
*/
typedef enum {
SYSCTL_CLKDIV_4, /*!< Divider by 4 */
SYSCTL_CLKDIV_1, /*!< Divider by 1 */
SYSCTL_CLKDIV_2, /*!< Divider by 2 */
SYSCTL_CLKDIV_8, /*!< Divider by 8, not for use with CAN */
SYSCTL_CLKDIV_6_CCAN = SYSCTL_CLKDIV_8 /*!< Divider by 6, CAN only */
} CHIP_SYSCTL_CLKDIV_T;
/**
* Peripheral clock selection for LPC175x/6x
* This is a list of clocks that can be divided on the 175x/6x
*/
typedef enum {
SYSCTL_PCLK_WDT, /*!< Watchdog divider */
SYSCTL_PCLK_TIMER0, /*!< Timer 0 divider */
SYSCTL_PCLK_TIMER1, /*!< Timer 1 divider */
SYSCTL_PCLK_UART0, /*!< UART 0 divider */
SYSCTL_PCLK_UART1, /*!< UART 1 divider */
SYSCTL_PCLK_RSVD5,
SYSCTL_PCLK_PWM1, /*!< PWM 1 divider */
SYSCTL_PCLK_I2C0, /*!< I2C 0 divider */
SYSCTL_PCLK_SPI, /*!< SPI divider */
SYSCTL_PCLK_RSVD9,
SYSCTL_PCLK_SSP1, /*!< SSP 1 divider */
SYSCTL_PCLK_DAC, /*!< DAC divider */
SYSCTL_PCLK_ADC, /*!< ADC divider */
SYSCTL_PCLK_CAN1, /*!< CAN 1 divider */
SYSCTL_PCLK_CAN2, /*!< CAN 2 divider */
SYSCTL_PCLK_ACF, /*!< ACF divider */
SYSCTL_PCLK_QEI, /*!< QEI divider */
SYSCTL_PCLK_GPIOINT, /*!< GPIOINT divider */
SYSCTL_PCLK_PCB, /*!< PCB divider */
SYSCTL_PCLK_I2C1, /*!< I2C 1 divider */
SYSCTL_PCLK_RSVD20,
SYSCTL_PCLK_SSP0, /*!< SSP 0 divider */
SYSCTL_PCLK_TIMER2, /*!< Timer 2 divider */
SYSCTL_PCLK_TIMER3, /*!< Timer 3 divider */
SYSCTL_PCLK_UART2, /*!< UART 2 divider */
SYSCTL_PCLK_UART3, /*!< UART 3 divider */
SYSCTL_PCLK_I2C2, /*!< I2C 2 divider */
SYSCTL_PCLK_I2S, /*!< I2S divider */
SYSCTL_PCLK_RSVD28,
SYSCTL_PCLK_RIT, /*!< Repetitive timer divider */
SYSCTL_PCLK_SYSCON, /*!< SYSCON divider */
SYSCTL_PCLK_MCPWM /*!< Motor control PWM divider */
} CHIP_SYSCTL_PCLK_T;
/**
* @brief Selects a clock divider for a peripheral
* @param clk: Clock to set divider for
* @param div: Divider for the clock
* @return Nothing
* @note Selects the divider for a peripheral. A peripheral clock is generated
* from the CPU clock divided by its peripheral clock divider.
* Only peripheral clocks that are defined in the PCLKSEL registers of
* the clock and power controller can used this function.
* (LPC175X/6X only)
*/
void Chip_Clock_SetPCLKDiv(CHIP_SYSCTL_PCLK_T clk, CHIP_SYSCTL_CLKDIV_T div);
/**
* @brief Gets a clock divider for a peripheral
* @param clk: Clock to set divider for
* @return The divider for the clock
* @note Selects the divider for a peripheral. A peripheral clock is generated
* from the CPU clock divided by its peripheral clock divider.
* Only peripheral clocks that are defined in the PCLKSEL registers of
* the clock and power controller can used this function.
* (LPC175X/6X only)
*/
uint32_t Chip_Clock_GetPCLKDiv(CHIP_SYSCTL_PCLK_T clk);
#else
/**
* @brief Sets a clock divider for all peripherals
* @param div: Divider for all peripherals, 0 = disable
* @return Nothing
* @note All the peripherals in the device use the same clock divider. The
* divider is based on the CPU's clock rate. Use 0 to disable all
* peripheral clocks or a divider of 1 to 15. (LPC177X/8X and 407X/8X)
*/
STATIC INLINE void Chip_Clock_SetPCLKDiv(uint32_t div)
{
LPC_SYSCTL->PCLKSEL = div;
}
/**
* @brief Gets the clock divider for all peripherals
* @return Divider for all peripherals, 0 = disabled
* @note All the peripherals in the device use the same clock divider. The
* divider is based on the CPU's clock rate. (LPC177X/8X and 407X/8X)
*/
STATIC INLINE uint32_t Chip_Clock_GetPCLKDiv(void)
{
return LPC_SYSCTL->PCLKSEL & 0x1F;
}
#endif
#if !defined(CHIP_LPC175X_6X)
/**
* Clock sources for the SPIFI clock divider
*/
typedef enum CHIP_SYSCTL_SPIFICLKSRC {
SYSCTL_SPIFICLKSRC_SYSCLK, /*!< SYSCLK clock as SPIFI divider source */
SYSCTL_SPIFICLKSRC_MAINPLL, /*!< PLL0 clock as SPIFI divider source */
SYSCTL_SPIFICLKSRC_USBPLL, /*!< PLL1 clock as SPIFI divider source */
SYSCTL_SPIFICLKSRC_RESERVED
} CHIP_SYSCTL_SPIFICLKSRC_T;
/**
* @brief Sets the SPIFI clock divider source
* @param src: SPIFI clock divider source clock
* @return Nothing
*/
void Chip_Clock_SetSPIFIClockSource(CHIP_SYSCTL_SPIFICLKSRC_T src);
/**
* @brief Gets the SPIFI clock divider source
* @return SPIFI clock divider source clock
*/
STATIC INLINE CHIP_SYSCTL_SPIFICLKSRC_T Chip_Clock_GetSPIFIClockSource(void)
{
return (CHIP_SYSCTL_SPIFICLKSRC_T) ((LPC_SYSCTL->SPIFICLKSEL >> 8) & 0x3);
}
/**
* @brief Sets the SPIFI clock divider
* @param div: SPIFI clock divider, 0 to disable
* @return Nothing
* @note Divider values are between 1 and 31
*/
void Chip_Clock_SetSPIFIClockDiv(uint32_t div);
/**
* @brief Gets the SPIFI clock divider
* @return SPIFI clock divider
* @note Divider values are between 1 and 31, 0 is disabled
*/
STATIC INLINE uint32_t Chip_Clock_GetSPIFIClockDiv(void)
{
return LPC_SYSCTL->SPIFICLKSEL & 0x1F;
}
/**
* @brief Set the LCD clock prescaler
* @param div: Divider value, minimum of 1
* @return Nothing
*/
STATIC INLINE void Chip_Clock_SetLCDClockDiv(uint32_t div)
{
LPC_SYSCTL->LCD_CFG = (div - 1);
}
/**
* @brief Get the LCD clock prescaler
* @return Current divider value
*/
STATIC INLINE uint32_t Chip_Clock_GetLCDClockDiv(void)
{
return (LPC_SYSCTL->LCD_CFG & 0x1F) + 1;
}
#endif
/**
* Clock sources for the CLKOUT pin
*/
typedef enum {
SYSCTL_CLKOUTSRC_CPU, /*!< CPU clock as CLKOUT source */
SYSCTL_CLKOUTSRC_MAINOSC, /*!< Main oscillator clock as CLKOUT source */
SYSCTL_CLKOUTSRC_IRC, /*!< IRC oscillator clock as CLKOUT source */
SYSCTL_CLKOUTSRC_USB, /*!< USB clock as CLKOUT source */
SYSCTL_CLKOUTSRC_RTC, /*!< RTC clock as CLKOUT source */
#if defined(CHIP_LPC175X_6X)
SYSCTL_CLKOUTSRC_RESERVED1,
SYSCTL_CLKOUTSRC_RESERVED2,
#else
SYSCTL_CLKOUTSRC_SPIFI, /*!< SPIFI clock as CLKOUT source */
SYSCTL_CLKOUTSRC_WATCHDOGOSC, /*!< Watchdog oscillator as CLKOUT source */
#endif
SYSCTL_CLKOUTSRC_RESERVED3
} CHIP_SYSCTL_CLKOUTSRC_T;
/**
* @brief Selects a source clock and divider rate for the CLKOUT pin
* @param src: source selected
* @param div: Divider for the clock source on CLKOUT, 1 to 16
* @return Nothing
* @note This function will disable the CLKOUT signal if its enabled. Use
* Chip_Clock_EnableCLKOUT to re-enable CLKOUT after a call to this
* function.
*/
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
/**
* @brief Enables the clock on the CLKOUT pin
* @return Nothing
*/
STATIC INLINE void Chip_Clock_EnableCLKOUT(void)
{
LPC_SYSCTL->CLKOUTCFG |= (1 << 8);
}
/**
* @brief Disables the clock on the CLKOUT pin
* @return Nothing
*/
STATIC INLINE void Chip_Clock_DisableCLKOUT(void)
{
LPC_SYSCTL->CLKOUTCFG &= ~(1 << 8);
}
/**
* @brief Returns the CLKOUT activity indication status
* @return true if CLKOUT is enabled, false if disabled and stopped
* @note CLKOUT activity indication. Reads as true when CLKOUT is
* enabled. Read as false when CLKOUT has been disabled via
* the CLKOUT_EN bit and the clock has completed being stopped.
*/
STATIC INLINE bool Chip_Clock_IsCLKOUTEnabled(void)
{
return (bool) ((LPC_SYSCTL->CLKOUTCFG & (1 << 9)) != 0);
}
/**
* @brief Returns the main oscillator clock rate
* @return main oscillator clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
{
return OscRateIn;
}
/**
* @brief Returns the internal oscillator (IRC) clock rate
* @return internal oscillator (IRC) clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
{
return SYSCTL_IRC_FREQ;
}
/**
* @brief Returns the RTC oscillator clock rate
* @return RTC oscillator clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
{
return RTCOscRateIn;
}
/**
* @brief Returns the current SYSCLK clock rate
* @return SYSCLK clock rate
* @note SYSCLK is used for sourcing PLL0, SPIFI FLASH, the USB clock
* divider, and the CPU clock divider.
*/
uint32_t Chip_Clock_GetSYSCLKRate(void);
/**
* @brief Return Main PLL (PLL0) input clock rate
* @return PLL0 input clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetMainPLLInClockRate(void)
{
return Chip_Clock_GetSYSCLKRate();
}
/**
* @brief Return PLL0 (Main PLL) output clock rate
* @return PLL0 output clock rate
*/
uint32_t Chip_Clock_GetMainPLLOutClockRate(void);
/**
* @brief Return USB PLL input clock rate
* @return USB PLL input clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
{
return Chip_Clock_GetMainOscRate();
}
/**
* @brief Return USB PLL output clock rate
* @return USB PLL output clock rate
*/
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
/**
* @brief Return main clock rate
* @return main clock rate
*/
uint32_t Chip_Clock_GetMainClockRate(void);
/**
* @brief Return system clock rate
* @return system clock rate
*/
uint32_t Chip_Clock_GetSystemClockRate(void);
/**
* @brief Gets the USB clock (USB_CLK) rate
* @return USB clock (USB_CLK) clock rate
* @note The clock source and divider are used to generate the USB clock rate.
*/
uint32_t Chip_Clock_GetUSBClockRate(void);
#if !defined(CHIP_LPC175X_6X)
/**
* @brief Returns the SPIFI clock rate
* @return SPIFI clock clock rate
*/
uint32_t Chip_Clock_GetSPIFIClockRate(void);
/**
* @brief Returns clock rate for EMC
* @return Clock rate for the peripheral
*/
STATIC INLINE uint32_t Chip_Clock_GetEMCClockRate(void)
{
return Chip_Clock_GetSystemClockRate() / Chip_Clock_GetEMCClockDiv();
}
#endif
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief Returns clock rate for a peripheral (from peripheral clock)
* @param clk: Clock to get rate of
* @return Clock rate for the peripheral
* @note This covers most common peripheral clocks, but not every clock
* in the system. LPC177x/8x and LPC407x/8x devices use the same
* clock for all periphreals, while the LPC175x/6x have unique
* dividers (except to RTC ) that may alter the peripheral clock rate.
*/
uint32_t Chip_Clock_GetPeripheralClockRate(void);
#else
/**
* @brief Returns clock rate for a peripheral (from peripheral clock)
* @param clk: Clock to get rate of
* @return Clock rate for the peripheral
* @note This covers most common peripheral clocks, but not every clock
* in the system. LPC177x/8x and LPC407x/8x devices use the same
* clock for all periphreals, while the LPC175x/6x have unique
* dividers (except to RTC ) that may alter the peripheral clock rate.
*/
uint32_t Chip_Clock_GetPeripheralClockRate(CHIP_SYSCTL_PCLK_T clk);
/**
* @brief Returns clock rate for RTC
* @return Clock rate for the peripheral
*/
STATIC INLINE uint32_t Chip_Clock_GetRTCClockRate(void)
{
return Chip_Clock_GetSystemClockRate() / 8;
}
#endif
/**
* @brief Returns clock rate for Ethernet
* @return Clock rate for the peripheral
*/
STATIC INLINE uint32_t Chip_Clock_GetENETClockRate(void)
{
return Chip_Clock_GetSystemClockRate();
}
/**
* @brief Returns clock rate for GPDMA
* @return Clock rate for the peripheral
*/
STATIC INLINE uint32_t Chip_Clock_GetGPDMAClockRate(void)
{
return Chip_Clock_GetSystemClockRate();
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CLOCK_17XX_40XX_H_ */

408
hw/mcu/nxp/lpc_chip_175x_6x/inc/cmp_17xx_40xx.h Normal file
View File

@ -0,0 +1,408 @@
/*
* @brief LPC40xx Comparator driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMP_17XX_40XX_H_
#define __CMP_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CMP_17XX_40XX CHIP: LPC40xx Comparator driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC40XX)
/** The number of embeded comparators supported */
#define CMP_NUM 2
/**
* @brief Comparator (CMP) register block structure
*/
typedef struct { /*!< Comparator structure */
__IO uint32_t CMP_CTRL; /*!< Comparator block control register */
__IO uint32_t CMP_CTRLx[CMP_NUM]; /*!< Specific comparator control register */
} LPC_CMP_T;
/**
* @brief Comparator control definition
*/
typedef enum {
CMP_ENCTRL_DISABLE, /*!< Disable */
CMP_ENCTRL_DIS_IN_DS_PWD, /*!< Disable in deep sleep mode and power down mode*/
CMP_ENCTRL_DIS_IN_PWD, /*!< Disable in power down mode*/
CMP_ENCTRL_ENABLE, /*!< Enable/Power-up*/
} CMP_ENCTRL_T;
/*!< Comparator control register Bitmask */
#define CMP_CTRL_BITMASK (0xF30F)
/*!< The comparator current source control bitmask*/
#define CMP_CTRL_PD_IREF_BITMASK (0x03)
/*!< Control the comparator current source (n is CMP_ENCTRL_T value)*/
#define CMP_CTRL_PD_IREF(n) ((((uint32_t) (n)) & 0x03))
/*!< The comparator bandgap reference control bitmask*/
#define CMP_CTRL_PD_VBG_BITMASK (((uint32_t) 0x03) << 2)
/*!< Control the comparator bandgap reference (n is CMP_ENCTRL_T value)*/
#define CMP_CTRL_PD_VBG(n) ((((uint32_t) (n)) & 0x03) << 2)
/*!< The CMP_ROSC ouput control bitmask */
#define CMP_CTRL_ROSC_BITMASK ((uint32_t) 0x300)
/*!< The CMP_ROSC output is set by CMP1, reset by CMP0 */
#define CMP_CTRL_ROSCCTL_CMP1 (0x00)
/*!< The CMP_ROSC output is set by CMP0, reset by CMP1 */
#define CMP_CTRL_ROSCCTL_CMP0 (((uint32_t) 0x01) << 8)
/*!< The CMP_ROSC output is reset by the internal chip reset */
#define CMP_CTRL_EXT_RESET_INTERNAL (0x00)
/*!< The CMP_ROSC output is reset by the CMP_RESET input */
#define CMP_CTRL_EXT_RESET_CMPRESET (((uint32_t) 0x01) << 9)
/*!< Timer Capture input control bitmask */
#define CMP_CTRL_TIMERCAPTURE_BITMASK ((uint32_t) 0xF000)
/*!< Selects the comparator 0 level output as the input for Timer0 capture input 2 */
#define CMP_CTRL_T0CAP2_0LEVEL (0x00)
/*!< Selects the comparator 1 level output as the input for Timer0 capture input 2 */
#define CMP_CTRL_T0CAP2_1LEVEL (((uint32_t) 0x01) << 12)
/*!< Selects the comparator 0 edge output as the input for Timer0 capture input 3 */
#define CMP_CTRL_T0CAP3_0EDGE (0x00)
/*!< Selects the comparator 1 edge output as the input for Timer0 capture input 3 */
#define CMP_CTRL_T0CAP3_1EDGE (((uint32_t) 0x01) << 13)
/*!< Selects the comparator 1 edge output as the input for Timer1 capture input 2 */
#define CMP_CTRL_T1CAP2_1EDGE (0x00)
/*!< Selects the comparator 0 level output as the input for Timer1 capture input 2 */
#define CMP_CTRL_T1CAP2_0LEVEL (((uint32_t) 0x01) << 14)
/*!< Selects the comparator 1 level output as the input for Timer1 capture input 3 */
#define CMP_CTRL_T1CAP3_1LEVEL (0x00)
/*!< Selects the comparator 0 edge output as the input for Timer1 capture input 3 */
#define CMP_CTRL_T1CAP3_0EDGE (((uint32_t) 0x01) << 15)
/*!< The comparator x control register Bitmask */
#define CMP_CTRLx_BITMASK ((uint32_t) 0x1F7FF77F)
/*!< The comparator x enable bitmask*/
#define CMP_CTRLx_EN_BITMASK (0x03)
/*!< Control the comparator x (n is CMP_ENCTRL_T value)*/
#define CMP_CTRLx_EN(n) ((((uint32_t) (n)) & 0x03))
/*!< Enable the output of compartor x */
#define CMP_CTRLx_OE (((uint32_t) 0x01) << 2)
/*!< The status of compartor x, reflects the comparator x output*/
#define CMP_CTRLx_STAT (((uint32_t) 0x01) << 3)
/*!< Comparator VM input control bitmask */
#define CMP_CTRLx_VM_BITMASK (((uint32_t) 0x07) << 4)
/*!< Select the VM input*/
#define CMP_CTRLx_VM(n) ((((uint32_t) (n)) & 0x07) << 4)
/*!< Comparator VP input control bitmask */
#define CMP_CTRLx_VP_BITMASK (((uint32_t) 0x07) << 8)
/*!< Select the VP input */
#define CMP_CTRLx_VP(n) ((((uint32_t) (n)) & 0x07) << 8)
/*!< Synchronize the Comparator x output with the internal bus clock for outpur to other peripherals */
#define CMP_CTRLx_SYNC (((uint32_t) 0x01) << 12)
/*!< Comparator Hysteresis control bitmask */
#define CMP_CTRLx_HYS_BITMASK (((uint32_t) 0x03) << 13)
/*!< Determine the difference required between the comparator inputs before the comparator output switch*/
#define CMP_CTRLx_HYS(n) ((((uint32_t) (n)) & 0x03) << 13)
/*!< Interrupt control bitmask */
#define CMP_CTRLx_INTCTRL_BITMASK ((uint32_t) 0x78000)
/*!< Comparator output is used as-is for generating interrupts. */
#define CMP_CTRLx_INTPOL_NORMAL (0x00)
/*!< Comparator output is used inverted for generating interrupts. */
#define CMP_CTRLx_INTPOL_INV (((uint32_t) 0x01) << 15)
/*!< Comparator x interrupt is edge triggered. */
#define CMP_CTRLx_INTTYPE_EDGE (0x00)
/*!< Comparator x interrupt is level triggered.*/
#define CMP_CTRLx_INTTYPE_LEVEL (((uint32_t) 0x01) << 16)
/*!< Comparator x interrupt edge control bitmask */
#define CMP_CTRLx_INTEDGE_BITMASK (((uint32_t) 0x03) << 17)
/*!< Select edge on which triggered interrupt is active*/
#define CMP_CTRLx_INTEDGE(n) ((((uint32_t) (n)) & 0x03) << 17)
/*!< Comparator interrupt flag */
#define CMP_CTRLx_INTFLAG (((uint32_t) 0x01) << 19)
/*!< The VLAD Enable bitmask*/
#define CMP_CTRLx_VLADEN_BITMASK (((uint32_t) 0x03) << 20)
/*!< Control the comparator x (n is CMP_ENCTRL_T value)*/
#define CMP_CTRLx_VLADEN(n) ((((uint32_t) (n)) & 0x03) << 20)
/*!< Select VREF_CMP pin as voltage reference for comparator voltage ladder */
#define CMP_CTRLx_VLADREF_VREFCMP (0x00)
/*!< Select VDDA pin as voltage reference for comparator voltage ladder */
#define CMP_CTRLx_VLADREF_VDDA (((uint32_t) 0x01) << 22)
/*!< Volatge ladder value bitmask */
#define CMP_CTRLx_VSEL_BITMASK ((uint32_t) ((0x1F) << 24))
/*!< Voltage ladder value for Comparator */
#define CMP_CTRLx_VSEL(n) ((((uint32_t) (n)) & 0x1F) << 24)
/**
* @brief Comparator VM/VP input definitions
*/
typedef enum {
CMP_INPUT_VREF_DIV, /*!< Vref divider.*/
CMP_INPUT_CMPx_IN0, /*!< Use the input 0 of the comparator*/
CMP_INPUT_CMPx_IN1, /*!< Use the input 1 of the comparator*/
CMP_INPUT_CMPx_IN2, /*!< Use the input 2 of the comparator*/
CMP_INPUT_CMPx_IN3, /*!< Use the input 3 of the comparator*/
CMP_INPUT_CMP_OTHER_IN0, /*!< Use the input 0 of the other comparator.*/
CMP_INPUT_INTERNAL_09VBG, /*!< internal 0.9 V band gap reference.*/
} CMP_INPUT_T;
/**
* @brief Comparator hysteresis selection definitions
*/
typedef enum {
CMP_HYS_NONE = CMP_CTRLx_HYS(0), /*!<No hysteresis (the output will switch as the voltages cross) */
CMP_HYS_5MV = CMP_CTRLx_HYS(1), /*!< 5mV hysteresis */
CMP_HYS_10MV = CMP_CTRLx_HYS(2), /*!< 10mV hysteresis */
CMP_HYS_15MV = CMP_CTRLx_HYS(3), /*!< 15mV hysteresis */
} CMP_HYS_T;
/**
* @brief Comparator interrupt edge selection definitions
*/
typedef enum {
CMP_INTEDGE_FALLING = CMP_CTRLx_INTEDGE(0), /*!< Interrupt is active on falling edge */
CMP_INTEDGE_RISING = CMP_CTRLx_INTEDGE(1), /*!< Interrupt is active on rising edge */
CMP_INTEDGE_BOTH = CMP_CTRLx_INTEDGE(2), /*!< Interrupt is active on falling and rising edges */
} CMP_INTEDGE_T;
/**
* @brief Initializes the CMP
* @return Nothing
*/
void Chip_CMP_Init(void);
/**
* @brief Deinitializes the CMP
* @return Nothing
*/
void Chip_CMP_DeInit(void);
/**
* @brief Enables comparator current source
* @param en : Enable mode
* @return Nothing
*/
STATIC INLINE void Chip_CMP_EnableCurrentSrc(CMP_ENCTRL_T en)
{
LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_PD_IREF_BITMASK)) | CMP_CTRL_PD_IREF(en);
}
/**
* @brief Enables comparator bandgap reference
* @param en : Enable mode
* @return Nothing
*/
STATIC INLINE void Chip_CMP_EnableBandGap(CMP_ENCTRL_T en)
{
LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_PD_VBG_BITMASK)) | CMP_CTRL_PD_VBG(en);
}
/**
* @brief Control CMP_ROSC
* @param flag : Or-ed bit value of CMP_CTRL_ROSCCTL_* and CMP_CTRL_EXT_RESET_*
* @return Nothing
*/
STATIC INLINE void Chip_CMP_ControlROSC(uint32_t flag)
{
LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_ROSC_BITMASK)) | flag;
}
/**
* @brief Control CMP_ROSC
* @param flag : Or-ed bit value of CMP_CTRL_T*CAP*
* @return Nothing
*/
STATIC INLINE void Chip_CMP_SetTimerCapInput(uint32_t flag)
{
LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_TIMERCAPTURE_BITMASK)) | flag;
}
/**
* @brief Sets up voltage ladder
* @param id : Comparator ID
* @param ladSel : Voltage ladder value (0~31).
* @param flag :0(CMP_VREF used)/CMP_CTRLx_VLADREF_VDDA (VDDA used)
* @return Nothing
* @note VREF divider 0 = ladSel*VRef0/31
*/
STATIC INLINE void Chip_CMP_SetupVoltLadder(uint8_t id,
uint16_t ladSel, uint32_t flag)
{
LPC_CMP->CMP_CTRLx[id] =
(LPC_CMP->CMP_CTRLx[id] & (~(CMP_CTRLx_VSEL_BITMASK | CMP_CTRLx_VLADREF_VDDA))) | CMP_CTRLx_VSEL(
ladSel) | flag;
}
/**
* @brief Enables voltage ladder
* @param id : Comparator ID
* @param en : enable option
* @return Nothing
*/
STATIC INLINE void Chip_CMP_EnableVoltLadder(uint8_t id, CMP_ENCTRL_T en)
{
LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_VLADEN_BITMASK)) | CMP_CTRLx_VLADEN(en);
}
/**
* @brief Selects positive voltage input
* @param id : Comparator ID
* @param input : Selected input
* @return Nothing
*/
STATIC INLINE void Chip_CMP_SetPosVoltRef(uint8_t id, CMP_INPUT_T input)
{
LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_VP_BITMASK)) | CMP_CTRLx_VP(input);
}
/**
* @brief Selects negative voltage input
* @param id : Comparator ID
* @param input : Selected input
* @return Nothing
*/
STATIC INLINE void Chip_CMP_SetNegVoltRef(uint8_t id, CMP_INPUT_T input)
{
LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_VM_BITMASK)) | CMP_CTRLx_VM(input);
}
/**
* @brief Selects hysteresis level
* @param id : Comparator ID
* @param hys : Selected Hysteresis level
* @return Nothing
*/
STATIC INLINE void Chip_CMP_SetHysteresis(uint8_t id, CMP_HYS_T hys)
{
LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_HYS_BITMASK)) | hys;
}
/**
* @brief Enables specified comparator
* @param id : Comparator ID
* @param en : Enable mode
* @return Nothing
*/
STATIC INLINE void Chip_CMP_Enable(uint8_t id, CMP_ENCTRL_T en)
{
LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_EN_BITMASK)) | CMP_CTRLx_EN(en);
}
/**
* @brief Returns the current comparator status
* @param id : Comparator Id (0/1)
* @return SET/RESET
*/
STATIC INLINE FlagStatus Chip_CMP_GetCmpStatus(uint8_t id)
{
return (LPC_CMP->CMP_CTRLx[id] & CMP_CTRLx_STAT) ? SET : RESET;
}
/**
* @brief Enable comparator output
* @param id : Comparator ID
* @return Nothing
*/
STATIC INLINE void Chip_CMP_EnableOuput(uint8_t id)
{
LPC_CMP->CMP_CTRLx[id] |= CMP_CTRLx_OE;
}
/**
* @brief Disable comparator output
* @param id : Comparator ID
* @return Nothing
*/
STATIC INLINE void Chip_CMP_DisableOutput(uint8_t id)
{
LPC_CMP->CMP_CTRLx[id] &= ~CMP_CTRLx_OE;
}
/**
* @brief Synchronizes Comparator output to bus clock
* @param id : Comparator ID
* @return Nothing
*/
STATIC INLINE void Chip_CMP_EnableSyncCmpOut(uint8_t id)
{
LPC_CMP->CMP_CTRLx[id] |= CMP_CTRLx_SYNC;
}
/**
* @brief Sets comparator output to be used directly (no sync)
* @param id : Comparator ID
* @return Nothing
*/
STATIC INLINE void Chip_CMP_DisableSyncCmpOut(uint8_t id)
{
LPC_CMP->CMP_CTRLx[id] &= ~CMP_CTRLx_SYNC;
}
/**
* @brief Sets up comparator interrupt
* @param id : Comparator ID
* @param intFlag : Or-ed value of CMP_CTRLx_INTTYPE_*, CMP_CTRLx_INTPOL_*
* @param edgeSel : the edge on which interrupt occurs.
* @return Nothing
*/
STATIC INLINE void Chip_CMP_ConfigInt(uint8_t id,
uint32_t intFlag,
CMP_INTEDGE_T edgeSel)
{
LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_INTCTRL_BITMASK)) | intFlag | edgeSel;
}
/**
* @brief Get the CMP interrupt status
* @param id : Comparator ID
* @return SET/RESET
*/
STATIC INLINE FlagStatus Chip_CMP_GetIntStatus(uint8_t id)
{
return (LPC_CMP->CMP_CTRLx[id] & CMP_CTRLx_INTFLAG) ? SET : RESET;
}
/**
* @brief Clears the CMP interrupt
* @param id : Comparator ID
* @return Nothing
*/
STATIC INLINE void Chip_CMP_ClearIntStatus(uint8_t id)
{
LPC_CMP->CMP_CTRLx[id] |= CMP_CTRLx_INTFLAG;
}
#endif /* defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CMP_17XX_40XX_H_ */

66
hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis.h Normal file
View File

@ -0,0 +1,66 @@
/*
* @brief LPC17xx/40xx selective CMSIS inclusion file
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_H_
#define __CMSIS_H_
#include "lpc_types.h"
#include "sys_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Select correct CMSIS include file based on CHIP_* definition */
#if defined(CHIP_LPC175X_6X)
#include "cmsis_175x_6x.h"
typedef LPC175X_6X_IRQn_Type IRQn_Type;
#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
#elif defined(CHIP_LPC177X_8X)
#include "cmsis_177x_8x.h"
typedef LPC177X_8X_IRQn_Type IRQn_Type;
#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
#elif defined(CHIP_LPC40XX)
#include "cmsis_40xx.h"
typedef LPC40XX_IRQn_Type IRQn_Type;
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else
#error "No CHIP_* definition is defined"
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_H_ */

163
hw/mcu/nxp/lpc_chip_175x_6x/inc/cmsis_175x_6x.h Normal file
View File

@ -0,0 +1,163 @@
/*
* @brief Basic CMSIS include file for LPC175x/6x
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_175X_6X_H_
#define __CMSIS_175X_6X_H_
#include "lpc_types.h"
#include "sys_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CMSIS_175X_6X CHIP: LPC175x/6x CMSIS include file
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
#pragma diag_suppress 2525
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
// #pragma push // FIXME not usable for IAR
#pragma language=extended
#else
#error Not supported compiler type
#endif
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
#if !defined(CHIP_LPC175X_6X)
#error Incorrect or missing device variant (CHIP_LPC175X_6X)
#endif
/** @defgroup CMSIS_175X_6X_IRQ CHIP_175X_6X: LPC175x/6x peripheral interrupt numbers
* @{
*/
typedef enum {
/* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 CDebug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/* --------------------------- LPC17xx Specific Interrupt Numbers ------------------------------- */
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART_IRQn = UART0_IRQn, /*!< Alias for UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */
I2C_IRQn = I2C0_IRQn, /*!< Alias for I2C0 Interrupt */
I2C1_IRQn = 11, /*!< I2C1 Interrupt */
I2C2_IRQn = 12, /*!< I2C2 Interrupt */
SPI_IRQn = 13, /*!< SPI Interrupt */
SSP0_IRQn = 14, /*!< SSP0 Interrupt */
SSP_IRQn = SSP0_IRQn, /*!< Alias for SSP0 Interrupt */
SSP1_IRQn = 15, /*!< SSP1 Interrupt */
PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
RTC_IRQn = 17, /*!< Real Time Clock and event recorder Interrupt */
EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
ADC_IRQn = 22, /*!< A/D Converter Interrupt */
BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
USB_IRQn = 24, /*!< USB Interrupt */
CAN_IRQn = 25, /*!< CAN Interrupt */
DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
I2S_IRQn = 27, /*!< I2S Interrupt */
ETHERNET_IRQn = 28, /*!< Ethernet Interrupt */
RITIMER_IRQn = 29, /*!< Repetitive Interrupt Interrupt */
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
USBActivity_IRQn = 33, /*!< USB Activity interrupt */
CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
} LPC175X_6X_IRQn_Type;
/**
* @}
*/
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/** @defgroup CMSIS_175X_6X_COMMON CHIP: LPC175x/6x Cortex CMSIS definitions
* @{
*/
#define __CM3_REV 0x0200
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /*!< FPU present or not */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_175X_6X_H_ */

1627
hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cm3.h Normal file
View File

File diff suppressed because it is too large Load Diff

636
hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmFunc.h Normal file
View File

@ -0,0 +1,636 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

688
hw/mcu/nxp/lpc_chip_175x_6x/inc/core_cmInstr.h Normal file
View File

@ -0,0 +1,688 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

236
hw/mcu/nxp/lpc_chip_175x_6x/inc/crc_17xx_40xx.h Normal file
View File

@ -0,0 +1,236 @@
/*
* @brief LPC17xx/40xx Cyclic Redundancy Check (CRC) Engine driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CRC_17XX_40XX_H_
#define __CRC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CRC_17XX_40XX CHIP: LPC17xx/40xx Cyclic Redundancy Check Engine driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief CRC register block structure
*/
typedef struct { /*!< CRC Structure */
__IO uint32_t MODE; /*!< CRC Mode Register */
__IO uint32_t SEED; /*!< CRC SEED Register */
union {
__I uint32_t SUM; /*!< CRC Checksum Register. */
__O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/
__O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/
__O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/
};
} LPC_CRC_T;
/*
* @brief CRC MODE register description
*/
#define CRC_MODE_POLY_BITMASK ((0x03)) /** CRC polynomial Bit mask */
#define CRC_MODE_POLY_CCITT (0x00) /** Select CRC-CCITT polynomial */
#define CRC_MODE_POLY_CRC16 (0x01) /** Select CRC-16 polynomial */
#define CRC_MODE_POLY_CRC32 (0x02) /** Select CRC-32 polynomial */
#define CRC_MODE_WRDATA_BITMASK (0x03 << 2) /** CRC WR_Data Config Bit mask */
#define CRC_MODE_WRDATA_BIT_RVS (1 << 2) /** Select Bit order reverse for WR_DATA (per byte) */
#define CRC_MODE_WRDATA_CMPL (1 << 3) /** Select One's complement for WR_DATA */
#define CRC_MODE_SUM_BITMASK (0x03 << 4) /** CRC Sum Config Bit mask */
#define CRC_MODE_SUM_BIT_RVS (1 << 4) /** Select Bit order reverse for CRC_SUM */
#define CRC_MODE_SUM_CMPL (1 << 5) /** Select One's complement for CRC_SUM */
#define MODE_CFG_CCITT (0x00) /** Pre-defined mode word for default CCITT setup */
#define MODE_CFG_CRC16 (0x15) /** Pre-defined mode word for default CRC16 setup */
#define MODE_CFG_CRC32 (0x36) /** Pre-defined mode word for default CRC32 setup */
#define CRC_SEED_CCITT (0x0000FFFF)/** Initial seed value for CCITT mode */
#define CRC_SEED_CRC16 (0x00000000)/** Initial seed value for CRC16 mode */
#define CRC_SEED_CRC32 (0xFFFFFFFF)/** Initial seed value for CRC32 mode */
/**
* @brief CRC polynomial
*/
typedef enum IP_CRC_001_POLY {
CRC_POLY_CCITT = CRC_MODE_POLY_CCITT, /**< CRC-CCIT polynomial */
CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16, /**< CRC-16 polynomial */
CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32, /**< CRC-32 polynomial */
CRC_POLY_LAST,
} CRC_POLY_T;
/**
* @brief Initializes the CRC Engine
* @return Nothing
*/
STATIC INLINE void Chip_CRC_Init(void) {}
/**
* @brief Deinitializes the CRC Engine
* @return Nothing
*/
STATIC INLINE void Chip_CRC_Deinit(void) {}
/**
* @brief Set the polynomial used for the CRC calculation
* @param poly : The enumerated polynomial to be used
* @param flags : An Or'ed value of flags that setup the mode
* @return Nothing
* @note Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS,
* CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL.
*/
STATIC INLINE void Chip_CRC_SetPoly(CRC_POLY_T poly, uint32_t flags)
{
LPC_CRC->MODE = (uint32_t) poly | flags;
}
/**
* @brief Engage the CRC engine with defaults based on the polynomial to be used
* @param poly : The enumerated polynomial to be used
* @return Nothing
*/
void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly);
/**
* @brief Set the CRC Mode bits
* @param mode : Mode value
* @return Nothing
*/
STATIC INLINE void Chip_CRC_SetMode(uint32_t mode)
{
LPC_CRC->MODE = mode;
}
/**
* @brief Get the CRC Mode bits
* @return The current value of the CRC Mode bits
*/
STATIC INLINE uint32_t Chip_CRC_GetMode(void)
{
return LPC_CRC->MODE;
}
/**
* @brief Set the seed bits used by the CRC_SUM register
* @param seed : Seed value
* @return Nothing
*/
STATIC INLINE void Chip_CRC_SetSeed(uint32_t seed)
{
LPC_CRC->SEED = seed;
}
/**
* @brief Get the CRC seed value
* @return Seed value
*/
STATIC INLINE uint32_t Chip_CRC_GetSeed(void)
{
return LPC_CRC->SEED;
}
/**
* @brief Convenience function for writing 8-bit data to the CRC engine
* @param data : 8-bit data to write
* @return Nothing
*/
STATIC INLINE void Chip_CRC_Write8(uint8_t data)
{
LPC_CRC->WRDATA8 = data;
}
/**
* @brief Convenience function for writing 16-bit data to the CRC engine
* @param data : 16-bit data to write
* @return Nothing
*/
STATIC INLINE void Chip_CRC_Write16(uint16_t data)
{
LPC_CRC->WRDATA16 = data;
}
/**
* @brief Convenience function for writing 32-bit data to the CRC engine
* @param data : 32-bit data to write
* @return Nothing
*/
STATIC INLINE void Chip_CRC_Write32(uint32_t data)
{
LPC_CRC->WRDATA32 = data;
}
/**
* @brief Gets the CRC Sum based on the Mode and Seed as previously configured
* @return CRC Checksum value
*/
STATIC INLINE uint32_t Chip_CRC_Sum(void)
{
return LPC_CRC->SUM;
}
/**
* @brief Convenience function for computing a standard CCITT checksum from an 8-bit data block
* @param data : Pointer to the block of 8-bit data
* @param bytes : The number of bytes pointed to by data
* @return Check sum value
*/
uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes);
/**
* @brief Convenience function for computing a standard CRC16 checksum from 16-bit data block
* @param data : Pointer to the block of 16-bit data
* @param hwords : The number of 16 byte entries pointed to by data
* @return Check sum value
*/
uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords);
/**
* @brief Convenience function for computing a standard CRC32 checksum from 32-bit data block
* @param data : Pointer to the block of 32-bit data
* @param words : The number of 32-bit entries pointed to by data
* @return Check sum value
*/
uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words);
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CRC_17XX_40XX_H_ */

166
hw/mcu/nxp/lpc_chip_175x_6x/inc/dac_17xx_40xx.h Normal file
View File

@ -0,0 +1,166 @@
/*
* @brief LPC17xx/40xx D/A conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __DAC_17XX_40XX_H_
#define __DAC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup DAC_17XX_40XX CHIP: LPC17xx/40xx D/A conversion driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief DAC register block structure
*/
typedef struct { /*!< DAC Structure */
__IO uint32_t CR; /*!< DAC register. Holds the conversion data. */
__IO uint32_t CTRL; /*!< DAC control register. */
__IO uint32_t CNTVAL; /*!< DAC counter value register. */
} LPC_DAC_T;
/** After the selected settling time after this field is written with a
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
is VALUE/1024 ? VREF */
#define DAC_VALUE(n) ((uint32_t) ((n & 0x3FF) << 6))
/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
* and the maximum current is 700 microAmpere
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
* and the maximum current is 350 microAmpere
*/
#define DAC_BIAS_EN ((uint32_t) (1 << 16))
/** Value to reload interrupt DMA counter */
#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
/** DCAR double buffering */
#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
/** DCAR Time out count enable */
#define DAC_CNT_ENA ((uint32_t) (1 << 2))
/** DCAR DMA access */
#define DAC_DMA_ENA ((uint32_t) (1 << 3))
/** DCAR DACCTRL mask bit */
#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
/**
* @brief Current option in DAC configuration option
*/
typedef enum IP_DAC_CURRENT_OPT {
DAC_MAX_UPDATE_RATE_1MHz = 0, /*!< Shorter settling times and higher power consumption;
allows for a maximum update rate of 1 MHz */
DAC_MAX_UPDATE_RATE_400kHz /*!< Longer settling times and lower power consumption;
allows for a maximum update rate of 400 kHz */
} DAC_CURRENT_OPT_T;
/**
* @brief Initial DAC configuration
* - Maximum current is 700 uA
* - Value to AOUT is 0
* @param pDAC : pointer to LPC_DAC_T
* @return Nothing
*/
void Chip_DAC_Init(LPC_DAC_T *pDAC);
/**
* @brief Shutdown DAC
* @param pDAC : pointer to LPC_DAC_T
* @return Nothing
*/
void Chip_DAC_DeInit(LPC_DAC_T *pDAC);
/**
* @brief Update value to DAC buffer
* @param pDAC : pointer to LPC_DAC_T
* @param dac_value : value 10 bit to be converted to output
* @return Nothing
*/
void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value);
/**
* @brief Set maximum update rate for DAC
* @param pDAC : pointer to LPC_DAC_T
* @param bias : Using Bias value, should be:
* - 0 is 1MHz
* - 1 is 400kHz
* @return Nothing
*/
void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias);
/**
* @brief Enables the DMA operation and controls DMA timer
* @param pDAC : pointer to LPC_DAC_T
* @param dacFlags : An Or'ed value of the following DAC values:
* - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature
* - DAC_CNT_ENA :enable/disable timer out counter
* - DAC_DMA_ENA :enable/disable DMA access
* @return Nothing
* @note Pass an Or'ed value of the DAC flags to enable those options.
*/
STATIC INLINE void Chip_DAC_ConfigDAConverterControl(LPC_DAC_T *pDAC, uint32_t dacFlags)
{
uint32_t temp;
temp = pDAC->CTRL & ~DAC_DACCTRL_MASK;
pDAC->CTRL = temp | dacFlags;
}
/**
* @brief Set reload value for interrupt/DMA counter
* @param pDAC : pointer to LPC_DAC_T
* @param time_out : time out to reload for interrupt/DMA counter
* @return Nothing
*/
STATIC INLINE void Chip_DAC_SetDMATimeOut(LPC_DAC_T *pDAC, uint32_t time_out)
{
pDAC->CNTVAL = DAC_CCNT_VALUE(time_out);
}
/**
* @brief Get status for interrupt/DMA time out
* @param pDAC : pointer to LPC_DAC_T
* @return interrupt/DMA time out status, should be SET or RESET
*/
STATIC INLINE IntStatus Chip_DAC_GetIntStatus(LPC_DAC_T *pDAC)
{
return (pDAC->CTRL & 0x01) ? SET : RESET;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __DAC_17XX_40XX_H_ */

320
hw/mcu/nxp/lpc_chip_175x_6x/inc/eeprom_17xx_40xx.h Normal file
View File

@ -0,0 +1,320 @@
/*
* @brief LPC17xx/40xx EEPROM driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __EEPROM_17XX_40XX_H_
#define __EEPROM_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup EEPROM_17XX_40XX CHIP: LPC17xx/40xx EEPROM driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief EEPROM register block structure
*/
typedef struct { /* EEPROM Structure */
__IO uint32_t CMD; /*!< EEPROM command register */
__IO uint32_t ADDR; /*!< EEPROM address register */
__O uint32_t WDATA; /*!< EEPROM write data register */
__I uint32_t RDATA; /*!< EEPROM read data register */
__IO uint32_t WSTATE; /*!< EEPROM wait state register */
__IO uint32_t CLKDIV; /*!< EEPROM clock divider register */
__IO uint32_t PWRDWN; /*!< EEPROM power-down register */
uint32_t RESERVED0[975];
__O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */
__O uint32_t INTENSET; /*!< EEPROM interrupt enable set */
__I uint32_t INTSTAT; /*!< EEPROM interrupt status */
__I uint32_t INTEN; /*!< EEPROM interrupt enable */
__O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */
__O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */
} LPC_EEPROM_T;
#define EEPROM_PAGE_SIZE 64 /*!< EEPROM byes per page */
#define EEPROM_PAGE_NUM 63 /*!< EEPROM pages */
/*
* @brief Macro defines for EEPROM command register
*/
#define EEPROM_CMD_8BITS_READ (0) /*!< EEPROM 8-bit read command */
#define EEPROM_CMD_16BITS_READ (1) /*!< EEPROM 16-bit read command */
#define EEPROM_CMD_32BITS_READ (2) /*!< EEPROM 32-bit read command */
#define EEPROM_CMD_8BITS_WRITE (3) /*!< EEPROM 8-bit write command */
#define EEPROM_CMD_16BITS_WRITE (4) /*!< EEPROM 16-bit write command */
#define EEPROM_CMD_32BITS_WRITE (5) /*!< EEPROM 32-bit write command */
#define EEPROM_CMD_ERASE_PRG_PAGE (6) /*!< EEPROM erase/program command */
#define EEPROM_CMD_RDPREFETCH (1 << 3)/*!< EEPROM read pre-fetch enable */
/*
* @brief Macro defines for EEPROM power down register
*/
#define EEPROM_PWRDWN (1 << 0)
/*
* @brief Macro defines for EEPROM interrupt related registers
*/
#define EEPROM_INT_ENDOFRW (1 << 26)
#define EEPROM_INT_ENDOFPROG (1 << 28)
/**
* @brief EEPROM Mode type definition
*/
typedef enum IP_EEPROM_RWSIZE {
EEPROM_RWSIZE_8BITS = 1,
EEPROM_RWSIZE_16BITS = 2,
EEPROM_RWSIZE_32BITS = 4
} EEPROM_RWSIZE_T;
/**
* @brief Put EEPROM device in power down mode
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_EnablePowerDown(LPC_EEPROM_T *pEEPROM)
{
pEEPROM->PWRDWN = EEPROM_PWRDWN;
}
/**
* @brief Bring EEPROM device out of power down mode
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_DisablePowerDown(LPC_EEPROM_T *pEEPROM)
{
pEEPROM->PWRDWN = 0;
}
/**
* @brief Initializes EEPROM
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @return Nothing
*/
void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM);
/**
* @brief De-initializes EEPROM
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_DeInit(LPC_EEPROM_T *pEEPROM)
{
/* Enable EEPROM power down mode */
Chip_EEPROM_EnablePowerDown(pEEPROM);
}
/**
* @brief Select an EEPROM command
* @param pEEPROM : pointer to EEPROM peripheral block
* @param cmd : EEPROM command.
* @return Nothing
* @note cmd is or-ed bits value of EEPROM_CMD_[8|16|32]BITS_READ/EEPROM_CMD_[8|16|32]BITS_WRITE
* with EEPROM_CMD_RDPREFETCH flag.
* Read and erase/program operations are started on the EEPROM device as a side-effect of calling this function.
* Write operations are started as a side-effect of writing data to data register.
*/
STATIC INLINE void Chip_EEPROM_SetCmd(LPC_EEPROM_T *pEEPROM, uint32_t cmd)
{
pEEPROM->CMD = cmd;
}
/**
* @brief Set EEPROM address
* @param pEEPROM : pointer to EEPROM peripheral block
* @param pageAddr : Page address.
* @param pageOffset : Page address.
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_SetAddr(LPC_EEPROM_T *pEEPROM, uint32_t pageAddr, uint32_t pageOffset)
{
pEEPROM->ADDR = (pageAddr << 6) | pageOffset;
}
/**
* @brief Write EEPROM data
* @param pEEPROM : pointer to EEPROM peripheral block
* @param data : EEPROM data.
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_WriteData(LPC_EEPROM_T *pEEPROM, uint32_t data)
{
pEEPROM->WDATA = data;
}
/**
* @brief Read EEPROM data
* @param pEEPROM : pointer to EEPROM peripheral block
* @return data
*/
STATIC INLINE uint32_t Chip_EEPROM_ReadData(LPC_EEPROM_T *pEEPROM)
{
return pEEPROM->RDATA;
}
/**
* @brief Set EEPROM wait state
* @param pEEPROM : pointer to EEPROM peripheral block
* @param ws : Wait State value.
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_SetWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws)
{
pEEPROM->WSTATE = ws;
}
/**
* @brief Write data to EEPROM at specific address
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @param pageOffset : offset of data in page register(0 - 63)
* @param pageAddress: page address (0-62)
* @param pData : buffer that contain data that will be written to buffer
* @param wsize : Write size:<br>
* - EEPROM_RWSIZE_8BITS : 8-bit read/write mode<br>
* - EEPROM_RWSIZE_16BITS : 16-bit read/write mode<br>
* - EEPROM_RWSIZE_32BITS : 32-bit read/write mode<br>
* @param byteNum : number written data (bytes)
* @return SUCCESS on successful write of data, or ERROR
* @note This function actually write data into EEPROM memory and automatically
* write into next page if current page is overflowed
*/
Status Chip_EEPROM_Write(LPC_EEPROM_T *pEEPROM, uint16_t pageOffset,
uint16_t pageAddress,
void *pData,
EEPROM_RWSIZE_T wsize,
uint32_t byteNum);
/**
* @brief Read data to EEPROM at specific address
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @param pageOffset : offset of data in page register(0 - 63)
* @param pageAddress: page address (0-62)
* @param pData : buffer that contain data read from read data register
* @param rsize : Read size:<br>
* - EEPROM_RWSIZE_8BITS : 8-bit read/write mode<br>
* - EEPROM_RWSIZE_16BITS : 16-bit read/write mode<br>
* - EEPROM_RWSIZE_32BITS : 32-bit read/write mode<br>
* @param byteNum : number read data (bytes)
* @return Nothing
*/
void Chip_EEPROM_Read(LPC_EEPROM_T *pEEPROM, uint16_t pageOffset,
uint16_t pageAddress,
void *pData,
EEPROM_RWSIZE_T rsize,
uint32_t byteNum);
/**
* @brief Erase a page at the specific address
* @param pEEPROM : The base of EEPROM peripheral on the chip
* @param address : EEPROM page address (0-62)
* @return Nothing
*/
void Chip_EEPROM_Erase(LPC_EEPROM_T *pEEPROM, uint16_t address);
/**
* @brief Enable EEPROM interrupt
* @param pEEPROM : pointer to EEPROM peripheral block
* @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_EnableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
{
pEEPROM->INTENSET = mask;
}
/**
* @brief Disable EEPROM interrupt
* @param pEEPROM : pointer to EEPROM peripheral block
* @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_DisableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
{
pEEPROM->INTENCLR = mask;
}
/**
* @brief Get the value of the EEPROM interrupt enable register
* @param pEEPROM : pointer to EEPROM peripheral block
* @return Or-ed bits value of EEPROM_INT_*
*/
STATIC INLINE uint32_t Chip_EEPROM_GetIntEnable(LPC_EEPROM_T *pEEPROM)
{
return pEEPROM->INTEN;
}
/**
* @brief Get EEPROM interrupt status
* @param pEEPROM : pointer to EEPROM peripheral block
* @return Or-ed bits value of EEPROM_INT_*
*/
STATIC INLINE uint32_t Chip_EEPROM_GetIntStatus(LPC_EEPROM_T *pEEPROM)
{
return pEEPROM->INTSTAT;
}
/**
* @brief Set EEPROM interrupt status
* @param pEEPROM : pointer to EEPROM peripheral block
* @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_SetIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
{
pEEPROM->INTSTATSET = mask;
}
/**
* @brief Clear EEPROM interrupt status
* @param pEEPROM : pointer to EEPROM peripheral block
* @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_ClearIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
{
pEEPROM->INTSTATCLR = mask;
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __EEPROM_17XX_40XX_H_ */

358
hw/mcu/nxp/lpc_chip_175x_6x/inc/emc_17xx_40xx.h Normal file
View File

@ -0,0 +1,358 @@
/*
* @brief LPC17xx/40xx EMC driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __EMC_17XX_40XX_H_
#define __EMC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup EMC_17XX_40XX CHIP: LPC17xx/40xx External Memory Controller driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
* The EMC interface clocks must be enabled outside this driver prior to
* calling any function of this driver.
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief External Memory Controller (EMC) register block structure
*/
typedef struct { /*!< EMC Structure */
__IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */
__I uint32_t STATUS; /*!< Provides EMC status information. */
__IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */
__I uint32_t RESERVED0[5];
__IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */
__IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */
__IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */
__I uint32_t RESERVED1;
__IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */
__IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */
__IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */
__IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */
__IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */
__IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */
__IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */
__IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */
__IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */
__IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */
__IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */
__I uint32_t RESERVED2[9];
__IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */
__I uint32_t RESERVED3[31];
__IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */
__IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
__I uint32_t RESERVED4[6];
__IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */
__IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
__I uint32_t RESERVED5[6];
__IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */
__IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
__I uint32_t RESERVED6[6];
__IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */
__IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
__I uint32_t RESERVED7[38];
__IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */
__IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */
__IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
__IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */
__IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
__IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */
__IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */
__I uint32_t RESERVED8;
__IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */
__IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */
__IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
__IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */
__IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
__IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */
__IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */
__I uint32_t RESERVED9;
__IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */
__IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */
__IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
__IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */
__IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
__IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */
__IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */
__I uint32_t RESERVED10;
__IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */
__IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */
__IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
__IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */
__IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
__IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */
__IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */
} LPC_EMC_T;
/**
* Dynamic Chip Select Address
*/
#define EMC_ADDRESS_DYCS0 (0xA0000000)
#define EMC_ADDRESS_DYCS1 (0xB0000000)
#define EMC_ADDRESS_DYCS2 (0xC0000000)
#define EMC_ADDRESS_DYCS3 (0xD0000000)
/**
* Static Chip Select Address
*/
#define EMC_ADDRESS_CS0 (0x80000000)
#define EMC_ADDRESS_CS1 (0x90000000)
#define EMC_ADDRESS_CS2 (0x98000000)
#define EMC_ADDRESS_CS3 (0x9C000000)
/**
* @brief EMC register support bitfields and mask
*/
/* Reserve for extending support to ARM9 or nextgen LPC */
#define EMC_SUPPORT_ONLY_PL172 /*!< Reserve for extending support to ARM9 or nextgen LPC */
#define EMC_CONFIG_ENDIAN_LITTLE (0) /*!< Value for EMC to operate in Little Endian Mode */
#define EMC_CONFIG_ENDIAN_BIG (1) /*!< Value for EMC to operate in Big Endian Mode */
#define EMC_CONFIG_BUFFER_ENABLE (1 << 19) /*!< EMC Buffer enable bit in EMC Dynamic Configuration register */
#define EMC_CONFIG_WRITE_PROTECT (1 << 20) /*!< EMC Write protect bit in EMC Dynamic Configuration register */
/* Dynamic Memory Configuration Register Bit Definitions */
#define EMC_DYN_CONFIG_MD_BIT (3) /*!< Memory device bit in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as SDRAM in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as LPSDRAM in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_LPSDRAM_BIT (12) /*!< LPSDRAM bit in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT) /*!< LPSDRAM value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_SIZE_BIT (9) /*!< Device Size starting bit in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 16Mb Device Size value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 64Mb Device Size value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 128Mb Device Size value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 256Mb Device Size value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 512Mb Device Size value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_BUS_BIT (7) /*!< Device bus width starting bit in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 8-bit bus width value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 16-bit bus width value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14) /*!< Device data bus width starting bit in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */
#define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
/*!< Memory configuration values in EMC Dynamic Configuration Register */
#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */
#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */
#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */
#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */
#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */
#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */
#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */
#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */
#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */
#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */
#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */
#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */
#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */
/*!< Dynamic Memory Mode Register Bit Definition */
#define EMC_DYN_MODE_BURST_LEN_BIT (0) /*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_LEN_1 (0) /*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_LEN_2 (1) /*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_LEN_4 (2) /*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_LEN_8 (3) /*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_LEN_FULL (7) /*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_TYPE_BIT (3) /*!< Burst Type bit in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Sequential in Dynamic Memory Mode Register */
#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Interleaved in Dynamic Memory Mode Register */
/*!< CAS Latency in Dynamic Mode Register */
#define EMC_DYN_MODE_CAS_BIT (4) /*!< CAS latency starting bit in Dynamic Memory Mode register */
#define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 1 cycle */
#define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 2 cycle */
#define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 3 cycle */
/*!< Operation Mode in Dynamic Mode register */
#define EMC_DYN_MODE_OPMODE_BIT (7) /*!< Dynamic Mode Operation bit */
#define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT) /*!< Value for Dynamic standard operation Mode */
/*!< Write Burst Mode in Dynamic Mode register */
#define EMC_DYN_MODE_WBMODE_BIT (9) /*!< Write Burst Mode bit */
#define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode programmed */
#define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode Single LOC */
/*!< Dynamic Memory Control Register Bit Definitions */
#define EMC_DYN_CONTROL_ENABLE (0x03) /*!< Control Enable value */
/*!< Static Memory Configuration Register Bit Definitions */
#define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0) /*!< Static Memory Configuration - 8-bit width */
#define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1) /*!< Static Memory Configuration - 16-bit width */
#define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2) /*!< Static Memory Configuration - 32-bit width */
#define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3) /*!< Page Mode bit No */
#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT) /*!< Value to enable Page Mode */
#define EMC_STATIC_CONFIG_CS_POL_BIT (6) /*!< Chip Select bit No */
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active High */
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active Low */
#define EMC_STATIC_CONFIG_BLS_BIT (7) /*!< BLS Configuration bit No */
#define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS High Configuration value */
#define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS Low Configuration value */
#define EMC_STATIC_CONFIG_EW_BIT (8) /*!< Ext Wait bit No */
#define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Enabled value */
#define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Diabled value */
/*!< Q24.8 Fixed Point Helper */
#define Q24_8_FP(x) ((x) * 256)
#define EMC_NANOSECOND(x) Q24_8_FP(x)
#define EMC_CLOCK(x) Q24_8_FP(-(x))
/**
* @brief EMC Dynamic Device Configuration structure used for IP drivers
*/
typedef struct {
uint32_t BaseAddr; /*!< Base Address */
uint8_t RAS; /*!< RAS value */
uint32_t ModeRegister; /*!< Mode Register value */
uint32_t DynConfig; /*!< Dynamic Configuration value */
} IP_EMC_DYN_DEVICE_CONFIG_T;
/**
* @brief EMC Dynamic Configure Struct
*/
typedef struct {
int32_t RefreshPeriod; /*!< Refresh period */
uint32_t ReadConfig; /*!< Clock*/
int32_t tRP; /*!< Precharge Command Period */
int32_t tRAS; /*!< Active to Precharge Command Period */
int32_t tSREX; /*!< Self Refresh Exit Time */
int32_t tAPR; /*!< Last Data Out to Active Time */
int32_t tDAL; /*!< Data In to Active Command Time */
int32_t tWR; /*!< Write Recovery Time */
int32_t tRC; /*!< Active to Active Command Period */
int32_t tRFC; /*!< Auto-refresh Period */
int32_t tXSR; /*!< Exit Selt Refresh */
int32_t tRRD; /*!< Active Bank A to Active Bank B Time */
int32_t tMRD; /*!< Load Mode register command to Active Command */
IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4]; /*!< Device Configuration array */
} IP_EMC_DYN_CONFIG_T;
/**
* @brief EMC Static Configure Structure
*/
typedef struct {
uint8_t ChipSelect; /*!< Chip select */
uint32_t Config; /*!< Configuration value */
int32_t WaitWen; /*!< Write Enable Wait */
int32_t WaitOen; /*!< Output Enable Wait */
int32_t WaitRd; /*!< Read Wait */
int32_t WaitPage; /*!< Page Access Wait */
int32_t WaitWr; /*!< Write Wait */
int32_t WaitTurn; /*!< Turn around wait */
} IP_EMC_STATIC_CONFIG_T;
/**
* @brief Dyanmic memory setup
* @param Dynamic_Config : Pointer to dynamic memory setup data
* @return None
*/
void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config);
/**
* @brief Static memory setup
* @param Static_Config : Pointer to static memory setup data
* @return None
*/
void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config);
/**
* @brief Enable Dynamic Memory Controller
* @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable
* @return None
*/
void Chip_EMC_Dynamic_Enable(uint8_t Enable);
/**
* @brief Mirror CS1 to CS0 and DYCS0
* @param Enable : 1 = Mirror, 0 = Normal Memory Map
* @return None
*/
void Chip_EMC_Mirror(uint8_t Enable);
/**
* @brief Enable EMC
* @param Enable : 1 = Enable, 0 = Disable
* @return None
*/
void Chip_EMC_Enable(uint8_t Enable);
/**
* @brief Set EMC LowPower Mode
* @param Enable : 1 = Enable, 0 = Disable
* @return None
* @note This function should only be called when the memory
* controller is not busy (bit 0 of the status register is not set).
*/
void Chip_EMC_LowPowerMode(uint8_t Enable);
/**
* @brief Initialize EMC
* @param Enable : 1 = Enable, 0 = Disable
* @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2
* @param EndianMode : Endian Mode, 0 = Little, 1 = Big
* @return None
*/
void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
/**
* @brief Set Static Memory Extended Wait in Clock
* @param Wait16Clks : Number of '16 clock' delay cycles
* @return None
*/
STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
{
LPC_EMC->STATICEXTENDEDWAIT = Wait16Clks;
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __EMC_17XX_40XX_H_ */

914
hw/mcu/nxp/lpc_chip_175x_6x/inc/enet_17xx_40xx.h Normal file
View File

@ -0,0 +1,914 @@
/*
* @brief LPC17xx/40xx Ethernet driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ENET_17XX_40XX_H_
#define __ENET_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ENET_17XX_40XX CHIP: LPC17xx/40xx Ethernet driver (2)
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief Ethernet MAC register block structure
*/
typedef struct {
__IO uint32_t MAC1; /*!< MAC Configuration register 1 */
__IO uint32_t MAC2; /*!< MAC Configuration register 2 */
__IO uint32_t IPGT; /*!< Back-to-Back Inter-Packet-Gap register */
__IO uint32_t IPGR; /*!< Non Back-to-Back Inter-Packet-Gap register */
__IO uint32_t CLRT; /*!< Collision window / Retry register */
__IO uint32_t MAXF; /*!< Maximum Frame register */
__IO uint32_t SUPP; /*!< PHY Support register */
__IO uint32_t TEST; /*!< Test register */
__IO uint32_t MCFG; /*!< MII Mgmt Configuration register */
__IO uint32_t MCMD; /*!< MII Mgmt Command register */
__IO uint32_t MADR; /*!< MII Mgmt Address register */
__O uint32_t MWTD; /*!< MII Mgmt Write Data register */
__I uint32_t MRDD; /*!< MII Mgmt Read Data register */
__I uint32_t MIND; /*!< MII Mgmt Indicators register */
uint32_t RESERVED0[2];
__IO uint32_t SA[3]; /*!< Station Address registers */
} ENET_MAC_T;
/**
* @brief Ethernet Transfer register Block Structure
*/
typedef struct {
__IO uint32_t DESCRIPTOR; /*!< Descriptor base address register */
__IO uint32_t STATUS; /*!< Status base address register */
__IO uint32_t DESCRIPTORNUMBER; /*!< Number of descriptors register */
__IO uint32_t PRODUCEINDEX; /*!< Produce index register */
__IO uint32_t CONSUMEINDEX; /*!< Consume index register */
} ENET_TRANSFER_INFO_T;
/**
* @brief Ethernet Control register block structure
*/
typedef struct {
__IO uint32_t COMMAND; /*!< Command register */
__I uint32_t STATUS; /*!< Status register */
ENET_TRANSFER_INFO_T RX; /*!< Receive block registers */
ENET_TRANSFER_INFO_T TX; /*!< Transmit block registers */
uint32_t RESERVED0[10];
__I uint32_t TSV0; /*!< Transmit status vector 0 register */
__I uint32_t TSV1; /*!< Transmit status vector 1 register */
__I uint32_t RSV; /*!< Receive status vector register */
uint32_t RESERVED1[3];
__IO uint32_t FLOWCONTROLCOUNTER; /*!< Flow control counter register */
__I uint32_t FLOWCONTROLSTATUS; /*!< Flow control status register */
} ENET_CONTROL_T;
/**
* @brief Ethernet Receive Filter register block structure
*/
typedef struct {
__IO uint32_t CONTROL; /*!< Receive filter control register */
__I uint32_t WOLSTATUS; /*!< Receive filter WoL status register */
__O uint32_t WOLCLEAR; /*!< Receive filter WoL clear register */
uint32_t RESERVED;
__IO uint32_t HashFilterL; /*!< Hash filter table LSBs register */
__IO uint32_t HashFilterH; /*!< Hash filter table MSBs register */
} ENET_RXFILTER_T;
/**
* @brief Ethernet Module Control register block structure
*/
typedef struct {
__I uint32_t INTSTATUS; /*!< Interrupt status register */
__IO uint32_t INTENABLE; /*!< Interrupt enable register */
__O uint32_t INTCLEAR; /*!< Interrupt clear register */
__O uint32_t INTSET; /*!< Interrupt set register */
uint32_t RESERVED;
__IO uint32_t POWERDOWN; /*!< Power-down register */
} ENET_MODULE_CTRL_T;
/**
* @brief Ethernet register block structure
*/
typedef struct {
ENET_MAC_T MAC; /*!< MAC registers */
uint32_t RESERVED1[45];
ENET_CONTROL_T CONTROL; /*!< Control registers */
uint32_t RESERVED4[34];
ENET_RXFILTER_T RXFILTER; /*!< RxFilter registers */
uint32_t RESERVED6[882];
ENET_MODULE_CTRL_T MODULE_CONTROL; /*!< Module Control registers */
} LPC_ENET_T;
/*
* @brief MAC Configuration Register 1 bit definitions
*/
#define ENET_MAC1_MASK 0xcf1f /*!< MAC1 register mask */
#define ENET_MAC1_RXENABLE 0x00000001 /*!< Receive Enable */
#define ENET_MAC1_PARF 0x00000002 /*!< Pass All Receive Frames */
#define ENET_MAC1_RXFLOWCTRL 0x00000004 /*!< RX Flow Control */
#define ENET_MAC1_TXFLOWCTRL 0x00000008 /*!< TX Flow Control */
#define ENET_MAC1_LOOPBACK 0x00000010 /*!< Loop Back Mode */
#define ENET_MAC1_RESETTX 0x00000100 /*!< Reset TX Logic */
#define ENET_MAC1_RESETMCSTX 0x00000200 /*!< Reset MAC TX Control Sublayer */
#define ENET_MAC1_RESETRX 0x00000400 /*!< Reset RX Logic */
#define ENET_MAC1_RESETMCSRX 0x00000800 /*!< Reset MAC RX Control Sublayer */
#define ENET_MAC1_SIMRESET 0x00004000 /*!< Simulation Reset */
#define ENET_MAC1_SOFTRESET 0x00008000 /*!< Soft Reset MAC */
/*
* @brief MAC Configuration Register 2 bit definitions
*/
#define ENET_MAC2_MASK 0x73ff /*!< MAC2 register mask */
#define ENET_MAC2_FULLDUPLEX 0x00000001 /*!< Full-Duplex Mode */
#define ENET_MAC2_FLC 0x00000002 /*!< Frame Length Checking */
#define ENET_MAC2_HFEN 0x00000004 /*!< Huge Frame Enable */
#define ENET_MAC2_DELAYEDCRC 0x00000008 /*!< Delayed CRC Mode */
#define ENET_MAC2_CRCEN 0x00000010 /*!< Append CRC to every Frame */
#define ENET_MAC2_PADCRCEN 0x00000020 /*!< Pad all Short Frames */
#define ENET_MAC2_VLANPADEN 0x00000040 /*!< VLAN Pad Enable */
#define ENET_MAC2_AUTODETPADEN 0x00000080 /*!< Auto Detect Pad Enable */
#define ENET_MAC2_PPENF 0x00000100 /*!< Pure Preamble Enforcement */
#define ENET_MAC2_LPENF 0x00000200 /*!< Long Preamble Enforcement */
#define ENET_MAC2_NOBACKOFF 0x00001000 /*!< No Backoff Algorithm */
#define ENET_MAC2_BP_NOBACKOFF 0x00002000 /*!< Backoff Presurre / No Backoff */
#define ENET_MAC2_EXCESSDEFER 0x00004000 /*!< Excess Defer */
/*
* @brief Back-to-Back Inter-Packet-Gap Register bit definitions
*/
/** Programmable field representing the nibble time offset of the minimum possible period
* between the end of any transmitted packet to the beginning of the next */
#define ENET_IPGT_BTOBINTEGAP(n) ((n) & 0x7F)
/** Recommended value for Full Duplex of Programmable field representing the nibble time
* offset of the minimum possible period between the end of any transmitted packet to the
* beginning of the next */
#define ENET_IPGT_FULLDUPLEX (ENET_IPGT_BTOBINTEGAP(0x15))
/** Recommended value for Half Duplex of Programmable field representing the nibble time
* offset of the minimum possible period between the end of any transmitted packet to the
* beginning of the next */
#define ENET_IPGT_HALFDUPLEX (ENET_IPGT_BTOBINTEGAP(0x12))
/*
* @brief Non Back-to-Back Inter-Packet-Gap Register bit definitions
*/
/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
#define ENET_IPGR_NBTOBINTEGAP2(n) ((n) & 0x7F)
/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
#define ENET_IPGR_P2_DEF (ENET_IPGR_NBTOBINTEGAP2(0x12))
/** Programmable field representing the optional carrierSense window referenced in
* IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
#define ENET_IPGR_NBTOBINTEGAP1(n) (((n) & 0x7F) << 8)
/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
#define ENET_IPGR_P1_DEF ENET_IPGR_NBTOBINTEGAP1(0x0C)
/*
* @brief Collision Window/Retry Register bit definitions
*/
/** Programmable field specifying the number of retransmission attempts following a collision before
* aborting the packet due to excessive collisions */
#define ENET_CLRT_RETRANSMAX(n) ((n) & 0x0F)
/** Programmable field representing the slot time or collision window during which collisions occur
* in properly configured networks */
#define ENET_CLRT_COLLWIN(n) (((n) & 0x3F) << 8)
/** Default value for Collision Window / Retry register */
#define ENET_CLRT_DEF ((ENET_CLRT_RETRANSMAX(0x0F)) | (ENET_CLRT_COLLWIN(0x37)))
/*
* @brief Maximum Frame Register bit definitions
*/
/** Represents a maximum receive frame of 1536 octets */
#define ENET_MAXF_MAXFLEN(n) ((n) & 0xFFFF)
#define ENET_MAXF_MAXFLEN_DEF (0x600)
/* PHY Support Register */
#define ENET_SUPP_100Mbps_SPEED 0x00000100 /*!< Reduced MII Logic Current Speed */
/*
* @brief Test Register bit definitions
*/
#define ENET_TEST_SCPQ 0x00000001 /*!< Shortcut Pause Quanta */
#define ENET_TEST_TESTPAUSE 0x00000002 /*!< Test Pause */
#define ENET_TEST_TESTBP 0x00000004 /*!< Test Back Pressure */
/*
* @brief MII Management Configuration Register bit definitions
*/
#define ENET_MCFG_SCANINC 0x00000001 /*!< Scan Increment PHY Address */
#define ENET_MCFG_SUPPPREAMBLE 0x00000002 /*!< Suppress Preamble */
#define ENET_MCFG_CLOCKSEL(n) (((n) & 0x0F) << 2) /*!< Clock Select Field */
#define ENET_MCFG_RES_MII 0x00008000 /*!< Reset MII Management Hardware */
#define ENET_MCFG_RESETMIIMGMT 2500000UL /*!< MII Clock max */
/*
* @brief MII Management Command Register bit definitions
*/
#define ENET_MCMD_READ 0x00000001 /*!< MII Read */
#define ENET_MCMD_SCAN 0x00000002 /*!< MII Scan continuously */
#define ENET_MII_WR_TOUT 0x00050000 /*!< MII Write timeout count */
#define ENET_MII_RD_TOUT 0x00050000 /*!< MII Read timeout count */
/*
* @brief MII Management Address Register bit definitions
*/
#define ENET_MADR_REGADDR(n) ((n) & 0x1F) /*!< MII Register Address field */
#define ENET_MADR_PHYADDR(n) (((n) & 0x1F) << 8) /*!< PHY Address Field */
/*
* @brief MII Management Write Data Register bit definitions
*/
#define ENET_MWTD_DATA(n) ((n) & 0xFFFF) /*!< Data field for MMI Management Write Data register */
/**
* @brief MII Management Read Data Register bit definitions
*/
#define ENET_MRDD_DATA(n) ((n) & 0xFFFF) /*!< Data field for MMI Management Read Data register */
/*
* @brief MII Management Indicators Register bit definitions
*/
#define ENET_MIND_BUSY 0x00000001 /*!< MII is Busy */
#define ENET_MIND_SCANNING 0x00000002 /*!< MII Scanning in Progress */
#define ENET_MIND_NOTVALID 0x00000004 /*!< MII Read Data not valid */
#define ENET_MIND_MIILINKFAIL 0x00000008 /*!< MII Link Failed */
/*
* @brief Command Register bit definitions
*/
#define ENET_COMMAND_RXENABLE 0x00000001 /*!< Enable Receive */
#define ENET_COMMAND_TXENABLE 0x00000002 /*!< Enable Transmit */
#define ENET_COMMAND_REGRESET 0x00000008 /*!< Reset Host Registers */
#define ENET_COMMAND_TXRESET 0x00000010 /*!< Reset Transmit Datapath */
#define ENET_COMMAND_RXRESET 0x00000020 /*!< Reset Receive Datapath */
#define ENET_COMMAND_PASSRUNTFRAME 0x00000040 /*!< Pass Runt Frames */
#define ENET_COMMAND_PASSRXFILTER 0x00000080 /*!< Pass RX Filter */
#define ENET_COMMAND_TXFLOWCONTROL 0x00000100 /*!< TX Flow Control */
#define ENET_COMMAND_RMII 0x00000200 /*!< Reduced MII Interface */
#define ENET_COMMAND_FULLDUPLEX 0x00000400 /*!< Full Duplex */
/*
* @brief Status Register bit definitions
*/
#define ENET_STATUS_RXSTATUS 0x00000001 /*!< Receive Channel Active Status */
#define ENET_STATUS_TXSTATUS 0x00000002 /*!< Transmit Channel Active Status */
/*
* @brief Transmit Status Vector 0 Register bit definitions
*/
#define ENET_TSV0_CRCERR 0x00000001 /*!< CRC error */
#define ENET_TSV0_LCE 0x00000002 /*!< Length Check Error */
#define ENET_TSV0_LOR 0x00000004 /*!< Length Out of Range */
#define ENET_TSV0_DONE 0x00000008 /*!< Tramsmission Completed */
#define ENET_TSV0_MULTICAST 0x00000010 /*!< Multicast Destination */
#define ENET_TSV0_BROADCAST 0x00000020 /*!< Broadcast Destination */
#define ENET_TSV0_PACKETDEFER 0x00000040 /*!< Packet Deferred */
#define ENET_TSV0_EXDF 0x00000080 /*!< Excessive Packet Deferral */
#define ENET_TSV0_EXCOL 0x00000100 /*!< Excessive Collision */
#define ENET_TSV0_LCOL 0x00000200 /*!< Late Collision Occured */
#define ENET_TSV0_GIANT 0x00000400 /*!< Giant Frame */
#define ENET_TSV0_UNDERRUN 0x00000800 /*!< Buffer Underrun */
#define ENET_TSV0_TOTALBYTES 0x0FFFF000 /*!< Total Bytes Transferred */
#define ENET_TSV0_CONTROLFRAME 0x10000000 /*!< Control Frame */
#define ENET_TSV0_PAUSE 0x20000000 /*!< Pause Frame */
#define ENET_TSV0_BACKPRESSURE 0x40000000 /*!< Backpressure Method Applied */
#define ENET_TSV0_VLAN 0x80000000 /*!< VLAN Frame */
/*
* @brief Transmit Status Vector 0 Register bit definitions
*/
#define ENET_TSV1_TBC 0x0000FFFF /*!< Transmit Byte Count */
#define ENET_TSV1_TCC 0x000F0000 /*!< Transmit Collision Count */
/*
* @brief Receive Status Vector Register bit definitions
*/
#define ENET_RSV_RBC 0x0000FFFF /*!< Receive Byte Count */
#define ENET_RSV_PPI 0x00010000 /*!< Packet Previously Ignored */
#define ENET_RSV_RXDVSEEN 0x00020000 /*!< RXDV Event Previously Seen */
#define ENET_RSV_CESEEN 0x00040000 /*!< Carrier Event Previously Seen */
#define ENET_RSV_RCV 0x00080000 /*!< Receive Code Violation */
#define ENET_RSV_CRCERR 0x00100000 /*!< CRC Error */
#define ENET_RSV_LCERR 0x00200000 /*!< Length Check Error */
#define ENET_RSV_LOR 0x00400000 /*!< Length Out of Range */
#define ENET_RSV_ROK 0x00800000 /*!< Frame Received OK */
#define ENET_RSV_MULTICAST 0x01000000 /*!< Multicast Frame */
#define ENET_RSV_BROADCAST 0x02000000 /*!< Broadcast Frame */
#define ENET_RSV_DRIBBLENIBBLE 0x04000000 /*!< Dribble Nibble */
#define ENET_RSV_CONTROLFRAME 0x08000000 /*!< Control Frame */
#define ENET_RSV_PAUSE 0x10000000 /*!< Pause Frame */
#define ENET_RSV_UO 0x20000000 /*!< Unsupported Opcode */
#define ENET_RSV_VLAN 0x40000000 /*!< VLAN Frame */
/*
* @brief Flow Control Counter Register bit definitions
*/
#define ENET_FLOWCONTROLCOUNTER_MC(n) ((n) & 0xFFFF) /*!< Mirror Counter */
#define ENET_FLOWCONTROLCOUNTER_PT(n) (((n) & 0xFFFF) << 16) /*!< Pause Timer */
/*
* @brief Flow Control Status Register bit definitions
*/
#define ENET_FLOWCONTROLSTATUS_MCC(n) ((n) & 0xFFFF) /*!< Mirror Counter Current */
/*
* @brief Receive Filter Control Register bit definitions
*/
#define ENET_RXFILTERCTRL_AUE 0x00000001 /*!< Accept Unicast Frames Enable */
#define ENET_RXFILTERCTRL_ABE 0x00000002 /*!< Accept Broadcast Frames Enable */
#define ENET_RXFILTERCTRL_AME 0x00000004 /*!< Accept Multicast Frames Enable */
#define ENET_RXFILTERCTRL_AUHE 0x00000008 /*!< Accept Unicast Hash Filter Frames */
#define ENET_RXFILTERCTRL_AMHE 0x00000010 /*!< Accept Multicast Hash Filter Fram */
#define ENET_RXFILTERCTRL_APE 0x00000020 /*!< Accept Perfect Match Enable */
#define ENET_RXFILTERCTRL_MPEW 0x00001000 /*!< Magic Packet Filter WoL Enable */
#define ENET_RXFILTERCTRL_RFEW 0x00002000 /*!< Perfect Filter WoL Enable */
/*
* @brief Receive Filter WoL Status/Clear Register bit definitions
*/
#define ENET_RXFILTERWOLSTATUS_AUW 0x00000001 /*!< Unicast Frame caused WoL */
#define ENET_RXFILTERWOLSTATUS_ABW 0x00000002 /*!< Broadcast Frame caused WoL */
#define ENET_RXFILTERWOLSTATUS_AMW 0x00000004 /*!< Multicast Frame caused WoL */
#define ENET_RXFILTERWOLSTATUS_AUHW 0x00000008 /*!< Unicast Hash Filter Frame WoL */
#define ENET_RXFILTERWOLSTATUS_AMHW 0x00000010 /*!< Multicast Hash Filter Frame WoL */
#define ENET_RXFILTERWOLSTATUS_APW 0x00000020 /*!< Perfect Filter WoL */
#define ENET_RXFILTERWOLSTATUS_RFW 0x00000080 /*!< RX Filter caused WoL */
#define ENET_RXFILTERWOLSTATUS_MPW 0x00000100 /*!< Magic Packet Filter caused WoL */
#define ENET_RXFILTERWOLSTATUS_BITMASK 0x01BF /*!< Receive Filter WoL Status/Clear bitmasl value */
/*
* @brief Interrupt Status/Enable/Clear/Set Register bit definitions
*/
#define ENET_INT_RXOVERRUN 0x00000001 /*!< Overrun Error in RX Queue */
#define ENET_INT_RXERROR 0x00000002 /*!< Receive Error */
#define ENET_INT_RXFINISHED 0x00000004 /*!< RX Finished Process Descriptors */
#define ENET_INT_RXDONE 0x00000008 /*!< Receive Done */
#define ENET_INT_TXUNDERRUN 0x00000010 /*!< Transmit Underrun */
#define ENET_INT_TXERROR 0x00000020 /*!< Transmit Error */
#define ENET_INT_TXFINISHED 0x00000040 /*!< TX Finished Process Descriptors */
#define ENET_INT_TXDONE 0x00000080 /*!< Transmit Done */
#define ENET_INT_SOFT 0x00001000 /*!< Software Triggered Interrupt */
#define ENET_INT_WAKEUP 0x00002000 /*!< Wakeup Event Interrupt */
/*
* @brief Power Down Register bit definitions
*/
#define ENET_POWERDOWN_PD 0x80000000 /*!< Power Down MAC */
/**
* @brief RX Descriptor structure
*/
typedef struct {
uint32_t Packet; /*!< Base address of the data buffer for storing receive data */
uint32_t Control; /*!< Control information */
} ENET_RXDESC_T;
/**
* @brief RX Descriptor Control structure type definition
*/
#define ENET_RCTRL_SIZE(n) (((n) - 1) & 0x7FF) /*!< Buffer size field */
#define ENET_RCTRL_INT 0x80000000 /*!< Generate RxDone Interrupt */
/**
* @brief RX Status structure
*/
typedef struct {
uint32_t StatusInfo; /*!< Receive status return flags.*/
uint32_t StatusHashCRC; /*!< The concatenation of the destination address hash CRC and the source
address hash CRC */
} ENET_RXSTAT_T;
/*
* @brief RX Status Hash CRC Word definition
*/
#define ENET_RHASH_SA 0x000001FF /*!< Hash CRC for Source Address */
#define ENET_RHASH_DA 0x001FF000 /*!< Hash CRC for Destination Address */
/* RX Status Information Word */
#define ENET_RINFO_SIZE(n) (((n) & 0x7FF) + 1) /*!< Data size in bytes */
#define ENET_RINFO_CTRL_FRAME 0x00040000 /*!< Control Frame */
#define ENET_RINFO_VLAN 0x00080000 /*!< VLAN Frame */
#define ENET_RINFO_FAIL_FILT 0x00100000 /*!< RX Filter Failed */
#define ENET_RINFO_MCAST 0x00200000 /*!< Multicast Frame */
#define ENET_RINFO_BCAST 0x00400000 /*!< Broadcast Frame */
#define ENET_RINFO_CRC_ERR 0x00800000 /*!< CRC Error in Frame */
#define ENET_RINFO_SYM_ERR 0x01000000 /*!< Symbol Error from PHY */
#define ENET_RINFO_LEN_ERR 0x02000000 /*!< Length Error */
#define ENET_RINFO_RANGE_ERR 0x04000000 /*!< Range Error (exceeded max. size) */
#define ENET_RINFO_ALIGN_ERR 0x08000000 /*!< Alignment Error */
#define ENET_RINFO_OVERRUN 0x10000000 /*!< Receive overrun */
#define ENET_RINFO_NO_DESCR 0x20000000 /*!< No new Descriptor available */
#define ENET_RINFO_LAST_FLAG 0x40000000 /*!< Last Fragment in Frame */
#define ENET_RINFO_ERR 0x80000000 /*!< Error Occured (OR of all errors) */
/** RX Error status mask */
#define ENET_RINFO_ERR_MASK (ENET_RINFO_FAIL_FILT | ENET_RINFO_CRC_ERR | ENET_RINFO_SYM_ERR | \
ENET_RINFO_LEN_ERR | ENET_RINFO_ALIGN_ERR | ENET_RINFO_OVERRUN)
/**
* @brief TX Descriptor structure
*/
typedef struct {
uint32_t Packet; /*!< Base address of the data buffer containing transmit data */
uint32_t Control; /*!< Control information */
} ENET_TXDESC_T;
/*
* @brief TX Descriptor Control structure type definition
*/
#define ENET_TCTRL_SIZE(n) (((n) - 1) & 0x7FF) /*!< Size of data buffer in bytes */
#define ENET_TCTRL_OVERRIDE 0x04000000 /*!< Override Default MAC Registers */
#define ENET_TCTRL_HUGE 0x08000000 /*!< Enable Huge Frame */
#define ENET_TCTRL_PAD 0x10000000 /*!< Pad short Frames to 64 bytes */
#define ENET_TCTRL_CRC 0x20000000 /*!< Append a hardware CRC to Frame */
#define ENET_TCTRL_LAST 0x40000000 /*!< Last Descriptor for TX Frame */
#define ENET_TCTRL_INT 0x80000000 /*!< Generate TxDone Interrupt */
/**
* @brief TX Status structure
*/
typedef struct {
uint32_t StatusInfo; /*!< Receive status return flags.*/
} ENET_TXSTAT_T;
/* TX Status Information Word */
#define ENET_TINFO_COL_CNT 0x01E00000 /*!< Collision Count */
#define ENET_TINFO_DEFER 0x02000000 /*!< Packet Deferred (not an error) */
#define ENET_TINFO_EXCESS_DEF 0x04000000 /*!< Excessive Deferral */
#define ENET_TINFO_EXCESS_COL 0x08000000 /*!< Excessive Collision */
#define ENET_TINFO_LATE_COL 0x10000000 /*!< Late Collision Occured */
#define ENET_TINFO_UNDERRUN 0x20000000 /*!< Transmit Underrun */
#define ENET_TINFO_NO_DESCR 0x40000000 /*!< No new Descriptor available */
#define ENET_TINFO_ERR 0x80000000 /*!< Error Occured (OR of all errors) */
/**
* @brief Maximum size of an ethernet buffer
*/
#define ENET_ETH_MAX_FLEN (1536)
/**
* @brief ENET Buffer status definition
*/
typedef enum {
ENET_BUFF_EMPTY, /* buffer is empty */
ENET_BUFF_PARTIAL_FULL, /* buffer contains some packets */
ENET_BUFF_FULL, /* buffer is full */
} ENET_BUFF_STATUS_T;
/**
* @brief Resets the ethernet interface
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
* @note Resets the ethernet interface. This should be called prior to
* Chip_ENET_Init with a small delay after this call.
*/
STATIC INLINE void Chip_ENET_Reset(LPC_ENET_T *pENET)
{
/* This should be called prior to IP_ENET_Init. The MAC controller may
not be ready for a call to init right away so a small delay should
occur after this call. */
pENET->MAC.MAC1 = ENET_MAC1_RESETTX | ENET_MAC1_RESETMCSTX | ENET_MAC1_RESETRX |
ENET_MAC1_RESETMCSRX | ENET_MAC1_SIMRESET | ENET_MAC1_SOFTRESET;
pENET->CONTROL.COMMAND = ENET_COMMAND_REGRESET | ENET_COMMAND_TXRESET | ENET_COMMAND_RXRESET |
ENET_COMMAND_PASSRUNTFRAME;
}
/**
* @brief Sets the address of the interface
* @param pENET : The base of ENET peripheral on the chip
* @param macAddr : Pointer to the 6 bytes used for the MAC address
* @return Nothing
*/
STATIC INLINE void Chip_ENET_SetADDR(LPC_ENET_T *pENET, const uint8_t *macAddr)
{
/* Save MAC address */
pENET->MAC.SA[0] = ((uint32_t) macAddr[5] << 8) | ((uint32_t) macAddr[4]);
pENET->MAC.SA[1] = ((uint32_t) macAddr[3] << 8) | ((uint32_t) macAddr[2]);
pENET->MAC.SA[2] = ((uint32_t) macAddr[1] << 8) | ((uint32_t) macAddr[0]);
}
/**
* @brief Sets up the PHY link clock divider and PHY address
* @param pENET : The base of ENET peripheral on the chip
* @param div : Divider index, not a divider value, see user manual
* @param addr : PHY address, used with MII read and write
* @return Nothing
* @note The MII clock divider rate is divided from the peripheral clock returned
* from the Chip_Clock_GetSystemClockRate() function. Use Chip_ENET_FindMIIDiv()
* with a desired clock rate to find the correct divider index value.
*/
void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr);
/**
* @brief Starts a PHY write via the MII
* @param pENET : The base of ENET peripheral on the chip
* @param reg : PHY register to write
* @param data : Data to write to PHY register
* @return Nothing
* @note Start a PHY write operation. Does not block, requires calling
* IP_ENET_IsMIIBusy to determine when write is complete.
*/
void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data);
/**
* @brief Starts a PHY read via the MII
* @param pENET : The base of ENET peripheral on the chip
* @param reg : PHY register to read
* @return Nothing
* @note Start a PHY read operation. Does not block, requires calling
* IP_ENET_IsMIIBusy to determine when read is complete and calling
* IP_ENET_ReadMIIData to get the data.
*/
void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg);
/**
* @brief Returns MII link (PHY) busy status
* @param pENET : The base of ENET peripheral on the chip
* @return Returns true if busy, otherwise false
*/
STATIC INLINE bool Chip_ENET_IsMIIBusy(LPC_ENET_T *pENET)
{
return (pENET->MAC.MIND & ENET_MIND_BUSY) ? true : false;
}
/**
* @brief Returns the value read from the PHY
* @param pENET : The base of ENET peripheral on the chip
* @return Read value from PHY
*/
uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET);
/**
* @brief Enables ethernet transmit
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_TXEnable(LPC_ENET_T *pENET)
{
/* Descriptor list head pointers must be setup prior to enable */
pENET->CONTROL.COMMAND |= ENET_COMMAND_TXENABLE;
}
/**
* @brief Disables ethernet transmit
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_TXDisable(LPC_ENET_T *pENET)
{
pENET->CONTROL.COMMAND &= ~ENET_COMMAND_TXENABLE;
}
/**
* @brief Enables ethernet packet reception
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_RXEnable(LPC_ENET_T *pENET)
{
/* Descriptor list head pointers must be setup prior to enable */
pENET->CONTROL.COMMAND |= ENET_COMMAND_RXENABLE;
pENET->MAC.MAC1 |= ENET_MAC1_RXENABLE;
}
/**
* @brief Disables ethernet packet reception
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
{
pENET->CONTROL.COMMAND &= ~ENET_COMMAND_RXENABLE;
pENET->MAC.MAC1 &= ~ENET_MAC1_RXENABLE;
}
/**
* @brief Reset Tx Logic
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_ResetTXLogic(LPC_ENET_T *pENET)
{
pENET->MAC.MAC1 |= ENET_MAC1_RESETTX;
}
/**
* @brief Reset Rx Logic
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_ResetRXLogic(LPC_ENET_T *pENET)
{
pENET->MAC.MAC1 |= ENET_MAC1_RESETRX;
}
/**
* @brief Enable Rx Filter
* @param pENET : The base of ENET peripheral on the chip
* @param mask : Filter mask (Or-ed bit values of ENET_RXFILTERCTRL_*)
* @return Nothing
*/
STATIC INLINE void Chip_ENET_EnableRXFilter(LPC_ENET_T *pENET, uint32_t mask)
{
pENET->CONTROL.COMMAND &= ~ENET_COMMAND_PASSRXFILTER;
pENET->RXFILTER.CONTROL |= mask;
}
/**
* @brief Disable Rx Filter
* @param pENET : The base of ENET peripheral on the chip
* @param mask : Filter mask (Or-ed bit values of ENET_RXFILTERCTRL_*)
* @return Nothing
*/
STATIC INLINE void Chip_ENET_DisableRXFilter(LPC_ENET_T *pENET, uint32_t mask)
{
pENET->RXFILTER.CONTROL &= ~mask;
}
/**
* @brief Sets full duplex operation for the interface
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
void Chip_ENET_SetFullDuplex(LPC_ENET_T *pENET);
/**
* @brief Sets half duplex operation for the interface
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
void Chip_ENET_SetHalfDuplex(LPC_ENET_T *pENET);
/**
* @brief Selects 100Mbps for the current speed
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_Set100Mbps(LPC_ENET_T *pENET)
{
pENET->MAC.SUPP = ENET_SUPP_100Mbps_SPEED;
}
/**
* @brief Selects 10Mbps for the current speed
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_ENET_Set10Mbps(LPC_ENET_T *pENET)
{
pENET->MAC.SUPP = 0;
}
/**
* @brief Configures the initial ethernet transmit descriptors
* @param pENET : The base of ENET peripheral on the chip
* @param pDescs : Pointer to TX descriptor list
* @param pStatus : Pointer to TX status list
* @param descNum : the number of desciptors
* @return Nothing
*/
void Chip_ENET_InitTxDescriptors(LPC_ENET_T *pENET, ENET_TXDESC_T *pDescs,
ENET_TXSTAT_T *pStatus,
uint32_t descNum);
/**
* @brief Configures the initial ethernet receive descriptors
* @param pENET : The base of ENET peripheral on the chip
* @param pDescs : Pointer to TX descriptor list
* @param pStatus : Pointer to TX status list
* @param descNum : the number of desciptors
* @return Nothing
*/
void Chip_ENET_InitRxDescriptors(LPC_ENET_T *pENET, ENET_RXDESC_T *pDescs,
ENET_RXSTAT_T *pStatus,
uint32_t descNum);
/**
* @brief Get the current Tx Produce Descriptor Index
* @param pENET : The base of ENET peripheral on the chip
* @return Tx Produce Index
*/
STATIC INLINE uint16_t Chip_ENET_GetTXProduceIndex(LPC_ENET_T *pENET)
{
return pENET->CONTROL.TX.PRODUCEINDEX;
}
/**
* @brief Get the current Tx Consume Descriptor Index
* @param pENET : The base of ENET peripheral on the chip
* @return Tx Consume Index
*/
STATIC INLINE uint16_t Chip_ENET_GetTXConsumeIndex(LPC_ENET_T *pENET)
{
return pENET->CONTROL.TX.CONSUMEINDEX;
}
/**
* @brief Get the current Rx Produce Descriptor Index
* @param pENET : The base of ENET peripheral on the chip
* @return Rx Produce Index
*/
STATIC INLINE uint16_t Chip_ENET_GetRXProduceIndex(LPC_ENET_T *pENET)
{
return pENET->CONTROL.RX.PRODUCEINDEX;
}
/**
* @brief Get the current Rx Consume Descriptor Index
* @param pENET : The base of ENET peripheral on the chip
* @return Rx Consume Index
*/
STATIC INLINE uint16_t Chip_ENET_GetRXConsumeIndex(LPC_ENET_T *pENET)
{
return pENET->CONTROL.RX.CONSUMEINDEX;
}
/**
* @brief Get the buffer status with the current Produce Index and Consume Index
* @param pENET : The base of ENET peripheral on the chip
* @param produceIndex : Produce Index
* @param consumeIndex : Consume Index
* @param buffSize : Buffer size
* @return Status (One of status value: ENET_BUFF_EMPTY/ENET_BUFF_FULL/ENET_BUFF_PARTIAL_FULL)
*/
ENET_BUFF_STATUS_T Chip_ENET_GetBufferStatus(LPC_ENET_T *pENET, uint16_t produceIndex,
uint16_t consumeIndex,
uint16_t buffSize);
/**
* @brief Get the number of descriptors filled
* @param pENET : The base of ENET peripheral on the chip
* @param produceIndex : Produce Index
* @param consumeIndex : Consume Index
* @param buffSize : Buffer size
* @return the number of descriptors
*/
uint32_t Chip_ENET_GetFillDescNum(LPC_ENET_T *pENET, uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize);
/**
* @brief Get the number of free descriptors
* @param pENET : The base of ENET peripheral on the chip
* @param produceIndex : Produce Index
* @param consumeIndex : Consume Index
* @param buffSize : Buffer size
* @return the number of descriptors
*/
STATIC INLINE uint32_t Chip_ENET_GetFreeDescNum(LPC_ENET_T *pENET,
uint16_t produceIndex,
uint16_t consumeIndex,
uint16_t buffSize)
{
return buffSize - 1 - Chip_ENET_GetFillDescNum(pENET, produceIndex, consumeIndex, buffSize);
}
/**
* @brief Check if Tx buffer is full
* @param pENET : The base of ENET peripheral on the chip
* @return true/false
*/
STATIC INLINE bool Chip_ENET_IsTxFull(LPC_ENET_T *pENET)
{
return ((pENET->CONTROL.TX.CONSUMEINDEX == (pENET->CONTROL.TX.PRODUCEINDEX + 1)) ||
((pENET->CONTROL.TX.CONSUMEINDEX == 0) &&
(pENET->CONTROL.TX.PRODUCEINDEX == pENET->CONTROL.TX.DESCRIPTORNUMBER))) ? true : false;
}
/**
* @brief Check if Rx buffer is empty
* @param pENET : The base of ENET peripheral on the chip
* @return true/false
*/
STATIC INLINE bool Chip_ENET_IsRxEmpty(LPC_ENET_T *pENET)
{
uint32_t tem = pENET->CONTROL.RX.PRODUCEINDEX;
return (pENET->CONTROL.RX.CONSUMEINDEX != tem) ? false : true;
}
/**
* @brief Increase the current Tx Produce Descriptor Index
* @param pENET : The base of ENET peripheral on the chip
* @return The new index value
*/
uint16_t Chip_ENET_IncTXProduceIndex(LPC_ENET_T *pENET);
/**
* @brief Increase the current Rx Consume Descriptor Index
* @param pENET : The base of ENET peripheral on the chip
* @return The new index value
*/
uint16_t Chip_ENET_IncRXConsumeIndex(LPC_ENET_T *pENET);
/**
* @brief Enable ENET interrupts
* @param pENET : The base of ENET peripheral on the chip
* @param mask : Interrupt mask (Or-ed bit values of ENET_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_ENET_EnableInt(LPC_ENET_T *pENET, uint32_t mask)
{
pENET->MODULE_CONTROL.INTENABLE |= mask;
}
/**
* @brief Disable ENET interrupts
* @param pENET : The base of ENET peripheral on the chip
* @param mask : Interrupt mask (Or-ed bit values of ENET_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_ENET_DisableInt(LPC_ENET_T *pENET, uint32_t mask)
{
pENET->MODULE_CONTROL.INTENABLE &= ~mask;
}
/**
* @brief Get the interrupt status
* @param pENET : The base of ENET peripheral on the chip
* @return interrupt status (Or-ed bit values of ENET_INT_*)
*/
STATIC INLINE uint32_t Chip_ENET_GetIntStatus(LPC_ENET_T *pENET)
{
return pENET->MODULE_CONTROL.INTSTATUS;
}
/**
* @brief Clear the interrupt status
* @param pENET : The base of ENET peripheral on the chip
* @param mask : Interrupt mask (Or-ed bit values of ENET_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_ENET_ClearIntStatus(LPC_ENET_T *pENET, uint32_t mask)
{
pENET->MODULE_CONTROL.INTCLEAR = mask;
}
/**
* @brief Initialize ethernet interface
* @param pENET : The base of ENET peripheral on the chip
* @param useRMII : true to setup interface for RMII, false for MII
* @return Nothing
* @note Performs basic initialization of the ethernet interface in a default
* state. This is enough to place the interface in a usable state, but
* may require more setup outside this function.
*/
void Chip_ENET_Init(LPC_ENET_T *pENET, bool useRMII);
/**
* @brief De-initialize the ethernet interface
* @param pENET : The base of ENET peripheral on the chip
* @return Nothing
*/
void Chip_ENET_DeInit(LPC_ENET_T *pENET);
/**
* @brief Find the divider index for a desired MII clock rate
* @param pENET : The base of ENET peripheral on the chip
* @param clockRate : Clock rate to get divider index for
* @return MII divider index to get the closest clock rate for clockRate
* @note Use this function to get a divider index for the Chip_ENET_SetupMII()
* function determined from the desired MII clock rate.
*/
uint32_t Chip_ENET_FindMIIDiv(LPC_ENET_T *pENET, uint32_t clockRate);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ENET_17XX_40XX_H_ */

184
hw/mcu/nxp/lpc_chip_175x_6x/inc/error.h Normal file
View File

@ -0,0 +1,184 @@
/*
* @brief Error code returned by Boot ROM drivers/library functions
* @ingroup Common
*
* This file contains unified error codes to be used across driver,
* middleware, applications, hal and demo software.
*
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_ERROR_H__
#define __LPC_ERROR_H__
/** Error code returned by Boot ROM drivers/library functions
*
* Error codes are a 32-bit value with :
* - The 16 MSB contains the peripheral code number
* - The 16 LSB contains an error code number associated to that peripheral
*
*/
typedef enum {
/**\b 0x00000000*/ LPC_OK = 0, /**< enum value returned on Success */
/**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */
/**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */
/**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */
/* ISP related errors */
ERR_ISP_BASE = 0x00000000,
/*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
/*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */
/*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */
/*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
/*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
/*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */
/*0x00000007*/ ERR_ISP_INVALID_SECTOR,
/*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
/*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
/*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
/*0x0000000B*/ ERR_ISP_BUSY,/* Flash programming hardware interface is busy */
/*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */
/*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */
/*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
/*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */
/*0x00000010*/ ERR_ISP_INVALID_CODE,/* Unlock code is invalid */
/*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
/*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
/*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
/* ROM API related errors */
ERR_API_BASE = 0x00010000,
/**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/
/**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */
/**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */
/**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */
/**\b 0x00010005*/ ERR_API_MOD_INIT,/**< API is called before module init */
/* SPIFI API related errors */
ERR_SPIFI_BASE = 0x00020000,
/*0x00020001*/ ERR_SPIFI_DEVICE_ERROR = ERR_SPIFI_BASE + 1,
/*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
/*0x00020003*/ ERR_SPIFI_TIMEOUT,
/*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
/*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
/*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
/*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
/*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
/*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
/* Security API related errors */
ERR_SEC_BASE = 0x00030000,
/*0x00030001*/ ERR_SEC_AES_WRONG_CMD = ERR_SEC_BASE + 1,
/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
/* USB device stack related errors */
ERR_USBD_BASE = 0x00040000,
/**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1,/**< invalid request */
/**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */
/**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */
/**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */
/**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */
/**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/
/**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC, /**< Bad config descriptor*/
/**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC, /**< Bad interface descriptor*/
/**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
/**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF,/**< Bad alignment of buffer passed. */
/**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR,/**< Too many class handlers. */
/* CGU related errors */
ERR_CGU_BASE = 0x00050000,
/*0x00050001*/ ERR_CGU_NOT_IMPL = ERR_CGU_BASE + 1,
/*0x00050002*/ ERR_CGU_INVALID_PARAM,
/*0x00050003*/ ERR_CGU_INVALID_SLICE,
/*0x00050004*/ ERR_CGU_OUTPUT_GEN,
/*0x00050005*/ ERR_CGU_DIV_SRC,
/*0x00050006*/ ERR_CGU_DIV_VAL,
/*0x00050007*/ ERR_CGU_SRC,
/* I2C related errors */
ERR_I2C_BASE = 0x00060000,
/*0x00060001*/ ERR_I2C_NAK = ERR_I2C_BASE + 1,
/*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW,
/*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR,
/*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION,
/*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED,
/*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT,
/*0x00060007*/ ERR_I2C_GENERAL_FAILURE,
/*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT,
/*0x00060009*/ ERR_I2C_TIMEOUT,
/*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW,
/* UART related errors */
ERR_UART_BASE = 0x00080000,
/**\b 0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE + 1, /*!< Receive is busy */
/**\b 0x00080002*/ ERR_UART_TXD_BUSY, /*!< Transmit is busy */
/**\b 0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, /*!< Overrun, Frame, Parity , Receive Noise error */
/**\b 0x00080004*/ ERR_UART_UNDERRUN, /*!< Underrun */
/**\b 0x00080005*/ ERR_UART_PARAM, /*!< Parameter error */
ERR_DMA_BASE = 0x000D0000,
/*0x000D0001*/ ERR_DMA_ERROR_INT = ERR_DMA_BASE + 1,
/*0x000D0002*/ ERR_DMA_CHANNEL_NUMBER,
/*0x000D0003*/ ERR_DMA_CHANNEL_DISABLED,
/*0x000D0004*/ ERR_DMA_BUSY,
/*0x000D0005*/ ERR_DMA_NOT_ALIGNMENT,
/*0x000D0006*/ ERR_DMA_PING_PONG_EN,
/*0x000D0007*/ ERR_DMA_CHANNEL_VALID_PENDING,
/* SPI related errors */
ERR_SPI_BASE = 0x000E0000,
/*0x000E0001*/ ERR_SPI_RXOVERRUN=ERR_SPI_BASE+1,
/*0x000E0002*/ ERR_SPI_TXUNDERRUN,
/*0x000E0003*/ ERR_SPI_SELNASSERT,
/*0x000E0004*/ ERR_SPI_SELNDEASSERT,
/*0x000E0005*/ ERR_SPI_CLKSTALL,
/*0x000E0006*/ ERR_SPI_PARAM,
/*0x000E0007*/ ERR_SPI_INVALID_LENGTH,
/* ADC related errors */
ERR_ADC_BASE = 0x000F0000,
/*0x000F0001*/ ERR_ADC_OVERRUN = ERR_ADC_BASE + 1,
/*0x000F0002*/ ERR_ADC_INVALID_CHANNEL,
/*0x000F0003*/ ERR_ADC_INVALID_SEQUENCE,
/*0x000F0004*/ ERR_ADC_INVALID_SETUP,
/*0x000F0005*/ ERR_ADC_PARAM,
/*0x000F0006*/ ERR_ADC_INVALID_LENGTH,
/*0x000F0007*/ ERR_ADC_NO_POWER
} ErrorCode_t;
#ifndef offsetof
#define offsetof(s, m) (int) &(((s *) 0)->m)
#endif
#define COMPILE_TIME_ASSERT(pred) switch (0) { \
case 0: \
case pred:; }
#endif /* __LPC_ERROR_H__ */

133
hw/mcu/nxp/lpc_chip_175x_6x/inc/fmc_17xx_40xx.h Normal file
View File

@ -0,0 +1,133 @@
/*
* @brief LPC17xx/40xx FLASH Memory Controller (FMC) driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __FMC_17XX_40XX_H_
#define __FMC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup FMC_17XX_40XX CHIP: LPC17xx/40xx FLASH Memory Controller driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief FLASH Memory Controller Unit register block structure
*/
typedef struct { /*!< FMC Structure */
__I uint32_t RESERVED1[8];
__IO uint32_t FMSSTART;
__IO uint32_t FMSSTOP;
__I uint32_t RESERVED3;
__I uint32_t FMSW[4];
__I uint32_t RESERVED4[1001];
__I uint32_t FMSTAT;
__I uint32_t RESERVED5;
__O uint32_t FMSTATCLR;
} LPC_FMC_T;
/* Flash signature start and busy status bit */
#define FMC_FLASHSIG_BUSY (1UL << 17)
/* Flash signature clear status bit */
#define FMC_FLASHSIG_STAT (1 << 2)
/**
* @brief Start computation of a signature for a FLASH memory range
* @param start : Starting FLASH address for computation, must be aligned on 16 byte boundary
* @param stop : Ending FLASH address for computation, must be aligned on 16 byte boundary
* @return Nothing
* @note Only bits 20..4 are used for the FLASH signature computation.
* Use the Chip_FMC_IsSignatureBusy() function to determine when the
* signature computation operation is complete and use the
* Chip_FMC_GetSignature() function to get the computed signature.
*/
STATIC INLINE void Chip_FMC_ComputeSignature(uint32_t start, uint32_t stop)
{
LPC_FMC->FMSSTART = (start >> 4);
LPC_FMC->FMSTATCLR = FMC_FLASHSIG_STAT;
LPC_FMC->FMSSTOP = (stop >> 4) | FMC_FLASHSIG_BUSY;
}
/**
* @brief Start computation of a signature for a FLASH memory address and block count
* @param start : Starting FLASH address for computation, must be aligned on 16 byte boundary
* @param blocks : Number of 16 byte blocks used for computation
* @return Nothing
* @note Only bits 20..4 are used for the FLASH signature computation.
* Use the Chip_FMC_IsSignatureBusy() function to determine when the
* signature computation operation is complete and the
* Chip_FMC_GetSignature() function to get the computed signature.
*/
STATIC INLINE void Chip_FMC_ComputeSignatureBlocks(uint32_t start, uint32_t blocks)
{
Chip_FMC_ComputeSignature(start, (start + (blocks * 16)));
}
/**
* @brief Clear signature generation completion flag
* @return Nothing
*/
STATIC INLINE void Chip_FMC_ClearSignatureBusy(void)
{
LPC_FMC->FMSTATCLR = FMC_FLASHSIG_STAT;
}
/**
* @brief Check for signature generation completion
* @return true if the signature computation is running, false if finished
*/
STATIC INLINE bool Chip_FMC_IsSignatureBusy(void)
{
return (bool) ((LPC_FMC->FMSTAT & FMC_FLASHSIG_STAT) == 0);
}
/**
* @brief Returns the generated FLASH signature value
* @param index : Signature index to get - use 0 to FMSW0, 1 to FMSW1, etc.
* @return the generated FLASH signature value
*/
STATIC INLINE uint32_t Chip_FMC_GetSignature(int index)
{
return LPC_FMC->FMSW[index];
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __FMC_17XX_40XX_H_ */

450
hw/mcu/nxp/lpc_chip_175x_6x/inc/gpdma_17xx_40xx.h Normal file
View File

@ -0,0 +1,450 @@
/*
* @brief LPC17xx/40xx General Purpose DMA driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPDMA_17XX_40XX_H_
#define __GPDMA_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPDMA_17XX_40XX CHIP: LPC17xx/40xx General Purpose DMA driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief Number of channels on GPDMA
*/
#define GPDMA_NUMBER_CHANNELS 8
/**
* @brief GPDMA Channel register block structure
*/
typedef struct {
__IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */
__IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */
__IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */
__IO uint32_t CONTROL; /*!< DMA Channel Control Register */
__IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */
__I uint32_t RESERVED1[3];
} GPDMA_CH_T;
/**
* @brief GPDMA register block
*/
typedef struct { /*!< GPDMA Structure */
__I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */
__I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */
__O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */
__I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */
__O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */
__I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */
__I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */
__I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */
__IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */
__IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */
__IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */
__IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */
__IO uint32_t CONFIG; /*!< DMA Configuration Register */
__IO uint32_t SYNC; /*!< DMA Synchronization Register */
__I uint32_t RESERVED0[50];
GPDMA_CH_T CH[GPDMA_NUMBER_CHANNELS];
} LPC_GPDMA_T;
/**
* @brief Macro defines for DMA channel control registers
*/
#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /*!< Transfer size*/
#define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /*!< Source burst size*/
#define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /*!< Destination burst size*/
#define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /*!< Source transfer width*/
#define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /*!< Destination transfer width*/
#define GPDMA_DMACCxControl_SI ((1UL << 26)) /*!< Source increment*/
#define GPDMA_DMACCxControl_DI ((1UL << 27)) /*!< Destination increment*/
#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0
#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0
#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /*!< Indicates that the access is in user mode or privileged mode*/
#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /*!< Indicates that the access is bufferable or not bufferable*/
#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /*!< Indicates that the access is cacheable or not cacheable*/
#define GPDMA_DMACCxControl_I ((1UL << 31)) /*!< Terminal count interrupt enable bit */
/**
* @brief Macro defines for DMA Configuration register
*/
#define GPDMA_DMACConfig_E ((0x01)) /*!< DMA Controller enable*/
#define GPDMA_DMACConfig_M ((0x02)) /*!< AHB Master endianness configuration*/
#define GPDMA_DMACConfig_BITMASK ((0x03))
/**
* @brief Macro defines for DMA Channel Configuration registers
*/
#define GPDMA_DMACCxConfig_E ((1UL << 0)) /*!< DMA control enable*/
#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /*!< Source peripheral*/
#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /*!< Destination peripheral*/
#define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /*!< This value indicates the type of transfer*/
#define GPDMA_DMACCxConfig_IE ((1UL << 14)) /*!< Interrupt error mask*/
#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /*!< Terminal count interrupt mask*/
#define GPDMA_DMACCxConfig_L ((1UL << 16)) /*!< Lock*/
#define GPDMA_DMACCxConfig_A ((1UL << 17)) /*!< Active*/
#define GPDMA_DMACCxConfig_H ((1UL << 18)) /*!< Halt*/
/**
* @brief GPDMA Interrupt Clear Status
*/
typedef enum {
GPDMA_STATCLR_INTTC, /*!< GPDMA Interrupt Terminal Count Request Clear */
GPDMA_STATCLR_INTERR /*!< GPDMA Interrupt Error Clear */
} GPDMA_STATECLEAR_T;
/**
* @brief GPDMA Type of Interrupt Status
*/
typedef enum {
GPDMA_STAT_INT, /*!< GPDMA Interrupt Status */
GPDMA_STAT_INTTC, /*!< GPDMA Interrupt Terminal Count Request Status */
GPDMA_STAT_INTERR, /*!< GPDMA Interrupt Error Status */
GPDMA_STAT_RAWINTTC, /*!< GPDMA Raw Interrupt Terminal Count Status */
GPDMA_STAT_RAWINTERR, /*!< GPDMA Raw Error Interrupt Status */
GPDMA_STAT_ENABLED_CH /*!< GPDMA Enabled Channel Status */
} GPDMA_STATUS_T;
/**
* @brief GPDMA Type of DMA controller
*/
typedef enum {
GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), /*!< Memory to memory - DMA control */
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), /*!< Memory to peripheral - DMA control */
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), /*!< Peripheral to memory - DMA control */
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), /*!< Source peripheral to destination peripheral - DMA control */
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), /*!< Source peripheral to destination peripheral - destination peripheral control */
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), /*!< Memory to peripheral - peripheral control */
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), /*!< Peripheral to memory - peripheral control */
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) /*!< Source peripheral to destination peripheral - source peripheral control */
} GPDMA_FLOW_CONTROL_T;
/**
* @brief GPDMA structure using for DMA configuration
*/
typedef struct {
uint32_t ChannelNum; /*!< DMA channel number, should be in
* range from 0 to 7.
* Note: DMA channel 0 has the highest priority
* and DMA channel 7 the lowest priority.
*/
uint32_t TransferSize; /*!< Length/Size of transfer */
uint32_t TransferWidth; /*!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
uint32_t SrcAddr; /*!< Physical Source Address, used in case TransferType is chosen as
* GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
uint32_t DstAddr; /*!< Physical Destination Address, used in case TransferType is chosen as
* GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
uint32_t TransferType; /*!< Transfer Type, should be one of the following:
* - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
* - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
* - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
* - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
*/
} GPDMA_CH_CFG_T;
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief GPDMA request connections
*/
#define GPDMA_CONN_MEMORY ((0UL)) /*!< Memory */
#define GPDMA_CONN_SDC ((1UL)) /*!< SD card */
#define GPDMA_CONN_SSP0_Tx ((2UL)) /*!< SSP0 Tx */
#define GPDMA_CONN_SSP0_Rx ((3UL)) /*!< SSP0 Rx */
#define GPDMA_CONN_SSP1_Tx ((4UL)) /*!< SSP1 Tx */
#define GPDMA_CONN_SSP1_Rx ((5UL)) /*!< SSP1 Rx */
#define GPDMA_CONN_SSP2_Tx ((6UL)) /*!< SSP2 Tx */
#define GPDMA_CONN_SSP2_Rx ((7UL)) /*!< SSP2 Rx */
#define GPDMA_CONN_ADC ((8UL)) /*!< ADC */
#define GPDMA_CONN_DAC ((9UL)) /*!< DAC */
#define GPDMA_CONN_UART0_Tx ((10UL)) /*!< UART0 Tx */
#define GPDMA_CONN_UART0_Rx ((11UL)) /*!< UART0 Rx */
#define GPDMA_CONN_UART1_Tx ((12UL)) /*!< UART1 Tx */
#define GPDMA_CONN_UART1_Rx ((13UL)) /*!< UART1 Rx */
#define GPDMA_CONN_UART2_Tx ((14UL)) /*!< UART2 Tx */
#define GPDMA_CONN_UART2_Rx ((15UL)) /*!< UART2 Rx */
#define GPDMA_CONN_MAT0_0 ((16UL)) /*!< MAT0.0 */
#define GPDMA_CONN_MAT0_1 ((17UL)) /*!< MAT0.1 */
#define GPDMA_CONN_MAT1_0 ((18UL)) /*!< MAT1.0 */
#define GPDMA_CONN_MAT1_1 ((19UL)) /*!< MAT1.1 */
#define GPDMA_CONN_MAT2_0 ((20UL)) /*!< MAT2.0 */
#define GPDMA_CONN_MAT2_1 ((21UL)) /*!< MAT2.1 */
#define GPDMA_CONN_I2S_Channel_0 ((22UL)) /*!< I2S channel 0 */
#define GPDMA_CONN_I2S_Channel_1 ((23UL)) /*!< I2S channel 1 */
#define GPDMA_CONN_UART3_Tx ((26UL)) /*!< UART3 Tx */
#define GPDMA_CONN_UART3_Rx ((27UL)) /*!< UART3 Rx */
#define GPDMA_CONN_UART4_Tx ((28UL)) /*!< UART3 Tx */
#define GPDMA_CONN_UART4_Rx ((29UL)) /*!< UART3 Rx */
#define GPDMA_CONN_MAT3_0 ((30UL)) /*!< MAT3.0 */
#define GPDMA_CONN_MAT3_1 ((31UL)) /*!< MAT3.1 */
#elif defined(CHIP_LPC175X_6X)
/**
* @brief GPDMA request connections
*/
#define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
#define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
#define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
#define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
#define GPDMA_CONN_ADC ((4UL)) /**< ADC */
#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
#define GPDMA_CONN_DAC ((7UL)) /**< DAC */
#define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
#define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
#define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
#define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
#define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
#define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
#define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
#define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
#define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
#define GPDMA_CONN_MEMORY ((24UL))
#endif
/**
* @brief GPDMA Burst size in Source and Destination definitions
*/
#define GPDMA_BSIZE_1 ((0UL)) /*!< Burst size = 1 */
#define GPDMA_BSIZE_4 ((1UL)) /*!< Burst size = 4 */
#define GPDMA_BSIZE_8 ((2UL)) /*!< Burst size = 8 */
#define GPDMA_BSIZE_16 ((3UL)) /*!< Burst size = 16 */
#define GPDMA_BSIZE_32 ((4UL)) /*!< Burst size = 32 */
#define GPDMA_BSIZE_64 ((5UL)) /*!< Burst size = 64 */
#define GPDMA_BSIZE_128 ((6UL)) /*!< Burst size = 128 */
#define GPDMA_BSIZE_256 ((7UL)) /*!< Burst size = 256 */
/**
* @brief Width in Source transfer width and Destination transfer width definitions
*/
#define GPDMA_WIDTH_BYTE ((0UL)) /*!< Width = 1 byte */
#define GPDMA_WIDTH_HALFWORD ((1UL)) /*!< Width = 2 bytes */
#define GPDMA_WIDTH_WORD ((2UL)) /*!< Width = 4 bytes */
/**
* @brief Flow control definitions
*/
#define DMA_CONTROLLER 0 /*!< Flow control is DMA controller*/
#define SRC_PER_CONTROLLER 1 /*!< Flow control is Source peripheral controller*/
#define DST_PER_CONTROLLER 2 /*!< Flow control is Destination peripheral controller*/
/**
* @brief DMA channel handle structure
*/
typedef struct {
FunctionalState ChannelStatus; /*!< DMA channel status */
} DMA_ChannelHandle_t;
/**
* @brief Transfer Descriptor structure typedef
*/
typedef struct DMA_TransferDescriptor {
uint32_t src; /*!< Source address */
uint32_t dst; /*!< Destination address */
uint32_t lli; /*!< Pointer to next descriptor structure */
uint32_t ctrl; /*!< Control word that has transfer size, type etc. */
} DMA_TransferDescriptor_t;
/**
* @brief Initialize the GPDMA
* @param pGPDMA : The base of GPDMA on the chip
* @return Nothing
*/
void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);
/**
* @brief Shutdown the GPDMA
* @param pGPDMA : The base of GPDMA on the chip
* @return Nothing
*/
void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);
/**
* @brief Initialize channel configuration strucutre
* @param pGPDMA : The base of GPDMA on the chip
* @param GPDMACfg : Pointer to configuration structure to be initialized
* @param ChannelNum : Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()*
* @param src : Address of Memory or one of GPDMA_CONN_MEMORY
* PeripheralConnection_ID , which is the source
* @param dst : Address of Memory or one of GPDMA_CONN_MEMORY
* PeripheralConnection_ID, which is the destination
* @param Size : The number of DMA transfers
* @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
* @return ERROR on error, SUCCESS on success
*/
int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
GPDMA_CH_CFG_T *GPDMACfg,
uint8_t ChannelNum,
uint32_t src,
uint32_t dst,
uint32_t Size,
GPDMA_FLOW_CONTROL_T TransferType);
/**
* @brief Enable or Disable the GPDMA Channel
* @param pGPDMA : The base of GPDMA on the chip
* @param channelNum : The GPDMA channel : 0 - 7
* @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA
* @return Nothing
*/
void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState);
/**
* @brief Stop a stream DMA transfer
* @param pGPDMA : The base of GPDMA on the chip
* @param ChannelNum : Channel Number to be closed
* @return Nothing
*/
void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
/**
* @brief The GPDMA stream interrupt status checking
* @param pGPDMA : The base of GPDMA on the chip
* @param ChannelNum : Channel Number to be checked on interruption
* @return Status:
* - SUCCESS : DMA transfer success
* - ERROR : DMA transfer failed
*/
Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
/**
* @brief Read the status from different registers according to the type
* @param pGPDMA : The base of GPDMA on the chip
* @param type : Status mode, should be:
* - GPDMA_STAT_INT : GPDMA Interrupt Status
* - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status
* - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status
* - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status
* - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status
* - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
* @param channel : The GPDMA channel : 0 - 7
* @return SET is interrupt is pending or RESET if not pending
*/
IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel);
/**
* @brief Clear the Interrupt Flag from different registers according to the type
* @param pGPDMA : The base of GPDMA on the chip
* @param type : Flag mode, should be:
* - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request
* - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
* @param channel : The GPDMA channel : 0 - 7
* @return Nothing
*/
void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel);
/**
* @brief Get a free GPDMA channel for one DMA connection
* @param pGPDMA : The base of GPDMA on the chip
* @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 17xx/40xx )
* @return The channel number which is selected
*/
uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA,
uint32_t PeripheralConnection_ID);
/**
* @brief Do a DMA transfer M2M, M2P,P2M or P2P
* @param pGPDMA : The base of GPDMA on the chip
* @param ChannelNum : Channel used for transfer
* @param src : Address of Memory or PeripheralConnection_ID which is the source
* @param dst : Address of Memory or PeripheralConnection_ID which is the destination
* @param TransferType: Select the transfer controller and the type of transfer. Should be:
* - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
* - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
* - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
* - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
* - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
* - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
* - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
* - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
* @param Size : The number of DMA transfers
* @return ERROR on error, SUCCESS on success
*/
Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum,
uint32_t src,
uint32_t dst,
GPDMA_FLOW_CONTROL_T TransferType,
uint32_t Size);
/**
* @brief Do a DMA transfer using linked list of descriptors
* @param pGPDMA : The base of GPDMA on the chip
* @param ChannelNum : Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()*
* @param DMADescriptor : First node in the linked list of descriptors
* @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
* @return ERROR on error, SUCCESS on success
*/
Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum,
const DMA_TransferDescriptor_t *DMADescriptor,
GPDMA_FLOW_CONTROL_T TransferType);
/**
* @brief Prepare a single DMA descriptor
* @param pGPDMA : The base of GPDMA on the chip
* @param DMADescriptor : DMA Descriptor to be initialized
* @param src : Address of Memory or one of GPDMA_CONN_MEMORY
* PeripheralConnection_ID, which is the source
* @param dst : Address of Memory or one of GPDMA_CONN_MEMORY
* PeripheralConnection_ID, which is the destination
* @param Size : The number of DMA transfers
* @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
* @param NextDescriptor : Pointer to next descriptor (0 if no more descriptors available)
* @return ERROR on error, SUCCESS on success
*/
Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
DMA_TransferDescriptor_t *DMADescriptor,
uint32_t src,
uint32_t dst,
uint32_t Size,
GPDMA_FLOW_CONTROL_T TransferType,
const DMA_TransferDescriptor_t *NextDescriptor);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPDMA_17XX_40XX_H_ */

491
hw/mcu/nxp/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h Normal file
View File

@ -0,0 +1,491 @@
/*
* @brief LPC17xx/40xx GPIO driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIO_17XX_40XX_H_
#define __GPIO_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIO_17XX_40XX CHIP: LPC17xx/40xx GPIO driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#define GPIO_PORT_BITS 32
/**
* @brief GPIO port (GPIO_PORT) for LPC175x_6x, LPC177x_8x and LPC407x_8x
*/
typedef struct { /* GPIO_PORT Structure */
__IO uint32_t DIR; /*!< Offset 0x0000: GPIO Port Direction control register */
uint32_t RESERVED0[3];
__IO uint32_t MASK; /*!< Offset 0x0010: GPIO Mask register */
__IO uint32_t PIN; /*!< Offset 0x0014: Pin value register using FIOMASK */
__IO uint32_t SET; /*!< Offset 0x0018: Output Set register using FIOMASK */
__O uint32_t CLR; /*!< Offset 0x001C: Output Clear register using FIOMASK */
} LPC_GPIO_T;
/**
* @brief Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/**
* @brief De-Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/**
* @brief Set a GPIO pin state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
* @note This function replaces Chip_GPIO_WritePortBit()
*/
STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
{
if (setting) { /* Set Port */
pGPIO[port].SET |= 1UL << pin;
}
else { /* Clear Port */
pGPIO[port].CLR |= 1UL << pin;
}
}
/**
* @brief Set a GPIO port/bit state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
{
Chip_GPIO_SetPinState(pGPIO, port, pin, setting);
}
/**
* @brief Get a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pin : GPIO pin to get state for
* @return true if the GPIO is high, false if low
* @note This function replaces Chip_GPIO_ReadPortBit()
*/
STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) ((pGPIO[port].PIN >> pin) & 1);
}
/**
* @brief Read a GPIO state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param pin : GPIO pin to read
* @return true of the GPIO is high, false if low
* @note It is recommended to use the Chip_GPIO_GetPinState() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin)
{
return Chip_GPIO_GetPinState(pGPIO, port, pin);
}
/**
* @brief Set GPIO direction for a single GPIO pin to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where a pin is located
* @param pin : GPIO pin to set direction on as output
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DIR |= 1UL << pin;
}
/**
* @brief Set GPIO direction for a single GPIO pin to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pin : GPIO pin to set direction on as input
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DIR &= ~(1UL << pin);
}
/**
* @brief Set GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pin : GPIO pin to set direction for
* @param output : true for output, false for input
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
{
if (output) {
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
}
else {
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
}
}
/**
* @brief Set a GPIO direction
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param bit : GPIO bit to set
* @param setting : true for output, false for input
* @return Nothing
* @note It is recommended to use the Chip_GPIO_SetPinDIROutput(),
* Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
* of this function.
*/
STATIC INLINE void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t bit, bool setting)
{
Chip_GPIO_SetPinDIR(pGPIO, port, bit, setting);
}
/**
* @brief Get GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pin : GPIO pin to get direction for
* @return true if the GPIO is an output, false if input
*/
STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) (((pGPIO[port].DIR) >> pin) & 1);
}
/**
* @brief Read a GPIO direction (out or in)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param bit : GPIO bit to read
* @return true of the GPIO is an output, false if input
* @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
{
return Chip_GPIO_GetPinDIR(pGPIO, port, bit);
}
/**
* @brief Set Direction for a GPIO port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port Number
* @param bitValue : GPIO bit to set
* @param out : Direction value, 0 = input, !0 = output
* @return None
* @note Bits set to '0' are not altered. It is recommended to use the
* Chip_GPIO_SetPortDIR() function instead.
*/
STATIC INLINE void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
{
Chip_GPIO_SetPinDIR(pGPIO, portNum, bitValue, out);
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the output direction, each bit's position that is
* high sets the corresponding pin number for that bit to an output.
*/
STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
{
pGPIO[port].DIR |= pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
{
pGPIO[port].DIR &= ~pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input or output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n)
* @param outSet : Direction value, false = set as inputs, true = set as outputs
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
STATIC INLINE void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
/**
* @brief Get GPIO direction for a all GPIO pins
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @return a bitfield containing the input and output states for each pin
* @note For pins 0..n, a high state in a bit corresponds to an output state for the
* same pin, while a low state corresponds to an input state.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].DIR;
}
/**
* @brief Set GPIO port mask value for GPIO masked read and write
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : port Number
* @param mask : Mask value for read and write (only low bits are enabled)
* @return Nothing
* @note Controls which bits are set or unset when using the masked
* GPIO read and write functions. A low state indicates the pin is settable
* and readable via the masked write and read functions.
*/
STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask)
{
pGPIO[port].MASK = mask;
}
/**
* @brief Get GPIO port mask value used for GPIO masked read and write
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : port Number
* @return Returns value set with the Chip_GPIO_SetPortMask() function.
* @note A high bit in the return value indicates that that GPIO pin for the
* port cannot be set using the masked write function.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].MASK;
}
/**
* @brief Set all GPIO pin states, but mask via the MASK register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
pGPIO[port].PIN = value;
}
/**
* @brief Get all GPIO pin states but mask via the MASK register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @return Current (masked) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].PIN;
}
/**
* @brief Set all GPIO raw pin states (does not bypass masking on this chip!)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
Chip_GPIO_SetMaskedPortValue(pGPIO, port, value);
}
/**
* @brief Get all GPIO raw pin states (does not bypass masking on this chip!)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @return Current (raw) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return Chip_GPIO_GetMaskedPortValue(pGPIO, port);
}
/**
* @brief Set selected GPIO output pins to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pins : pins (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO[port].SET = pins;
}
/**
* @brief Set a GPIO port/bit to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number
* @param bitValue : bit(s) in the port to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output. It is recommended to use the
* Chip_GPIO_SetPortOutHigh() function instead.
*/
STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
{
Chip_GPIO_SetPortOutHigh(pGPIO,portNum,bitValue);
}
/**
* @brief Set an individual GPIO output pin to the high state
* @param pGPIO : The base of GPIO peripheral on the chip'
* @param port : GPIO Port number where pin is located
* @param pin : pin number (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].SET = (1 << pin);
}
/**
* @brief Set selected GPIO output pins to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pins : pins (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO[port].CLR = pins;
}
/**
* @brief Set a GPIO port/bit to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number
* @param bitValue : bit(s) in the port to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
{
Chip_GPIO_SetPortOutLow(pGPIO, portNum, bitValue);
}
/**
* @brief Set an individual GPIO output pin to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where pin is located
* @param pin : pin number (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].CLR = (1 << pin);
}
/**
* @brief Toggle an individual GPIO output pin to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
bool setting = !Chip_GPIO_GetPinState(pGPIO, port, pin);
Chip_GPIO_SetPinState(pGPIO, port, pin, setting);
}
/**
* @brief Read current bit states for the selected port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number to read
* @return Current value of GPIO port
* @note The current states of the bits for the port are read, regardless of
* whether the GPIO port bits are input or output.
*/
STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
{
return pGPIO[portNum].PIN;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_17XX_40XX_H_ */

227
hw/mcu/nxp/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h Normal file
View File

@ -0,0 +1,227 @@
/*
* @brief LPC17xx/40xx GPIO driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIOINT_17XX_40XX_H_
#define __GPIOINT_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIOINT_17XX_40XX CHIP: LPC17xx/40xx GPIO Interrupt driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief GPIO Interupt registers for Portn
*/
typedef struct {
__I uint32_t STATR; /*!< GPIO Interrupt Status Register for Rising edge */
__I uint32_t STATF; /*!< GPIO Interrupt Status Register for Falling edge */
__O uint32_t CLR; /*!< GPIO Interrupt Clear Register */
__IO uint32_t ENR; /*!< GPIO Interrupt Enable Register 0 for Rising edge */
__IO uint32_t ENF; /*!< GPIO Interrupt Enable Register 0 for Falling edge */
} GPIOINT_PORT_T;
/**
* @brief GPIO Interrupt register block structure
*/
typedef struct {
__I uint32_t STATUS; /*!< GPIO overall Interrupt Status Register */
GPIOINT_PORT_T IO0; /*!< GPIO Interrupt Registers for Port 0 */
uint32_t RESERVED0[3];
GPIOINT_PORT_T IO2; /*!< GPIO Interrupt Registers for Port 2 */
} LPC_GPIOINT_T;
/**
* @brief GPIO interrupt capable ports
*/
typedef enum {
GPIOINT_PORT0, /*!< GPIO PORT 0 */
GPIOINT_PORT2 = 2 /*!< GPIO PORT 2 */
}LPC_GPIOINT_PORT_T;
/**
* @brief Initialize GPIO interrupt block
* @param pGPIOINT : The base address of GPIO interrupt block
* @return Nothing
* @note This function enables the clock to IOCON, GPIO and GPIOINT
* peripheral blocks.
*/
STATIC INLINE void Chip_GPIOINT_Init(LPC_GPIOINT_T *pGPIOINT)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/**
* @brief De-Initialize GPIO Interrupt block
* @param pGPIOINT : The base of GPIO interrupt peripheral on the chip
* @return Nothing
* @note This function disables the clock to IOCON, GPIO and GPIOINT
* peripheral blocks This function should not be called
* if IOCON or GPIO needs to be used after calling this function.
*/
STATIC INLINE void Chip_GPIOINT_DeInit(LPC_GPIOINT_T *pGPIOINT)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/**
* @brief Enable interrupts on falling edge of given @a pins
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @param pins : Pins set to 1 will have falling edge interrupt enabled,
* Pins set to 0 will have falling edge interrupt disabled
* @return Nothing
*/
STATIC INLINE void Chip_GPIOINT_SetIntFalling(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port, uint32_t pins)
{
if (port == GPIOINT_PORT0) {
pGPIOINT->IO0.ENF = pins;
} else {
pGPIOINT->IO2.ENF = pins;
}
}
/**
* @brief Enable interrupts on rising edge of given @a pins
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @param pins : Pins set to 1 will have rising edge interrupt enabled,
* Pins set to 0 will have rising edge interrupt disabled
* @return Nothing
*/
STATIC INLINE void Chip_GPIOINT_SetIntRising(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port, uint32_t pins)
{
if (port == GPIOINT_PORT0) {
pGPIOINT->IO0.ENR = pins;
} else {
pGPIOINT->IO2.ENR = pins;
}
}
/**
* @brief Get the pins that has falling edge interrupt enabled
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @return Pins that are configured for Falling edge interrupt enabled
*/
STATIC INLINE uint32_t Chip_GPIOINT_GetIntFalling(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
{
if (port == GPIOINT_PORT0) {
return pGPIOINT->IO0.ENF;
} else {
return pGPIOINT->IO2.ENF;
}
}
/**
* @brief Get pins that has rising edge interrupt enabled
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @return Pins that are configured for rising edge interrupt enabled
*/
STATIC INLINE uint32_t Chip_GPIOINT_GetIntRising(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
{
if (port == GPIOINT_PORT0) {
return pGPIOINT->IO0.ENR;
} else {
return pGPIOINT->IO2.ENR;
}
}
/**
* @brief Get status of the pins for falling edge
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @return Pins that has detected falling edge
*/
STATIC INLINE uint32_t Chip_GPIOINT_GetStatusFalling(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
{
if (port == GPIOINT_PORT0) {
return pGPIOINT->IO0.STATF;
} else {
return pGPIOINT->IO2.STATF;
}
}
/**
* @brief Get status of the pins for rising edge
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @return Pins that has detected rising edge
*/
STATIC INLINE uint32_t Chip_GPIOINT_GetStatusRising(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
{
if (port == GPIOINT_PORT0) {
return pGPIOINT->IO0.STATR;
} else {
return pGPIOINT->IO2.STATR;
}
}
/**
* @brief Clear the falling and rising edge interrupt for given @a pins
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @param pins : Pins to clear the interrupts for
* @return Nothing
*/
STATIC INLINE void Chip_GPIOINT_ClearIntStatus(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port, uint32_t pins)
{
if (port == GPIOINT_PORT0) {
pGPIOINT->IO0.CLR = pins;
} else {
pGPIOINT->IO2.CLR = pins;
}
}
/**
* @brief Checks if an interrupt is pending on a given port
* @param pGPIOINT : The base address of GPIO interrupt block
* @param port : GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
* @return true if any pin in given port has a pending interrupt
*/
STATIC INLINE bool Chip_GPIOINT_IsIntPending(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
{
return ((pGPIOINT->STATUS & (1 << (int)port)) != 0);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIOINT_17XX_40XX_H_ */

541
hw/mcu/nxp/lpc_chip_175x_6x/inc/i2c_17xx_40xx.h Normal file
View File

@ -0,0 +1,541 @@
/*
* @brief LPC17xx/40xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2C_17XX_40XX_H_
#define __I2C_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup I2C_17XX_40XX CHIP: LPC17xx/40xx I2C driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief I2C register block structure
*/
typedef struct { /* I2C0 Structure */
__IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< Monitor mode control register. */
__IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
__IO uint32_t MASK[4]; /*!< I2C Slave address mask register */
} LPC_I2C_T;
/**
* @brief Return values for SLAVE handler
* @note
* Chip drivers will usally be designed to match their events with this value
*/
#define RET_SLAVE_TX 6 /**< Return value, when 1 byte TX'd successfully */
#define RET_SLAVE_RX 5 /**< Return value, when 1 byte RX'd successfully */
#define RET_SLAVE_IDLE 2 /**< Return value, when slave enter idle mode */
#define RET_SLAVE_BUSY 0 /**< Return value, when slave is busy */
/**
* @brief I2C state handle return values
*/
#define I2C_STA_STO_RECV 0x20
/*
* @brief I2C Control Set register description
*/
#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20))/*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */
/*
* @brief I2C Control Clear register description
*/
#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */
#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */
#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */
#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */
#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */
/*
* @brief I2C Common Control register description
*/
#define I2C_CON_AA (1UL << 2) /*!< Assert acknowledge bit */
#define I2C_CON_SI (1UL << 3) /*!< I2C interrupt bit */
#define I2C_CON_STO (1UL << 4) /*!< I2C STOP bit */
#define I2C_CON_STA (1UL << 5) /*!< START flag bit */
#define I2C_CON_I2EN (1UL << 6) /*!< I2C interface bit */
/*
* @brief I2C Status Code definition (I2C Status register)
*/
#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */
#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */
/*
* @brief I2C return status code definitions
*/
#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */
#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */
/*
* @brief I2C Master transmit mode
*/
#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
/*
* @brief I2C Master receive mode
*/
#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */
/*
* @brief I2C Slave receive mode
*/
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */
// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
SLV/TRX (Slave Transmit) */
/*
* @brief I2C Slave transmit mode
*/
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */
/*
* @brief I2C Data register definition
*/
#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */
#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
its sending data length that can be supported */
/*
* @brief I2C Monitor mode control register description
*/
#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/*
* @brief I2C Data buffer register description
*/
#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */
/*
* @brief I2C Slave Address registers definition
*/
#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */
#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */
/*
* @brief I2C Mask Register definition
*/
#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */
/*
* @brief I2C SCL HIGH duty cycle Register definition
*/
#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */
/*
* @brief I2C SCL LOW duty cycle Register definition
*/
#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */
/*
* @brief I2C status values
*/
#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */
/*
* @brief I2C state handle return values
*/
#define I2C_OK 0x00
#define I2C_BYTE_SENT 0x01
#define I2C_BYTE_RECV 0x02
#define I2C_LAST_BYTE_RECV 0x04
#define I2C_SEND_END 0x08
#define I2C_RECV_END 0x10
#define I2C_STA_STO_RECV 0x20
#define I2C_ERR (0x10000000)
#define I2C_NAK_RECV (0x10000000 | 0x01)
#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
/*
* @brief I2C monitor control configuration defines
*/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/**
* @brief I2C Slave Identifiers
*/
typedef enum {
I2C_SLAVE_GENERAL, /**< Slave ID for general calls */
I2C_SLAVE_0, /**< Slave ID fo Slave Address 0 */
I2C_SLAVE_1, /**< Slave ID fo Slave Address 1 */
I2C_SLAVE_2, /**< Slave ID fo Slave Address 2 */
I2C_SLAVE_3, /**< Slave ID fo Slave Address 3 */
I2C_SLAVE_NUM_INTERFACE /**< Number of slave interfaces */
} I2C_SLAVE_ID;
/**
* @brief I2C transfer status
*/
typedef enum {
I2C_STATUS_DONE, /**< Transfer done successfully */
I2C_STATUS_NAK, /**< NAK received during transfer */
I2C_STATUS_ARBLOST, /**< Aribitration lost during transfer */
I2C_STATUS_BUSERR, /**< Bus error in I2C transfer */
I2C_STATUS_BUSY, /**< I2C is busy doing transfer */
} I2C_STATUS_T;
/**
* @brief Master transfer data structure definitions
*/
typedef struct {
uint8_t slaveAddr; /**< 7-bit I2C Slave address */
const uint8_t *txBuff; /**< Pointer to array of bytes to be transmitted */
int txSz; /**< Number of bytes in transmit array,
if 0 only receive transfer will be carried on */
uint8_t *rxBuff; /**< Pointer memory where bytes received from I2C be stored */
int rxSz; /**< Number of bytes to received,
if 0 only transmission we be carried on */
I2C_STATUS_T status; /**< Status of the current I2C transfer */
} I2C_XFER_T;
/**
* @brief I2C interface IDs
* @note
* All Chip functions will take this as the first parameter,
* I2C_NUM_INTERFACE must never be used for calling any Chip
* functions, it is only used to find the number of interfaces
* available in the Chip.
*/
typedef enum I2C_ID {
I2C0, /**< ID I2C0 */
I2C1, /**< ID I2C1 */
I2C2, /**< ID I2C2 */
I2C_NUM_INTERFACE /**< Number of I2C interfaces in the chip */
} I2C_ID_T;
/**
* @brief I2C master events
*/
typedef enum {
I2C_EVENT_WAIT = 1, /**< I2C Wait event */
I2C_EVENT_DONE, /**< Done event that wakes up Wait event */
I2C_EVENT_LOCK, /**< Re-entrency lock event for I2C transfer */
I2C_EVENT_UNLOCK, /**< Re-entrency unlock event for I2C transfer */
I2C_EVENT_SLAVE_RX, /**< Slave receive event */
I2C_EVENT_SLAVE_TX, /**< Slave transmit event */
} I2C_EVENT_T;
/**
* @brief Event handler function type
*/
typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);
/**
* @brief Initializes the LPC_I2C peripheral with specified parameter.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_Init(I2C_ID_T id);
/**
* @brief De-initializes the I2C peripheral registers to their default reset values
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_DeInit(I2C_ID_T id);
/**
* @brief Set up clock rate for LPC_I2C peripheral.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param clockrate : Target clock rate value to initialized I2C peripheral (Hz)
* @return Nothing
* @note
* Parameter @a clockrate for I2C0 should be from 1000 up to 1000000
* (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. If the @a clockrate
* is more than 400 KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()
* must be called prior to calling this function.
*/
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);
/**
* @brief Get current clock rate for LPC_I2C peripheral.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return The current I2C peripheral clock rate
*/
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);
/**
* @brief Transmit and Receive data in master mode
* @param id : I2C peripheral selected (I2C0, I2C1 etc)
* @param xfer : Pointer to a I2C_XFER_T structure see notes below
* @return
* Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes
* not sent due to error, xfer->rxSz will have the number of bytes yet
* to be received.
* @note
* The parameter @a xfer should have its member @a slaveAddr initialized
* to the 7-Bit slave address to which the master will do the xfer, Bit0
* to bit6 should have the address and Bit8 is ignored. During the transfer
* no code (like event handler) must change the content of the memory
* pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
* initialized to the memory from which the I2C must pick the data to be
* transfered to slave and the number of bytes to send respectively, similarly
* @a rxBuff and @a rxSz must have pointer to memroy where data received
* from slave be stored and the number of data to get from slave respectilvely.
*/
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);
/**
* @brief Transmit data to I2C slave using I2C Master mode
* @param id : I2C peripheral ID (I2C0, I2C1 .. etc)
* @param slaveAddr : Slave address to which the data be written
* @param buff : Pointer to buffer having the array of data
* @param len : Number of bytes to be transfered from @a buff
* @return Number of bytes successfully transfered
*/
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);
/**
* @brief Transfer a command to slave and receive data from slave after a repeated start
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param slaveAddr : Slave address of the I2C device
* @param cmd : Command (Address/Register) to be written
* @param buff : Pointer to memory that will hold the data received
* @param len : Number of bytes to receive
* @return Number of bytes successfully received
*/
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);
/**
* @brief Get pointer to current function handling the events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Pointer to function handing events of I2C
*/
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);
/**
* @brief Set function that must handle I2C events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Pointer to function that will handle the event (Should not be NULL)
* @return 1 when successful, 0 when a transfer is on going with its own event handler
*/
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);
/**
* @brief Set function that must handle I2C events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param slaveAddr : Slave address from which data be read
* @param buff : Pointer to memory where data read be stored
* @param len : Number of bytes to read from slave
* @return Number of bytes read successfully
*/
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);
/**
* @brief Default event handler for polling operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Event ID of the event that called the function
* @return Nothing
*/
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);
/**
* @brief Default event handler for interrupt base operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Event ID of the event that called the function
* @return Nothing
*/
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);
/**
* @brief I2C Master transfer state change handler
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
* @note Usually called from the appropriate Interrupt handler
*/
void Chip_I2C_MasterStateHandler(I2C_ID_T id);
/**
* @brief Disable I2C peripheral's operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_Disable(I2C_ID_T id);
/**
* @brief Checks if master xfer in progress
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return 1 if master xfer in progress 0 otherwise
* @note
* This API is generally used in interrupt handler
* of the application to decide whether to call
* master state handler or to call slave state handler
*/
int Chip_I2C_IsMasterActive(I2C_ID_T id);
/**
* @brief Setup a slave I2C device
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param sid : I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)
* @param xfer : Pointer to transfer structure (see note below for more info)
* @param event : Event handler for slave transfers
* @param addrMask : Address mask to use along with slave address (see notes below for more info)
* @return Nothing
* @note
* Parameter @a xfer should point to a valid I2C_XFER_T structure object
* and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),
* Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will
* be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers
* where slave can receive or send the data from, size of which will be provided by
* @a rxSz and @a txSz respectively. Function pointed to by @a event will be called
* for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully
* from the master and stored inside memory pointed by xfer->rxBuff, incremented
* the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of
* data from xfer->txBuff was sent to master successfully, incremented the pointer
* and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers
* with the slave).<br>
* <br>Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1
* to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as
* don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then
* 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered
* slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual
* address which was received from master.<br>
* <br><b>General Call Handling</b><br>
* Slave can receive data from master using general call address (0x00). General call
* handling must be setup as given below
* - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL
* - xfer->slaveAddr ignored, argument @a addrMask ignored
* - function provided by @a event will registered to be called when slave received data using addr 0x00
* - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer
* - To handle General Call only (No other slaves are configured)
* - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
* - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL
* - provide @a addrMask (typically 0, if not you better be knowing what you are doing)
* - To handler General Call when other slave is active
* - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
* - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]
* - Set Bit0 of @a xfer->slaveAddr as 1
* - Provide appropriate @a addrMask
* - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC
* @warning
* If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler
* will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer
* then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be
* called to notify this. For more info see section below<br>
* <br><b> Last data handling in slave </b><br>
* If the user wants to implement a slave which will read a byte from a specific location over and over
* again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read
* the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from
* xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another
* byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will
* occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte
* event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer
* and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte
* in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and
* the process repeats.
*/
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask);
/**
* @brief I2C Slave event handler
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_SlaveStateHandler(I2C_ID_T id);
/**
* @brief I2C peripheral state change checking
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return 1 if I2C peripheral @a id has changed its state,
* 0 if there is no state change
* @note
* This function must be used by the application when
* the polling has to be done based on state change.
*/
int Chip_I2C_IsStateChanged(I2C_ID_T id);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2C_17XX_40XX_H_ */

534
hw/mcu/nxp/lpc_chip_175x_6x/inc/i2s_17xx_40xx.h Normal file
View File

@ -0,0 +1,534 @@
/*
* @brief LPC17xx/40xx I2S driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2S_17XX_40XX_H_
#define __I2S_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup I2S_17XX_40XX CHIP: LPC17xx/40xx I2S driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief I2S DMA request channel define
*/
typedef enum {
I2S_DMA_REQUEST_CHANNEL_1, /*!< DMA request channel 1 */
I2S_DMA_REQUEST_CHANNEL_2, /*!< DMA request channel 2 */
I2S_DMA_REQUEST_CHANNEL_NUM,/*!< The number of DMA request channels */
} I2S_DMA_CHANNEL_T;
/**
* @brief I2S register block structure
*/
typedef struct { /*!< I2S Structure */
__IO uint32_t DAO; /*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
__IO uint32_t DAI; /*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
__O uint32_t TXFIFO; /*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
__I uint32_t RXFIFO; /*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
__I uint32_t STATE; /*!< I2S Status Feedback Register. Contains status information about the I2S interface */
__IO uint32_t DMA[I2S_DMA_REQUEST_CHANNEL_NUM]; /*!< I2S DMA Configuration Registers. Contains control information for DMA request channels */
__IO uint32_t IRQ; /*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
__IO uint32_t TXRATE; /*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
__IO uint32_t RXRATE; /*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
__IO uint32_t TXBITRATE; /*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
__IO uint32_t RXBITRATE; /*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
__IO uint32_t TXMODE; /*!< I2S Transmit mode control */
__IO uint32_t RXMODE; /*!< I2S Receive mode control */
} LPC_I2S_T;
/*
* @brief I2S configuration parameter defines
*/
/* I2S Wordwidth bit */
#define I2S_WORDWIDTH_8 (0UL << 0) /*!< 8 bit Word */
#define I2S_WORDWIDTH_16 (1UL << 0) /*!< 16 bit word */
#define I2S_WORDWIDTH_32 (3UL << 0) /*!< 32 bit word */
/* I2S Channel bit */
#define I2S_STEREO (0UL << 2) /*!< Stereo audio */
#define I2S_MONO (1UL << 2) /*!< Mono audio */
/* I2S Master/Slave mode bit */
#define I2S_MASTER_MODE (0UL << 5) /*!< I2S in master mode */
#define I2S_SLAVE_MODE (1UL << 5) /*!< I2S in slave mode */
/* I2S Stop bit */
#define I2S_STOP_ENABLE (0UL << 3) /*!< I2S stop enable mask */
#define I2S_STOP_DISABLE (1UL << 3) /*!< I2S stop disable mask */
/* I2S Reset bit */
#define I2S_RESET_ENABLE (1UL << 4) /*!< I2S reset enable mask */
#define I2S_RESET_DISABLE (0UL << 4) /*!< I2S reset disable mask */
/* I2S Mute bit */
#define I2S_MUTE_ENABLE (1UL << 15) /*!< I2S mute enable mask */
#define I2S_MUTE_DISABLE (0UL << 15) /*!< I2S mute disbale mask */
/*
* @brief Macro defines for DAO-Digital Audio Output register
*/
/* I2S wordwide - the number of bytes in data*/
#define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAO 8 bit */
#define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAO 16 bit */
#define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAO 32 bit */
#define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
/* I2S control mono or stereo format */
#define I2S_DAO_MONO ((uint32_t) (1 << 2)) /*!< DAO mono audio mask */
/* I2S control stop mode */
#define I2S_DAO_STOP ((uint32_t) (1 << 3)) /*!< DAO stop mask */
/* I2S control reset mode */
#define I2S_DAO_RESET ((uint32_t) (1 << 4)) /*!< DAO reset mask */
/* I2S control master/slave mode */
#define I2S_DAO_SLAVE ((uint32_t) (1 << 5)) /*!< DAO slave mode mask */
/* I2S word select half period minus one */
#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6)) /*!< DAO Word select set macro */
#define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAO Word select mask */
/* I2S control mute mode */
#define I2S_DAO_MUTE ((uint32_t) (1 << 15)) /*!< DAO mute mask */
/*
* @brief Macro defines for DAI-Digital Audio Input register
*/
/* I2S wordwide - the number of bytes in data*/
#define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAI 8 bit */
#define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAI 16 bit */
#define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAI 32 bit */
#define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3)) /*!< DAI word wide mask */
/* I2S control mono or stereo format */
#define I2S_DAI_MONO ((uint32_t) (1 << 2)) /*!< DAI mono mode mask */
/* I2S control stop mode */
#define I2S_DAI_STOP ((uint32_t) (1 << 3)) /*!< DAI stop bit mask */
/* I2S control reset mode */
#define I2S_DAI_RESET ((uint32_t) (1 << 4)) /*!< DAI reset bit mask */
/* I2S control master/slave mode */
#define I2S_DAI_SLAVE ((uint32_t) (1 << 5)) /*!< DAI slave mode mask */
/* I2S word select half period minus one (9 bits)*/
#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6)) /*!< DAI Word select set macro */
#define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAI Word select mask */
/*
* @brief Macro defines for STAT register (Status Feedback register)
*/
#define I2S_STATE_IRQ ((uint32_t) (1))/*!< I2S Status Receive or Transmit Interrupt */
#define I2S_STATE_DMA1 ((uint32_t) (1 << 1)) /*!< I2S Status Receive or Transmit DMA1 */
#define I2S_STATE_DMA2 ((uint32_t) (1 << 2)) /*!< I2S Status Receive or Transmit DMA2 */
#define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))/*!< I2S Status Current level of the Receive FIFO (5 bits)*/
#define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16)) /*!< I2S Status Current level of the Transmit FIFO (5 bits)*/
/*
* @brief Macro defines for DMA1 register (DMA1 Configuration register)
*/
#define I2S_DMA1_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA1 for I2S receive */
#define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */
#define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */
/*
* @brief Macro defines for DMA2 register (DMA2 Configuration register)
*/
#define I2S_DMA2_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA2 for I2S receive */
#define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */
#define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */
/*
* @brief Macro defines for IRQ register (Interrupt Request Control register)
*/
#define I2S_IRQ_RX_ENABLE ((uint32_t) (1))/*!< I2S control I2S receive interrupt */
#define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control I2S transmit interrupt */
#define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8)) /*!< I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
#define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16)) /*!< I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
/*
* @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
*/
#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Transmit MCLK rate denominator */
#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Receive MCLK rate denominator */
#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Receive MCLK rate denominator */
/*
* @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
*/
#define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
#define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
/*
* @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
*/
#define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Transmit select clock source (2 bits)*/
#define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Transmit control 4-pin mode */
#define I2S_TXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Transmit control the TX_MCLK output */
#define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Receive select clock source */
#define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Receive control 4-pin mode */
#define I2S_RXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Receive control the TX_MCLK output */
/**
* @brief I2S Audio Format Structure
*/
typedef struct {
uint32_t SampleRate; /*!< Sample Rate */
uint8_t ChannelNumber; /*!< Channel Number - 1 is mono, 2 is stereo */
uint8_t WordWidth; /*!< Word Width - 8, 16 or 32 bits */
} I2S_AUDIO_FORMAT_T;
/**
* @brief Initialize for I2S
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
*/
void Chip_I2S_Init(LPC_I2S_T *pI2S);
/**
* @brief Shutdown I2S
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
* @note Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
*/
void Chip_I2S_DeInit(LPC_I2S_T *pI2S);
/**
* @brief Send a 32-bit data to TXFIFO for transmition
* @param pI2S : The base of I2S peripheral on the chip
* @param data : Data to be transmited
* @return Nothing
* @note The function writes to TXFIFO without checking any condition.
*/
STATIC INLINE void Chip_I2S_Send(LPC_I2S_T *pI2S, uint32_t data)
{
pI2S->TXFIFO = data;
}
/**
* @brief Get received data from RXFIFO
* @param pI2S : The base of I2S peripheral on the chip
* @return Data received in RXFIFO
* @note The function reads from RXFIFO without checking any condition.
*/
STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_T *pI2S)
{
return pI2S->RXFIFO;
}
/**
* @brief Start transmit data
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_I2S_TxStart(LPC_I2S_T *pI2S)
{
pI2S->DAO &= ~(I2S_DAO_RESET | I2S_DAO_STOP | I2S_DAO_MUTE);
}
/**
* @brief Start receive data
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_I2S_RxStart(LPC_I2S_T *pI2S)
{
pI2S->DAI &= ~(I2S_DAI_RESET | I2S_DAI_STOP);
}
/**
* @brief Disables accesses on FIFOs, places the transmit channel in mute mode
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_I2S_TxPause(LPC_I2S_T *pI2S)
{
pI2S->DAO |= I2S_DAO_STOP;
}
/**
* @brief Disables accesses on FIFOs, places the transmit channel in mute mode
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_I2S_RxPause(LPC_I2S_T *pI2S)
{
pI2S->DAI |= I2S_DAI_STOP;
}
/**
* @brief Mute the Transmit channel
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
* @note The data output from I2S transmit channel is always zeroes
*/
STATIC INLINE void Chip_I2S_EnableMute(LPC_I2S_T *pI2S)
{
pI2S->DAO |= I2S_DAO_MUTE;
}
/**
* @brief Un-Mute the I2S channel
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_I2S_DisableMute(LPC_I2S_T *pI2S)
{
pI2S->DAO &= ~I2S_DAO_MUTE;
}
/**
* @brief Stop I2S asynchronously
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
* @note Pause, resets the transmit channel and FIFO asynchronously
*/
STATIC INLINE void Chip_I2S_TxStop(LPC_I2S_T *pI2S)
{
pI2S->DAO &= ~I2S_DAO_MUTE;
pI2S->DAO |= I2S_DAO_STOP | I2S_DAO_RESET;
}
/**
* @brief Stop I2S asynchronously
* @param pI2S : The base of I2S peripheral on the chip
* @return Nothing
* @note Pause, resets the transmit channel and FIFO asynchronously
*/
STATIC INLINE void Chip_I2S_RxStop(LPC_I2S_T *pI2S)
{
pI2S->DAI |= I2S_DAI_STOP | I2S_DAI_RESET;
}
/**
* @brief Set the I2S transmit mode
* @param pI2S : The base of I2S peripheral on the chip
* @param clksel : Clock source selection for the receive bit clock divider
* @param fpin : Receive 4-pin mode selection
* @param mcena : Enable for the RX_MCLK output
* @return Nothing
* @note In addition to master and slave modes, which are independently configurable for
* the transmitter and the receiver, several different clock sources are possible,
* including variations that share the clock and/or WS between the transmitter and
* receiver. It also allows using I2S with fewer pins, typically four.
*/
STATIC INLINE void Chip_I2S_TxModeConfig(LPC_I2S_T *pI2S,
uint32_t clksel,
uint32_t fpin,
uint32_t mcena)
{
pI2S->TXMODE = clksel | fpin | mcena;
}
/**
* @brief Set the I2S receive mode
* @param pI2S : The base of I2S peripheral on the chip
* @param clksel : Clock source selection for the receive bit clock divider
* @param fpin : Receive 4-pin mode selection
* @param mcena : Enable for the RX_MCLK output
* @return Nothing
* @note In addition to master and slave modes, which are independently configurable for
* the transmitter and the receiver, several different clock sources are possible,
* including variations that share the clock and/or WS between the transmitter and
* receiver. It also allows using I2S with fewer pins, typically four.
*/
STATIC INLINE void Chip_I2S_RxModeConfig(LPC_I2S_T *pI2S,
uint32_t clksel,
uint32_t fpin,
uint32_t mcena)
{
pI2S->RXMODE = clksel | fpin | mcena;
}
/**
* @brief Get the current level of the Transmit FIFO
* @param pI2S : The base of I2S peripheral on the chip
* @return Current level of the Transmit FIFO
*/
STATIC INLINE uint8_t Chip_I2S_GetTxLevel(LPC_I2S_T *pI2S)
{
return (pI2S->STATE >> 16) & 0xF;
}
/**
* @brief Get the current level of the Receive FIFO
* @param pI2S : The base of I2S peripheral on the chip
* @return Current level of the Receive FIFO
*/
STATIC INLINE uint8_t Chip_I2S_GetRxLevel(LPC_I2S_T *pI2S)
{
return (pI2S->STATE >> 8) & 0xF;
}
/**
* @brief Set the clock frequency for I2S interface
* @param pI2S : The base of I2S peripheral on the chip
* @param div : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
* @return Nothing
* @note The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.
* For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz
*/
STATIC INLINE void Chip_I2S_SetTxBitRate(LPC_I2S_T *pI2S, uint32_t div)
{
pI2S->TXBITRATE = div;
}
/**
* @brief Set the clock frequency for I2S interface
* @param pI2S : The base of I2S peripheral on the chip
* @param div : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
* @return Nothing
* @note The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.
* For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz
*/
STATIC INLINE void Chip_I2S_SetRxBitRate(LPC_I2S_T *pI2S, uint32_t div)
{
pI2S->RXBITRATE = div;
}
/**
* @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK
* @param pI2S : The base of I2S peripheral on the chip
* @param xDiv : I2S transmit MCLK rate numerator
* @param yDiv : I2S transmit MCLK rate denominator
* @return Nothing
* @note Values of the numerator (X) and the denominator (Y) must be chosen to
* produce a frequency twice that desired for the transmitter MCLK, which
* must be an integer multiple of the transmitter bit clock rate.
* The equation for the fractional rate generator is:
* MCLK = PCLK * (X/Y) /2
* Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
* greater than or equal to X.
*/
STATIC INLINE void Chip_I2S_SetTxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv)
{
pI2S->TXRATE = yDiv | (xDiv << 8);
}
/**
* @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK
* @param pI2S : The base of I2S peripheral on the chip
* @param xDiv : I2S transmit MCLK rate numerator
* @param yDiv : I2S transmit MCLK rate denominator
* @return Nothing
* @note Values of the numerator (X) and the denominator (Y) must be chosen to
* produce a frequency twice that desired for the transmitter MCLK, which
* must be an integer multiple of the transmitter bit clock rate.
* The equation for the fractional rate generator is:
* MCLK = PCLK * (X/Y) /2
* Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
* greater than or equal to X.
*/
STATIC INLINE void Chip_I2S_SetRxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv)
{
pI2S->RXRATE = yDiv | (xDiv << 8);
}
/**
* @brief Configure I2S for Audio Format input
* @param pI2S : The base I2S peripheral on the chip
* @param format : Audio Format
* @return SUCCESS or ERROR
*/
Status Chip_I2S_TxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format);
/**
* @brief Configure I2S for Audio Format input
* @param pI2S : The base I2S peripheral on the chip
* @param format : Audio Format
* @return SUCCESS or ERROR
*/
Status Chip_I2S_RxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format);
/**
* @brief Enable/Disable Interrupt with a specific FIFO depth
* @param pI2S : The base I2S peripheral on the chip
* @param newState : ENABLE or DISABLE interrupt
* @param depth : FIFO level creating an irq request
* @return Nothing
*/
void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth);
/**
* @brief Enable/Disable Interrupt with a specific FIFO depth
* @param pI2S : The base I2S peripheral on the chip
* @param newState : ENABLE or DISABLE interrupt
* @param depth : FIFO level creating an irq request
* @return Nothing
*/
void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth);
/**
* @brief Enable/Disable DMA with a specific FIFO depth
* @param pI2S : The base I2S peripheral on the chip
* @param dmaNum : Should be
* - I2S_DMA_REQUEST_CHANNEL_1 : Using DMA1
* - I2S_DMA_REQUEST_CHANNEL_2 : Using DMA2
* @param newState : ENABLE or DISABLE interrupt
* @param depth : FIFO level creating an irq request
* @return Nothing
*/
void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth);
/**
* @brief Enable/Disable DMA with a specific FIFO depth
* @param pI2S : The base I2S peripheral on the chip
* @param dmaNum : Should be
* - I2S_DMA_REQUEST_CHANNEL_1 : Using DMA1
* - I2S_DMA_REQUEST_CHANNEL_2 : Using DMA2
* @param newState : ENABLE or DISABLE interrupt
* @param depth : FIFO level creating an irq request
* @return Nothing
*/
void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2S_17XX_40XX_H_ */

184
hw/mcu/nxp/lpc_chip_175x_6x/inc/iap.h Normal file
View File

@ -0,0 +1,184 @@
/*
* @brief Common IAP support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __IAP_H_
#define __IAP_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup COMMON_IAP CHIP: Common Chip ISP/IAP commands and return codes
* @ingroup CHIP_Common
* @{
*/
/* IAP command definitions */
#define IAP_PREWRRITE_CMD 50 /*!< Prepare sector for write operation command */
#define IAP_WRISECTOR_CMD 51 /*!< Write Sector command */
#define IAP_ERSSECTOR_CMD 52 /*!< Erase Sector command */
#define IAP_BLANK_CHECK_SECTOR_CMD 53 /*!< Blank check sector */
#define IAP_REPID_CMD 54 /*!< Read PartID command */
#define IAP_READ_BOOT_CODE_CMD 55 /*!< Read Boot code version */
#define IAP_COMPARE_CMD 56 /*!< Compare two RAM address locations */
#define IAP_REINVOKE_ISP_CMD 57 /*!< Reinvoke ISP */
#define IAP_READ_UID_CMD 58 /*!< Read UID */
#define IAP_ERASE_PAGE_CMD 59 /*!< Erase page */
#define IAP_EEPROM_WRITE 61 /*!< EEPROM Write command */
#define IAP_EEPROM_READ 62 /*!< EEPROM READ command */
/* IAP response definitions */
#define IAP_CMD_SUCCESS 0 /*!< Command is executed successfully */
#define IAP_INVALID_COMMAND 1 /*!< Invalid command */
#define IAP_SRC_ADDR_ERROR 2 /*!< Source address is not on word boundary */
#define IAP_DST_ADDR_ERROR 3 /*!< Destination address is not on a correct boundary */
#define IAP_SRC_ADDR_NOT_MAPPED 4 /*!< Source address is not mapped in the memory map */
#define IAP_DST_ADDR_NOT_MAPPED 5 /*!< Destination address is not mapped in the memory map */
#define IAP_COUNT_ERROR 6 /*!< Byte count is not multiple of 4 or is not a permitted value */
#define IAP_INVALID_SECTOR 7 /*!< Sector number is invalid or end sector number is greater than start sector number */
#define IAP_SECTOR_NOT_BLANK 8 /*!< Sector is not blank */
#define IAP_SECTOR_NOT_PREPARED 9 /*!< Command to prepare sector for write operation was not executed */
#define IAP_COMPARE_ERROR 10 /*!< Source and destination data not equal */
#define IAP_BUSY 11 /*!< Flash programming hardware interface is busy */
#define IAP_PARAM_ERROR 12 /*!< nsufficient number of parameters or invalid parameter */
#define IAP_ADDR_ERROR 13 /*!< Address is not on word boundary */
#define IAP_ADDR_NOT_MAPPED 14 /*!< Address is not mapped in the memory map */
#define IAP_CMD_LOCKED 15 /*!< Command is locked */
#define IAP_INVALID_CODE 16 /*!< Unlock code is invalid */
#define IAP_INVALID_BAUD_RATE 17 /*!< Invalid baud rate setting */
#define IAP_INVALID_STOP_BIT 18 /*!< Invalid stop bit setting */
#define IAP_CRP_ENABLED 19 /*!< Code read protection enabled */
/* IAP_ENTRY API function type */
typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]);
/**
* @brief Prepare sector for write operation
* @param strSector : Start sector number
* @param endSector : End sector number
* @return Status code to indicate the command is executed successfully or not
* @note This command must be executed before executing "Copy RAM to flash"
* or "Erase Sector" command.
* The end sector must be greater than or equal to start sector number
*/
uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector);
/**
* @brief Copy RAM to flash
* @param dstAdd : Destination flash address where data bytes are to be written
* @param srcAdd : Source flash address where data bytes are to be read
* @param byteswrt : Number of bytes to be written
* @return Status code to indicate the command is executed successfully or not
* @note The addresses should be a 256 byte boundary and the number of bytes
* should be 256 | 512 | 1024 | 4096
*/
uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt);
/**
* @brief Erase sector
* @param strSector : Start sector number
* @param endSector : End sector number
* @return Status code to indicate the command is executed successfully or not
* @note The end sector must be greater than or equal to start sector number
*/
uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector);
/**
* @brief Blank check a sector or multiples sector of on-chip flash memory
* @param strSector : Start sector number
* @param endSector : End sector number
* @return Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK
* @note The end sector must be greater than or equal to start sector number
*/
// FIXME - There are two return value (result[0] & result[1]
// Result0:Offset of the first non blank word location if the Status Code is
// SECTOR_NOT_BLANK.
// Result1:Contents of non blank word location.
uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector);
/**
* @brief Read part identification number
* @return Part identification number
*/
uint32_t Chip_IAP_ReadPID(void);
/**
* @brief Read boot code version number
* @return Boot code version number
*/
uint8_t Chip_IAP_ReadBootCode(void);
/**
* @brief Compare the memory contents at two locations
* @param dstAdd : Destination of the RAM address of data bytes to be compared
* @param srcAdd : Source of the RAM address of data bytes to be compared
* @param bytescmp : Number of bytes to be compared
* @return Offset of the first mismatch of the status code is COMPARE_ERROR
* @note The addresses should be a word boundary and number of bytes should be
* a multiply of 4
*/
uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp);
/**
* @brief IAP reinvoke ISP to invoke the bootloader in ISP mode
* @return none
*/
uint8_t Chip_IAP_ReinvokeISP(void);
/**
* @brief Read the unique ID
* @return Status code to indicate the command is executed successfully or not
*/
uint32_t Chip_IAP_ReadUID(void);
/**
* @brief Erase a page or multiple papers of on-chip flash memory
* @param strPage : Start page number
* @param endPage : End page number
* @return Status code to indicate the command is executed successfully or not
* @note The page number must be greater than or equal to start page number
*/
// FIXME - There are four return value
// Result0:The first 32-bit word (at the lowest address)
// Result1:The second 32-bit word.
// Result2:The third 32-bit word.
// Result3:The fourth 32-bit word.
uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IAP_H_ */

274
hw/mcu/nxp/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h Normal file
View File

@ -0,0 +1,274 @@
/*
* @brief LPC17xx/40xx IOCON registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __IOCON_17XX_40XX_H_
#define __IOCON_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup IOCON_17XX_40XX CHIP: LPC17xx/40xx I/O configuration driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format
*/
typedef struct {
uint32_t pingrp:3; /* Pin group */
uint32_t pinnum:5; /* Pin number */
uint32_t modefunc:24; /* Function and mode. */
} PINMUX_GRP_T;
/**
* @brief IOCON register block
*/
typedef struct {
#if defined(CHIP_LPC175X_6X)
__IO uint32_t PINSEL[11];
uint32_t RESERVED0[5];
__IO uint32_t PINMODE[10];
__IO uint32_t PINMODE_OD[5];
__IO uint32_t I2CPADCFG;
#else
__IO uint32_t p[5][32];
#endif
} LPC_IOCON_T;
/**
* IOCON function and mode selection definitions
* See the User Manual for specific modes and functions supoprted by the
* various LPC11xx devices. Functionality can vary per device.
*/
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
#if defined(CHIP_LPC175X_6X)
#define IOCON_MODE_INACT (0x2 << 2) /*!< No addition pin function */
#define IOCON_MODE_PULLDOWN (0x3 << 2) /*!< Selects pull-down function */
#define IOCON_MODE_PULLUP (0x0 << 2) /*!< Selects pull-up function */
#define IOCON_MODE_REPEATER (0x1 << 2) /*!< Selects pin repeater function */
#else
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
#define IOCON_ADMODE_EN (0x0 << 7) /*!< Enables analog input function (analog pins only) */
#define IOCON_DIGMODE_EN (0x1 << 7) /*!< Enables digital function (analog pins only) */
#define IOCON_FILT_DIS (0x1 << 8) /*!< Disables noise pulses filtering (10nS glitch filter) */
#define IOCON_HS_DIS (0x1 << 8) /*!< I2C glitch filter and slew rate disabled */
#define IOCON_HIDRIVE_EN (0x1 << 9) /*!< Sink current is 20 mA */
#define IOCON_FASTSLEW_EN (0x1 << 9) /*!< Enables fast slew */
#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
#define IOCON_DAC_EN (0x1 << 16) /*!< Enables DAC function */
#endif
/**
* IOCON function and mode selection definitions (old)
* For backwards compatibility.
*/
#define FUNC0 0x0 /** Function 0 */
#define FUNC1 0x1 /** Function 1 */
#define FUNC2 0x2 /** Function 2 */
#define FUNC3 0x3 /** Function 3 */
#if defined(CHIP_LPC175X_6X)
#define MD_PLN (0x2)
#define MD_PDN (0x3)
#define MD_PUP (0x0)
#define MD_BUK (0x1)
#else
#define MD_PLN (0x0 << 3)
#define MD_PDN (0x1 << 3)
#define MD_PUP (0x2 << 3)
#define MD_BUK (0x3 << 3)
#define MD_HYS_ENA (0x1 << 5) /*!< Macro to enable hysteresis- use with Chip_IOCON_PinMux */
#define MD_HYS_DIS (0x0 << 5) /*!< Macro to disable hysteresis- use with Chip_IOCON_PinMux */
#define MD_IINV_ENA (0x1 << 6) /*!< Macro to enable input inversion- use with Chip_IOCON_PinMux */
#define MD_IINV_DIS (0x0 << 6) /*!< Macro to disable input inversion- use with Chip_IOCON_PinMux */
#define MD_OD_ENA (0x1 << 10) /*!< Macro to enable simulated open drain mode- use with Chip_IOCON_PinMux */
#define MD_OD_DIS (0x0 << 10) /*!< Macro to disable simulated open drain mode- use with Chip_IOCON_PinMux */
#define MD_HS_ENA (0x0 << 8) /*!< Macro to enable I2C 50ns glitch filter and slew rate control- use with Chip_IOCON_PinMux */
#define MD_HS_DIS (0x1 << 8) /*!< Macro to disable I2C 50ns glitch filter and slew rate control- use with Chip_IOCON_PinMux */
#define MD_ANA_ENA (0x0 << 7) /*!< Macro to enable analog mode (ADC)- use with Chip_IOCON_PinMux */
#define MD_ANA_DIS (0x1 << 7) /*!< Macro to disable analog mode (ADC)- use with Chip_IOCON_PinMux */
#define MD_FILT_ENA (0x0 << 8) /*!< Macro to enable input filter- use with Chip_IOCON_PinMux */
#define MD_FILT_DIS (0x1 << 8) /*!< Macro to disable input filter- use with Chip_IOCON_PinMux */
#define MD_DAC_ENA (0x1 << 16) /*!< Macro to enable DAC- use with Chip_IOCON_PinMux */
#define MD_DAC_DIS (0x0 << 16) /*!< Macro to disable DAC- use with Chip_IOCON_PinMux */
#define MD_STD_SLEW_RATE (0x0 << 9) /*!< Macro to enable standard mode, slew rate control is enabled - use with Chip_IOCON_PinMux */
#define MD_FAST_SLEW_RATE (0x1 << 9) /*!< Macro to enable fast mode, slew rate control is disabled - use with Chip_IOCON_PinMux */
#define MD_HD_ENA (0x1 << 9) /*!< Macro to enable high drive output- use with Chip_IOCON_PinMux */
#define MD_HD_DIS (0x0 << 9) /*!< Macro to disable high drive output- use with Chip_IOCON_PinMux */
#define FUNC4 0x4 /** Function 4 */
#define FUNC5 0x5 /** Function 5 */
#define FUNC6 0x6 /** Function 6 */
#define FUNC7 0x7 /** Function 7 */
#endif /* defined(CHIP_LPC175X_6X)*/
/**
* @brief Initialize the IOCON peripheral
* @param pIOCON : The base of IOCON peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_Init(LPC_IOCON_T *pIOCON)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
#if defined(CHIP_LPC175X_6X)
/* PINSEL and PINMODE register index calculation.*/
#define IOCON_REG_INDEX(port, pin) (2 * port + (pin / 16))
/* Bit position calculation in PINSEL and PINMODE register.*/
#define IOCON_BIT_INDEX(pin) ((pin % 16) * 2)
/**
* @brief Sets I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : GPIO port to mux
* @param pin : GPIO pin to mux
* @param modefunc : OR'ed values or type IOCON_*
* @return Nothing
*/
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc);
/**
* @brief Setup pin modes and function
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : port number
* @param pin : gpio pin number
* @param mode : OR'ed values or type IOCON_*
* @param func : Pin function, value of type IOCON_FUNC0 to IOCON_FUNC3
* @return Nothing
*/
void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t mode, uint8_t func);
/**
* @brief Enable open drain mode
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : port number
* @param pin : gpio pin number
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_EnableOD(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin)
{
pIOCON->PINMODE_OD[port] |= (0x01UL << pin);
}
/**
* @brief Disable open drain mode
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : port number
* @param pin : gpio pin number
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_DisableOD(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin)
{
pIOCON->PINMODE_OD[port] &= ~(0x01UL << pin);
}
/**
* @brief I2C pin configuration definitions
*/
typedef enum {
I2CPADCFG_STD_MODE = 0x00, /*!< Standard I2C mode */
I2CPADCFG_FAST_MODE = I2CPADCFG_STD_MODE, /*!< Fast mode */
I2CPADCFG_FAST_MODE_PLUS = 0x05, /*!< Fast mode plus */
I2CPADCFG_NON_I2C = 0x0A, /*!< For non-I2C use*/
} IOCON_I2CPINS_CONFIG;
/**
* @brief Configure I2C pad pins (P0.27 and P0.28)
* @param pIOCON : The base of IOCON peripheral on the chip
* @param cfg : pin configurations
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_SetI2CPad(LPC_IOCON_T *pIOCON, IOCON_I2CPINS_CONFIG cfg)
{
pIOCON->I2CPADCFG = cfg;
}
#else
/**
* @brief Sets I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : GPIO port to mux
* @param pin : GPIO pin to mux
* @param modefunc : OR'ed values or type IOCON_*
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
{
pIOCON->p[port][pin] = modefunc;
}
/**
* @brief Setup pin modes and function
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : port number
* @param pin : gpio pin number
* @param mode : OR'ed values or type IOCON_*
* @param func : Pin function, value of type IOCON_FUNC0 to IOCON_FUNC7
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t mode, uint8_t func)
{
Chip_IOCON_PinMuxSet(pIOCON, port, pin, (mode | func));
}
#endif /* defined(CHIP_LPC175X_6X) */
/**
* @brief Set all I/O Control pin muxing
* @param pIOCON : The base of IOCON peripheral on the chip
* @param pinArray : Pointer to array of pin mux selections
* @param arrayLength : Number of entries in pinArray
* @return Nothing
*/
void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IOCON_17XX_40XX_H_ */

387
hw/mcu/nxp/lpc_chip_175x_6x/inc/lcd_17xx_40xx.h Normal file
View File

@ -0,0 +1,387 @@
/*
* @brief LPC17xx/40xx LCD driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LCD_17XX_40XX_H_
#define __LCD_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup LCD_17XX_40XX CHIP: LPC17xx/40xx LCD driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief LCD Controller register block structure
*/
typedef struct { /*!< LCD Structure */
__IO uint32_t TIMH; /*!< Horizontal Timing Control register */
__IO uint32_t TIMV; /*!< Vertical Timing Control register */
__IO uint32_t POL; /*!< Clock and Signal Polarity Control register */
__IO uint32_t LE; /*!< Line End Control register */
__IO uint32_t UPBASE; /*!< Upper Panel Frame Base Address register */
__IO uint32_t LPBASE; /*!< Lower Panel Frame Base Address register */
__IO uint32_t CTRL; /*!< LCD Control register */
__IO uint32_t INTMSK; /*!< Interrupt Mask register */
__I uint32_t INTRAW; /*!< Raw Interrupt Status register */
__I uint32_t INTSTAT; /*!< Masked Interrupt Status register */
__O uint32_t INTCLR; /*!< Interrupt Clear register */
__I uint32_t UPCURR; /*!< Upper Panel Current Address Value register */
__I uint32_t LPCURR; /*!< Lower Panel Current Address Value register */
__I uint32_t RESERVED0[115];
__IO uint16_t PAL[256]; /*!< 256x16-bit Color Palette registers */
__I uint32_t RESERVED1[256];
__IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */
__IO uint32_t CRSR_CTRL; /*!< Cursor Control register */
__IO uint32_t CRSR_CFG; /*!< Cursor Configuration register */
__IO uint32_t CRSR_PAL0; /*!< Cursor Palette register 0 */
__IO uint32_t CRSR_PAL1; /*!< Cursor Palette register 1 */
__IO uint32_t CRSR_XY; /*!< Cursor XY Position register */
__IO uint32_t CRSR_CLIP; /*!< Cursor Clip Position register */
__I uint32_t RESERVED2[2];
__IO uint32_t CRSR_INTMSK; /*!< Cursor Interrupt Mask register */
__O uint32_t CRSR_INTCLR; /*!< Cursor Interrupt Clear register */
__I uint32_t CRSR_INTRAW; /*!< Cursor Raw Interrupt Status register */
__I uint32_t CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */
} LPC_LCD_T;
/**
* @brief LCD Palette entry format
*/
typedef struct {
uint32_t Rl : 5;
uint32_t Gl : 5;
uint32_t Bl : 5;
uint32_t Il : 1;
uint32_t Ru : 5;
uint32_t Gu : 5;
uint32_t Bu : 5;
uint32_t Iu : 1;
} LCD_PALETTE_ENTRY_T;
/**
* @brief LCD Panel type
*/
typedef enum {
LCD_TFT = 0x02, /*!< standard TFT */
LCD_MONO_4 = 0x01, /*!< 4-bit STN mono */
LCD_MONO_8 = 0x05, /*!< 8-bit STN mono */
LCD_CSTN = 0x00 /*!< color STN */
} LCD_PANEL_OPT_T;
/**
* @brief LCD Color Format
*/
typedef enum {
LCD_COLOR_FORMAT_RGB = 0,
LCD_COLOR_FORMAT_BGR
} LCD_COLOR_FORMAT_OPT_T;
/** LCD Interrupt control mask register bits */
#define LCD_INTMSK_FUFIM 0x2 /*!< FIFO underflow interrupt enable */
#define LCD_INTMSK_LNBUIM 0x4 /*!< LCD next base address update interrupt enable */
#define LCD_INTMSK_VCOMPIM 0x8 /*!< Vertical compare interrupt enable */
#define LCD_INTMSK_BERIM 0x10 /*!< AHB master error interrupt enable */
#define CLCDC_LCDCTRL_ENABLE _BIT(0) /*!< LCD control enable bit */
#define CLCDC_LCDCTRL_PWR _BIT(11) /*!< LCD control power enable bit */
/**
* @brief A structure for LCD Configuration
*/
typedef struct {
uint8_t HBP; /*!< Horizontal back porch in clocks */
uint8_t HFP; /*!< Horizontal front porch in clocks */
uint8_t HSW; /*!< HSYNC pulse width in clocks */
uint16_t PPL; /*!< Pixels per line */
uint8_t VBP; /*!< Vertical back porch in clocks */
uint8_t VFP; /*!< Vertical front porch in clocks */
uint8_t VSW; /*!< VSYNC pulse width in clocks */
uint16_t LPP; /*!< Lines per panel */
uint8_t IOE; /*!< Invert output enable, 1 = invert */
uint8_t IPC; /*!< Invert panel clock, 1 = invert */
uint8_t IHS; /*!< Invert HSYNC, 1 = invert */
uint8_t IVS; /*!< Invert VSYNC, 1 = invert */
uint8_t ACB; /*!< AC bias frequency in clocks (not used) */
uint8_t BPP; /*!< Maximum bits per pixel the display supports */
LCD_PANEL_OPT_T LCD; /*!< LCD panel type */
LCD_COLOR_FORMAT_OPT_T color_format; /*!<BGR or RGB */
uint8_t Dual; /*!< Dual panel, 1 = dual panel display */
} LCD_CONFIG_T;
/**
* @brief LCD Cursor Size
*/
typedef enum {
LCD_CURSOR_32x32 = 0,
LCD_CURSOR_64x64
} LCD_CURSOR_SIZE_OPT_T;
/**
* @brief Initialize the LCD controller
* @param pLCD : The base of LCD peripheral on the chip
* @param LCD_ConfigStruct : Pointer to LCD configuration
* @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
*/
void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_CONFIG_T *LCD_ConfigStruct);
/**
* @brief Shutdown the LCD controller
* @param pLCD : The base of LCD peripheral on the chip
* @return Nothing
*/
void Chip_LCD_DeInit(LPC_LCD_T *pLCD);
/**
* @brief Power-on the LCD Panel (power pin)
* @param pLCD : The base of LCD peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_LCD_PowerOn(LPC_LCD_T *pLCD)
{
volatile int i;
pLCD->CTRL |= CLCDC_LCDCTRL_PWR;
for (i = 0; i < 1000000; i++) {}
pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
}
/**
* @brief Power-off the LCD Panel (power pin)
* @param pLCD : The base of LCD peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_LCD_PowerOff(LPC_LCD_T *pLCD)
{
volatile int i;
pLCD->CTRL &= ~CLCDC_LCDCTRL_PWR;
for (i = 0; i < 1000000; i++) {}
pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
}
/**
* @brief Enable/Disable the LCD Controller
* @param pLCD : The base of LCD peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_LCD_Enable(LPC_LCD_T *pLCD)
{
pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
}
/**
* @brief Enable/Disable the LCD Controller
* @param pLCD : The base of LCD peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_LCD_Disable(LPC_LCD_T *pLCD)
{
pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
}
/**
* @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
* Buffer for Dual Panel
* @param pLCD : The base of LCD peripheral on the chip
* @param buffer : address of buffer
* @return None
*/
STATIC INLINE void Chip_LCD_SetUPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)
{
pLCD->UPBASE = (uint32_t) buffer;
}
/**
* @brief Set LCD Lower Panel Frame Buffer for Dual Panel
* @param pLCD : The base of LCD peripheral on the chip
* @param buffer : address of buffer
* @return None
*/
STATIC INLINE void Chip_LCD_SetLPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)
{
pLCD->LPBASE = (uint32_t) buffer;
}
/**
* @brief Configure Cursor
* @param pLCD : The base of LCD peripheral on the chip
* @param cursor_size : specify size of cursor
* - LCD_CURSOR_32x32 :cursor size is 32x32 pixels
* - LCD_CURSOR_64x64 :cursor size is 64x64 pixels
* @param sync : cursor sync mode
* - TRUE :cursor sync to the frame sync pulse
* - FALSE :cursor async mode
* @return None
*/
void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync);
/**
* @brief Enable Cursor
* @param pLCD : The base of LCD peripheral on the chip
* @param cursor_num : specify number of cursor is going to be written
* this param must < 4
* @return None
*/
STATIC INLINE void Chip_LCD_Cursor_Enable(LPC_LCD_T *pLCD, uint8_t cursor_num)
{
pLCD->CRSR_CTRL = (cursor_num << 4) | 1;
}
/**
* @brief Disable Cursor
* @param pLCD : The base of LCD peripheral on the chip
* @param cursor_num : specify number of cursor is going to be written
* this param must < 4
* @return None
*/
STATIC INLINE void Chip_LCD_Cursor_Disable(LPC_LCD_T *pLCD, uint8_t cursor_num)
{
pLCD->CRSR_CTRL = (cursor_num << 4);
}
/**
* @brief Load Cursor Palette
* @param pLCD : The base of LCD peripheral on the chip
* @param palette_color : cursor palette 0 value
* @return None
*/
STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(LPC_LCD_T *pLCD, uint32_t palette_color)
{
/* 7:0 - Red
15:8 - Green
23:16 - Blue
31:24 - Not used*/
pLCD->CRSR_PAL0 = (uint32_t) palette_color;
}
/**
* @brief Load Cursor Palette
* @param pLCD : The base of LCD peripheral on the chip
* @param palette_color : cursor palette 1 value
* @return None
*/
STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(LPC_LCD_T *pLCD, uint32_t palette_color)
{
/* 7:0 - Red
15:8 - Green
23:16 - Blue
31:24 - Not used*/
pLCD->CRSR_PAL1 = (uint32_t) palette_color;
}
/**
* @brief Set Cursor Position
* @param pLCD : The base of LCD peripheral on the chip
* @param x : horizontal position
* @param y : vertical position
* @return None
*/
STATIC INLINE void Chip_LCD_Cursor_SetPos(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)
{
pLCD->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);
}
/**
* @brief Set Cursor Clipping Position
* @param pLCD : The base of LCD peripheral on the chip
* @param x : horizontal position, should be in range: 0..63
* @param y : vertical position, should be in range: 0..63
* @return None
*/
STATIC INLINE void Chip_LCD_Cursor_SetClip(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)
{
pLCD->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);
}
/**
* @brief Enable Controller Interrupt
* @param pLCD : The base of LCD peripheral on the chip
* @param ints : OR'ed interrupt bits to enable
* @return None
*/
STATIC INLINE void Chip_LCD_EnableInts(LPC_LCD_T *pLCD, uint32_t ints)
{
pLCD->INTMSK = ints;
}
/**
* @brief Disable Controller Interrupt
* @param pLCD : The base of LCD peripheral on the chip
* @param ints : OR'ed interrupt bits to disable
* @return None
*/
STATIC INLINE void Chip_LCD_DisableInts(LPC_LCD_T *pLCD, uint32_t ints)
{
pLCD->INTMSK = pLCD->INTMSK & ~(ints);
}
/**
* @brief Clear Controller Interrupt
* @param pLCD : The base of LCD peripheral on the chip
* @param ints : OR'ed interrupt bits to clear
* @return None
*/
STATIC INLINE void Chip_LCD_ClearInts(LPC_LCD_T *pLCD, uint32_t ints)
{
pLCD->INTCLR = pLCD->INTMSK & (ints);
}
/**
* @brief Write Cursor Image into Internal Cursor Image Buffer
* @param pLCD : The base of LCD peripheral on the chip
* @param cursor_num : Cursor index
* @param Image : Pointer to image data
* @return None
*/
void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image);
/**
* @brief Load LCD Palette
* @param pLCD : The base of LCD peripheral on the chip
* @param palette : Address of palette table to load
* @return None
*/
void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette);
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* __LCD_17XX_40XX_H_ */

216
hw/mcu/nxp/lpc_chip_175x_6x/inc/lpc_types.h Normal file
View File

@ -0,0 +1,216 @@
/*
* @brief Common types used in LPC functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_TYPES_H_
#define __LPC_TYPES_H_
#include <stdint.h>
#include <stdbool.h>
/** @defgroup LPC_Types CHIP: LPC Common Types
* @ingroup CHIP_Common
* @{
*/
/** @defgroup LPC_Types_Public_Types LPC Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Boolean Type definition
*/
#if !defined(__cplusplus)
// typedef enum {false = 0, true = !false} bool;
#endif
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum {
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)();
/**
* @}
*/
/** @defgroup LPC_Types_Public_Macros LPC Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1 << (n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f, v) ((v) << (f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void *) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility */
/** @addtogroup LPC_Types_Public_Types
* @{
*/
/** LPC type for character type */
typedef char CHAR;
/** LPC type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** LPC type for 8 bit signed value */
typedef int8_t INT_8;
/** LPC type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** LPC type for 16 bit signed value */
typedef int16_t INT_16;
/** LPC type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** LPC type for 32 bit signed value */
typedef int32_t INT_32;
/** LPC type for 64 bit signed value */
typedef int64_t INT_64;
/** LPC type for 64 bit unsigned value */
typedef uint64_t UNS_64;
#ifdef __CODE_RED
#define BOOL_32 bool
#define BOOL_16 bool
#define BOOL_8 bool
#else
/** 32 bit boolean type */
typedef bool BOOL_32;
/** 16 bit boolean type */
typedef bool BOOL_16;
/** 8 bit boolean type */
typedef bool BOOL_8;
#endif
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __LPC_TYPES_H_ */

80
hw/mcu/nxp/lpc_chip_175x_6x/inc/mcpwm_17xx_40xx.h Normal file
View File

@ -0,0 +1,80 @@
/*
* @brief LPC17xx/40xx Motor Control PWM driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __MCPWM_17XX_40XX_H_
#define __MCPWM_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup MCPWM_17XX_40XX CHIP: LPC17xx/40xx Motor Control PWM driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief Motor Control PWM register block structure
*/
typedef struct { /*!< MCPWM Structure */
__I uint32_t CON; /*!< PWM Control read address */
__O uint32_t CON_SET; /*!< PWM Control set address */
__O uint32_t CON_CLR; /*!< PWM Control clear address */
__I uint32_t CAPCON; /*!< Capture Control read address */
__O uint32_t CAPCON_SET; /*!< Capture Control set address */
__O uint32_t CAPCON_CLR; /*!< Event Control clear address */
__IO uint32_t TC[3]; /*!< Timer Counter register */
__IO uint32_t LIM[3]; /*!< Limit register */
__IO uint32_t MAT[3]; /*!< Match register */
__IO uint32_t DT; /*!< Dead time register */
__IO uint32_t CCP; /*!< Communication Pattern register */
__I uint32_t CAP[3]; /*!< Capture register */
__I uint32_t INTEN; /*!< Interrupt Enable read address */
__O uint32_t INTEN_SET; /*!< Interrupt Enable set address */
__O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */
__I uint32_t CNTCON; /*!< Count Control read address */
__O uint32_t CNTCON_SET; /*!< Count Control set address */
__O uint32_t CNTCON_CLR; /*!< Count Control clear address */
__I uint32_t INTF; /*!< Interrupt flags read address */
__O uint32_t INTF_SET; /*!< Interrupt flags set address */
__O uint32_t INTF_CLR; /*!< Interrupt flags clear address */
__O uint32_t CAP_CLR; /*!< Capture clear address */
} LPC_MCPWM_T;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __MCPWM_17XX_40XX_H_ */

135
hw/mcu/nxp/lpc_chip_175x_6x/inc/pmu_17xx_40xx.h Normal file
View File

@ -0,0 +1,135 @@
/*
* @brief LPC17xx_40xx PMU chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __PMU_17XX_40XX_H_
#define __PMU_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup PMU_17XX_40XX CHIP: LPC17xx_40xx PMU driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief LPC17xx_40xx Power Management Unit register block structure
*/
typedef struct {
__IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
} LPC_PMU_T;
/**
* @brief LPC17xx_40xx low power mode type definitions
*/
typedef enum CHIP_PMU_MCUPOWER {
PMU_MCU_SLEEP = 0, /*!< Sleep mode */
PMU_MCU_DEEP_SLEEP, /*!< Deep Sleep mode */
PMU_MCU_POWER_DOWN, /*!< Power down mode */
PMU_MCU_DEEP_PWRDOWN /*!< Deep power down mode */
} CHIP_PMU_MCUPOWER_T;
/**
* PMU PCON register bit fields & masks
*/
#define PMU_PCON_PM0_FLAG (1 << 0)
#define PMU_PCON_PM1_FLAG (1 << 1)
#define PMU_PCON_BODRPM_FLAG (1 << 2)
#define PMU_PCON_BOGD_FLAG (1 << 3)
#define PMU_PCON_BORD_FLAG (1 << 4)
#define PMU_PCON_SMFLAG (1 << 8) /*!< Sleep mode flag */
#define PMU_PCON_DSFLAG (1 << 9) /*!< Deep Sleep mode flag */
#define PMU_PCON_PDFLAG (1 << 10) /*!< Power-down flag */
#define PMU_PCON_DPDFLAG (1 << 11) /*!< Deep power-down flag */
/**
* @brief Enter MCU Sleep mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
* and memories are active.
*/
void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
/**
* @brief Enter MCU Deep Sleep mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note In Deep-sleep mode, the peripherals receive no internal clocks.
* The flash is in stand-by mode. The SRAM memory and all peripheral registers
* as well as the processor maintain their internal states. The WWDT, WKT,
* and BOD can remain active to wake up the system on an interrupt.
*/
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
/**
* @brief Enter MCU Power down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note In Power-down mode, the peripherals receive no internal clocks.
* The internal SRAM memory and all peripheral registers as well as the
* processor maintain their internal states. The flash memory is powered
* down. The WWDT, WKT, and BOD can remain active to wake up the system
* on an interrupt.
*/
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
/**
* @brief Enter MCU Deep Power down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note For maximal power savings, the entire system is shut down
* except for the general purpose registers in the PMU and the self
* wake-up timer. Only the general purpose registers in the PMU maintain
* their internal states. The part can wake up on a pulse on the WAKEUP
* pin or when the self wake-up timer times out. On wake-up, the part
* reboots.
*/
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
/**
* @brief Place the MCU in a low power state
* @param pPMU : Pointer to PMU register block
* @param SleepMode : Sleep mode
* @return None
*/
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PMU_17XX_40XX_H_ */

86
hw/mcu/nxp/lpc_chip_175x_6x/inc/qei_17xx_40xx.h Normal file
View File

@ -0,0 +1,86 @@
/*
* @brief LPC17xx/40xx Quadrature Encoder Interface driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __QEI_17XX_40XX_H_
#define __QEI_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup QEI_17XX_40XX CHIP: LPc17xx/40xx Quadrature Encoder Interface driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief Quadrature Encoder Interface register block structure
*/
typedef struct { /*!< QEI Structure */
__O uint32_t CON; /*!< Control register */
__I uint32_t STAT; /*!< Encoder status register */
__IO uint32_t CONF; /*!< Configuration register */
__I uint32_t POS; /*!< Position register */
__IO uint32_t MAXPOS; /*!< Maximum position register */
__IO uint32_t CMPOS0; /*!< position compare register 0 */
__IO uint32_t CMPOS1; /*!< position compare register 1 */
__IO uint32_t CMPOS2; /*!< position compare register 2 */
__I uint32_t INXCNT; /*!< Index count register */
__IO uint32_t INXCMP0; /*!< Index compare register 0 */
__IO uint32_t LOAD; /*!< Velocity timer reload register */
__I uint32_t TIME; /*!< Velocity timer register */
__I uint32_t VEL; /*!< Velocity counter register */
__I uint32_t CAP; /*!< Velocity capture register */
__IO uint32_t VELCOMP; /*!< Velocity compare register */
__IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
__IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
__IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
__IO uint32_t WINDOW; /*!< Index acceptance window register */
__IO uint32_t INXCMP1; /*!< Index compare register 1 */
__IO uint32_t INXCMP2; /*!< Index compare register 2 */
__I uint32_t RESERVED0[993];
__O uint32_t IEC; /*!< Interrupt enable clear register */
__O uint32_t IES; /*!< Interrupt enable set register */
__I uint32_t INTSTAT; /*!< Interrupt status register */
__I uint32_t IE; /*!< Interrupt enable register */
__O uint32_t CLR; /*!< Interrupt status clear register */
__O uint32_t SET; /*!< Interrupt status set register */
} LPC_QEI_T;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __QEI_17XX_40XX_H_ */

188
hw/mcu/nxp/lpc_chip_175x_6x/inc/ring_buffer.h Normal file
View File

@ -0,0 +1,188 @@
/*
* @brief Common ring buffer support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __RING_BUFFER_H_
#define __RING_BUFFER_H_
#include "lpc_types.h"
/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
* @ingroup CHIP_Common
* @{
*/
/**
* @brief Ring buffer structure
*/
typedef struct {
void *data;
int count;
int itemSz;
uint32_t head;
uint32_t tail;
} RINGBUFF_T;
/**
* @def RB_VHEAD(rb)
* volatile typecasted head index
*/
#define RB_VHEAD(rb) (*(volatile uint32_t *) &(rb)->head)
/**
* @def RB_VTAIL(rb)
* volatile typecasted tail index
*/
#define RB_VTAIL(rb) (*(volatile uint32_t *) &(rb)->tail)
/**
* @brief Initialize ring buffer
* @param RingBuff : Pointer to ring buffer to initialize
* @param buffer : Pointer to buffer to associate with RingBuff
* @param itemSize : Size of each buffer item size
* @param count : Size of ring buffer
* @note Memory pointed by @a buffer must have correct alignment of
* @a itemSize, and @a count must be a power of 2 and must at
* least be 2 or greater.
* @return Nothing
*/
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
/**
* @brief Resets the ring buffer to empty
* @param RingBuff : Pointer to ring buffer
* @return Nothing
*/
STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff)
{
RingBuff->head = RingBuff->tail = 0;
}
/**
* @brief Return size the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Size of the ring buffer in bytes
*/
STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff)
{
return RingBuff->count;
}
/**
* @brief Return number of items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Number of items in the ring buffer
*/
STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
{
return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff);
}
/**
* @brief Return number of free items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Number of free items in the ring buffer
*/
STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff)
{
return RingBuff->count - RingBuffer_GetCount(RingBuff);
}
/**
* @brief Return number of items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return 1 if the ring buffer is full, otherwise 0
*/
STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff)
{
return (RingBuffer_GetCount(RingBuff) >= RingBuff->count);
}
/**
* @brief Return empty status of ring buffer
* @param RingBuff : Pointer to ring buffer
* @return 1 if the ring buffer is empty, otherwise 0
*/
STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
{
return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff);
}
/**
* @brief Insert a single item into ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : pointer to item
* @return 1 when successfully inserted,
* 0 on error (Buffer not initialized using
* RingBuffer_Init() or attempted to insert
* when buffer is full)
*/
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data);
/**
* @brief Insert an array of items into ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to first element of the item array
* @param num : Number of items in the array
* @return number of items successfully inserted,
* 0 on error (Buffer not initialized using
* RingBuffer_Init() or attempted to insert
* when buffer is full)
*/
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num);
/**
* @brief Pop an item from the ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to memory where popped item be stored
* @return 1 when item popped successfuly onto @a data,
* 0 When error (Buffer not initialized using
* RingBuffer_Init() or attempted to pop item when
* the buffer is empty)
*/
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data);
/**
* @brief Pop an array of items from the ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to memory where popped items be stored
* @param num : Max number of items array @a data can hold
* @return Number of items popped onto @a data,
* 0 on error (Buffer not initialized using RingBuffer_Init()
* or attempted to pop when the buffer is empty)
*/
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num);
/**
* @}
*/
#endif /* __RING_BUFFER_H_ */

199
hw/mcu/nxp/lpc_chip_175x_6x/inc/ritimer_17xx_40xx.h Normal file
View File

@ -0,0 +1,199 @@
/*
* @brief LPC17xx/40xx RITimer driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __RITIMER_17XX_40XX_H_
#define __RITIMER_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup RIT_17XX_40XX CHIP: LPC17xx/40xx Repetitive Interrupt Timer driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC175X_6X)
/**
* @brief Repetitive Interrupt Timer register block structure
*/
typedef struct { /*!< RITIMER Structure */
__IO uint32_t COMPVAL; /*!< Compare register */
__IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
__IO uint32_t CTRL; /*!< Control register. */
__IO uint32_t COUNTER; /*!< 32-bit counter */
#if defined(CHIP_LPC1347)
__IO uint32_t COMPVAL_H; /*!< Compare upper register */
__IO uint32_t MASK_H; /*!< Mask upper register */
__I uint32_t RESERVED0[1];
__IO uint32_t COUNTER_H; /*!< Counter upper register */
#endif
} LPC_RITIMER_T;
/*
* @brief RITIMER register support bitfields and mask
*/
/*
* RIT control register
*/
/** Set by H/W when the counter value equals the masked compare value */
#define RIT_CTRL_INT ((uint32_t) (1))
/** Set timer enable clear to 0 when the counter value equals the masked compare value */
#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
/** Set timer enable on debug */
#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
/** Set timer enable */
#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
/**
* @brief Initialize the RIT
* @param pRITimer : RITimer peripheral selected
* @return None
*/
void Chip_RIT_Init(LPC_RITIMER_T *pRITimer);
/**
* @brief Shutdown the RIT
* @param pRITimer : RITimer peripheral selected
* @return None
*/
void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer);
/**
* @brief Enable Timer
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL |= RIT_CTRL_TEN;
}
/**
* @brief Disable Timer
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL &= ~RIT_CTRL_TEN;
}
/**
* @brief Enable timer debug
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL |= RIT_CTRL_ENBR;
}
/**
* @brief Disable timer debug
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL &= ~RIT_CTRL_ENBR;
}
/**
* @brief Check whether interrupt flag is set or not
* @param pRITimer : RITimer peripheral selected
* @return Current interrupt status, either ET or UNSET
*/
IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer);
/**
* @brief Set a tick value for the interrupt to time out
* @param pRITimer : RITimer peripheral selected
* @param val : value (in ticks) of the interrupt to be set
* @return None
*/
STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val)
{
pRITimer->COMPVAL = val;
}
/**
* @brief Enables or clears the RIT or interrupt
* @param pRITimer : RITimer peripheral selected
* @param val : RIT to be set, one or more RIT_CTRL_* values
* @return None
*/
STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val)
{
pRITimer->CTRL |= val;
}
/**
* @brief Clears the RIT interrupt
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL |= RIT_CTRL_INT;
}
/**
* @brief Returns the current RIT Counter value
* @param pRITimer : RITimer peripheral selected
* @return the current timer counter value
*/
STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer)
{
return pRITimer->COUNTER;
}
/**
* @brief Set timer interval value
* @param pRITimer : RITimer peripheral selected
* @param time_interval : timer interval value (ms)
* @return None
*/
void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval);
#endif /* defined(CHIP_LPC175X_6X) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __RITIMER_17XX_40XX_H_ */

91
hw/mcu/nxp/lpc_chip_175x_6x/inc/romapi_17xx_40xx.h Normal file
View File

@ -0,0 +1,91 @@
/*
* @brief LPC17xx/40xx ROM API declarations and functions
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ROMAPI_17XX40XX_H_
#define __ROMAPI_17XX40XX_H_
#include "iap.h"
#include "error.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ROMAPI_407X_8X CHIP: LPC17XX/40XX ROM API declarations and functions
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if !defined(CHIP_LPC175X_6X)
/**
* @brief LPC17XX/40XX High level ROM API structure
*/
typedef struct {
const uint32_t usbdApiBase; /*!< USBD API function table base address */
const uint32_t reserved0; /*!< Reserved */
const uint32_t reserved1; /*!< Reserved */
const uint32_t reserved2; /*!< Reserved */
const uint32_t reserved3; /*!< Reserved */
const uint32_t reserved4; /*!< Reserved */
const uint32_t reserved5; /*!< Reserved */
const uint32_t reserved6; /*!< Reserved */
const uint32_t reserved7; /*!< Reserved */
const uint32_t reserved8; /*!< Reserved */
const uint32_t reserved9; /*!< Reserved */
const uint32_t reserved10; /*!< Reserved */
} LPC_ROM_API_T;
/* Pointer to ROM API function address */
#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8
#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC)
#endif /* !defined(CHIP_LPC175X_6X) */
/* Pointer to ROM IAP entry functions */
#define IAP_ENTRY_LOCATION 0X1FFF1FF1
/**
* @brief LPC17XX/40XX IAP_ENTRY API function type
*/
static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4])
{
((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ROMAPI_17XX40XX_H_ */

646
hw/mcu/nxp/lpc_chip_175x_6x/inc/rtc_17xx_40xx.h Normal file
View File

@ -0,0 +1,646 @@
/*
* @brief LPC17xx/40xx RTC driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __RTC_17XX_40XX_H_
#define __RTC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup RTC_17XX_40XX CHIP: LPC17xx/40xx Real Time Clock driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
#endif
/**
* @brief RTC time type option
*/
typedef enum {
RTC_TIMETYPE_SECOND, /*!< Second */
RTC_TIMETYPE_MINUTE, /*!< Month */
RTC_TIMETYPE_HOUR, /*!< Hour */
RTC_TIMETYPE_DAYOFMONTH, /*!< Day of month */
RTC_TIMETYPE_DAYOFWEEK, /*!< Day of week */
RTC_TIMETYPE_DAYOFYEAR, /*!< Day of year */
RTC_TIMETYPE_MONTH, /*!< Month */
RTC_TIMETYPE_YEAR, /*!< Year */
RTC_TIMETYPE_LAST
} RTC_TIMEINDEX_T;
#if RTC_EV_SUPPORT
/**
* @brief Event Channel Identifier definitions
*/
typedef enum {
RTC_EV_CHANNEL_1 = 0,
RTC_EV_CHANNEL_2,
RTC_EV_CHANNEL_3,
RTC_EV_CHANNEL_NUM,
} RTC_EV_CHANNEL_T;
#endif /*RTC_EV_SUPPORT*/
/**
* @brief Real Time Clock register block structure
*/
typedef struct { /*!< RTC Structure */
__IO uint32_t ILR; /*!< Interrupt Location Register */
__I uint32_t RESERVED0;
__IO uint32_t CCR; /*!< Clock Control Register */
__IO uint32_t CIIR; /*!< Counter Increment Interrupt Register */
__IO uint32_t AMR; /*!< Alarm Mask Register */
__I uint32_t CTIME[3]; /*!< Consolidated Time Register 0,1,2 */
__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /*!< Timer field registers */
__IO uint32_t CALIBRATION; /*!< Calibration Value Register */
__IO uint32_t GPREG[5]; /*!< General Purpose Storage Registers */
__IO uint32_t RTC_AUXEN; /*!< RTC Auxiliary Enable register */
__IO uint32_t RTC_AUX; /*!< RTC Auxiliary control register*/
__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /*!< Alarm field registers */
#if RTC_EV_SUPPORT
__IO uint32_t ERSTATUS; /*!< Event Monitor/Recorder Status register*/
__IO uint32_t ERCONTROL; /*!< Event Monitor/Recorder Control register*/
__I uint32_t ERCOUNTERS; /*!< Event Monitor/Recorder Counters register*/
__I uint32_t RESERVED2;
__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /*!<Event Monitor/Recorder First Stamp registers*/
__I uint32_t RESERVED3;
__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /*!<Event Monitor/Recorder Last Stamp registers*/
#endif /*RTC_EV_SUPPORT*/
} LPC_RTC_T;
/**
* @brief Register File register block structure
*/
typedef struct {
__IO uint32_t REGFILE[5]; /*!< General purpose storage register */
} LPC_REGFILE_T;
/*
* @brief ILR register definitions
*/
/** ILR register mask */
#define RTC_ILR_BITMASK ((0x00000003))
/** Bit inform the source interrupt is counter increment*/
#define RTC_IRL_RTCCIF ((1 << 0))
/** Bit inform the source interrupt is alarm match*/
#define RTC_IRL_RTCALF ((1 << 1))
/*
* @brief CCR register definitions
*/
/** CCR register mask */
#define RTC_CCR_BITMASK ((0x00000013))
/** Clock enable */
#define RTC_CCR_CLKEN ((1 << 0))
/** Clock reset */
#define RTC_CCR_CTCRST ((1 << 1))
/** Calibration counter enable */
#define RTC_CCR_CCALEN ((1 << 4))
/*
* @brief CIIR and AMR register definitions
*/
/** Counter Increment Interrupt bit for second */
#define RTC_AMR_CIIR_IMSEC ((1 << 0))
/** Counter Increment Interrupt bit for minute */
#define RTC_AMR_CIIR_IMMIN ((1 << 1))
/** Counter Increment Interrupt bit for hour */
#define RTC_AMR_CIIR_IMHOUR ((1 << 2))
/** Counter Increment Interrupt bit for day of month */
#define RTC_AMR_CIIR_IMDOM ((1 << 3))
/** Counter Increment Interrupt bit for day of week */
#define RTC_AMR_CIIR_IMDOW ((1 << 4))
/** Counter Increment Interrupt bit for day of year */
#define RTC_AMR_CIIR_IMDOY ((1 << 5))
/** Counter Increment Interrupt bit for month */
#define RTC_AMR_CIIR_IMMON ((1 << 6))
/** Counter Increment Interrupt bit for year */
#define RTC_AMR_CIIR_IMYEAR ((1 << 7))
/** CIIR bit mask */
#define RTC_AMR_CIIR_BITMASK ((0xFF))
/*
* @brief RTC_AUX register definitions
*/
/** RTC Oscillator Fail detect flag */
#define RTC_AUX_RTC_OSCF ((1 << 4))
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/** RTC_ALARM pin control flag */
#define RTC_AUX_RTC_PDOUT ((1 << 6))
#endif
/*
* @brief RTC_AUXEN register definitions
*/
/** Oscillator Fail Detect interrupt enable*/
#define RTC_AUXEN_RTC_OSCFEN ((1 << 4))
/*
* @brief Consolidated Time Register 0 definitions
*/
#define RTC_CTIME0_SECONDS_MASK ((0x3F))
#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
#define RTC_CTIME0_DOW_MASK ((0x7000000))
/*
* @brief Consolidated Time Register 1 definitions
*/
#define RTC_CTIME1_DOM_MASK ((0x1F))
#define RTC_CTIME1_MONTH_MASK ((0xF00))
#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
/*
* @brief Consolidated Time Register 2 definitions
*/
#define RTC_CTIME2_DOY_MASK ((0xFFF))
/*
* @brief Time Counter Group and Alarm register group
*/
/** SEC register mask */
#define RTC_SEC_MASK (0x0000003F)
/** MIN register mask */
#define RTC_MIN_MASK (0x0000003F)
/** HOUR register mask */
#define RTC_HOUR_MASK (0x0000001F)
/** DOM register mask */
#define RTC_DOM_MASK (0x0000001F)
/** DOW register mask */
#define RTC_DOW_MASK (0x00000007)
/** DOY register mask */
#define RTC_DOY_MASK (0x000001FF)
/** MONTH register mask */
#define RTC_MONTH_MASK (0x0000000F)
/** YEAR register mask */
#define RTC_YEAR_MASK (0x00000FFF)
#define RTC_SECOND_MAX 59 /*!< Maximum value of second */
#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/
#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/
#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/
#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/
#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/
#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/
#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/
#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/
#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/
#define RTC_YEAR_MAX 4095/*!< Maximum value of year*/
/*
* @brief Calibration register
*/
/** Calibration value */
#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
/** Calibration direction */
#define RTC_CALIBRATION_LIBDIR ((1 << 17))
/** Calibration max value */
#define RTC_CALIBRATION_MAX ((0x20000))
/** Calibration definitions */
#define RTC_CALIB_DIR_FORWARD ((uint8_t) (0))
#define RTC_CALIB_DIR_BACKWARD ((uint8_t) (1))
#if RTC_EV_SUPPORT
/*
* @brief Event Monitor/Recorder Control register
*/
/** Event Monitor/Recorder Control register mask */
#define RTC_ERCTRL_BITMASK ((uint32_t) 0xC0F03C0F)
/** Enable event interrupt and wakeup */
#define RTC_ERCTRL_INTWAKE_EN ((uint32_t) (1 << 0))
/** Enables automatically clearing the RTC general purpose registers when an event occurs*/
#define RTC_ERCTRL_GPCLEAR_EN ((uint32_t) (1 << 1))
/** Select polarity for a channel event on the input pin.*/
#define RTC_ERCTRL_POL_NEGATIVE (0) /* Event as positive edge */
#define RTC_ERCTRL_POL_POSITIVE ((uint32_t) (1 << 2)) /* Event as negative edge */
/** Enable event input.*/
#define RTC_ERCTRL_INPUT_EN ((uint32_t) (1 << 3))
/** Configure a specific channel */
#define RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch) ((uint32_t) (0x0F << (10 * ch)))
#define RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) ((uint32_t) (flag << (10 * ch)))
/** Enable Event Monitor/Recorder and select its operating frequency.*/
#define RTC_ERCTRL_MODE_MASK (((uint32_t) 3) << 30)
#define RTC_ERCTRL_MODE_CLK_DISABLE (((uint32_t) 0) << 30)
#define RTC_ERCTRL_MODE_16HZ (((uint32_t) 1) << 30)
#define RTC_ERCTRL_MODE_64HZ (((uint32_t) 2) << 30)
#define RTC_ERCTRL_MODE_1KHZ (((uint32_t) 3) << 30)
#define RTC_ERCTRL_MODE(n) (((uint32_t) n) << 30)
/*
* @brief Event Monitor/Recorder Status register
*/
/** Event Flag for a specific channel */
#define RTC_ERSTATUS_CHANNEL_EV(ch) ((uint32_t) (1 << ch)) /* At least 1 event has occurred on a specific channel */
/** General purpose registers have been asynchronous cleared. */
#define RTC_ERSTATUS_GPCLEARED ((uint32_t) (1 << 3))
/** An interrupt/wakeup request is pending.*/
#define RTC_ERSTATUS_WAKEUP ((uint32_t) (((uint32_t) 1) << 31))
/*
* @brief Event Monitor/Recorder Counter register
*/
/** Value of the counter for Events occurred on a specific channel */
#define RTC_ER_COUNTER(ch, n) ((uint32_t) ((n >> (8 * ch)) & 0x07))
/*
* @brief Event Monitor/Recorder TimeStamp register
*/
#define RTC_ER_TIMESTAMP_SEC(n) ((uint32_t) (n & 0x3F))
#define RTC_ER_TIMESTAMP_MIN(n) ((uint32_t) ((n >> 6) & 0x3F))
#define RTC_ER_TIMESTAMP_HOUR(n) ((uint32_t) ((n >> 12) & 0x1F))
#define RTC_ER_TIMESTAMP_DOY(n) ((uint32_t) ((n >> 17) & 0x1FF))
/**
* @brief Event Monitor/Recorder Mode definition
*/
typedef enum IP_RTC_EV_MODE {
RTC_EV_MODE_DISABLE = 0, /*!< Event Monitor/Recoder is disabled */
RTC_EV_MODE_ENABLE_16HZ = 1, /*!< Event Monitor/Recoder is enabled and use 16Hz sample clock for event input */
RTC_EV_MODE_ENABLE_64HZ = 2, /*!< Event Monitor/Recoder is enabled and use 64Hz sample clock for event input */
RTC_EV_MODE_ENABLE_1KHZ = 3, /*!< Event Monitor/Recoder is enabled and use 1kHz sample clock for event input */
RTC_EV_MODE_LAST,
} RTC_EV_MODE_T;
/**
* @brief Event Monitor/Recorder Timestamp structure
*/
typedef struct {
uint8_t sec; /*!< Second */
uint8_t min; /*!< Minute */
uint8_t hour; /*!< Hour */
uint16_t dayofyear; /*!< Day of year */
} RTC_EV_TIMESTAMP_T;
#endif /*RTC_EV_SUPPORT*/
/**
* @brief RTC enumeration
*/
/** @brief RTC interrupt source */
typedef enum {
RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */
} RTC_INT_OPT_T;
typedef struct {
uint32_t time[RTC_TIMETYPE_LAST];
} RTC_TIME_T;
/**
* @brief Reset clock tick counter in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @return None
*/
void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC);
/**
* @brief Start/Stop RTC peripheral
* @param pRTC : RTC peripheral selected
* @param NewState : New State of this function, should be:
* - ENABLE :The time counters are enabled
* - DISABLE :The time counters are disabled
* @return None
*/
void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState);
/**
* @brief Enable/Disable Counter increment interrupt for a time type in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
* @param NewState : ENABLE or DISABLE
* @return None
*/
void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState);
/**
* @brief Enable/Disable Alarm interrupt for a time type in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
* @param NewState : ENABLE or DISABLE
* @return None
*/
void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState);
/**
* @brief Set current time value for a time type in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param Timetype : time field index type to set
* @param TimeValue : Value to palce in time field
* @return None
*/
STATIC INLINE void Chip_RTC_SetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
{
pRTC->TIME[Timetype] = TimeValue;
}
/**
* @brief Get current time value for a type time type
* @param pRTC : RTC peripheral selected
* @param Timetype : Time field index type to get
* @return Value of time field according to specified time type
*/
STATIC INLINE uint32_t Chip_RTC_GetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype)
{
return pRTC->TIME[Timetype];
}
/**
* @brief Set full time in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param pFullTime : Pointer to full time data
* @return None
*/
void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
/**
* @brief Get full time from the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param pFullTime : Pointer to full time record to fill
* @return None
*/
void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
/**
* @brief Set alarm time value for a time type
* @param pRTC : RTC peripheral selected
* @param Timetype : Time index field to set
* @param ALValue : Alarm time value to set
* @return None
*/
STATIC INLINE void Chip_RTC_SetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
{
pRTC->ALRM[Timetype] = ALValue;
}
/**
* @brief Get alarm time value for a time type
* @param pRTC : RTC peripheral selected
* @param Timetype : Time index field to get
* @return Value of Alarm time according to specified time type
*/
STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype)
{
return pRTC->ALRM[Timetype];
}
/**
* @brief Set full alarm time in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param pFullTime : Pointer to full time record to set alarm
* @return None
*/
void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
/**
* @brief Get full alarm time in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param pFullTime : Pointer to full time record to fill
* @return None
*/
void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
/**
* @brief Write value to General purpose registers
* @param pRegFile : RegFile peripheral selected
* @param index : General purpose register index
* @param value : Value to write
* @return None
* @note These General purpose registers can be used to store important
* information when the main power supply is off. The value in these
* registers is not affected by chip reset. These registers are
* powered in the RTC power domain.
*/
STATIC INLINE void Chip_REGFILE_Write(LPC_REGFILE_T *pRegFile, uint8_t index, uint32_t value)
{
pRegFile->REGFILE[index] = value;
}
/**
* @brief Read value from General purpose registers
* @param pRegFile : RegFile peripheral selected
* @param index : General purpose register index
* @return Read Value
* @note These General purpose registers can be used to store important
* information when the main power supply is off. The value in these
* registers is not affected by chip reset. These registers are
* powered in the RTC power domain.
*/
STATIC INLINE uint32_t Chip_REGFILE_Read(LPC_REGFILE_T *pRegFile, uint8_t index)
{
return pRegFile->REGFILE[index];
}
/**
* @brief Enable/Disable calibration counter in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param NewState : New State of this function, should be:
* - ENABLE :The calibration counter is enabled and counting
* - DISABLE :The calibration counter is disabled and reset to zero
* @return None
*/
void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState);
/**
* @brief Configures Calibration in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param CalibValue : Calibration value, should be in range from 0 to 131,072
* @param CalibDir : Calibration Direction, should be:
* - RTC_CALIB_DIR_FORWARD :Forward calibration
* - RTC_CALIB_DIR_BACKWARD :Backward calibration
* @return None
*/
STATIC INLINE void Chip_RTC_CalibConfig(LPC_RTC_T *pRTC, uint32_t CalibValue, uint8_t CalibDir)
{
pRTC->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK)
| ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
}
/**
* @brief Clear specified Location interrupt pending in the RTC peripheral
* @param pRTC : RTC peripheral selected
* @param IntType : Interrupt location type, should be:
* - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.
* - RTC_INT_ALARM :Clear alarm interrupt pending
* @return None
*/
STATIC INLINE void Chip_RTC_ClearIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
{
pRTC->ILR = IntType;
}
/**
* @brief Check whether if specified location interrupt in the RTC peripheral is set or not
* @param pRTC : RTC peripheral selected
* @param IntType : Interrupt location type, should be:
* - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
* - RTC_INT_ALARM: Alarm generated an interrupt.
* @return New state of specified Location interrupt in RTC peripheral, SET OR RESET
*/
STATIC INLINE IntStatus Chip_RTC_GetIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
{
return (pRTC->ILR & IntType) ? SET : RESET;
}
#if RTC_EV_SUPPORT
/**
* @brief Configure a specific event channel
* @param pRTC : RTC peripheral selected
* @param ch : Channel number
* @param flag : Configuration flag
* @return None
* @note flag is or-ed bit value of RTC_ERCTRL_INTWAKE_EN,RTC_ERCTRL_GPCLEAR_EN,
* RTC_ERCTRL_POL_POSITIVE and RTC_ERCTRL_INPUT_EN.
*/
STATIC INLINE void Chip_RTC_EV_Config(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, uint32_t flag)
{
uint32_t temp;
temp = pRTC->ERCONTROL & (~(RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch))) & RTC_ERCTRL_BITMASK;
pRTC->ERCONTROL = temp | (RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) & RTC_ERCTRL_BITMASK);
}
/**
* @brief Enable/Disable and select clock frequency for Event Monitor/Recorder
* @param pRTC : RTC peripheral selected
* @param mode : selected mode
* @return None
*/
STATIC INLINE void Chip_RTC_EV_SetMode(LPC_RTC_T *pRTC, RTC_EV_MODE_T mode)
{
uint32_t temp;
temp = pRTC->ERCONTROL & (~RTC_ERCTRL_MODE_MASK) & RTC_ERCTRL_BITMASK;
pRTC->ERCONTROL = temp | RTC_ERCTRL_MODE(mode);
}
/**
* @brief Get Event Monitor/Recorder Status
* @param pRTC : RTC peripheral selected
* @return Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP
*/
STATIC INLINE uint8_t Chip_RTC_EV_GetStatus(LPC_RTC_T *pRTC)
{
return pRTC->ERSTATUS & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
}
/**
* @brief Clear Event Monitor/Recorder Status
* @param pRTC : RTC peripheral selected
* @param flag : Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP
* @return Nothing
*/
STATIC INLINE void Chip_RTC_EV_ClearStatus(LPC_RTC_T *pRTC, uint32_t flag)
{
pRTC->ERSTATUS = flag & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
}
/**
* @brief Get status of a specific event channel
* @param pRTC : RTC peripheral selected
* @param ch : Channel number
* @return SET (At least 1 event occurred on the channel), RESET: no event occured.
*/
STATIC INLINE FlagStatus Chip_RTC_EV_GetChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
{
return (pRTC->ERSTATUS & RTC_ERSTATUS_CHANNEL_EV(ch)) ? SET : RESET;
}
/**
* @brief Clear status of a specific event channel
* @param pRTC : RTC peripheral selected
* @param ch : Channel number
* @return Nothing.
*/
STATIC INLINE void Chip_RTC_EV_ClearChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
{
pRTC->ERSTATUS = RTC_ERSTATUS_CHANNEL_EV(ch);
}
/**
* @brief Get counter value of a specific event channel
* @param pRTC : RTC peripheral selected
* @param ch : Channel number
* @return counter value
*/
STATIC INLINE uint8_t Chip_RTC_EV_GetCounter(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
{
return RTC_ER_COUNTER(ch, pRTC->ERCOUNTERS);
}
/**
* @brief Get first time stamp of a specific event channel
* @param pRTC : RTC peripheral selected
* @param ch : Channel number
* @param pTimeStamp : pointer to Timestamp buffer
* @return Nothing.
*/
void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp);
/**
* @brief Get last time stamp of a specific event channel
* @param pRTC : RTC peripheral selected
* @param ch : Channel number
* @param pTimeStamp : pointer to Timestamp buffer
* @return Nothing.
*/
void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp);
#endif /*RTC_EV_SUPPORT*/
/**
* @brief Initialize the RTC peripheral
* @param pRTC : RTC peripheral selected
* @return None
*/
void Chip_RTC_Init(LPC_RTC_T *pRTC);
/**
* @brief De-initialize the RTC peripheral
* @param pRTC : RTC peripheral selected
* @return None
*/
void Chip_RTC_DeInit(LPC_RTC_T *pRTC);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __RTC_17XX_40XX_H_ */

583
hw/mcu/nxp/lpc_chip_175x_6x/inc/sdc_17xx_40xx.h Normal file
View File

@ -0,0 +1,583 @@
/*
* @brief LPC17xx/40xx SD Card Interface driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SDC_17XX_40XX_H_
#define __SDC_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SDC_17XX_40XX CHIP: LPC17xx/40xx SD Card Interafce driver
* @ingroup CHIP_17XX_40XX_Drivers
* SD/MMC card Interface
* @{
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/**
* @brief SD/MMC card Interface (SDC) register block structure
*/
typedef struct {
__IO uint32_t POWER; /*!< Power Control register */
__IO uint32_t CLOCK; /*!< Clock control regsiter */
__IO uint32_t ARGUMENT; /*!< Command argument register */
__IO uint32_t COMMAND; /*!< Command register */
__I uint32_t RESPCMD; /*!< Command response register */
__I uint32_t RESPONSE[4]; /*!< Response registers */
__IO uint32_t DATATIMER; /*!< Data timer register */
__IO uint32_t DATALENGTH; /*!< Data length register */
__IO uint32_t DATACTRL; /*!< Data control register */
__I uint32_t DATACNT; /*!< Data count register */
__I uint32_t STATUS; /*!< Status register */
__O uint32_t CLEAR; /*!< Clear register */
__IO uint32_t MASK0; /*!< Mask 0 register */
uint32_t RESERVED0[2];
__I uint32_t FIFOCNT; /*!< FIFO count register */
uint32_t RESERVED1[13];
__IO uint32_t FIFO[16]; /*!< FIFO registers */
} LPC_SDC_T;
/**
* @brief SDC Power Control Register bit definitions
*/
/** SDC Power Control Register Bitmask */
#define SDC_PWR_BITMASK ((uint32_t) 0xC3)
/** SDC Power Control Bit Mask */
#define SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)
/** SDC Power Control */
#define SDC_PWR_CTRL(n) (((uint32_t) (n & 0x03)) << 0)
/** SD_CMD Output Control */
#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
/** Rod Control */
#define SDC_PWR_ROD (((uint32_t) 1) << 7)
/**
* @brief SDC Clock Control Register bit definitions
*/
/** SDC Clock Control Register Bitmask */
#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
/** SDC Clock Divider Bitmask */
#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
/** Set SDC Clock Divide value */
#define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
/**
* @brief SDC Command Register bit definitions
*/
/** SDC Command Register Bitmask */
#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
/** SDC Command Index Bitmask */
#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
/** Set SDC Command Index */
#define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
/** No response is expected */
#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
/** Short response is expected */
#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
/** Long response is expected */
#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
/** Response bit mask */
#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
/** Mark that command timer is disabled and CPSM waits for interrupt request */
#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
/** Mark that CPSM waits for CmdPend before starting sending a command*/
#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
/** Enable CPSM */
#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
/**
* @brief SDC Command Response Register bit definitions
*/
/** SDC Command Response value */
#define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
/**
* @brief SDC Data Length Register bit definitions
*/
/** SDC Data Length set */
#define SDC_DATALENGTH_LEN(n) ((uint32_t) n & 0xFFFF)
/**
* @brief SDC Data Control Register bit definitions
*/
/** SDC Data Control Register Bitmask */
#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
/** Enable Data Transfer */
#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
/** Mark that Data is transfer from card to controller */
#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
/** Mark that Data is transfer from controller to card */
#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
/** Mark that the transfer mode is Stream Data Transfer */
#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
/** Mark that the transfer mode is Block Data Transfer */
#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
/** Enable DMA */
#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
/** Set Data Block size */
#define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
/** Get Data Block size value */
#define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
/**
* @brief SDC Data Counter Register bit definitions
*/
#define SDC_DATACNT_VAL(n) ((uint32_t) n & 0xFFFF)
/**
* @brief SDC Status Register bit definitions
*/
/** Command Response received (CRC check failed) */
#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
/** Data block sent/received (CRC check failed). */
#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
/** Command response timeout.. */
#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
/** Data timeout. */
#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
/** Transmit FIFO underrun error. */
#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
/** Receive FIFO overrun error. */
#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
/** Command response received (CRC check passed). */
#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
/** Command sent (no response required).*/
#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
/** Data end (data counter is zero).*/
#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
/** Start bit not detected on all data signals in wide bus mode..*/
#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
/** Data block sent/received (CRC check passed).*/
#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
/** Command transfer in progress.*/
#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
/** Data transmit in progress.*/
#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
/** Data receive in progress.*/
#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
/** Transmit FIFO half empty.*/
#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
/** Receive FIFO half full.*/
#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
/** Transmit FIFO full.*/
#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
/** Receive FIFO full.*/
#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
/** Transmit FIFO empty.*/
#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
/** Receive FIFO empty.*/
#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
/** Data available in transmit FIFO.*/
#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
/** Data available in receive FIFO.*/
#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
/** Command Error Status */
#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
/** Data Error Status */
#define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
| SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)
/** FIFO Status*/
#define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
| SDC_STATUS_TXFIFOFULL | SDC_STATUS_RXFIFOFULL \
| SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
| SDC_STATUS_DATABLOCKEND)
/** Data Transfer Status*/
#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
/**
* @brief SDC Clear Register bit definitions
*/
/** Clear all status flag*/
#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
/** Clears CmdCrcFail flag.*/
#define SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)
/** Clears DataCrcFail flag. */
#define SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)
/** Clears CmdTimeOut flag. */
#define SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)
/** Clears DataTimeOut flag. */
#define SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)
/** Clears TxUnderrun flag. */
#define SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)
/**Clears RxOverrun flag. */
#define SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)
/** Clears CmdRespEnd flag. */
#define SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)
/** Clears CmdSent flag.*/
#define SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)
/**Clears DataEnd flag.*/
#define SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)
/** Clears StartBitErr flag.*/
#define SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)
/** Clears DataBlockEnd flag.*/
#define SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)
/**
* @brief SDC Interrupt Mask Register bit definitions
*/
/** Mask CmdCrcFail flag.*/
#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
/** Mask DataCrcFail flag. */
#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
/** Mask CmdTimeOut flag. */
#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
/** Mask DataTimeOut flag. */
#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
/** Mask TxUnderrun flag. */
#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
/** Mask RxOverrun flag. */
#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
/** Mask CmdRespEnd flag. */
#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
/** Mask CmdSent flag.*/
#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
/** Mask DataEnd flag.*/
#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
/** Mask StartBitErr flag.*/
#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
/** Mask DataBlockEnd flag.*/
#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
/** Mask CmdActive flag.*/
#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
/** Mask TxActive flag.*/
#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
/** Mask RxActive flag.*/
#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
/** Mask TxFifoHalfEmpty flag.*/
#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
/** Mask RxFifoHalfFull flag.*/
#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
/** Mask TxFifoFull flag.*/
#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
/** Mask RxFifoFull flag.*/
#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
/** Mask TxFifoEmpty flag.*/
#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
/** Mask RxFifoEmpty flag.*/
#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
/** Mask TxDataAvlbl flag.*/
#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
/** Mask RxDataAvlbl flag.*/
#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
/** CMD error interrupt mask */
#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
/** Data Transmit Error interrupt mask */
#define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
SDC_MASK0_STARTBITERR)
/** Data Receive Error interrupt mask */
#define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
SDC_MASK0_STARTBITERR)
/** TX FIFO interrupt mask*/
#define SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
/** RX FIFO interrupt mask*/
#define SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
/** Data Transfer interrupt mask*/
#define SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
/**
* @brief SDC FIFO Counter Register bit definitions
*/
#define SDC_FIFOCNT_VAL(n) ((uint32_t) n & 0x7FFF)
/* The number of bytes used to store card status*/
#define SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)
/**
* @brief SDC Card bus clock rate definitions
*/
/* Card bus clock in Card Identification Mode */
#define SDC_IDENT_CLOCK_RATE (400000) /* 400KHz */
/* Card bus clock in Data Transfer Mode */
#define SDC_TRAN_CLOCK_RATE (20000000) /* 20MHz */
/**
* @brief SDC Power Control Options
*/
typedef enum SDC_PWR_CTRL {
SDC_POWER_OFF = 0, /*!< Power-off */
SDC_POWER_UP = 2, /*!< Power-up */
SDC_POWER_ON = 3, /*!< Power-on */
} SDC_PWR_CTRL_T;
/**
* @brief SDC Clock Control Options
*/
typedef enum SDC_CLOCK_CTRL {
SDC_CLOCK_ENABLE = 8, /*!< Enable SD Card Bus Clock */
SDC_CLOCK_POWER_SAVE = 9, /*!< Disable SD_CLK output when bus is idle */
SDC_CLOCK_DIVIDER_BYPASS = 10, /*!< Enable bypass of clock divide logic */
SDC_CLOCK_WIDEBUS_MODE = 11, /*!< Enable wide bus mode (SD_DAT[3:0] is used instead of SD_DAT[0]) */
} SDC_CLOCK_CTRL_T;
/**
* @brief SDC Response type
*/
typedef enum SDC_RESPONSE {
SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP, /*!< No response */
SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, /*!< Short response */
SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP, /*!< Long response */
} SDC_RESPONSE_T;
/**
* @brief SDC Data Transfer Direction definitions
*/
typedef enum SDC_TRANSFER_DIR {
SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, /*!< Transfer from card */
SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD, /*!< Transfer to card */
} SDC_TRANSFER_DIR_T;
/**
* @brief SDC Data Transfer Mode definitions
*/
typedef enum SDC_TRANSFER_MODE {
SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, /*!< Stream transfer mode */
SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK, /*!< Block transfer mode */
} SDC_TRANSFER_MODE_T;
/**
* @brief SDC Data Block size definitions (in bytes)
*/
typedef enum SDC_BLOCK_SIZE {
SDC_BLOCK_SIZE_1 = 0, /*!< Block size - 1 byte */
SDC_BLOCK_SIZE_2, /*!< Block size - 2 bytes */
SDC_BLOCK_SIZE_4, /*!< Block size - 4 bytes */
SDC_BLOCK_SIZE_8, /*!< Block size - 8 bytes */
SDC_BLOCK_SIZE_16, /*!< Block size - 16 bytes */
SDC_BLOCK_SIZE_32, /*!< Block size - 32 bytes */
SDC_BLOCK_SIZE_64, /*!< Block size - 64 bytes */
SDC_BLOCK_SIZE_128, /*!< Block size - 128 bytes */
SDC_BLOCK_SIZE_256, /*!< Block size - 256 bytes */
SDC_BLOCK_SIZE_512, /*!< Block size - 512 bytes */
SDC_BLOCK_SIZE_1024, /*!< Block size - 1024 bytes */
SDC_BLOCK_SIZE_2048, /*!< Block size - 2048 bytes */
} SDC_BLOCK_SIZE_T;
/**
* @brief SDC Return code definitions
*/
typedef enum CHIP_SDC_RET_CODE {
SDC_RET_OK = 0,
SDC_RET_CMD_FAILED = -1,
SDC_RET_BAD_PARAMETERS = -2,
SDC_RET_BUS_NOT_IDLE = -3,
SDC_RET_TIMEOUT = -4,
SDC_RET_ERR_STATE = -5,
SDC_RET_NOT_READY = -6,
SDC_RET_FAILED = -7,
} CHIP_SDC_RET_CODE_T;
/**
* @brief SDC Command Response structure
*/
typedef struct {
uint8_t CmdIndex; /*!< Command Index of the command response received */
uint32_t Data[SDC_CARDSTATUS_BYTENUM]; /* Card Status which can be stored in 1 or 4 bytes */
} SDC_RESP_T;
/**
* @brief SDC Data Transfer Setup structure
*/
typedef struct {
uint16_t BlockNum; /*!< The number of block which will be transfered */
SDC_BLOCK_SIZE_T BlockSize; /*!< Data Block Length */
SDC_TRANSFER_DIR_T Dir; /*!< Direction */
SDC_TRANSFER_MODE_T Mode; /*!< Mode */
bool DMAUsed; /*!< true: DMA used */
uint32_t Timeout; /*!< Data Transfer timeout periods (in Card Bus Clock)*/
} SDC_DATA_TRANSFER_T;
/**
* @brief Set the power state of SDC peripheral
* @param pSDC : Pointer to SDC register block
* @param pwrMode : Power mode
* @param flag : Output control flag
* @return Nothing
* @note When the external power supply is switched on, the software first enters the power-up
* state, and waits until the supply output is stable before moving to the power-on state.
* During the power-up state, SD_PWR is set HIGH. The card bus outlets are disabled
* during both states.
* flag is or-ed bit value of SDC_PWR_OPENDRAIN and SDC_PWR_ROD
*/
void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag);
/**
* @brief Set clock divider value for SDC peripheral
* @param pSDC : Pointer to SDC register block
* @param div : clock divider
* @return Nothing
* @note While the SD card interface is in identification mode, the SD_CLK frequency must be less
* than 400 kHz. The clock frequency can be changed to the maximum card bus frequency
* when relative card addresses are assigned to all cards.
* SD_CLK frequency = MCLK / [2x(ClkDiv+1)].
*/
void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div);
/**
* @brief Set or Reset clock control of SDC peripheral
* @param pSDC : Pointer to SDC register block
* @param ctrlType : Clock Control type
* @param NewState : New State to set
* @return Nothing
*/
void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
FunctionalState NewState);
/**
* @brief Set the clock frequency for SDC peripheral
* @param pSDC : Pointer to SDC peripheral base address
* @param freq : Expected clock frequency
* @return None
*/
void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq);
/**
* @brief Set SDC Command Information
* @param pSDC : Pointer to SDC register block
* @param Cmd : Command value
* @param Arg : Argument for the command
* @return Nothing
*/
void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg);
/**
* @brief Reset SDC Command Information
* @param pSDC : Pointer to SDC register block
* @return Nothing
*/
void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC);
/**
* @brief Get SDC Response
* @param pSDC : Pointer to SDC register block
* @param pResp : Pointer to buffer storing response data
* @return Nothing
*/
void Chip_SDC_GetResp(LPC_SDC_T *pSDC, SDC_RESP_T *pResp);
/**
* @brief Set SDC Data Timeout Period
* @param pSDC : Pointer to SDC register block
* @param timeout : Data timeout value in card bus clock periods
* @return Nothing
*/
STATIC INLINE void Chip_SDC_SetDataTimer(LPC_SDC_T *pSDC, uint32_t timeout)
{
pSDC->DATATIMER = timeout;
}
/**
* @brief Set SDC Data Transfer Information
* @param pSDC : Pointer to SDC register block
* @param pTransfer : Pointer to Data Transfer structure
* @return Nothing
*/
void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer);
/**
* @brief Write Data to FIFO
* @param pSDC : Pointer to SDC register block
* @param pSrc : Pointer to data buffer
* @param bFirstHalf : true (write to the first half of FIFO) false (write to the second half of FIFO)
* @return Nothing
*/
void Chip_SDC_WriteFIFO(LPC_SDC_T *pSDC, uint32_t *pSrc, bool bFirstHalf);
/**
* @brief Write Data to FIFO
* @param pSDC : Pointer to SDC register block
* @param pDst : The buffer hold the data read
* @param bFirstHalf : true (read the first half of FIFO) false (read the second half of FIFO)
* @return Nothing
*/
void Chip_SDC_ReadFIFO(LPC_SDC_T *pSDC, uint32_t *pDst, bool bFirstHalf);
/**
* @brief Get status of SDC Peripheral
* @param pSDC : Pointer to SDC register block
* @return Status (Or-ed bit value of SDC_STATUS_*)
*/
STATIC INLINE uint32_t Chip_SDC_GetStatus(LPC_SDC_T *pSDC)
{
return pSDC->STATUS;
}
/**
* @brief Clear status of SDC Peripheral
* @param pSDC : Pointer to SDC register block
* @param flag : Status flag(s) to be cleared (Or-ed bit value of SDC_CLEAR_*)
* @return None
*/
STATIC INLINE void Chip_SDC_ClearStatus(LPC_SDC_T *pSDC, uint32_t flag)
{
pSDC->CLEAR = flag;
}
/**
* @brief Set interrupt mask for SDC Peripheral
* @param pSDC : Pointer to SDC register block
* @param mask : Interrupt mask (Or-ed bit value of SDC_MASK0_*)
* @return None
*/
STATIC INLINE void Chip_SDC_SetIntMask(LPC_SDC_T *pSDC, uint32_t mask)
{
pSDC->MASK0 = mask;
}
/**
* @brief Initialize the SDC card controller
* @param pSDC : Pointer to SDC register block
* @return None
*/
void Chip_SDC_Init(LPC_SDC_T *pSDC);
/**
* @brief Deinitialise SDC peripheral
* @param pSDC : Pointer to SDC peripheral base address
* @return None
*/
void Chip_SDC_DeInit(LPC_SDC_T *pSDC);
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SDC_17XX_40XX_H_ */

202
hw/mcu/nxp/lpc_chip_175x_6x/inc/sdmmc_17xx_40xx.h Normal file
View File

@ -0,0 +1,202 @@
/*
* @brief LPC17xx/40xx SDMMC Card Interface driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SDMMC_17XX_40XX_H_
#define __SDMMC_17XX_40XX_H_
#include "sdmmc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SDMMC_17XX_40XX CHIP: LPC17xx/40xx SDMMC card driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/*
* SD/MMC Response type definitions
*/
#define CMDRESP_NONE_TYPE (SDC_COMMAND_NO_RSP)
#define CMDRESP_R1_TYPE (SDC_COMMAND_SHORT_RSP)
#define CMDRESP_R1b_TYPE (SDC_COMMAND_SHORT_RSP)
#define CMDRESP_R2_TYPE (SDC_COMMAND_LONG_RSP)
#define CMDRESP_R3_TYPE (SDC_COMMAND_SHORT_RSP)
#define CMDRESP_R6_TYPE (SDC_COMMAND_SHORT_RSP)
#define CMDRESP_R7_TYPE (SDC_COMMAND_SHORT_RSP)
#ifdef SDC_DMA_ENABLE
/**
* @brief SDC Event structure
*/
typedef struct {
uint8_t DmaChannel; /*!< DMA Channel used for transfer data */
} SDMMC_EVENT_T;
#else
/**
* @brief SDC Event structure
*/
typedef struct {
void *Buffer; /*!< Pointer to data buffer */
uint32_t Size; /*!< Transfer size */
uint32_t Index; /*!< Current transfer index */
uint8_t Dir; /*!< Transfer direction 0: transmit, 1: receive */
} SDMMC_EVENT_T;
#endif /* SDC_DMA_ENABLE */
/*
* SD command values (Command Index, Response)
*/
#define SD_GO_IDLE_STATE (SDC_COMMAND_INDEX(MMC_GO_IDLE_STATE) | CMDRESP_NONE_TYPE | SDC_COMMAND_INTERRUPT) /*!< GO_IDLE_STATE(MMC) or RESET(SD) */
#define SD_CMD1_SEND_OP_COND (SDC_COMMAND_INDEX(MMC_SEND_OP_COND) | CMDRESP_R3_TYPE | 0) /*!< SEND_OP_COND(MMC) or ACMD41(SD) */
#define SD_CMD2_ALL_SEND_CID (SDC_COMMAND_INDEX(MMC_ALL_SEND_CID) | CMDRESP_R2_TYPE | 0) /*!< ALL_SEND_CID */
#define SD_CMD3_SET_RELATIVE_ADDR (SDC_COMMAND_INDEX(MMC_SET_RELATIVE_ADDR) | CMDRESP_R1_TYPE | 0) /*!< SET_RELATE_ADDR */
#define SD_CMD3_SEND_RELATIVE_ADDR (SDC_COMMAND_INDEX(SD_SEND_RELATIVE_ADDR) | CMDRESP_R6_TYPE | 0) /*!< SEND_RELATE_ADDR */
#define SD_CMD7_SELECT_CARD (SDC_COMMAND_INDEX(MMC_SELECT_CARD) | CMDRESP_R1b_TYPE | 0) /*!< SELECT/DESELECT_CARD */
#define SD_CMD8_SEND_IF_COND (SDC_COMMAND_INDEX(SD_CMD8) | CMDRESP_R7_TYPE | 0) /*!< SEND_IF_COND */
#define SD_CMD9_SEND_CSD (SDC_COMMAND_INDEX(MMC_SEND_CSD) | CMDRESP_R2_TYPE | 0) /*!< SEND_CSD */
#define SD_CMD12_STOP_TRANSMISSION (SDC_COMMAND_INDEX(MMC_STOP_TRANSMISSION) | CMDRESP_R1_TYPE | 0) /*!< STOP_TRANSMISSION */
#define SD_CMD13_SEND_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) | CMDRESP_R1_TYPE | 0) /*!< SEND_STATUS */
/* Block-Oriented Read Commands (class 2) */
#define SD_CMD16_SET_BLOCKLEN (SDC_COMMAND_INDEX(MMC_SET_BLOCKLEN) | CMDRESP_R1_TYPE | 0) /*!< SET_BLOCK_LEN */
#define SD_CMD17_READ_SINGLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_SINGLE_BLOCK) | CMDRESP_R1_TYPE | 0) /*!< READ_SINGLE_BLOCK */
#define SD_CMD18_READ_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_MULTIPLE_BLOCK) | CMDRESP_R1_TYPE | 0) /*!< READ_MULTIPLE_BLOCK */
/* Block-Oriented Write Commands (class 4) */
#define SD_CMD24_WRITE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_BLOCK) | CMDRESP_R1_TYPE | 0) /*!< WRITE_BLOCK */
#define SD_CMD25_WRITE_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_MULTIPLE_BLOCK) | CMDRESP_R1_TYPE | 0) /*!< WRITE_MULTIPLE_BLOCK */
/* Erase Commands (class 5) */
#define SD_CMD32_ERASE_WR_BLK_START (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_START) | CMDRESP_R1_TYPE | 0) /*!< ERASE_WR_BLK_START */
#define SD_CMD33_ERASE_WR_BLK_END (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_END) | CMDRESP_R1_TYPE | 0) /*!< ERASE_WR_BLK_END */
#define SD_CMD38_ERASE (SDC_COMMAND_INDEX(SD_ERASE) | CMDRESP_R1b_TYPE | 0) /*!< ERASE */
/* Application-Specific Commands (class 8) */
#define SD_CMD55_APP_CMD (SDC_COMMAND_INDEX(MMC_APP_CMD) | CMDRESP_R1_TYPE | 0) /*!< APP_CMD */
#define SD_ACMD6_SET_BUS_WIDTH (SDC_COMMAND_INDEX(SD_APP_SET_BUS_WIDTH) | CMDRESP_R1_TYPE | 0) /*!< SET_BUS_WIDTH */
#define SD_ACMD13_SEND_SD_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) | CMDRESP_R1_TYPE | 0) /*!< SEND_SD_STATUS */
#define SD_ACMD41_SD_SEND_OP_COND (SDC_COMMAND_INDEX(SD_APP_OP_COND) | CMDRESP_R3_TYPE | 0) /*!< SD_SEND_OP_COND */
/**
* @brief SD card interrupt service routine
* @param pSDC : Pointer to SDC peripheral base address
* @param txBuf : Pointer to TX Buffer (If it is NULL, dont send data to card)
* @param txCnt : Pointer to buffer storing the current transmit index
* @param rxBuf : Pointer to RX Buffer (If it is NULL, dont read data from card)
* @param rxCnt : Pointer to buffer storing the current receive index
* @return Positive value: Data transfer
* Negative value: Error in data transfer
* Zero: Data transfer completed
*/
int32_t Chip_SDMMC_IRQHandler (LPC_SDC_T *pSDC, uint8_t *txBuf, uint32_t *txCnt,
uint8_t *rxBuf, uint32_t *rxCnt);
/**
* @brief Function to enumerate the SD/MMC/SDHC/MMC+ cards
* @param pSDC : Pointer to SDC peripheral base address
* @param pCardInfo : Pointer to pre-allocated card info structure
* @return 1 if a card is acquired, otherwise 0
*/
int32_t Chip_SDMMC_Acquire(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
/**
* @brief Get card's current state (idle, transfer, program, etc.)
* @param pSDC : Pointer to SDC peripheral base address
* @param pCardInfo : Pointer to pre-allocated card info structure
* @return Current SD card state
*/
SDMMC_STATE_T Chip_SDMMC_GetCardState(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
/**
* @brief Get 'card status' of SD Memory card
* @param pSDC : Pointer to SDC peripheral base address
* @param pCardInfo : Pointer to pre-allocated card info structure
* @return Current SD card status
*/
uint32_t Chip_SDMMC_GetCardStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
/**
* @brief Get 'sd status' of SD Memory card
* @param pSDC : Pointer to SDC peripheral base address
* @param pCardInfo : Pointer to pre-allocated card info structure
* @param pStatus : Pointer to buffer storing status (it must be 64-byte-length)
* @return Number of bytes read
*/
int32_t Chip_SDMMC_GetSDStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo, uint32_t *pStatus);
/**
* @brief Performs the read of data from the SD/MMC card
* @param pSDC : The base of SDC peripheral on the chip
* @param pCardInfo : Pointer to Card information structure
* @param buffer : Pointer to data buffer to copy to
* @param startblock : Start block number
* @param blockNum : Number of block to read
* @return Bytes read, or 0 on error
*/
int32_t Chip_SDMMC_ReadBlocks(LPC_SDC_T *pSDC,
SDMMC_CARD_T *pCardInfo,
void *buffer,
int32_t startblock,
int32_t blockNum);
/**
* @brief Performs write of data to the SD/MMC card
* @param pSDC : The base of SDC peripheral on the chip
* @param pCardInfo : Pointer to Card information structure
* @param buffer : Pointer to data buffer to copy to
* @param startblock : Start block number
* @param blockNum : Number of block to write
* @return Number of bytes actually written, or 0 on error
*/
int32_t Chip_SDMMC_WriteBlocks(LPC_SDC_T *pSDC,
SDMMC_CARD_T *pCardInfo,
void *buffer,
int32_t startblock,
int32_t blockNum);
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SDC_17XX_40XX_H_ */

416
hw/mcu/nxp/lpc_chip_175x_6x/inc/spi_17xx_40xx.h Normal file
View File

@ -0,0 +1,416 @@
/*
* @brief LPC17xx/40xx SPI driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SPI_17XX_40XX_H_
#define __SPI_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SPI_17XX_40XX CHIP: LPC17xx/40xx SPI driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC175X_6X)
/**
* @brief SPI register block structure
*/
typedef struct { /*!< SPI Structure */
__IO uint32_t CR; /*!< SPI Control Register. This register controls the operation of the SPI. */
__I uint32_t SR; /*!< SPI Status Register. This register shows the status of the SPI. */
__IO uint32_t DR; /*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
__IO uint32_t CCR; /*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
__I uint32_t RESERVED0[3];
__IO uint32_t INT; /*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
} LPC_SPI_T;
/*
* Macro defines for SPI Control register
*/
/* SPI CFG Register BitMask */
#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
/** Enable of controlling the number of bits per transfer */
#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
/** Mask of field of bit controlling */
#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
/** Set the number of bits per a transfer */
#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
/** SPI Clock Phase Select*/
#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/
/** SPI Clock Polarity Select*/
#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
/** SPI Slave Mode Select */
#define SPI_CR_SLAVE_EN ((uint32_t) 0)
/** SPI Master Mode Select */
#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
/** SPI MSB First mode enable */
#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
/** SPI LSB First mode enable */
#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/
/** SPI interrupt enable */
#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
/*
* Macro defines for SPI Status register
*/
/** SPI STAT Register BitMask */
#define SPI_SR_BITMASK ((uint32_t) 0xF8)
/** Slave abort Flag */
#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
/* Mode fault Flag */
#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
/** Read overrun flag*/
#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
/** Write collision flag. */
#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
/** SPI transfer complete flag. */
#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
/** SPI error flag */
#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
/*
* Macro defines for SPI Test Control Register register
*/
/*Enable SPI Test Mode */
#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
/*
* Macro defines for SPI Interrupt register
*/
/** SPI interrupt flag */
#define SPI_INT_SPIF ((uint32_t) (1 << 0))
/**
* Macro defines for SPI Data register
*/
/** Receiver Data */
#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
/** @brief SPI Mode*/
typedef enum {
SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
} SPI_MODE_T;
/** @brief SPI Clock Mode*/
typedef enum {
SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */
SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 1 */
SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 0 */
SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */
SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,/**< alias */
SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,/**< alias */
SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,/**< alias */
SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,/**< alias */
} SPI_CLOCK_MODE_T;
/** @brief SPI Data Order Mode*/
typedef enum {
SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
} SPI_DATA_ORDER_T;
/*
* @brief Number of bits per frame
*/
typedef enum {
SPI_BITS_8 = SPI_CR_BITS(8), /**< 8 bits/frame */
SPI_BITS_9 = SPI_CR_BITS(9), /**< 9 bits/frame */
SPI_BITS_10 = SPI_CR_BITS(10), /**< 10 bits/frame */
SPI_BITS_11 = SPI_CR_BITS(11), /**< 11 bits/frame */
SPI_BITS_12 = SPI_CR_BITS(12), /**< 12 bits/frame */
SPI_BITS_13 = SPI_CR_BITS(13), /**< 13 bits/frame */
SPI_BITS_14 = SPI_CR_BITS(14), /**< 14 bits/frame */
SPI_BITS_15 = SPI_CR_BITS(15), /**< 15 bits/frame */
SPI_BITS_16 = SPI_CR_BITS(16), /**< 16 bits/frame */
} SPI_BITS_T;
/** SPI callback function type*/
typedef void (*SPI_CALLBACK_T)(void);
/*
* @brief SPI config format
*/
typedef struct {
SPI_BITS_T bits; /*!< bits/frame */
SPI_CLOCK_MODE_T clockMode; /*!< Format config: clock phase/polarity */
SPI_DATA_ORDER_T dataOrder; /*!< Data order (MSB first/LSB first) */
} SPI_CONFIG_FORMAT_T;
/*
* @brief SPI data setup structure
*/
typedef struct {
uint8_t *pTxData; /*!< Pointer to transmit data */
uint8_t *pRxData; /*!< Pointer to receive data */
uint32_t cnt; /*!< Transfer counter */
uint32_t length; /*!< Length of transfer data */
SPI_CALLBACK_T fnBefFrame; /*!< Function to call before sending frame */
SPI_CALLBACK_T fnAftFrame; /*!< Function to call after sending frame */
SPI_CALLBACK_T fnBefTransfer; /*!< Function to call before starting a transfer */
SPI_CALLBACK_T fnAftTransfer; /*!< Function to call after a transfer complete */
} SPI_DATA_SETUP_T;
/**
* @brief Get the current status of SPI controller
* @return SPI controller status (Or-ed value of SPI_SR_*)
*/
STATIC INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI)
{
return pSPI->SR;
}
/**
* @brief Send SPI 16-bit data
* @param pSPI : The base of SPI peripheral on the chip
* @param data : Transmit Data
* @return Nothing
*/
STATIC INLINE void Chip_SPI_SendFrame(LPC_SPI_T *pSPI, uint16_t data)
{
pSPI->DR = SPI_DR_DATA(data);
}
/**
* @brief Get received SPI data
* @param pSPI : The base of SPI peripheral on the chip
* @return receive data
*/
STATIC INLINE uint16_t Chip_SPI_ReceiveFrame(LPC_SPI_T *pSPI)
{
return SPI_DR_DATA(pSPI->DR);
}
/**
* @brief Set up output clocks per bit for SPI bus
* @param pSPI : The base of SPI peripheral on the chip
* @param counter : the number of SPI peripheral clock cycles that make up an SPI clock
* @return Nothing
* @note The counter must be an even number greater than or equal to 8. <br>
* The SPI SCK rate = PCLK_SPI / counter.
*/
STATIC INLINE void Chip_SPI_SetClockCounter(LPC_SPI_T *pSPI, uint32_t counter)
{
pSPI->CCR = counter;
}
/**
* @brief Set up the SPI frame format
* @param pSPI : The base SPI peripheral on the chip
* @param format : Pointer to Frame format structure
* @return Nothing
*/
STATIC INLINE void Chip_SPI_SetFormat(LPC_SPI_T *pSPI, SPI_CONFIG_FORMAT_T *format)
{
pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | format->bits | format->clockMode | format->dataOrder;
}
/**
* @brief Get the number of bits transferred in each frame
* @param pSPI : The base of SPI peripheral on the chip
* @return the number of bits transferred in each frame
*/
STATIC INLINE SPI_BITS_T Chip_SPI_GetDataSize(LPC_SPI_T *pSPI)
{
return (pSPI->CR & SPI_CR_BIT_EN) ? ((SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;
}
/**
* @brief Get the current CPHA & CPOL setting
* @param pSPI : The base of SPI peripheral on the chip
* @return CPHA & CPOL setting
*/
STATIC INLINE SPI_CLOCK_MODE_T Chip_SPI_GetClockMode(LPC_SPI_T *pSPI)
{
return (SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));
}
/**
* @brief Set the SPI working as master or slave mode
* @param pSPI : The base of SPI peripheral on the chip
* @return Operating mode
*/
STATIC INLINE SPI_MODE_T Chip_SPI_GetMode(LPC_SPI_T *pSPI)
{
return (SPI_MODE_T) (pSPI->CR & (1 << 5));
}
/**
* @brief Set the SPI operating modes, master or slave
* @param pSPI : The base SPI peripheral on the chip
* @param mode : master mode/slave mode
* @return Nothing
*/
STATIC INLINE void Chip_SPI_SetMode(LPC_SPI_T *pSPI, SPI_MODE_T mode)
{
pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;
}
/**
* @brief Set the clock frequency for SPI interface
* @param pSPI : The base SPI peripheral on the chip
* @param bitRate : The SPI bit rate
* @return Nothing
*/
void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate);
/**
* @brief Enable SPI interrupt
* @param pSPI : The base SPI peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SPI_Int_Enable(LPC_SPI_T *pSPI)
{
pSPI->CR |= SPI_CR_INT_EN;
}
/**
* @brief Disable SPI interrupt
* @param pSPI : The base SPI peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SPI_Int_Disable(LPC_SPI_T *pSPI)
{
pSPI->CR &= ~SPI_CR_INT_EN;
}
/**
* @brief Get the interrupt status
* @param pSPI : The base of SPI peripheral on the chip
* @return SPI interrupt Status (Or-ed bit value of SPI_INT_*)
*/
STATIC INLINE uint32_t Chip_SPI_Int_GetStatus(LPC_SPI_T *pSPI)
{
return pSPI->INT;
}
/**
* @brief Clear the interrupt status
* @param pSPI : The base of SPI peripheral on the chip
* @param mask : SPI interrupt mask (Or-ed bit value of SPI_INT_*)
* @return Nothing
*/
STATIC INLINE void Chip_SPI_Int_ClearStatus(LPC_SPI_T *pSPI, uint32_t mask)
{
pSPI->INT = mask;
}
/**
* @brief Initialize the SPI
* @param pSPI : The base SPI peripheral on the chip
* @return Nothing
*/
void Chip_SPI_Init(LPC_SPI_T *pSPI);
/**
* @brief Deinitialise the SPI
* @param pSPI : The base of SPI peripheral on the chip
* @return Nothing
* @note The SPI controller is disabled
*/
void Chip_SPI_DeInit(LPC_SPI_T *pSPI);
/**
* @brief Clean all data in RX FIFO of SPI
* @param pSPI : The base SPI peripheral on the chip
* @return Nothing
*/
void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI);
/**
* @brief SPI Interrupt Read/Write with 8-bit frame width
* @param pSPI : The base SPI peripheral on the chip
* @param xf_setup : Pointer to a SPI_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
/**
* @brief SPI Interrupt Read/Write with 16-bit frame width
* @param pSPI : The base SPI peripheral on the chip
* @param xf_setup : Pointer to a SPI_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
/**
* @brief SPI Polling Read/Write in blocking mode
* @param pSPI : The base SPI peripheral on the chip
* @param pXfSetup : Pointer to a SPI_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. It starts with writing phase and after that,
* a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
* through xf_setup param.
*/
uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup);
/**
* @brief SPI Polling Write in blocking mode
* @param pSPI : The base SPI peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : Buffer length
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a writing operation will send
* the needed data. After that, a dummy reading operation is generated to clear data buffer
*/
uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief SPI Polling Read in blocking mode
* @param pSPI : The base SPI peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : The length of buffer
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a dummy writing operation is generated
* to clear data buffer. After that, a reading operation will receive the needed data
*/
uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len);
#endif /* defined(CHIP_LPC175X_6X) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SPI_17XX_40XX_H_ */

79
hw/mcu/nxp/lpc_chip_175x_6x/inc/spifi_17xx_40xx.h Normal file
View File

@ -0,0 +1,79 @@
/*
* @brief LPC17xx/40xx SPIFI driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SPIFI_17XX_40XX_H_
#define __SPIFI_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SPIFI_17XX_40XX CHIP: LPC17xx/40xx SPIFI Driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if defined(CHIP_LPC40XX)
/** SPIFI memory base address */
#define SPIFLASH_BASE_ADDRESS (0x28000000)
/** SPIFI API ROM address */
#define SPIFI_ROM_PTR (0x1FFF1954)
/**
* @brief Initialize the SPIFI
* @return None
*/
STATIC INLINE void Chip_SPIFI_Init(void)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SPIFI);
}
/**
* @brief Shutdown the SPIFI
* @return None
*/
STATIC INLINE void Chip_SPIFI_DeInit(void)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SPIFI);
}
#endif /* defined(CHIP_LPC40XX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SPIFI_17XX_40XX_H_ */

598
hw/mcu/nxp/lpc_chip_175x_6x/inc/ssp_17xx_40xx.h Normal file
View File

@ -0,0 +1,598 @@
/*
* @brief LPC17xx/40xx SSP driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SSP_17XX_40XX_H_
#define __SSP_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SSP_17XX_40XX CHIP: LPC17xx/40xx SSP driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief SSP register block structure
*/
typedef struct { /*!< SSPn Structure */
__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t CPSR; /*!< Clock Prescale Register */
__IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< Raw Interrupt Status Register */
__I uint32_t MIS; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
__IO uint32_t DMACR; /*!< SSPn DMA control register */
} LPC_SSP_T;
/**
* Macro defines for CR0 register
*/
/** SSP data size select, must be 4 bits to 16 bits */
#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
/** SSP control 0 Motorola SPI mode */
#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
/** SSP control 0 TI synchronous serial mode */
#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
/** SSP control 0 National Micro-wire mode */
#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
bus clock high between frames, (0) = low */
#define SSP_CR0_CPOL_LO ((uint32_t) (0))
#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
on the second clock transition of the frame, (0) = first */
#define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
/**
* Macro defines for CR1 register
*/
/** SSP control 1 loopback mode enable bit */
#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
/** SSP control 1 enable bit */
#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
/** SSP control 1 slave enable */
#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
#define SSP_CR1_MASTER_EN ((uint32_t) (0))
/** SSP control 1 slave out disable bit, disables transmit line in slave
mode */
#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
/** SSP CR1 bit mask */
#define SSP_CR1_BITMASK ((uint32_t) (0x0F))
/** SSP CPSR bit mask */
#define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
/**
* Macro defines for DR register
*/
/** SSP data bit mask */
#define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
/**
* Macro defines for SR register
*/
/** SSP SR bit mask */
#define SSP_SR_BITMASK ((uint32_t) (0x1F))
/** ICR bit mask */
#define SSP_ICR_BITMASK ((uint32_t) (0x03))
/**
* @brief SSP Type of Status
*/
typedef enum _SSP_STATUS {
SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
} SSP_STATUS_T;
/**
* @brief SSP Type of Interrupt Mask
*/
typedef enum _SSP_INTMASK {
SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
} SSP_INTMASK_T;
/**
* @brief SSP Type of Mask Interrupt Status
*/
typedef enum _SSP_MASKINTSTATUS {
SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */
SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_MASKINTSTATUS_T;
/**
* @brief SSP Type of Raw Interrupt Status
*/
typedef enum _SSP_RAWINTSTATUS {
SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */
SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_RAWINTSTATUS_T;
typedef enum _SSP_INTCLEAR {
SSP_RORIC = 0x0,
SSP_RTIC = 0x1,
SSP_INT_CLEAR_BITMASK = 0x3,
} SSP_INTCLEAR_T;
typedef enum _SSP_DMA {
SSP_DMA_RX = (1u), /**< DMA RX Enable */
SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */
SSP_DMA_BITMASK = ((uint32_t)(0x3)),
} SSP_DMA_T;
/*
* @brief SSP clock format
*/
typedef enum CHIP_SSP_CLOCK_FORMAT {
SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */
SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */
SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */
SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */
SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
} CHIP_SSP_CLOCK_MODE_T;
/*
* @brief SSP frame format
*/
typedef enum CHIP_SSP_FRAME_FORMAT {
SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */
CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), /**< Frame format: TI SSI */
SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */
} CHIP_SSP_FRAME_FORMAT_T;
/*
* @brief Number of bits per frame
*/
typedef enum CHIP_SSP_BITS {
SSP_BITS_4 = (3u << 0), /*!< 4 bits/frame */
SSP_BITS_5 = (4u << 0), /*!< 5 bits/frame */
SSP_BITS_6 = (5u << 0), /*!< 6 bits/frame */
SSP_BITS_7 = (6u << 0), /*!< 7 bits/frame */
SSP_BITS_8 = (7u << 0), /*!< 8 bits/frame */
SSP_BITS_9 = (8u << 0), /*!< 9 bits/frame */
SSP_BITS_10 = (9u << 0), /*!< 10 bits/frame */
SSP_BITS_11 = (10u << 0), /*!< 11 bits/frame */
SSP_BITS_12 = (11u << 0), /*!< 12 bits/frame */
SSP_BITS_13 = (12u << 0), /*!< 13 bits/frame */
SSP_BITS_14 = (13u << 0), /*!< 14 bits/frame */
SSP_BITS_15 = (14u << 0), /*!< 15 bits/frame */
SSP_BITS_16 = (15u << 0), /*!< 16 bits/frame */
} CHIP_SSP_BITS_T;
/*
* @brief SSP config format
*/
typedef struct SSP_ConfigFormat {
CHIP_SSP_BITS_T bits; /*!< Format config: bits/frame */
CHIP_SSP_CLOCK_MODE_T clockMode; /*!< Format config: clock phase/polarity */
CHIP_SSP_FRAME_FORMAT_T frameFormat; /*!< Format config: SPI/TI/Microwire */
} SSP_ConfigFormat;
/**
* @brief Enable SSP operation
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
{
pSSP->CR1 |= SSP_CR1_SSP_EN;
}
/**
* @brief Disable SSP operation
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
{
pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
/**
* @brief Enable loopback mode
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note Serial input is taken from the serial output (MOSI or MISO) rather
* than the serial input pin
*/
STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
{
pSSP->CR1 |= SSP_CR1_LBM_EN;
}
/**
* @brief Disable loopback mode
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note Serial input is taken from the serial output (MOSI or MISO) rather
* than the serial input pin
*/
STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
{
pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}
/**
* @brief Get the current status of SSP controller
* @param pSSP : The base of SSP peripheral on the chip
* @param Stat : Type of status, should be :
* - SSP_STAT_TFE
* - SSP_STAT_TNF
* - SSP_STAT_RNE
* - SSP_STAT_RFF
* - SSP_STAT_BSY
* @return SSP controller status, SET or RESET
*/
STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
{
return (pSSP->SR & Stat) ? SET : RESET;
}
/**
* @brief Get the masked interrupt status
* @param pSSP : The base of SSP peripheral on the chip
* @return SSP Masked Interrupt Status Register value
* @note The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
*/
STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
{
return pSSP->MIS;
}
/**
* @brief Get the raw interrupt status
* @param pSSP : The base of SSP peripheral on the chip
* @param RawInt : Interrupt condition to be get status, shoud be :
* - SSP_RORRIS
* - SSP_RTRIS
* - SSP_RXRIS
* - SSP_TXRIS
* @return Raw interrupt status corresponding to interrupt condition , SET or RESET
* @note Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
*/
STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
{
return (pSSP->RIS & RawInt) ? SET : RESET;
}
/**
* @brief Get the number of bits transferred in each frame
* @param pSSP : The base of SSP peripheral on the chip
* @return the number of bits transferred in each frame minus one
* @note The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
*/
STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
{
return SSP_CR0_DSS(pSSP->CR0);
}
/**
* @brief Clear the corresponding interrupt condition(s) in the SSP controller
* @param pSSP : The base of SSP peripheral on the chip
* @param IntClear: Type of cleared interrupt, should be :
* - SSP_RORIC
* - SSP_RTIC
* @return Nothing
* @note Software can clear one or more interrupt condition(s) in the SSP controller
*/
STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
{
pSSP->ICR = IntClear;
}
/**
* @brief Enable interrupt for the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
{
pSSP->IMSC |= SSP_TXIM;
}
/**
* @brief Disable interrupt for the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
{
pSSP->IMSC &= (~SSP_TXIM);
}
/**
* @brief Get received SSP data
* @param pSSP : The base of SSP peripheral on the chip
* @return SSP 16-bit data received
*/
STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
{
return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
}
/**
* @brief Send SSP 16-bit data
* @param pSSP : The base of SSP peripheral on the chip
* @param tx_data : SSP 16-bit data to be transmited
* @return Nothing
*/
STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
{
pSSP->DR = SSP_DR_BITMASK(tx_data);
}
/**
* @brief Set up output clocks per bit for SSP bus
* @param pSSP : The base of SSP peripheral on the chip
* @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one
* @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK
* @return Nothing
* @note The bit frequency is PCLK / (prescale x[clk_rate+1])
*/
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
/**
* @brief Set up the SSP frame format
* @param pSSP : The base of SSP peripheral on the chip
* @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
* @param frameFormat : Frame format, should be :
* - SSP_FRAMEFORMAT_SPI
* - SSP_FRAME_FORMAT_TI
* - SSP_FRAMEFORMAT_MICROWIRE
* @param clockMode : Select Clock polarity and Clock phase, should be :
* - SSP_CLOCK_CPHA0_CPOL0
* - SSP_CLOCK_CPHA0_CPOL1
* - SSP_CLOCK_CPHA1_CPOL0
* - SSP_CLOCK_CPHA1_CPOL1
* @return Nothing
* @note Note: The clockFormat is only used in SPI mode
*/
STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
{
pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
}
/**
* @brief Set the SSP working as master or slave mode
* @param pSSP : The base of SSP peripheral on the chip
* @param mode : Operating mode, should be
* - SSP_MODE_MASTER
* - SSP_MODE_SLAVE
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
{
pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
}
/**
* @brief Enable DMA for SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)
{
pSSP->DMACR |= SSP_DMA_BITMASK;
}
/**
* @brief Disable DMA for SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)
{
pSSP->DMACR &= ~SSP_DMA_BITMASK;
}
/*
* @brief SSP mode
*/
typedef enum CHIP_SSP_MODE {
SSP_MODE_MASTER = (0 << 2), /**< Master mode */
SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */
} CHIP_SSP_MODE_T;
/*
* @brief SPI address
*/
typedef struct {
uint8_t port; /*!< Port Number */
uint8_t pin; /*!< Pin number */
} SPI_Address_t;
/*
* @brief SSP data setup structure
*/
typedef struct {
void *tx_data; /*!< Pointer to transmit data */
uint32_t tx_cnt; /*!< Transmit counter */
void *rx_data; /*!< Pointer to transmit data */
uint32_t rx_cnt; /*!< Receive counter */
uint32_t length; /*!< Length of transfer data */
} Chip_SSP_DATA_SETUP_T;
/** SSP configuration parameter defines */
/** Clock phase control bit */
#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
/** Clock polarity control bit */
/* There's no bug here!!!
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
* That means the active clock is in HI state.
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
* high between frames. That means the active clock is in LO state.
*/
#define SSP_CPOL_HI SSP_CR0_CPOL_LO
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
/** SSP master mode enable */
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE SSP_CR1_MASTER_EN
/**
* @brief Clean all data in RX FIFO of SSP
* @param pSSP : The base SSP peripheral on the chip
* @return Nothing
*/
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
/**
* @brief SSP Interrupt Read/Write with 8-bit frame width
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Interrupt Read/Write with 16-bit frame width
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Polling Read/Write in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. It starts with writing phase and after that,
* a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
* through xf_setup param.
*/
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Polling Write in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : Buffer length
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a writing operation will send
* the needed data. After that, a dummy reading operation is generated to clear data buffer
*/
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief SSP Polling Read in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : The length of buffer
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a dummy writing operation is generated
* to clear data buffer. After that, a reading operation will receive the needed data
*/
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief Initialize the SSP
* @param pSSP : The base SSP peripheral on the chip
* @return Nothing
*/
void Chip_SSP_Init(LPC_SSP_T *pSSP);
/**
* @brief Deinitialise the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note The SSP controller is disabled
*/
void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
/**
* @brief Set the SSP operating modes, master or slave
* @param pSSP : The base SSP peripheral on the chip
* @param master : 1 to set master, 0 to set slave
* @return Nothing
*/
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
/**
* @brief Set the clock frequency for SSP interface
* @param pSSP : The base SSP peripheral on the chip
* @param bitRate : The SSP bit rate
* @return Nothing
*/
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SSP_17XX_40XX_H_ */

137
hw/mcu/nxp/lpc_chip_175x_6x/inc/stopwatch.h Normal file
View File

@ -0,0 +1,137 @@
/*
* @brief Common stopwatch support
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __STOPWATCH_H_
#define __STOPWATCH_H_
#include "cmsis.h"
/** @defgroup Stop_Watch CHIP: Stopwatch primitives.
* @ingroup CHIP_Common
* @{
*/
/**
* @brief Initialize stopwatch
* @return Nothing
*/
void StopWatch_Init(void);
/**
* @brief Start a stopwatch
* @return Current cycle count
*/
uint32_t StopWatch_Start(void);
/**
* @brief Returns number of ticks elapsed since stopwatch was started
* @param startTime : Time returned by StopWatch_Start().
* @return Number of ticks elapsed since stopwatch was started
*/
STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime)
{
return StopWatch_Start() - startTime;
}
/**
* @brief Returns number of ticks per second of the stopwatch timer
* @return Number of ticks per second of the stopwatch timer
*/
uint32_t StopWatch_TicksPerSecond(void);
/**
* @brief Converts from stopwatch ticks to mS.
* @param ticks : Duration in ticks to convert to mS.
* @return Number of mS in given number of ticks
*/
uint32_t StopWatch_TicksToMs(uint32_t ticks);
/**
* @brief Converts from stopwatch ticks to uS.
* @param ticks : Duration in ticks to convert to uS.
* @return Number of uS in given number of ticks
*/
uint32_t StopWatch_TicksToUs(uint32_t ticks);
/**
* @brief Converts from mS to stopwatch ticks.
* @param mS : Duration in mS to convert to ticks.
* @return Number of ticks in given number of mS
*/
uint32_t StopWatch_MsToTicks(uint32_t mS);
/**
* @brief Converts from uS to stopwatch ticks.
* @param uS : Duration in uS to convert to ticks.
* @return Number of ticks in given number of uS
*/
uint32_t StopWatch_UsToTicks(uint32_t uS);
/**
* @brief Delays the given number of ticks using stopwatch primitives
* @param ticks : Number of ticks to delay
* @return Nothing
*/
STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks)
{
uint32_t startTime = StopWatch_Start();
while (StopWatch_Elapsed(startTime) < ticks) {}
}
/**
* @brief Delays the given number of mS using stopwatch primitives
* @param mS : Number of mS to delay
* @return Nothing
*/
STATIC INLINE void StopWatch_DelayMs(uint32_t mS)
{
uint32_t ticks = StopWatch_MsToTicks(mS);
uint32_t startTime = StopWatch_Start();
while (StopWatch_Elapsed(startTime) < ticks) {}
}
/**
* @brief Delays the given number of uS using stopwatch primitives
* @param uS : Number of uS to delay
* @return Nothing
*/
STATIC INLINE void StopWatch_DelayUs(uint32_t uS)
{
uint32_t ticks = StopWatch_UsToTicks(uS);
uint32_t startTime = StopWatch_Start();
while (StopWatch_Elapsed(startTime) < ticks) {}
}
/**
* @}
*/
#endif /* __STOPWATCH_H_ */

36
hw/mcu/nxp/lpc_chip_175x_6x/inc/sys_config.h Normal file
View File

@ -0,0 +1,36 @@
/*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SYS_CONFIG_H_
#define __SYS_CONFIG_H_
/* Build for 175x/6x chip family */
#define CHIP_LPC175X_6X
#endif /* __SYS_CONFIG_H_ */

360
hw/mcu/nxp/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h Normal file
View File

@ -0,0 +1,360 @@
/*
* @brief LPC17xx/40xx System and Control driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef _SYSCTL_17XX_40XX_H_
#define _SYSCTL_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SYSCTL_17XX_40XX CHIP: LPC17xx/40xx System Control block driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief LPC17XX/40XX Clock and Power PLL register block structure
*/
typedef struct {
__IO uint32_t PLLCON; /*!< (R/W) PLL Control Register */
__IO uint32_t PLLCFG; /*!< (R/W) PLL Configuration Register */
__I uint32_t PLLSTAT; /*!< (R/ ) PLL Status Register */
__O uint32_t PLLFEED; /*!< ( /W) PLL Feed Register */
uint32_t RESERVED1[4];
} SYSCTL_PLL_REGS_T;
/**
* Selectable PLLs
*/
typedef enum {
SYSCTL_MAIN_PLL, /*!< Main PLL (PLL0) */
SYSCTL_USB_PLL, /*!< USB PLL (PLL1) */
} CHIP_SYSCTL_PLL_T;
/**
* @brief LPC17XX/40XX Clock and Power register block structure
*/
typedef struct {
__IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
uint32_t RESERVED0[15];
__IO uint32_t MEMMAP; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
uint32_t RESERVED1[15];
SYSCTL_PLL_REGS_T PLL[SYSCTL_USB_PLL + 1]; /*!< Offset: 0x080: PLL0 and PLL1 */
__IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
__IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
#if defined(CHIP_LPC175X_6X)
uint32_t RESERVED2[15];
#elif defined(CHIP_LPC177X_8X)
uint32_t RESERVED2[14];
__IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
#else
__IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control 1 for Peripherals Register */
uint32_t RESERVED2[13];
__IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
#endif
__IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
__IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
__IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
__IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
__IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
uint32_t RESERVED3[10];
__IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
uint32_t RESERVED4;
__IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
__IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
uint32_t RESERVED5[12];
__IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC40XX)
uint32_t RESERVED6[7];
#elif defined(CHIP_LPC177X_8X)
uint32_t RESERVED6;
uint32_t MATRIXARB;
uint32_t RESERVED6A[5];
#endif
__IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
__IO uint32_t RESERVED7;
#if defined(CHIP_LPC175X_6X)
__IO uint32_t PCLKSEL[2]; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
uint32_t RESERVED8[4];
#else
__IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
uint32_t RESERVED9;
__IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
__IO uint32_t SPIFICLKSEL;
__IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
uint32_t RESERVED10;
#endif
__IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
__IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
__IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
#if defined(CHIP_LPC175X_6X)
uint32_t RESERVED11[6];
#else
__IO uint32_t RSTCON[2]; /*!< Offset: 0x1CC (R/W) RESET Control0/1 Registers */
uint32_t RESERVED11[2];
__IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
__IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
#endif
} LPC_SYSCTL_T;
/**
* @brief FLASH Access time definitions
*/
typedef enum {
FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock */
FLASHTIM_40MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock */
FLASHTIM_60MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock */
FLASHTIM_80MHZ_CPU = 3, /*!< Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock */
FLASHTIM_100MHZ_CPU = 4, /*!< Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock */
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
FLASHTIM_120MHZ_CPU = 3, /*!< Flash accesses use 4 CPU clocks. Use for up to 120 MHz CPU clock with power boot on*/
#else
FLASHTIM_120MHZ_CPU = 4, /*!< Flash accesses use 5 CPU clocks. Use for up to 120 Mhz for LPC1759 and LPC1769 only.*/
#endif
FLASHTIM_SAFE_SETTING = 5, /*!< Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions */
} FMC_FLASHTIM_T;
/**
* @brief Set FLASH memory access time in clocks
* @param clks : Clock cycles for FLASH access (minus 1)
* @return Nothing
* @note See the user manual for valid settings for this register for when
* power boot is enabled or off.
*/
STATIC INLINE void Chip_SYSCTL_SetFLASHAccess(FMC_FLASHTIM_T clks)
{
uint32_t tmp = LPC_SYSCTL->FLASHCFG & 0xFFF;
/* Don't alter lower bits */
LPC_SYSCTL->FLASHCFG = tmp | (clks << 12);
}
/**
* System memory remap modes used to remap interrupt vectors
*/
typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */
REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */
} CHIP_SYSCTL_BOOT_MODE_REMAP_T;
/**
* @brief Re-map interrupt vectors
* @param remap : system memory map value
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
{
LPC_SYSCTL->MEMMAP = (uint32_t) remap;
}
/**
* System reset status
*/
#define SYSCTL_RST_POR (1 << 0) /*!< POR reset status */
#define SYSCTL_RST_EXTRST (1 << 1) /*!< External reset status */
#define SYSCTL_RST_WDT (1 << 2) /*!< Watchdog reset status */
#define SYSCTL_RST_BOD (1 << 3) /*!< Brown-out detect reset status */
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
#define SYSCTL_RST_SYSRST (1 << 4) /*!< software system reset status */
#define SYSCTL_RST_LOCKUP (1 << 5) /*!< "lockup" reset status */
#endif
/**
* @brief Get system reset status
* @return An Or'ed value of SYSCTL_RST_*
* @note This function returns the detected reset source(s).
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
{
return LPC_SYSCTL->RSID;
}
/**
* @brief Clear system reset status
* @param reset : An Or'ed value of SYSCTL_RST_* status to clear
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
{
LPC_SYSCTL->RSID = reset;
}
/**
* @brief Enable brown-out detection
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableBOD(void)
{
LPC_SYSCTL->PCON |= (1 << 3);
}
/**
* @brief Disable brown-out detection
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableBOD(void)
{
LPC_SYSCTL->PCON &= ~(1 << 3);
}
/**
* @brief Enable brown-out detection reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
{
LPC_SYSCTL->PCON |= (1 << 4);
}
/**
* @brief Disable brown-out detection reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
{
LPC_SYSCTL->PCON &= ~(1 << 4);
}
/**
* @brief Enable brown-out detection reduced power mode
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableBODRPM(void)
{
LPC_SYSCTL->PCON |= (1 << 5);
}
/**
* @brief Disable brown-out detection reduced power mode
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableBODRPM(void)
{
LPC_SYSCTL->PCON &= ~(1 << 5);
}
#define SYSCTL_PD_SMFLAG (1 << 8) /*!< Sleep Mode entry flag */
#define SYSCTL_PD_DSFLAG (1 << 9) /*!< Deep Sleep entry flag */
#define SYSCTL_PD_PDFLAG (1 << 10) /*!< Power-down entry flag */
#define SYSCTL_PD_DPDFLAG (1 << 11) /*!< Deep Power-down entry flag */
/**
* @brief Returns and clears the current sleep mode entry flags
* @param flags: One or more flags to clear, SYSCTL_PD_*
* @return An Or'ed value of the sleep flags, SYSCTL_PD_*
* @note These flags indicate the successful entry of one or more
* sleep modes.
*/
uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags);
#if !defined(CHIP_LPC175X_6X)
/**
* @brief Enable power boost for clock operation over 100MHz
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableBoost(void)
{
LPC_SYSCTL->PBOOST = 0x3;
}
/**
* @brief Disable power boost for clock operation under 100MHz
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableBoost(void)
{
LPC_SYSCTL->PBOOST = 0x0;
}
#endif
#if !defined(CHIP_LPC175X_6X)
/**
* Peripheral reset numbers
* This is a list of peripherals that can be reset
*/
typedef enum {
SYSCTL_RESET_LCD, /*!< LCD reset */
SYSCTL_RESET_TIMER0, /*!< Timer 0 reset */
SYSCTL_RESET_TIMER1, /*!< Timer 1 reset */
SYSCTL_RESET_UART0, /*!< UART 0 reset */
SYSCTL_RESET_UART1, /*!< UART 1 reset */
SYSCTL_RESET_PWM0, /*!< PWM0 reset */
SYSCTL_RESET_PWM1, /*!< PWM1 reset */
SYSCTL_RESET_I2C0, /*!< I2C0 reset */
SYSCTL_RESET_UART4, /*!< UART 4 reset */
SYSCTL_RESET_RTC, /*!< RTC reset */
SYSCTL_RESET_SSP1, /*!< SSP1 reset */
SYSCTL_RESET_EMC, /*!< EMC reset */
SYSCTL_RESET_ADC, /*!< ADC reset */
SYSCTL_RESET_CAN1, /*!< CAN1 reset */
SYSCTL_RESET_CAN2, /*!< CAN2 reset */
SYSCTL_RESET_GPIO, /*!< GPIO reset */
SYSCTL_RESET_SPIFI, /*!< SPIFI reset */
SYSCTL_RESET_MCPWM, /*!< MCPWM reset */
SYSCTL_RESET_QEI, /*!< QEI reset */
SYSCTL_RESET_I2C1, /*!< I2C1 reset */
SYSCTL_RESET_SSP2, /*!< SSP2 reset */
SYSCTL_RESET_SSP0, /*!< SSP0 reset */
SYSCTL_RESET_TIMER2, /*!< Timer 2 reset */
SYSCTL_RESET_TIMER3, /*!< Timer 3 reset */
SYSCTL_RESET_UART2, /*!< UART 2 reset */
SYSCTL_RESET_UART3, /*!< UART 3 reset */
SYSCTL_RESET_I2C2, /*!< I2C2 reset */
SYSCTL_RESET_I2S, /*!< I2S reset */
SYSCTL_RESET_PCSDC, /*!< SD Card interface reset */
SYSCTL_RESET_GPDMA, /*!< GP DMA reset */
SYSCTL_RESET_ENET, /*!< EMAC/Ethernet reset */
SYSCTL_RESET_USB, /*!< USB reset */
SYSCTL_RESET_IOCON, /*!< IOCON reset */
SYSCTL_RESET_DAC, /*!< DAC reset */
SYSCTL_RESET_CANACC, /*!< CAN acceptance filter reset */
} CHIP_SYSCTL_RESET_T;
/**
* @brief Resets a peripheral
* @param periph: Peripheral to reset
* @return Nothing
*/
void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph);
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYSCTL_17XX_40XX_H_ */

445
hw/mcu/nxp/lpc_chip_175x_6x/inc/timer_17xx_40xx.h Normal file
View File

@ -0,0 +1,445 @@
/*
* @brief LPC17xx/40xx 16/32-bit Timer/PWM driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __TIMER_17XX_40XX_H_
#define __TIMER_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup TIMER_17XX_40XX CHIP: LPc17xx/40xx 16/32-bit Timer driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief 32-bit Standard timer register block structure
*/
typedef struct { /*!< TIMERn Structure */
__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
__IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
__IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
__IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
} LPC_TIMER_T;
/** Macro to clear interrupt pending */
#define TIMER_IR_CLR(n) _BIT(n)
/** Macro for getting a timer match interrupt bit */
#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
/** Macro for getting a capture event interrupt bit */
#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
/** Timer/counter enable bit */
#define TIMER_ENABLE ((uint32_t) (1 << 0))
/** Timer/counter reset bit */
#define TIMER_RESET ((uint32_t) (1 << 1))
/** Bit location for interrupt on MRx match, n = 0 to 3 */
#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
/** Bit location for reset on MRx match, n = 0 to 3 */
#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
/** Bit location for stop on MRx match, n = 0 to 3 */
#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
#define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
/**
* @brief Initialize a timer
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
/**
* @brief Shutdown a timer
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
/**
* @brief Determine if a match interrupt is pending
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match interrupt number to check
* @return false if the interrupt is not pending, otherwise true
* @note Determine if the match interrupt for the passed timer and match
* counter is pending.
*/
STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
{
return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
}
/**
* @brief Determine if a capture interrupt is pending
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture interrupt number to check
* @return false if the interrupt is not pending, otherwise true
* @note Determine if the capture interrupt for the passed capture pin is
* pending.
*/
STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
{
return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
}
/**
* @brief Clears a (pending) match interrupt
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match interrupt number to clear
* @return Nothing
* @note Clears a pending timer match interrupt.
*/
STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->IR = TIMER_IR_CLR(matchnum);
}
/**
* @brief Clears a (pending) capture interrupt
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture interrupt number to clear
* @return Nothing
* @note Clears a pending timer capture interrupt.
*/
STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->IR = (0x10 << capnum);
}
/**
* @brief Enables the timer (starts count)
* @param pTMR : Pointer to timer IP register address
* @return Nothing
* @note Enables the timer to start counting.
*/
STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
{
pTMR->TCR |= TIMER_ENABLE;
}
/**
* @brief Disables the timer (stops count)
* @param pTMR : Pointer to timer IP register address
* @return Nothing
* @note Disables the timer to stop counting.
*/
STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
{
pTMR->TCR &= ~TIMER_ENABLE;
}
/**
* @brief Returns the current timer count
* @param pTMR : Pointer to timer IP register address
* @return Current timer terminal count value
* @note Returns the current timer terminal count.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
{
return pTMR->TC;
}
/**
* @brief Returns the current prescale count
* @param pTMR : Pointer to timer IP register address
* @return Current timer prescale count value
* @note Returns the current prescale count.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
{
return pTMR->PC;
}
/**
* @brief Sets the prescaler value
* @param pTMR : Pointer to timer IP register address
* @param prescale : Prescale value to set the prescale register to
* @return Nothing
* @note Sets the prescale count value.
*/
STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
{
pTMR->PR = prescale;
}
/**
* @brief Sets a timer match value
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer to set match count for
* @param matchval : Match value for the selected match count
* @return Nothing
* @note Sets one of the timer match values.
*/
STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
{
pTMR->MR[matchnum] = matchval;
}
/**
* @brief Reads a capture register
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture register to read
* @return The selected capture register value
* @note Returns the selected capture register value.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
return pTMR->CR[capnum];
}
/**
* @brief Resets the timer terminal and prescale counts to 0
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
/**
* @brief Enables a match interrupt that fires when the terminal count
* matches the match counter value.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
}
/**
* @brief Disables a match interrupt for a match counter.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
}
/**
* @brief For the specific match counter, enables reset of the terminal count register when a match occurs
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
}
/**
* @brief For the specific match counter, disables reset of the terminal count register when a match occurs
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
}
/**
* @brief Enable a match timer to stop the terminal count when a
* match count equals the terminal count.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
}
/**
* @brief Disable stop on match for a match timer. Disables a match timer
* to stop the terminal count when a match count equals the terminal count.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
}
/**
* @brief Enables capture on on rising edge of selected CAP signal for the
* selected capture register, enables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a rising edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_CAP_RISING(capnum);
}
/**
* @brief Disables capture on on rising edge of selected CAP signal. For the
* selected capture register, disables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a rising edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
}
/**
* @brief Enables capture on on falling edge of selected CAP signal. For the
* selected capture register, enables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a falling edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_CAP_FALLING(capnum);
}
/**
* @brief Disables capture on on falling edge of selected CAP signal. For the
* selected capture register, disables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a falling edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
}
/**
* @brief Enables interrupt on capture of selected CAP signal. For the
* selected capture register, an interrupt will be generated when the enabled
* rising or falling edge on CAPn.capnum is detected.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
}
/**
* @brief Disables interrupt on capture of selected CAP signal
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
}
/**
* @brief Standard timer initial match pin state and change state
*/
typedef enum IP_TIMER_PIN_MATCH_STATE {
TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */
TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */
TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */
TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */
} TIMER_PIN_MATCH_STATE_T;
/**
* @brief Sets external match control (MATn.matchnum) pin control. For the pin
* selected with matchnum, sets the function of the pin that occurs on
* a terminal count match for the match count.
* @param pTMR : Pointer to timer IP register address
* @param initial_state : Initial state of the pin, high(1) or low(0)
* @param matchState : Selects the match state for the pin
* @param matchnum : MATn.matchnum signal to use
* @return Nothing
* @note For the pin selected with matchnum, sets the function of the pin that occurs on
* a terminal count match for the match count.
*/
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
/**
* @brief Standard timer clock and edge for count source
*/
typedef enum IP_TIMER_CAP_SRC_STATE {
TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */
TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */
TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */
TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */
} TIMER_CAP_SRC_STATE_T;
/**
* @brief Sets timer count source and edge with the selected passed from CapSrc.
* If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
* @param pTMR : Pointer to timer IP register address
* @param capSrc : timer clock source and edge
* @param capnum : CAPn.capnum pin to use (if used)
* @return Nothing
* @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
*/
STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
TIMER_CAP_SRC_STATE_T capSrc,
int8_t capnum)
{
pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_17XX_40XX_H_ */

814
hw/mcu/nxp/lpc_chip_175x_6x/inc/uart_17xx_40xx.h Normal file
View File

@ -0,0 +1,814 @@
/*
* @brief LPC17xx/40xx UART chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __UART_17XX_40XX_H_
#define __UART_17XX_40XX_H_
#include "ring_buffer.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup UART_17XX_40XX CHIP: LPC17xx/40xx UART driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief USART register block structure
*/
typedef struct { /*!< USARTn Structure */
union {
__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
};
union {
__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
};
union {
__O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
__I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
__IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
__IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
__I uint32_t RESERVED1[1];
__IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
union {
__IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
__I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
};
__IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
} LPC_USART_T;
/**
* @brief Macro defines for UART Receive Buffer register
*/
#define UART_RBR_MASKBIT (0xFF) /*!< UART Received Buffer mask bit (8 bits) */
/**
* @brief Macro defines for UART Divisor Latch LSB register
*/
#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading LSB of divisor */
#define UART_DLL_MASKBIT (0xFF) /*!< Divisor latch LSB bit mask */
/**
* @brief Macro defines for UART Divisor Latch MSB register
*/
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading MSB of divisors */
#define UART_DLM_MASKBIT (0xFF) /*!< Divisor latch MSB bit mask */
/**
* @brief Macro defines for UART Interrupt Enable Register
*/
#define UART_IER_RBRINT (1 << 0) /*!< RBR Interrupt enable */
#define UART_IER_THREINT (1 << 1) /*!< THR Interrupt enable */
#define UART_IER_RLSINT (1 << 2) /*!< RX line status interrupt enable */
#define UART_IER_MSINT (1 << 3) /*!< Modem status interrupt enable - valid for 11xx, 17xx/40xx UART1, 18xx/43xx UART1 only */
#define UART_IER_CTSINT (1 << 7) /*!< CTS signal transition interrupt enable - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
#define UART_IER_ABEOINT (1 << 8) /*!< Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINT (1 << 9) /*!< Enables the auto-baud time-out interrupt */
#define UART_IER_BITMASK (0x307) /*!< UART interrupt enable register bit mask - valid for 13xx, 17xx/40xx UART0/2/3, 18xx/43xx UART0/2/3 only*/
#define UART1_IER_BITMASK (0x30F) /*!< UART1 interrupt enable register bit mask - valid for 11xx only */
#define UART2_IER_BITMASK (0x38F) /*!< UART2 interrupt enable register bit mask - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
/**
* @brief Macro defines for UART Interrupt Identification Register
*/
#define UART_IIR_INTSTAT_PEND (1 << 0) /*!< Interrupt pending status - Active low */
#define UART_IIR_FIFO_EN (3 << 6) /*!< These bits are equivalent to FCR[0] */
#define UART_IIR_ABEO_INT (1 << 8) /*!< End of auto-baud interrupt */
#define UART_IIR_ABTO_INT (1 << 9) /*!< Auto-baud time-out interrupt */
#define UART_IIR_BITMASK (0x3CF) /*!< UART interrupt identification register bit mask */
/* Interrupt ID bit definitions */
#define UART_IIR_INTID_MASK (7 << 1) /*!< Interrupt identification: Interrupt ID mask */
#define UART_IIR_INTID_RLS (3 << 1) /*!< Interrupt identification: Receive line interrupt */
#define UART_IIR_INTID_RDA (2 << 1) /*!< Interrupt identification: Receive data available interrupt */
#define UART_IIR_INTID_CTI (6 << 1) /*!< Interrupt identification: Character time-out indicator interrupt */
#define UART_IIR_INTID_THRE (1 << 1) /*!< Interrupt identification: THRE interrupt */
#define UART_IIR_INTID_MODEM (0 << 1) /*!< Interrupt identification: Modem interrupt */
/**
* @brief Macro defines for UART FIFO Control Register
*/
#define UART_FCR_FIFO_EN (1 << 0) /*!< UART FIFO enable */
#define UART_FCR_RX_RS (1 << 1) /*!< UART RX FIFO reset */
#define UART_FCR_TX_RS (1 << 2) /*!< UART TX FIFO reset */
#define UART_FCR_DMAMODE_SEL (1 << 3) /*!< UART DMA mode selection - valid for 17xx/40xx, 18xx/43xx only */
#define UART_FCR_BITMASK (0xCF) /*!< UART FIFO control bit mask */
#define UART_TX_FIFO_SIZE (16)
/* FIFO trigger level bit definitions */
#define UART_FCR_TRG_LEV0 (0) /*!< UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV1 (1 << 6) /*!< UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV2 (2 << 6) /*!< UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV3 (3 << 6) /*!< UART FIFO trigger level 3: 14 character */
/**
* @brief Macro defines for UART Line Control Register
*/
/* UART word length select bit definitions */
#define UART_LCR_WLEN_MASK (3 << 0) /*!< UART word length select bit mask */
#define UART_LCR_WLEN5 (0 << 0) /*!< UART word length select: 5 bit data mode */
#define UART_LCR_WLEN6 (1 << 0) /*!< UART word length select: 6 bit data mode */
#define UART_LCR_WLEN7 (2 << 0) /*!< UART word length select: 7 bit data mode */
#define UART_LCR_WLEN8 (3 << 0) /*!< UART word length select: 8 bit data mode */
/* UART Stop bit select bit definitions */
#define UART_LCR_SBS_MASK (1 << 2) /*!< UART stop bit select: bit mask */
#define UART_LCR_SBS_1BIT (0 << 2) /*!< UART stop bit select: 1 stop bit */
#define UART_LCR_SBS_2BIT (1 << 2) /*!< UART stop bit select: 2 stop bits (in 5 bit data mode, 1.5 stop bits) */
/* UART Parity enable bit definitions */
#define UART_LCR_PARITY_EN (1 << 3) /*!< UART Parity Enable */
#define UART_LCR_PARITY_DIS (0 << 3) /*!< UART Parity Disable */
#define UART_LCR_PARITY_ODD (0 << 4) /*!< UART Parity select: Odd parity */
#define UART_LCR_PARITY_EVEN (1 << 4) /*!< UART Parity select: Even parity */
#define UART_LCR_PARITY_F_1 (2 << 4) /*!< UART Parity select: Forced 1 stick parity */
#define UART_LCR_PARITY_F_0 (3 << 4) /*!< UART Parity select: Forced 0 stick parity */
#define UART_LCR_BREAK_EN (1 << 6) /*!< UART Break transmission enable */
#define UART_LCR_DLAB_EN (1 << 7) /*!< UART Divisor Latches Access bit enable */
#define UART_LCR_BITMASK (0xFF) /*!< UART line control bit mask */
/**
* @brief Macro defines for UART Modem Control Register
*/
#define UART_MCR_DTR_CTRL (1 << 0) /*!< Source for modem output pin DTR */
#define UART_MCR_RTS_CTRL (1 << 1) /*!< Source for modem output pin RTS */
#define UART_MCR_LOOPB_EN (1 << 4) /*!< Loop back mode select */
#define UART_MCR_AUTO_RTS_EN (1 << 6) /*!< Enable Auto RTS flow-control */
#define UART_MCR_AUTO_CTS_EN (1 << 7) /*!< Enable Auto CTS flow-control */
#define UART_MCR_BITMASK (0xD3) /*!< UART bit mask value */
/**
* @brief Macro defines for UART Line Status Register
*/
#define UART_LSR_RDR (1 << 0) /*!< Line status: Receive data ready */
#define UART_LSR_OE (1 << 1) /*!< Line status: Overrun error */
#define UART_LSR_PE (1 << 2) /*!< Line status: Parity error */
#define UART_LSR_FE (1 << 3) /*!< Line status: Framing error */
#define UART_LSR_BI (1 << 4) /*!< Line status: Break interrupt */
#define UART_LSR_THRE (1 << 5) /*!< Line status: Transmit holding register empty */
#define UART_LSR_TEMT (1 << 6) /*!< Line status: Transmitter empty */
#define UART_LSR_RXFE (1 << 7) /*!< Line status: Error in RX FIFO */
#define UART_LSR_TXFE (1 << 8) /*!< Line status: Error in RX FIFO */
#define UART_LSR_BITMASK (0xFF) /*!< UART Line status bit mask */
#define UART1_LSR_BITMASK (0x1FF) /*!< UART1 Line status bit mask - valid for 11xx, 18xx/43xx UART0/2/3 only */
/**
* @brief Macro defines for UART Modem Status Register
*/
#define UART_MSR_DELTA_CTS (1 << 0) /*!< Modem status: State change of input CTS */
#define UART_MSR_DELTA_DSR (1 << 1) /*!< Modem status: State change of input DSR */
#define UART_MSR_LO2HI_RI (1 << 2) /*!< Modem status: Low to high transition of input RI */
#define UART_MSR_DELTA_DCD (1 << 3) /*!< Modem status: State change of input DCD */
#define UART_MSR_CTS (1 << 4) /*!< Modem status: Clear To Send State */
#define UART_MSR_DSR (1 << 5) /*!< Modem status: Data Set Ready State */
#define UART_MSR_RI (1 << 6) /*!< Modem status: Ring Indicator State */
#define UART_MSR_DCD (1 << 7) /*!< Modem status: Data Carrier Detect State */
#define UART_MSR_BITMASK (0xFF) /*!< Modem status: MSR register bit-mask value */
/**
* @brief Macro defines for UART Auto baudrate control register
*/
#define UART_ACR_START (1 << 0) /*!< UART Auto-baud start */
#define UART_ACR_MODE (1 << 1) /*!< UART Auto baudrate Mode 1 */
#define UART_ACR_AUTO_RESTART (1 << 2) /*!< UART Auto baudrate restart */
#define UART_ACR_ABEOINT_CLR (1 << 8) /*!< UART End of auto-baud interrupt clear */
#define UART_ACR_ABTOINT_CLR (1 << 9) /*!< UART Auto-baud time-out interrupt clear */
#define UART_ACR_BITMASK (0x307) /*!< UART Auto Baudrate register bit mask */
/**
* Autobaud modes
*/
#define UART_ACR_MODE0 (0) /*!< Auto baudrate Mode 0 */
#define UART_ACR_MODE1 (1) /*!< Auto baudrate Mode 1 */
/**
* @brief Macro defines for UART RS485 Control register
*/
#define UART_RS485CTRL_NMM_EN (1 << 0) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
#define UART_RS485CTRL_RX_DIS (1 << 1) /*!< The receiver is disabled */
#define UART_RS485CTRL_AADEN (1 << 2) /*!< Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL_DTR (1 << 3) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
used for direction control */
#define UART_RS485CTRL_DCTRL_EN (1 << 4) /*!< Enable Auto Direction Control */
#define UART_RS485CTRL_OINV_1 (1 << 5) /*!< This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin. The direction control pin
will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_BITMASK (0x3F) /*!< RS485 control bit-mask value */
/**
* @brief Macro defines for UART IrDA Control Register - valid for 11xx, 17xx/40xx UART0/2/3, 18xx/43xx UART3 only
*/
#define UART_ICR_IRDAEN (1 << 0) /*!< IrDA mode enable */
#define UART_ICR_IRDAINV (1 << 1) /*!< IrDA serial input inverted */
#define UART_ICR_FIXPULSE_EN (1 << 2) /*!< IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV(n) ((n & 0x07) << 3) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_BITMASK (0x3F) /*!< UART IRDA bit mask */
/**
* @brief Macro defines for UART half duplex register - ????
*/
#define UART_HDEN_HDEN ((1 << 0)) /*!< enable half-duplex mode*/
/**
* @brief Macro defines for UART Smart card interface Control Register - valid for 11xx, 18xx/43xx UART0/2/3 only
*/
#define UART_SCICTRL_SCIEN (1 << 0) /*!< enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_NACKDIS (1 << 1) /*!< NACK response is inhibited*/
#define UART_SCICTRL_PROTSEL_T1 (1 << 2) /*!< ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_TXRETRY(n) ((n & 0x07) << 5) /*!< number of retransmission*/
#define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8) /*!< Extra guard time*/
/**
* @brief Macro defines for UART Fractional Divider Register
*/
#define UART_FDR_DIVADDVAL(n) (n & 0x0F) /*!< Baud-rate generation pre-scaler divisor */
#define UART_FDR_MULVAL(n) ((n << 4) & 0xF0) /*!< Baud-rate pre-scaler multiplier value */
#define UART_FDR_BITMASK (0xFF) /*!< UART Fractional Divider register bit mask */
/**
* @brief Macro defines for UART Tx Enable Register
*/
#define UART_TER1_TXEN (1 << 7) /*!< Transmit enable bit - valid for 11xx, 13xx, 17xx/40xx only */
#define UART_TER2_TXEN (1 << 0) /*!< Transmit enable bit - valid for 18xx/43xx only */
/**
* @brief Macro defines for UART Synchronous Control Register - 11xx, 18xx/43xx UART0/2/3 only
*/
#define UART_SYNCCTRL_SYNC (1 << 0) /*!< enable synchronous mode*/
#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) /*!< synchronous master mode*/
#define UART_SYNCCTRL_FES (1 << 2) /*!< sample on falling edge*/
#define UART_SYNCCTRL_TSBYPASS (1 << 3) /*!< to be defined*/
#define UART_SYNCCTRL_CSCEN (1 << 4) /*!< Continuous running clock enable (master mode only)*/
#define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5) /*!< Do not send start/stop bit*/
#define UART_SYNCCTRL_CCCLR (1 << 6) /*!< stop continuous clock*/
/**
* @brief Transmit a single data byte through the UART peripheral
* @param pUART : Pointer to selected UART peripheral
* @param data : Byte to transmit
* @return Nothing
* @note This function attempts to place a byte into the UART transmit
* FIFO or transmit hold register regard regardless of UART state
*/
STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
{
pUART->THR = (uint32_t) data;
}
/**
* @brief Read a single byte data from the UART peripheral
* @param pUART : Pointer to selected UART peripheral
* @return A single byte of data read
* @note This function reads a byte from the UART receive FIFO or
* receive hold register regard regardless of UART state. The
* FIFO status should be read first prior to using this function
*/
STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
}
/**
* @brief Enable UART interrupts
* @param pUART : Pointer to selected UART peripheral
* @param intMask : OR'ed Interrupts to enable in the Interrupt Enable Register (IER)
* @return Nothing
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to enable specific UART interrupts. The Divisor Latch Access Bit
* (DLAB) in LCR must be cleared in order to access the IER register.
* This function doesn't alter the DLAB state
*/
STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask)
{
pUART->IER |= intMask;
}
/**
* @brief Disable UART interrupts
* @param pUART : Pointer to selected UART peripheral
* @param intMask : OR'ed Interrupts to disable in the Interrupt Enable Register (IER)
* @return Nothing
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to disable specific UART interrupts. The Divisor Latch Access Bit
* (DLAB) in LCR must be cleared in order to access the IER register.
* This function doesn't alter the DLAB state
*/
STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask)
{
pUART->IER &= ~intMask;
}
/**
* @brief Returns UART interrupts that are enabled
* @param pUART : Pointer to selected UART peripheral
* @return Returns the enabled UART interrupts
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to determine which interrupts are enabled. You can check
* for multiple enabled bits if needed.
*/
STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART)
{
return pUART->IER;
}
/**
* @brief Read the Interrupt Identification Register (IIR)
* @param pUART : Pointer to selected UART peripheral
* @return Current pending interrupt status per the IIR register
*/
STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART)
{
return pUART->IIR;
}
/**
* @brief Setup the UART FIFOs
* @param pUART : Pointer to selected UART peripheral
* @param fcr : FIFO control register setup OR'ed flags
* @return Nothing
* @note Use OR'ed value of UART_FCR_* definitions with this function
* to select specific options. For example, to enable the FIFOs
* with a RX trip level of 8 characters, use something like
* (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2)
*/
STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr)
{
pUART->FCR = fcr;
}
/**
* @brief Configure data width, parity and stop bits
* @param pUART : Pointer to selected pUART peripheral
* @param config : UART configuration, OR'ed values of UART_LCR_* defines
* @return Nothing
* @note Select OR'ed config options for the UART from the UART_LCR_*
* definitions. For example, a configuration of 8 data bits, 1
* stop bit, and even (enabled) parity would be
* (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_EN | UART_LCR_PARITY_EVEN)
*/
STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config)
{
pUART->LCR = config;
}
/**
* @brief Enable access to Divisor Latches
* @param pUART : Pointer to selected UART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART)
{
pUART->LCR |= UART_LCR_DLAB_EN;
}
/**
* @brief Disable access to Divisor Latches
* @param pUART : Pointer to selected UART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART)
{
pUART->LCR &= ~UART_LCR_DLAB_EN;
}
/**
* @brief Set LSB and MSB divisor latch registers
* @param pUART : Pointer to selected UART peripheral
* @param dll : Divisor Latch LSB value
* @param dlm : Divisor Latch MSB value
* @return Nothing
* @note The Divisor Latch Access Bit (DLAB) in LCR must be set in
* order to access the USART Divisor Latches. This function
* doesn't alter the DLAB state.
*/
STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm)
{
pUART->DLL = (uint32_t) dll;
pUART->DLM = (uint32_t) dlm;
}
/**
* @brief Return modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @return Modem control register (status)
* @note Mask bits of the returned status value with UART_MCR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART)
{
return pUART->MCR;
}
/**
* @brief Set modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @param mcr : Modem control register flags to set
* @return Nothing
* @note Use an Or'ed value of UART_MCR_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr)
{
pUART->MCR |= mcr;
}
/**
* @brief Clear modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @param mcr : Modem control register flags to clear
* @return Nothing
* @note Use an Or'ed value of UART_MCR_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr)
{
pUART->MCR &= ~mcr;
}
/**
* @brief Return Line Status register/status (LSR)
* @param pUART : Pointer to selected UART peripheral
* @return Line Status register (status)
* @note Mask bits of the returned status value with UART_LSR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART)
{
return pUART->LSR;
}
/**
* @brief Return Modem Status register/status (MSR)
* @param pUART : Pointer to selected UART peripheral
* @return Modem Status register (status)
* @note Mask bits of the returned status value with UART_MSR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART)
{
return pUART->MSR;
}
/**
* @brief Write a byte to the scratchpad register
* @param pUART : Pointer to selected UART peripheral
* @param data : Byte value to write
* @return Nothing
*/
STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data)
{
pUART->SCR = (uint32_t) data;
}
/**
* @brief Returns current byte value in the scratchpad register
* @param pUART : Pointer to selected UART peripheral
* @return Byte value read from scratchpad register
*/
STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->SCR & 0xFF);
}
/**
* @brief Set autobaud register options
* @param pUART : Pointer to selected UART peripheral
* @param acr : Or'ed values to set for ACR register
* @return Nothing
* @note Use an Or'ed value of UART_ACR_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
{
pUART->ACR |= acr;
}
/**
* @brief Clear autobaud register options
* @param pUART : Pointer to selected UART peripheral
* @param acr : Or'ed values to clear for ACR register
* @return Nothing
* @note Use an Or'ed value of UART_ACR_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
{
pUART->ACR &= ~acr;
}
/**
* @brief Set RS485 control register options
* @param pUART : Pointer to selected UART peripheral
* @param ctrl : Or'ed values to set for RS485 control register
* @return Nothing
* @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
{
pUART->RS485CTRL |= ctrl;
}
/**
* @brief Clear RS485 control register options
* @param pUART : Pointer to selected UART peripheral
* @param ctrl : Or'ed values to clear for RS485 control register
* @return Nothing
* @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
{
pUART->RS485CTRL &= ~ctrl;
}
/**
* @brief Set RS485 address match value
* @param pUART : Pointer to selected UART peripheral
* @param addr : Address match value for RS-485/EIA-485 mode
* @return Nothing
*/
STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr)
{
pUART->RS485ADRMATCH = (uint32_t) addr;
}
/**
* @brief Read RS485 address match value
* @param pUART : Pointer to selected UART peripheral
* @return Address match value for RS-485/EIA-485 mode
*/
STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
}
/**
* @brief Set RS485 direction control (RTS or DTR) delay value
* @param pUART : Pointer to selected UART peripheral
* @param dly : direction control (RTS or DTR) delay value
* @return Nothing
* @note This delay time is in periods of the baud clock. Any delay
* time from 0 to 255 bit times may be programmed.
*/
STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly)
{
pUART->RS485DLY = (uint32_t) dly;
}
/**
* @brief Read RS485 direction control (RTS or DTR) delay value
* @param pUART : Pointer to selected UART peripheral
* @return direction control (RTS or DTR) delay value
* @note This delay time is in periods of the baud clock. Any delay
* time from 0 to 255 bit times may be programmed.
*/
STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RS485DLY & 0xFF);
}
/**
* @brief Initializes the pUART peripheral
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_Init(LPC_USART_T *pUART);
/**
* @brief De-initializes the pUART peripheral.
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_DeInit(LPC_USART_T *pUART);
/**
* @brief Enable transmission on UART TxD pin
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_TXEnable(LPC_USART_T *pUART);
/**
* @brief Disable transmission on UART TxD pin
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_TXDisable(LPC_USART_T *pUART);
/**
* @brief Check whether if UART is busy or not
* @param pUART : Pointer to selected pUART peripheral
* @return RESET if UART is not busy, otherwise return SET
*/
FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART);
/**
* @brief Transmit a byte array through the UART peripheral (non-blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to bytes to transmit
* @param numBytes : Number of bytes to transmit
* @return The actual number of bytes placed into the FIFO
* @note This function places data into the transmit FIFO until either
* all the data is in the FIFO or the FIFO is full. This function
* will not block in the FIFO is full. The actual number of bytes
* placed into the FIFO is returned. This function ignores errors.
*/
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes);
/**
* @brief Read data through the UART peripheral (non-blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to bytes array to fill
* @param numBytes : Size of the passed data array
* @return The actual number of bytes read
* @note This function reads data from the receive FIFO until either
* all the data has been read or the passed buffer is completely full.
* This function will not block. This function ignores errors.
*/
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes);
/**
* @brief Sets best dividers to get a target bit rate (without fractional divider)
* @param pUART : Pointer to selected UART peripheral
* @param baudrate : Target baud rate (baud rate = bit rate)
* @return The actual baud rate, or 0 if no rate can be found
*/
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
/**
* @brief Sets best dividers to get a target bit rate (with fractional divider)
* @param pUART : Pointer to selected UART peripheral
* @param baudrate : Target baud rate (baud rate = bit rate)
* @return The actual baud rate, or 0 if no rate can be found
*/
uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate);
/**
* @brief Transmit a byte array through the UART peripheral (blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to data to transmit
* @param numBytes : Number of bytes to transmit
* @return The number of bytes transmitted
* @note This function will send or place all bytes into the transmit
* FIFO. This function will block until the last bytes are in the FIFO.
*/
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes);
/**
* @brief Read data through the UART peripheral (blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to data array to fill
* @param numBytes : Size of the passed data array
* @return The size of the dat array
* @note This function reads data from the receive FIFO until the passed
* buffer is completely full. The function will block until full.
* This function ignores errors.
*/
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes);
/**
* @brief UART receive-only interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @return Nothing
* @note If ring buffer support is desired for the receive side
* of data transfer, the UART interrupt should call this
* function for a receive based interrupt status.
*/
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
/**
* @brief UART transmit-only interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @return Nothing
* @note If ring buffer support is desired for the transmit side
* of data transfer, the UART interrupt should call this
* function for a transmit based interrupt status.
*/
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
/**
* @brief Populate a transmit ring buffer and start UART transmit
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @param data : Pointer to buffer to move to ring buffer
* @param bytes : Number of bytes to move
* @return The number of bytes placed into the ring buffer
* @note Will move the data into the TX ring buffer and start the
* transfer. If the number of bytes returned is less than the
* number of bytes to send, the ring buffer is considered full.
*/
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes);
/**
* @brief Copy data from a receive ring buffer
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @param data : Pointer to buffer to fill from ring buffer
* @param bytes : Size of the passed buffer in bytes
* @return The number of bytes placed into the ring buffer
* @note Will move the data from the RX ring buffer up to the
* the maximum passed buffer size. Returns 0 if there is
* no data in the ring buffer.
*/
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes);
/**
* @brief UART receive/transmit interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRXRB : Pointer to transmit ring buffer
* @param pTXRB : Pointer to receive ring buffer
* @return Nothing
* @note This provides a basic implementation of the UART IRQ
* handler for support of a ring buffer implementation for
* transmit and receive.
*/
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB);
/**
* @brief Returns the Auto Baud status
* @param pUART : Pointer to selected UART peripheral
* @return RESET if autobaud not completed, SET if autobaud completed
*/
FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART);
/**
* @brief Start/stop autobaud operation
* @param pUART : Pointer to selected UART peripheral
* @param mode : Autobaud mode (UART_ACR_MODE0 or UART_ACR_MODE1)
* @param autorestart : Enable autorestart (true to enable or false to disable)
* @param NewState : ENABLE to start autobaud operation, DISABLE to
* stop autobaud operation
* @return Nothing
*/
void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart,
FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __UART_17XX_40XX_H_ */

160
hw/mcu/nxp/lpc_chip_175x_6x/inc/usb_17xx_40xx.h Normal file
View File

@ -0,0 +1,160 @@
/*
* @brief LPC17xx/40xx USB driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __USB_17XX_40XX_H_
#define __USB_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup USB_17XX_40XX CHIP: LPC17xx/40xx USB Device, Host, & OTG driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
/**
* @brief USB register block structure
*/
typedef struct {
__I uint32_t Revision; /* USB Host Registers */
__IO uint32_t Control;
__IO uint32_t CommandStatus;
__IO uint32_t InterruptStatus;
__IO uint32_t InterruptEnable;
__IO uint32_t InterruptDisable;
__IO uint32_t HCCA;
__I uint32_t PeriodCurrentED;
__IO uint32_t ControlHeadED;
__IO uint32_t ControlCurrentED;
__IO uint32_t BulkHeadED;
__IO uint32_t BulkCurrentED;
__I uint32_t DoneHead;
__IO uint32_t FmInterval;
__I uint32_t FmRemaining;
__I uint32_t FmNumber;
__IO uint32_t PeriodicStart;
__IO uint32_t LSTreshold;
__IO uint32_t RhDescriptorA;
__IO uint32_t RhDescriptorB;
__IO uint32_t RhStatus;
__IO uint32_t RhPortStatus1;
__IO uint32_t RhPortStatus2;
uint32_t RESERVED0[40];
__I uint32_t Module_ID;
__I uint32_t IntSt; /* USB On-The-Go Registers */
__IO uint32_t IntEn;
__O uint32_t IntSet;
__O uint32_t IntClr;
__IO uint32_t StCtrl;
__IO uint32_t Tmr;
uint32_t RESERVED1[58];
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t DevIntEn;
__O uint32_t DevIntClr;
__O uint32_t DevIntSet;
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
__I uint32_t CmdData;
__I uint32_t RxData; /* USB Device Transfer Registers */
__O uint32_t TxData;
__I uint32_t RxPLen;
__O uint32_t TxPLen;
__IO uint32_t Ctrl;
__O uint32_t DevIntPri;
__I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
__IO uint32_t EpIntEn;
__O uint32_t EpIntClr;
__O uint32_t EpIntSet;
__O uint32_t EpIntPri;
__IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
__O uint32_t EpInd;
__IO uint32_t MaxPSize;
__I uint32_t DMARSt; /* USB Device DMA Registers */
__O uint32_t DMARClr;
__O uint32_t DMARSet;
uint32_t RESERVED2[9];
__IO uint32_t UDCAH;
__I uint32_t EpDMASt;
__O uint32_t EpDMAEn;
__O uint32_t EpDMADis;
__I uint32_t DMAIntSt;
__IO uint32_t DMAIntEn;
uint32_t RESERVED3[2];
__I uint32_t EoTIntSt;
__O uint32_t EoTIntClr;
__O uint32_t EoTIntSet;
__I uint32_t NDDRIntSt;
__O uint32_t NDDRIntClr;
__O uint32_t NDDRIntSet;
__I uint32_t SysErrIntSt;
__O uint32_t SysErrIntClr;
__O uint32_t SysErrIntSet;
uint32_t RESERVED4[15];
union {
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_TX;
};
__IO uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[824];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} LPC_USB_T;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USB_17Xx_40XX_H_ */

704
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd.h Normal file
View File

@ -0,0 +1,704 @@
/***********************************************************************
* $Id:: mw_usbd.h 575 2012-11-20 01:35:56Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __USBD_H__
#define __USBD_H__
/** \file
* \brief Common definitions and declarations for the USB stack.
*
* Common definitions and declarations for the USB stack.
* \addtogroup USBD_Core
* @{
*/
#include "lpc_types.h"
#if defined(__GNUC__)
/* As per http://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html#Attribute-Syntax,
6.29 Attributes Syntax
"An attribute specifier list may appear as part of a struct, union or
enum specifier. It may go either immediately after the struct, union
or enum keyword, or after the closing brace. The former syntax is
preferred. Where attribute specifiers follow the closing brace, they
are considered to relate to the structure, union or enumerated type
defined, not to any enclosing declaration the type specifier appears
in, and the type defined is not complete until after the attribute
specifiers."
So use POST_PACK immediately after struct keyword
*/
#define PRE_PACK
#define POST_PACK __attribute__((__packed__))
#define ALIGNED(n) __attribute__((aligned (n)))
#elif defined(__arm)
#define PRE_PACK __packed
#define POST_PACK
#define ALIGNED(n) __align(n)
#elif defined(__ICCARM__)
#define PRE_PACK __packed
#define POST_PACK
#define PRAGMA_ALIGN_4096 _Pragma("data_alignment=4096")
#define PRAGMA_ALIGN_2048 _Pragma("data_alignment=2048")
#define PRAGMA_ALIGN_256 _Pragma("data_alignment=256")
#define PRAGMA_ALIGN_128 _Pragma("data_alignment=128")
#define PRAGMA_ALIGN_64 _Pragma("data_alignment=64")
#define PRAGMA_ALIGN_48 _Pragma("data_alignment=48")
#define PRAGMA_ALIGN_32 _Pragma("data_alignment=32")
#define PRAGMA_ALIGN_4 _Pragma("data_alignment=4")
#define ALIGNED(n) PRAGMA_ALIGN_##n
#pragma diag_suppress=Pe021
#endif
/** Structure to pack lower and upper byte to form 16 bit word. */
PRE_PACK struct POST_PACK _WB_T
{
uint8_t L; /**< lower byte */
uint8_t H; /**< upper byte */
};
/** Structure to pack lower and upper byte to form 16 bit word.*/
typedef struct _WB_T WB_T;
/** Union of \ref _WB_T struct and 16 bit word.*/
PRE_PACK union POST_PACK __WORD_BYTE
{
uint16_t W; /**< data member to do 16 bit access */
WB_T WB; /**< data member to do 8 bit access */
} ;
/** Union of \ref _WB_T struct and 16 bit word.*/
typedef union __WORD_BYTE WORD_BYTE;
/** bmRequestType.Dir defines
* @{
*/
/** Request from host to device */
#define REQUEST_HOST_TO_DEVICE 0
/** Request from device to host */
#define REQUEST_DEVICE_TO_HOST 1
/** @} */
/** bmRequestType.Type defines
* @{
*/
/** Standard Request */
#define REQUEST_STANDARD 0
/** Class Request */
#define REQUEST_CLASS 1
/** Vendor Request */
#define REQUEST_VENDOR 2
/** Reserved Request */
#define REQUEST_RESERVED 3
/** @} */
/** bmRequestType.Recipient defines
* @{
*/
/** Request to device */
#define REQUEST_TO_DEVICE 0
/** Request to interface */
#define REQUEST_TO_INTERFACE 1
/** Request to endpoint */
#define REQUEST_TO_ENDPOINT 2
/** Request to other */
#define REQUEST_TO_OTHER 3
/** @} */
/** Structure to define 8 bit USB request.*/
PRE_PACK struct POST_PACK _BM_T
{
uint8_t Recipient : 5; /**< Recipient type. */
uint8_t Type : 2; /**< Request type. */
uint8_t Dir : 1; /**< Direction type. */
};
/** Structure to define 8 bit USB request.*/
typedef struct _BM_T BM_T;
/** Union of \ref _BM_T struct and 8 bit byte.*/
PRE_PACK union POST_PACK _REQUEST_TYPE
{
uint8_t B; /**< byte wide access memeber */
BM_T BM; /**< bitfield structure access memeber */
} ;
/** Union of \ref _BM_T struct and 8 bit byte.*/
typedef union _REQUEST_TYPE REQUEST_TYPE;
/** USB Standard Request Codes
* @{
*/
/** GET_STATUS request */
#define USB_REQUEST_GET_STATUS 0
/** CLEAR_FEATURE request */
#define USB_REQUEST_CLEAR_FEATURE 1
/** SET_FEATURE request */
#define USB_REQUEST_SET_FEATURE 3
/** SET_ADDRESS request */
#define USB_REQUEST_SET_ADDRESS 5
/** GET_DESCRIPTOR request */
#define USB_REQUEST_GET_DESCRIPTOR 6
/** SET_DESCRIPTOR request */
#define USB_REQUEST_SET_DESCRIPTOR 7
/** GET_CONFIGURATION request */
#define USB_REQUEST_GET_CONFIGURATION 8
/** SET_CONFIGURATION request */
#define USB_REQUEST_SET_CONFIGURATION 9
/** GET_INTERFACE request */
#define USB_REQUEST_GET_INTERFACE 10
/** SET_INTERFACE request */
#define USB_REQUEST_SET_INTERFACE 11
/** SYNC_FRAME request */
#define USB_REQUEST_SYNC_FRAME 12
/** @} */
/** USB GET_STATUS Bit Values
* @{
*/
/** SELF_POWERED status*/
#define USB_GETSTATUS_SELF_POWERED 0x01
/** REMOTE_WAKEUP capable status*/
#define USB_GETSTATUS_REMOTE_WAKEUP 0x02
/** ENDPOINT_STALL status*/
#define USB_GETSTATUS_ENDPOINT_STALL 0x01
/** @} */
/** USB Standard Feature selectors
* @{
*/
/** ENDPOINT_STALL feature*/
#define USB_FEATURE_ENDPOINT_STALL 0
/** REMOTE_WAKEUP feature*/
#define USB_FEATURE_REMOTE_WAKEUP 1
/** TEST_MODE feature*/
#define USB_FEATURE_TEST_MODE 2
/** @} */
/** USB Default Control Pipe Setup Packet*/
PRE_PACK struct POST_PACK _USB_SETUP_PACKET
{
REQUEST_TYPE bmRequestType; /**< This bitmapped field identifies the characteristics
of the specific request. \sa _BM_T.
*/
uint8_t bRequest; /**< This field specifies the particular request. The
Type bits in the bmRequestType field modify the meaning
of this field. \sa USBD_REQUEST.
*/
WORD_BYTE wValue; /**< Used to pass a parameter to the device, specific
to the request.
*/
WORD_BYTE wIndex; /**< Used to pass a parameter to the device, specific
to the request. The wIndex field is often used in
requests to specify an endpoint or an interface.
*/
uint16_t wLength; /**< This field specifies the length of the data
transferred during the second phase of the control
transfer.
*/
} ;
/** USB Default Control Pipe Setup Packet*/
typedef struct _USB_SETUP_PACKET USB_SETUP_PACKET;
/** USB Descriptor Types
* @{
*/
/** Device descriptor type */
#define USB_DEVICE_DESCRIPTOR_TYPE 1
/** Configuration descriptor type */
#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2
/** String descriptor type */
#define USB_STRING_DESCRIPTOR_TYPE 3
/** Interface descriptor type */
#define USB_INTERFACE_DESCRIPTOR_TYPE 4
/** Endpoint descriptor type */
#define USB_ENDPOINT_DESCRIPTOR_TYPE 5
/** Device qualifier descriptor type */
#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6
/** Other speed configuration descriptor type */
#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7
/** Interface power descriptor type */
#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8
/** OTG descriptor type */
#define USB_OTG_DESCRIPTOR_TYPE 9
/** Debug descriptor type */
#define USB_DEBUG_DESCRIPTOR_TYPE 10
/** Interface association descriptor type */
#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11
/** @} */
/** USB Device Classes
* @{
*/
/** Reserved device class */
#define USB_DEVICE_CLASS_RESERVED 0x00
/** Audio device class */
#define USB_DEVICE_CLASS_AUDIO 0x01
/** Communications device class */
#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02
/** Human interface device class */
#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03
/** monitor device class */
#define USB_DEVICE_CLASS_MONITOR 0x04
/** physical interface device class */
#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05
/** power device class */
#define USB_DEVICE_CLASS_POWER 0x06
/** Printer device class */
#define USB_DEVICE_CLASS_PRINTER 0x07
/** Storage device class */
#define USB_DEVICE_CLASS_STORAGE 0x08
/** Hub device class */
#define USB_DEVICE_CLASS_HUB 0x09
/** miscellaneous device class */
#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF
/** Application device class */
#define USB_DEVICE_CLASS_APP 0xFE
/** Vendor specific device class */
#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF
/** @} */
/** bmAttributes in Configuration Descriptor
* @{
*/
/** Power field mask */
#define USB_CONFIG_POWERED_MASK 0x40
/** Bus powered */
#define USB_CONFIG_BUS_POWERED 0x80
/** Self powered */
#define USB_CONFIG_SELF_POWERED 0xC0
/** remote wakeup */
#define USB_CONFIG_REMOTE_WAKEUP 0x20
/** @} */
/** bMaxPower in Configuration Descriptor */
#define USB_CONFIG_POWER_MA(mA) ((mA)/2)
/** bEndpointAddress in Endpoint Descriptor
* @{
*/
/** Endopint address mask */
#define USB_ENDPOINT_DIRECTION_MASK 0x80
/** Macro to convert OUT endopint number to endpoint address value. */
#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)
/** Macro to convert IN endopint number to endpoint address value. */
#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)
/** @} */
/** bmAttributes in Endpoint Descriptor
* @{
*/
/** Endopint type mask */
#define USB_ENDPOINT_TYPE_MASK 0x03
/** Control Endopint type */
#define USB_ENDPOINT_TYPE_CONTROL 0x00
/** isochronous Endopint type */
#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
/** bulk Endopint type */
#define USB_ENDPOINT_TYPE_BULK 0x02
/** interrupt Endopint type */
#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
/** Endopint sync type mask */
#define USB_ENDPOINT_SYNC_MASK 0x0C
/** no synchronization Endopint */
#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
/** Asynchronous sync Endopint */
#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04
/** Adaptive sync Endopint */
#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08
/** Synchronous sync Endopint */
#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C
/** Endopint usage type mask */
#define USB_ENDPOINT_USAGE_MASK 0x30
/** Endopint data usage type */
#define USB_ENDPOINT_USAGE_DATA 0x00
/** Endopint feedback usage type */
#define USB_ENDPOINT_USAGE_FEEDBACK 0x10
/** Endopint implicit feedback usage type */
#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
/** Endopint reserved usage type */
#define USB_ENDPOINT_USAGE_RESERVED 0x30
/** @} */
/** Control endopint EP0's maximum packet size in high-speed mode.*/
#define USB_ENDPOINT_0_HS_MAXP 64
/** Control endopint EP0's maximum packet size in low-speed mode.*/
#define USB_ENDPOINT_0_LS_MAXP 8
/** Bulk endopint's maximum packet size in high-speed mode.*/
#define USB_ENDPOINT_BULK_HS_MAXP 512
/** USB Standard Device Descriptor */
PRE_PACK struct POST_PACK _USB_DEVICE_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes. */
uint8_t bDescriptorType; /**< DEVICE Descriptor Type. */
uint16_t bcdUSB; /**< BUSB Specification Release Number in
Binary-Coded Decimal (i.e., 2.10 is 210H).
This field identifies the release of the USB
Specification with which the device and its
descriptors are compliant.
*/
uint8_t bDeviceClass; /**< Class code (assigned by the USB-IF).
If this field is reset to zero, each interface
within a configuration specifies its own
class information and the various
interfaces operate independently.\n
If this field is set to a value between 1 and
FEH, the device supports different class
specifications on different interfaces and
the interfaces may not operate
independently. This value identifies the
class definition used for the aggregate
interfaces. \n
If this field is set to FFH, the device class
is vendor-specific.
*/
uint8_t bDeviceSubClass; /**< Subclass code (assigned by the USB-IF).
These codes are qualified by the value of
the bDeviceClass field. \n
If the bDeviceClass field is reset to zero,
this field must also be reset to zero. \n
If the bDeviceClass field is not set to FFH,
all values are reserved for assignment by
the USB-IF.
*/
uint8_t bDeviceProtocol; /**< Protocol code (assigned by the USB-IF).
These codes are qualified by the value of
the bDeviceClass and the
bDeviceSubClass fields. If a device
supports class-specific protocols on a
device basis as opposed to an interface
basis, this code identifies the protocols
that the device uses as defined by the
specification of the device class. \n
If this field is reset to zero, the device
does not use class-specific protocols on a
device basis. However, it may use classspecific
protocols on an interface basis. \n
If this field is set to FFH, the device uses a
vendor-specific protocol on a device basis.
*/
uint8_t bMaxPacketSize0; /**< Maximum packet size for endpoint zero
(only 8, 16, 32, or 64 are valid). For HS devices
is fixed to 64.
*/
uint16_t idVendor; /**< Vendor ID (assigned by the USB-IF). */
uint16_t idProduct; /**< Product ID (assigned by the manufacturer). */
uint16_t bcdDevice; /**< Device release number in binary-coded decimal. */
uint8_t iManufacturer; /**< Index of string descriptor describing manufacturer. */
uint8_t iProduct; /**< Index of string descriptor describing product. */
uint8_t iSerialNumber; /**< Index of string descriptor describing the device<63>s
serial number.
*/
uint8_t bNumConfigurations; /**< Number of possible configurations. */
} ;
/** USB Standard Device Descriptor */
typedef struct _USB_DEVICE_DESCRIPTOR USB_DEVICE_DESCRIPTOR;
/** USB 2.0 Device Qualifier Descriptor */
PRE_PACK struct POST_PACK _USB_DEVICE_QUALIFIER_DESCRIPTOR
{
uint8_t bLength; /**< Size of descriptor */
uint8_t bDescriptorType; /**< Device Qualifier Type */
uint16_t bcdUSB; /**< USB specification version number (e.g., 0200H for V2.00) */
uint8_t bDeviceClass; /**< Class Code */
uint8_t bDeviceSubClass; /**< SubClass Code */
uint8_t bDeviceProtocol; /**< Protocol Code */
uint8_t bMaxPacketSize0; /**< Maximum packet size for other speed */
uint8_t bNumConfigurations; /**< Number of Other-speed Configurations */
uint8_t bReserved; /**< Reserved for future use, must be zero */
} ;
/** USB 2.0 Device Qualifier Descriptor */
typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR USB_DEVICE_QUALIFIER_DESCRIPTOR;
/** USB Standard Configuration Descriptor */
PRE_PACK struct POST_PACK _USB_CONFIGURATION_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes */
uint8_t bDescriptorType; /**< CONFIGURATION Descriptor Type*/
uint16_t wTotalLength; /**< Total length of data returned for this
configuration. Includes the combined length
of all descriptors (configuration, interface,
endpoint, and class- or vendor-specific)
returned for this configuration.*/
uint8_t bNumInterfaces; /**< Number of interfaces supported by this configuration*/
uint8_t bConfigurationValue; /**< Value to use as an argument to the
SetConfiguration() request to select this
configuration. */
uint8_t iConfiguration; /**< Index of string descriptor describing this
configuration*/
uint8_t bmAttributes; /**< Configuration characteristics \n
D7: Reserved (set to one)\n
D6: Self-powered \n
D5: Remote Wakeup \n
D4...0: Reserved (reset to zero) \n
D7 is reserved and must be set to one for
historical reasons. \n
A device configuration that uses power from
the bus and a local source reports a non-zero
value in bMaxPower to indicate the amount of
bus power required and sets D6. The actual
power source at runtime may be determined
using the GetStatus(DEVICE) request (see
USB 2.0 spec Section 9.4.5). \n
If a device configuration supports remote
wakeup, D5 is set to one.*/
uint8_t bMaxPower; /**< Maximum power consumption of the USB
device from the bus in this specific
configuration when the device is fully
operational. Expressed in 2 mA units
(i.e., 50 = 100 mA). \n
Note: A device configuration reports whether
the configuration is bus-powered or selfpowered.
Device status reports whether the
device is currently self-powered. If a device is
disconnected from its external power source, it
updates device status to indicate that it is no
longer self-powered. \n
A device may not increase its power draw
from the bus, when it loses its external power
source, beyond the amount reported by its
configuration. \n
If a device can continue to operate when
disconnected from its external power source, it
continues to do so. If the device cannot
continue to operate, it fails operations it can
no longer support. The USB System Software
may determine the cause of the failure by
checking the status and noting the loss of the
device<EFBFBD>s power source.*/
} ;
/** USB Standard Configuration Descriptor */
typedef struct _USB_CONFIGURATION_DESCRIPTOR USB_CONFIGURATION_DESCRIPTOR;
/** USB Standard Interface Association Descriptor */
PRE_PACK struct POST_PACK _USB_IAD_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes*/
uint8_t bDescriptorType; /**< INTERFACE ASSOCIATION Descriptor Type*/
uint8_t bFirstInterface; /**< Interface number of the first interface that is
associated with this function.*/
uint8_t bInterfaceCount; /**< Number of contiguous interfaces that are
associated with this function. */
uint8_t bFunctionClass; /**< Class code (assigned by USB-IF). \n
A value of zero is not allowed in this descriptor.
If this field is FFH, the function class is vendorspecific.
All other values are reserved for assignment by
the USB-IF.*/
uint8_t bFunctionSubClass; /**< Subclass code (assigned by USB-IF). \n
If the bFunctionClass field is not set to FFH all
values are reserved for assignment by the USBIF.*/
uint8_t bFunctionProtocol; /**< Protocol code (assigned by the USB). \n
These codes are qualified by the values of the
bFunctionClass and bFunctionSubClass fields.*/
uint8_t iFunction; /**< Index of string descriptor describing this function.*/
} ;
/** USB Standard Interface Association Descriptor */
typedef struct _USB_IAD_DESCRIPTOR USB_IAD_DESCRIPTOR;
/** USB Standard Interface Descriptor */
PRE_PACK struct POST_PACK _USB_INTERFACE_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes*/
uint8_t bDescriptorType; /**< INTERFACE Descriptor Type*/
uint8_t bInterfaceNumber; /**< Number of this interface. Zero-based
value identifying the index in the array of
concurrent interfaces supported by this
configuration.*/
uint8_t bAlternateSetting; /**< Value used to select this alternate setting
for the interface identified in the prior field*/
uint8_t bNumEndpoints; /**< Number of endpoints used by this
interface (excluding endpoint zero). If this
value is zero, this interface only uses the
Default Control Pipe.*/
uint8_t bInterfaceClass; /**< Class code (assigned by the USB-IF). \n
A value of zero is reserved for future
standardization. \n
If this field is set to FFH, the interface
class is vendor-specific. \n
All other values are reserved for
assignment by the USB-IF.*/
uint8_t bInterfaceSubClass; /**< Subclass code (assigned by the USB-IF). \n
These codes are qualified by the value of
the bInterfaceClass field. \n
If the bInterfaceClass field is reset to zero,
this field must also be reset to zero. \n
If the bInterfaceClass field is not set to
FFH, all values are reserved for
assignment by the USB-IF.*/
uint8_t bInterfaceProtocol; /**< Protocol code (assigned by the USB). \n
These codes are qualified by the value of
the bInterfaceClass and the
bInterfaceSubClass fields. If an interface
supports class-specific requests, this code
identifies the protocols that the device
uses as defined by the specification of the
device class. \n
If this field is reset to zero, the device
does not use a class-specific protocol on
this interface. \n
If this field is set to FFH, the device uses
a vendor-specific protocol for this
interface.*/
uint8_t iInterface; /**< Index of string descriptor describing this interface*/
} ;
/** USB Standard Interface Descriptor */
typedef struct _USB_INTERFACE_DESCRIPTOR USB_INTERFACE_DESCRIPTOR;
/** USB Standard Endpoint Descriptor */
PRE_PACK struct POST_PACK _USB_ENDPOINT_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes*/
uint8_t bDescriptorType; /**< ENDPOINT Descriptor Type*/
uint8_t bEndpointAddress; /**< The address of the endpoint on the USB device
described by this descriptor. The address is
encoded as follows: \n
Bit 3...0: The endpoint number \n
Bit 6...4: Reserved, reset to zero \n
Bit 7: Direction, ignored for control endpoints
0 = OUT endpoint
1 = IN endpoint. \n \sa USBD_ENDPOINT_ADR_Type*/
uint8_t bmAttributes; /**< This field describes the endpoint<6E>s attributes when it is
configured using the bConfigurationValue. \n
Bits 1..0: Transfer Type
\li 00 = Control
\li 01 = Isochronous
\li 10 = Bulk
\li 11 = Interrupt \n
If not an isochronous endpoint, bits 5..2 are reserved
and must be set to zero. If isochronous, they are
defined as follows: \n
Bits 3..2: Synchronization Type
\li 00 = No Synchronization
\li 01 = Asynchronous
\li 10 = Adaptive
\li 11 = Synchronous \n
Bits 5..4: Usage Type
\li 00 = Data endpoint
\li 01 = Feedback endpoint
\li 10 = Implicit feedback Data endpoint
\li 11 = Reserved \n
Refer to Chapter 5 of USB 2.0 specification for more information. \n
All other bits are reserved and must be reset to zero.
Reserved bits must be ignored by the host.
\n \sa USBD_EP_ATTR_Type*/
uint16_t wMaxPacketSize; /**< Maximum packet size this endpoint is capable of
sending or receiving when this configuration is
selected. \n
For isochronous endpoints, this value is used to
reserve the bus time in the schedule, required for the
per-(micro)frame data payloads. The pipe may, on an
ongoing basis, actually use less bandwidth than that
reserved. The device reports, if necessary, the actual
bandwidth used via its normal, non-USB defined
mechanisms. \n
For all endpoints, bits 10..0 specify the maximum
packet size (in bytes). \n
For high-speed isochronous and interrupt endpoints: \n
Bits 12..11 specify the number of additional transaction
opportunities per microframe: \n
\li 00 = None (1 transaction per microframe)
\li 01 = 1 additional (2 per microframe)
\li 10 = 2 additional (3 per microframe)
\li 11 = Reserved \n
Bits 15..13 are reserved and must be set to zero.*/
uint8_t bInterval; /**< Interval for polling endpoint for data transfers.
Expressed in frames or microframes depending on the
device operating speed (i.e., either 1 millisecond or
125 <EFBFBD>s units).
\li For full-/high-speed isochronous endpoints, this value
must be in the range from 1 to 16. The bInterval value
is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a
bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$).
\li For full-/low-speed interrupt endpoints, the value of
this field may be from 1 to 255.
\li For high-speed interrupt endpoints, the bInterval value
is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a
bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value
must be from 1 to 16.
\li For high-speed bulk/control OUT endpoints, the
bInterval must specify the maximum NAK rate of the
endpoint. A value of 0 indicates the endpoint never
NAKs. Other values indicate at most 1 NAK each
bInterval number of microframes. This value must be
in the range from 0 to 255. \n
Refer to Chapter 5 of USB 2.0 specification for more information.
*/
} ;
/** USB Standard Endpoint Descriptor */
typedef struct _USB_ENDPOINT_DESCRIPTOR USB_ENDPOINT_DESCRIPTOR;
/** USB String Descriptor */
PRE_PACK struct POST_PACK _USB_STRING_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes*/
uint8_t bDescriptorType; /**< STRING Descriptor Type*/
uint16_t bString/*[]*/; /**< UNICODE encoded string */
} ;
/** USB String Descriptor */
typedef struct _USB_STRING_DESCRIPTOR USB_STRING_DESCRIPTOR;
/** USB Common Descriptor */
PRE_PACK struct POST_PACK _USB_COMMON_DESCRIPTOR
{
uint8_t bLength; /**< Size of this descriptor in bytes*/
uint8_t bDescriptorType; /**< Descriptor Type*/
} ;
/** USB Common Descriptor */
typedef struct _USB_COMMON_DESCRIPTOR USB_COMMON_DESCRIPTOR;
/** USB Other Speed Configuration */
PRE_PACK struct POST_PACK _USB_OTHER_SPEED_CONFIGURATION
{
uint8_t bLength; /**< Size of descriptor*/
uint8_t bDescriptorType; /**< Other_speed_Configuration Type*/
uint16_t wTotalLength; /**< Total length of data returned*/
uint8_t bNumInterfaces; /**< Number of interfaces supported by this speed configuration*/
uint8_t bConfigurationValue; /**< Value to use to select configuration*/
uint8_t IConfiguration; /**< Index of string descriptor*/
uint8_t bmAttributes; /**< Same as Configuration descriptor*/
uint8_t bMaxPower; /**< Same as Configuration descriptor*/
} ;
/** USB Other Speed Configuration */
typedef struct _USB_OTHER_SPEED_CONFIGURATION USB_OTHER_SPEED_CONFIGURATION;
/** \ingroup USBD_Core
* USB device stack/module handle.
*/
typedef void* USBD_HANDLE_T;
#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)
#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF)
#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))
#define USB_CONFIGURATION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))
#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))
#define USB_INTERFACE_ASSOC_DESC_SIZE (sizeof(USB_IAD_DESCRIPTOR))
#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))
#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))
#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))
/** @}*/
#endif /* __USBD_H__ */

377
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_adc.h Normal file
View File

@ -0,0 +1,377 @@
/***********************************************************************
* $Id:: mw_usbd_audio.h 165 2011-04-14 17:41:11Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB Audio Device Class Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __AUDIO_H__
#define __AUDIO_H__
/* Audio Interface Subclass Codes */
#define AUDIO_SUBCLASS_UNDEFINED 0x00
#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01
#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
#define AUDIO_SUBCLASS_MIDISTREAMING 0x03
/* Audio Interface Protocol Codes */
#define AUDIO_PROTOCOL_UNDEFINED 0x00
/* Audio Descriptor Types */
#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20
#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21
#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22
#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23
#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24
#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25
/* Audio Control Interface Descriptor Subtypes */
#define AUDIO_CONTROL_UNDEFINED 0x00
#define AUDIO_CONTROL_HEADER 0x01
#define AUDIO_CONTROL_INPUT_TERMINAL 0x02
#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03
#define AUDIO_CONTROL_MIXER_UNIT 0x04
#define AUDIO_CONTROL_SELECTOR_UNIT 0x05
#define AUDIO_CONTROL_FEATURE_UNIT 0x06
#define AUDIO_CONTROL_PROCESSING_UNIT 0x07
#define AUDIO_CONTROL_EXTENSION_UNIT 0x08
/* Audio Streaming Interface Descriptor Subtypes */
#define AUDIO_STREAMING_UNDEFINED 0x00
#define AUDIO_STREAMING_GENERAL 0x01
#define AUDIO_STREAMING_FORMAT_TYPE 0x02
#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03
/* Audio Endpoint Descriptor Subtypes */
#define AUDIO_ENDPOINT_UNDEFINED 0x00
#define AUDIO_ENDPOINT_GENERAL 0x01
/* Audio Descriptor Sizes */
#define AUDIO_CONTROL_INTERFACE_DESC_SZ(n) 0x08+n
#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07
#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C
#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09
#define AUDIO_MIXER_UNIT_DESC_SZ(p,n) 0x0A+p+n
#define AUDIO_SELECTOR_UNIT_DESC_SZ(p) 0x06+p
#define AUDIO_FEATURE_UNIT_DESC_SZ(ch,n) 0x07+(ch+1)*n
#define AUDIO_PROCESSING_UNIT_DESC_SZ(p,n,x) 0x0D+p+n+x
#define AUDIO_EXTENSION_UNIT_DESC_SZ(p,n) 0x0D+p+n
#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09
#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07
/* Audio Processing Unit Process Types */
#define AUDIO_UNDEFINED_PROCESS 0x00
#define AUDIO_UP_DOWN_MIX_PROCESS 0x01
#define AUDIO_DOLBY_PROLOGIC_PROCESS 0x02
#define AUDIO_3D_STEREO_PROCESS 0x03
#define AUDIO_REVERBERATION_PROCESS 0x04
#define AUDIO_CHORUS_PROCESS 0x05
#define AUDIO_DYN_RANGE_COMP_PROCESS 0x06
/* Audio Request Codes */
#define AUDIO_REQUEST_UNDEFINED 0x00
#define AUDIO_REQUEST_SET_CUR 0x01
#define AUDIO_REQUEST_GET_CUR 0x81
#define AUDIO_REQUEST_SET_MIN 0x02
#define AUDIO_REQUEST_GET_MIN 0x82
#define AUDIO_REQUEST_SET_MAX 0x03
#define AUDIO_REQUEST_GET_MAX 0x83
#define AUDIO_REQUEST_SET_RES 0x04
#define AUDIO_REQUEST_GET_RES 0x84
#define AUDIO_REQUEST_SET_MEM 0x05
#define AUDIO_REQUEST_GET_MEM 0x85
#define AUDIO_REQUEST_GET_STAT 0xFF
/* Audio Control Selector Codes */
#define AUDIO_CONTROL_UNDEFINED 0x00 /* Common Selector */
/* Terminal Control Selectors */
#define AUDIO_COPY_PROTECT_CONTROL 0x01
/* Feature Unit Control Selectors */
#define AUDIO_MUTE_CONTROL 0x01
#define AUDIO_VOLUME_CONTROL 0x02
#define AUDIO_BASS_CONTROL 0x03
#define AUDIO_MID_CONTROL 0x04
#define AUDIO_TREBLE_CONTROL 0x05
#define AUDIO_GRAPHIC_EQUALIZER_CONTROL 0x06
#define AUDIO_AUTOMATIC_GAIN_CONTROL 0x07
#define AUDIO_DELAY_CONTROL 0x08
#define AUDIO_BASS_BOOST_CONTROL 0x09
#define AUDIO_LOUDNESS_CONTROL 0x0A
/* Processing Unit Control Selectors: */
#define AUDIO_ENABLE_CONTROL 0x01 /* Common Selector */
#define AUDIO_MODE_SELECT_CONTROL 0x02 /* Common Selector */
/* - Up/Down-mix Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */
/* - Dolby Prologic Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */
/* - 3D Stereo Extender Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
#define AUDIO_SPACIOUSNESS_CONTROL 0x02
/* - Reverberation Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
#define AUDIO_REVERB_LEVEL_CONTROL 0x02
#define AUDIO_REVERB_TIME_CONTROL 0x03
#define AUDIO_REVERB_FEEDBACK_CONTROL 0x04
/* - Chorus Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
#define AUDIO_CHORUS_LEVEL_CONTROL 0x02
#define AUDIO_SHORUS_RATE_CONTROL 0x03
#define AUDIO_CHORUS_DEPTH_CONTROL 0x04
/* - Dynamic Range Compressor Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
#define AUDIO_COMPRESSION_RATE_CONTROL 0x02
#define AUDIO_MAX_AMPL_CONTROL 0x03
#define AUDIO_THRESHOLD_CONTROL 0x04
#define AUDIO_ATTACK_TIME_CONTROL 0x05
#define AUDIO_RELEASE_TIME_CONTROL 0x06
/* Extension Unit Control Selectors */
/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
/* Endpoint Control Selectors */
#define AUDIO_SAMPLING_FREQ_CONTROL 0x01
#define AUDIO_PITCH_CONTROL 0x02
/* Audio Format Specific Control Selectors */
/* MPEG Control Selectors */
#define AUDIO_MPEG_CONTROL_UNDEFINED 0x00
#define AUDIO_MPEG_DUAL_CHANNEL_CONTROL 0x01
#define AUDIO_MPEG_SECOND_STEREO_CONTROL 0x02
#define AUDIO_MPEG_MULTILINGUAL_CONTROL 0x03
#define AUDIO_MPEG_DYN_RANGE_CONTROL 0x04
#define AUDIO_MPEG_SCALING_CONTROL 0x05
#define AUDIO_MPEG_HILO_SCALING_CONTROL 0x06
/* AC-3 Control Selectors */
#define AUDIO_AC3_CONTROL_UNDEFINED 0x00
#define AUDIO_AC3_MODE_CONTROL 0x01
#define AUDIO_AC3_DYN_RANGE_CONTROL 0x02
#define AUDIO_AC3_SCALING_CONTROL 0x03
#define AUDIO_AC3_HILO_SCALING_CONTROL 0x04
/* Audio Format Types */
#define AUDIO_FORMAT_TYPE_UNDEFINED 0x00
#define AUDIO_FORMAT_TYPE_I 0x01
#define AUDIO_FORMAT_TYPE_II 0x02
#define AUDIO_FORMAT_TYPE_III 0x03
/* Audio Format Type Descriptor Sizes */
#define AUDIO_FORMAT_TYPE_I_DESC_SZ(n) 0x08+(n*3)
#define AUDIO_FORMAT_TYPE_II_DESC_SZ(n) 0x09+(n*3)
#define AUDIO_FORMAT_TYPE_III_DESC_SZ(n) 0x08+(n*3)
#define AUDIO_FORMAT_MPEG_DESC_SIZE 0x09
#define AUDIO_FORMAT_AC3_DESC_SIZE 0x0A
/* Audio Data Format Codes */
/* Audio Data Format Type I Codes */
#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000
#define AUDIO_FORMAT_PCM 0x0001
#define AUDIO_FORMAT_PCM8 0x0002
#define AUDIO_FORMAT_IEEE_FLOAT 0x0003
#define AUDIO_FORMAT_ALAW 0x0004
#define AUDIO_FORMAT_MULAW 0x0005
/* Audio Data Format Type II Codes */
#define AUDIO_FORMAT_TYPE_II_UNDEFINED 0x1000
#define AUDIO_FORMAT_MPEG 0x1001
#define AUDIO_FORMAT_AC3 0x1002
/* Audio Data Format Type III Codes */
#define AUDIO_FORMAT_TYPE_III_UNDEFINED 0x2000
#define AUDIO_FORMAT_IEC1937_AC3 0x2001
#define AUDIO_FORMAT_IEC1937_MPEG1_L1 0x2002
#define AUDIO_FORMAT_IEC1937_MPEG1_L2_3 0x2003
#define AUDIO_FORMAT_IEC1937_MPEG2_NOEXT 0x2003
#define AUDIO_FORMAT_IEC1937_MPEG2_EXT 0x2004
#define AUDIO_FORMAT_IEC1937_MPEG2_L1_LS 0x2005
#define AUDIO_FORMAT_IEC1937_MPEG2_L2_3 0x2006
/* Predefined Audio Channel Configuration Bits */
#define AUDIO_CHANNEL_M 0x0000 /* Mono */
#define AUDIO_CHANNEL_L 0x0001 /* Left Front */
#define AUDIO_CHANNEL_R 0x0002 /* Right Front */
#define AUDIO_CHANNEL_C 0x0004 /* Center Front */
#define AUDIO_CHANNEL_LFE 0x0008 /* Low Freq. Enhance. */
#define AUDIO_CHANNEL_LS 0x0010 /* Left Surround */
#define AUDIO_CHANNEL_RS 0x0020 /* Right Surround */
#define AUDIO_CHANNEL_LC 0x0040 /* Left of Center */
#define AUDIO_CHANNEL_RC 0x0080 /* Right of Center */
#define AUDIO_CHANNEL_S 0x0100 /* Surround */
#define AUDIO_CHANNEL_SL 0x0200 /* Side Left */
#define AUDIO_CHANNEL_SR 0x0400 /* Side Right */
#define AUDIO_CHANNEL_T 0x0800 /* Top */
/* Feature Unit Control Bits */
#define AUDIO_CONTROL_MUTE 0x0001
#define AUDIO_CONTROL_VOLUME 0x0002
#define AUDIO_CONTROL_BASS 0x0004
#define AUDIO_CONTROL_MID 0x0008
#define AUDIO_CONTROL_TREBLE 0x0010
#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020
#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040
#define AUDIO_CONTROL_DEALY 0x0080
#define AUDIO_CONTROL_BASS_BOOST 0x0100
#define AUDIO_CONTROL_LOUDNESS 0x0200
/* Processing Unit Control Bits: */
#define AUDIO_CONTROL_ENABLE 0x0001 /* Common Bit */
#define AUDIO_CONTROL_MODE_SELECT 0x0002 /* Common Bit */
/* - Up/Down-mix Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */
/* - Dolby Prologic Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */
/* - 3D Stereo Extender Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
#define AUDIO_CONTROL_SPACIOUSNESS 0x0002
/* - Reverberation Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
#define AUDIO_CONTROL_REVERB_TYPE 0x0002
#define AUDIO_CONTROL_REVERB_LEVEL 0x0004
#define AUDIO_CONTROL_REVERB_TIME 0x0008
#define AUDIO_CONTROL_REVERB_FEEDBACK 0x0010
/* - Chorus Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
#define AUDIO_CONTROL_CHORUS_LEVEL 0x0002
#define AUDIO_CONTROL_SHORUS_RATE 0x0004
#define AUDIO_CONTROL_CHORUS_DEPTH 0x0008
/* - Dynamic Range Compressor Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
#define AUDIO_CONTROL_COMPRESSION_RATE 0x0002
#define AUDIO_CONTROL_MAX_AMPL 0x0004
#define AUDIO_CONTROL_THRESHOLD 0x0008
#define AUDIO_CONTROL_ATTACK_TIME 0x0010
#define AUDIO_CONTROL_RELEASE_TIME 0x0020
/* Extension Unit Control Bits */
/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
/* Endpoint Control Bits */
#define AUDIO_CONTROL_SAMPLING_FREQ 0x01
#define AUDIO_CONTROL_PITCH 0x02
#define AUDIO_MAX_PACKETS_ONLY 0x80
/* Audio Terminal Types */
/* USB Terminal Types */
#define AUDIO_TERMINAL_USB_UNDEFINED 0x0100
#define AUDIO_TERMINAL_USB_STREAMING 0x0101
#define AUDIO_TERMINAL_USB_VENDOR_SPECIFIC 0x01FF
/* Input Terminal Types */
#define AUDIO_TERMINAL_INPUT_UNDEFINED 0x0200
#define AUDIO_TERMINAL_MICROPHONE 0x0201
#define AUDIO_TERMINAL_DESKTOP_MICROPHONE 0x0202
#define AUDIO_TERMINAL_PERSONAL_MICROPHONE 0x0203
#define AUDIO_TERMINAL_OMNI_DIR_MICROPHONE 0x0204
#define AUDIO_TERMINAL_MICROPHONE_ARRAY 0x0205
#define AUDIO_TERMINAL_PROCESSING_MIC_ARRAY 0x0206
/* Output Terminal Types */
#define AUDIO_TERMINAL_OUTPUT_UNDEFINED 0x0300
#define AUDIO_TERMINAL_SPEAKER 0x0301
#define AUDIO_TERMINAL_HEADPHONES 0x0302
#define AUDIO_TERMINAL_HEAD_MOUNTED_AUDIO 0x0303
#define AUDIO_TERMINAL_DESKTOP_SPEAKER 0x0304
#define AUDIO_TERMINAL_ROOM_SPEAKER 0x0305
#define AUDIO_TERMINAL_COMMUNICATION_SPEAKER 0x0306
#define AUDIO_TERMINAL_LOW_FREQ_SPEAKER 0x0307
/* Bi-directional Terminal Types */
#define AUDIO_TERMINAL_BIDIRECTIONAL_UNDEFINED 0x0400
#define AUDIO_TERMINAL_HANDSET 0x0401
#define AUDIO_TERMINAL_HEAD_MOUNTED_HANDSET 0x0402
#define AUDIO_TERMINAL_SPEAKERPHONE 0x0403
#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOSUPRESS 0x0404
#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOCANCEL 0x0405
/* Telephony Terminal Types */
#define AUDIO_TERMINAL_TELEPHONY_UNDEFINED 0x0500
#define AUDIO_TERMINAL_PHONE_LINE 0x0501
#define AUDIO_TERMINAL_TELEPHONE 0x0502
#define AUDIO_TERMINAL_DOWN_LINE_PHONE 0x0503
/* External Terminal Types */
#define AUDIO_TERMINAL_EXTERNAL_UNDEFINED 0x0600
#define AUDIO_TERMINAL_ANALOG_CONNECTOR 0x0601
#define AUDIO_TERMINAL_DIGITAL_AUDIO_INTERFACE 0x0602
#define AUDIO_TERMINAL_LINE_CONNECTOR 0x0603
#define AUDIO_TERMINAL_LEGACY_AUDIO_CONNECTOR 0x0604
#define AUDIO_TERMINAL_SPDIF_INTERFACE 0x0605
#define AUDIO_TERMINAL_1394_DA_STREAM 0x0606
#define AUDIO_TERMINAL_1394_DA_STREAM_TRACK 0x0607
/* Embedded Function Terminal Types */
#define AUDIO_TERMINAL_EMBEDDED_UNDEFINED 0x0700
#define AUDIO_TERMINAL_CALIBRATION_NOISE 0x0701
#define AUDIO_TERMINAL_EQUALIZATION_NOISE 0x0702
#define AUDIO_TERMINAL_CD_PLAYER 0x0703
#define AUDIO_TERMINAL_DAT 0x0704
#define AUDIO_TERMINAL_DCC 0x0705
#define AUDIO_TERMINAL_MINI_DISK 0x0706
#define AUDIO_TERMINAL_ANALOG_TAPE 0x0707
#define AUDIO_TERMINAL_PHONOGRAPH 0x0708
#define AUDIO_TERMINAL_VCR_AUDIO 0x0709
#define AUDIO_TERMINAL_VIDEO_DISC_AUDIO 0x070A
#define AUDIO_TERMINAL_DVD_AUDIO 0x070B
#define AUDIO_TERMINAL_TV_TUNER_AUDIO 0x070C
#define AUDIO_TERMINAL_SATELLITE_RECEIVER_AUDIO 0x070D
#define AUDIO_TERMINAL_CABLE_TUNER_AUDIO 0x070E
#define AUDIO_TERMINAL_DSS_AUDIO 0x070F
#define AUDIO_TERMINAL_RADIO_RECEIVER 0x0710
#define AUDIO_TERMINAL_RADIO_TRANSMITTER 0x0711
#define AUDIO_TERMINAL_MULTI_TRACK_RECORDER 0x0712
#define AUDIO_TERMINAL_SYNTHESIZER 0x0713
#endif /* __AUDIO_H__ */

249
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_cdc.h Normal file
View File

@ -0,0 +1,249 @@
/***********************************************************************
* $Id:: mw_usbd_cdc.h 165 2011-04-14 17:41:11Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB Communication Device Class User module Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __CDC_H
#define __CDC_H
#include "usbd.h"
/*----------------------------------------------------------------------------
* Definitions based on usbcdc11.pdf (www.usb.org)
*---------------------------------------------------------------------------*/
/* Communication device class specification version 1.10 */
#define CDC_V1_10 0x0110
/* Communication interface class code */
/* (usbcdc11.pdf, 4.2, Table 15) */
#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02
/* Communication interface class subclass codes */
/* (usbcdc11.pdf, 4.3, Table 16) */
#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01
#define CDC_ABSTRACT_CONTROL_MODEL 0x02
#define CDC_TELEPHONE_CONTROL_MODEL 0x03
#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04
#define CDC_CAPI_CONTROL_MODEL 0x05
#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06
#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07
/* Communication interface class control protocol codes */
/* (usbcdc11.pdf, 4.4, Table 17) */
#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01
/* Data interface class code */
/* (usbcdc11.pdf, 4.5, Table 18) */
#define CDC_DATA_INTERFACE_CLASS 0x0A
/* Data interface class protocol codes */
/* (usbcdc11.pdf, 4.7, Table 19) */
#define CDC_PROTOCOL_ISDN_BRI 0x30
#define CDC_PROTOCOL_HDLC 0x31
#define CDC_PROTOCOL_TRANSPARENT 0x32
#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50
#define CDC_PROTOCOL_Q921_DATA_LINK 0x51
#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52
#define CDC_PROTOCOL_V42 0x90
#define CDC_PROTOCOL_EURO_ISDN 0x91
#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92
#define CDC_PROTOCOL_CAPI 0x93
#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD
#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE
/* Type values for bDescriptorType field of functional descriptors */
/* (usbcdc11.pdf, 5.2.3, Table 24) */
#define CDC_CS_INTERFACE 0x24
#define CDC_CS_ENDPOINT 0x25
/* Type values for bDescriptorSubtype field of functional descriptors */
/* (usbcdc11.pdf, 5.2.3, Table 25) */
#define CDC_HEADER 0x00
#define CDC_CALL_MANAGEMENT 0x01
#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02
#define CDC_DIRECT_LINE_MANAGEMENT 0x03
#define CDC_TELEPHONE_RINGER 0x04
#define CDC_REPORTING_CAPABILITIES 0x05
#define CDC_UNION 0x06
#define CDC_COUNTRY_SELECTION 0x07
#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08
#define CDC_USB_TERMINAL 0x09
#define CDC_NETWORK_CHANNEL 0x0A
#define CDC_PROTOCOL_UNIT 0x0B
#define CDC_EXTENSION_UNIT 0x0C
#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D
#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E
#define CDC_ETHERNET_NETWORKING 0x0F
#define CDC_ATM_NETWORKING 0x10
/* CDC class-specific request codes */
/* (usbcdc11.pdf, 6.2, Table 46) */
/* see Table 45 for info about the specific requests. */
#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define CDC_SET_COMM_FEATURE 0x02
#define CDC_GET_COMM_FEATURE 0x03
#define CDC_CLEAR_COMM_FEATURE 0x04
#define CDC_SET_AUX_LINE_STATE 0x10
#define CDC_SET_HOOK_STATE 0x11
#define CDC_PULSE_SETUP 0x12
#define CDC_SEND_PULSE 0x13
#define CDC_SET_PULSE_TIME 0x14
#define CDC_RING_AUX_JACK 0x15
#define CDC_SET_LINE_CODING 0x20
#define CDC_GET_LINE_CODING 0x21
#define CDC_SET_CONTROL_LINE_STATE 0x22
#define CDC_SEND_BREAK 0x23
#define CDC_SET_RINGER_PARMS 0x30
#define CDC_GET_RINGER_PARMS 0x31
#define CDC_SET_OPERATION_PARMS 0x32
#define CDC_GET_OPERATION_PARMS 0x33
#define CDC_SET_LINE_PARMS 0x34
#define CDC_GET_LINE_PARMS 0x35
#define CDC_DIAL_DIGITS 0x36
#define CDC_SET_UNIT_PARAMETER 0x37
#define CDC_GET_UNIT_PARAMETER 0x38
#define CDC_CLEAR_UNIT_PARAMETER 0x39
#define CDC_GET_PROFILE 0x3A
#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define CDC_SET_ETHERNET_PMP_FILTER 0x41
#define CDC_GET_ETHERNET_PMP_FILTER 0x42
#define CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define CDC_GET_ETHERNET_STATISTIC 0x44
#define CDC_SET_ATM_DATA_FORMAT 0x50
#define CDC_GET_ATM_DEVICE_STATISTICS 0x51
#define CDC_SET_ATM_DEFAULT_VC 0x52
#define CDC_GET_ATM_VC_STATISTICS 0x53
/* Communication feature selector codes */
/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */
#define CDC_ABSTRACT_STATE 0x01
#define CDC_COUNTRY_SETTING 0x02
/* Feature Status returned for ABSTRACT_STATE Selector */
/* (usbcdc11.pdf, 6.2.3, Table 48) */
#define CDC_IDLE_SETTING (1 << 0)
#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
/* Control signal bitmap values for the SetControlLineState request */
/* (usbcdc11.pdf, 6.2.14, Table 51) */
#define CDC_DTE_PRESENT (1 << 0)
#define CDC_ACTIVATE_CARRIER (1 << 1)
/* CDC class-specific notification codes */
/* (usbcdc11.pdf, 6.3, Table 68) */
/* see Table 67 for Info about class-specific notifications */
#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
#define CDC_RESPONSE_AVAILABLE 0x01
#define CDC_AUX_JACK_HOOK_STATE 0x08
#define CDC_RING_DETECT 0x09
#define CDC_NOTIFICATION_SERIAL_STATE 0x20
#define CDC_CALL_STATE_CHANGE 0x28
#define CDC_LINE_STATE_CHANGE 0x29
#define CDC_CONNECTION_SPEED_CHANGE 0x2A
/* UART state bitmap values (Serial state notification). */
/* (usbcdc11.pdf, 6.3.5, Table 69) */
#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */
#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */
#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */
#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */
#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */
#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */
#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */
/*----------------------------------------------------------------------------
* Structures based on usbcdc11.pdf (www.usb.org)
*---------------------------------------------------------------------------*/
/* Header functional descriptor */
/* (usbcdc11.pdf, 5.2.3.1) */
/* This header must precede any list of class-specific descriptors. */
PRE_PACK struct POST_PACK _CDC_HEADER_DESCRIPTOR{
uint8_t bFunctionLength; /* size of this descriptor in bytes */
uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */
uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */
uint16_t bcdCDC; /* USB CDC specification release version */
};
typedef struct _CDC_HEADER_DESCRIPTOR CDC_HEADER_DESCRIPTOR;
/* Call management functional descriptor */
/* (usbcdc11.pdf, 5.2.3.2) */
/* Describes the processing of calls for the communication class interface. */
PRE_PACK struct POST_PACK _CDC_CALL_MANAGEMENT_DESCRIPTOR {
uint8_t bFunctionLength; /* size of this descriptor in bytes */
uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */
uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */
uint8_t bmCapabilities; /* capabilities that this configuration supports */
uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */
};
typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR CDC_CALL_MANAGEMENT_DESCRIPTOR;
/* Abstract control management functional descriptor */
/* (usbcdc11.pdf, 5.2.3.3) */
/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */
PRE_PACK struct POST_PACK _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {
uint8_t bFunctionLength; /* size of this descriptor in bytes */
uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */
uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */
uint8_t bmCapabilities; /* capabilities supported by this configuration */
};
typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;
/* Union functional descriptors */
/* (usbcdc11.pdf, 5.2.3.8) */
/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */
PRE_PACK struct POST_PACK _CDC_UNION_DESCRIPTOR {
uint8_t bFunctionLength; /* size of this descriptor in bytes */
uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */
uint8_t bDescriptorSubtype; /* union functional descriptor subtype */
uint8_t bMasterInterface; /* interface number designated as master */
};
typedef struct _CDC_UNION_DESCRIPTOR CDC_UNION_DESCRIPTOR;
/* Union functional descriptors with one slave interface */
/* (usbcdc11.pdf, 5.2.3.8) */
PRE_PACK struct POST_PACK _CDC_UNION_1SLAVE_DESCRIPTOR {
CDC_UNION_DESCRIPTOR sUnion; /* Union functional descriptor */
uint8_t bSlaveInterfaces[1]; /* Slave interface 0 */
};
typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR CDC_UNION_1SLAVE_DESCRIPTOR;
/* Line coding structure */
/* Format of the data returned when a GetLineCoding request is received */
/* (usbcdc11.pdf, 6.2.13) */
PRE_PACK struct POST_PACK _CDC_LINE_CODING {
uint32_t dwDTERate; /* Data terminal rate in bits per second */
uint8_t bCharFormat; /* Number of stop bits */
uint8_t bParityType; /* Parity bit type */
uint8_t bDataBits; /* Number of data bits */
};
typedef struct _CDC_LINE_CODING CDC_LINE_CODING;
/* Notification header */
/* Data sent on the notification endpoint must follow this header. */
/* see USB_SETUP_PACKET in file usb.h */
typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;
#endif /* __CDC_H */

529
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_cdcuser.h Normal file
View File

@ -0,0 +1,529 @@
/***********************************************************************
* $Id:: mw_usbd_cdcuser.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB Communication Device Class User module Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __CDCUSER_H__
#define __CDCUSER_H__
#include "error.h"
#include "usbd.h"
#include "usbd_cdc.h"
/** \file
* \brief Communication Device Class (CDC) API structures and function prototypes.
*
* Definition of functions exported by ROM based CDC function driver.
*
*/
/** \ingroup Group_USBD
* @defgroup USBD_CDC Communication Device Class (CDC) Function Driver
* \section Sec_CDCModDescription Module Description
* CDC Class Function Driver module. This module contains an internal implementation of the USB CDC Class.
*
* User applications can use this class driver instead of implementing the CDC-ACM class manually
* via the low-level USBD_HW and USBD_Core APIs.
*
* This module is designed to simplify the user code by exposing only the required interface needed to interface with
* Devices using the USB CDC-ACM Class.
*/
/*----------------------------------------------------------------------------
We need a buffer for incoming data on USB port because USB receives
much faster than UART transmits
*---------------------------------------------------------------------------*/
/* Buffer masks */
#define CDC_BUF_SIZE (128) /* Output buffer in bytes (power 2) */
/* large enough for file transfer */
#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)
/** \brief Communication Device Class function driver initialization parameter data structure.
* \ingroup USBD_CDC
*
* \details This data structure is used to pass initialization parameters to the
* Communication Device Class function driver's init function.
*
*/
typedef struct USBD_CDC_INIT_PARAM
{
/* memory allocation params */
uint32_t mem_base; /**< Base memory location from where the stack can allocate
data and buffers. \note The memory address set in this field
should be accessible by USB DMA controller. Also this value
should be aligned on 4 byte boundary.
*/
uint32_t mem_size; /**< The size of memory buffer which stack can use.
\note The \em mem_size should be greater than the size
returned by USBD_CDC_API::GetMemSize() routine.*/
/** Pointer to the control interface descriptor within the descriptor
* array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T
* structure. The stack assumes both HS and FS use same BULK endpoints.
*/
uint8_t* cif_intf_desc;
/** Pointer to the data interface descriptor within the descriptor
* array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T
* structure. The stack assumes both HS and FS use same BULK endpoints.
*/
uint8_t* dif_intf_desc;
/* user defined functions */
/* required functions */
/**
* Communication Interface Class specific get request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends CIC management element get requests.
* \note Applications implementing Abstract Control Model subclass can set this
* param to NULL. As the default driver parses ACM requests and calls the
* individual ACM call-back routines defined in this structure. For all other subclasses
* this routine should be provided by the application.
* \n
* The setup packet data (\em pSetup) is passed to the call-back so that application
* can extract the CIC request type and other associated data. By default the stack
* will assign \em pBuffer pointer to \em EP0Buff allocated at init. The application
* code can directly write data into this buffer as long as data is less than 64 byte.
* If more data has to be sent then application code should update \em pBuffer pointer
* and length accordingly.
*
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in, out] pBuffer Pointer to a pointer of data buffer containing request data.
* Pointer-to-pointer is used to implement zero-copy buffers.
* See \ref USBD_ZeroCopy for more details on zero-copy concept.
* \param[in, out] length Amount of data to be sent back to host.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);
/**
* Communication Interface Class specific set request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a CIC management element requests.
* \note Applications implementing Abstract Control Model subclass can set this
* param to NULL. As the default driver parses ACM requests and calls the
* individual ACM call-back routines defined in this structure. For all other subclasses
* this routine should be provided by the application.
* \n
* The setup packet data (\em pSetup) is passed to the call-back so that application can
* extract the CIC request type and other associated data. If a set request has data associated,
* then this call-back is called twice.
* -# First when setup request is received, at this time application code could update
* \em pBuffer pointer to point to the intended destination. The length param is set to 0
* so that application code knows this is first time. By default the stack will
* assign \em pBuffer pointer to \em EP0Buff allocated at init. Note, if data length is
* greater than 64 bytes and application code doesn't update \em pBuffer pointer the
* stack will send STALL condition to host.
* -# Second when the data is received from the host. This time the length param is set
* with number of data bytes received.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in, out] pBuffer Pointer to a pointer of data buffer containing request data.
* Pointer-to-pointer is used to implement zero-copy buffers.
* See \ref USBD_ZeroCopy for more details on zero-copy concept.
* \param[in] length Amount of data copied to destination buffer.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);
/**
* Communication Device Class specific BULK IN endpoint handler.
*
* The application software should provide the BULK IN endpoint handler.
* Applications should transfer data depending on the communication protocol type set in descriptors.
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*CDC_BulkIN_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
/**
* Communication Device Class specific BULK OUT endpoint handler.
*
* The application software should provide the BULK OUT endpoint handler.
* Applications should transfer data depending on the communication protocol type set in descriptors.
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*CDC_BulkOUT_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
/**
* Abstract control model(ACM) subclass specific SEND_ENCAPSULATED_COMMAND request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a SEND_ENCAPSULATED_COMMAND set request.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] buffer Pointer to the command buffer.
* \param[in] len Length of the command buffer.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len);
/**
* Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a GET_ENCAPSULATED_RESPONSE request.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in, out] buffer Pointer to a pointer of data buffer containing response data.
* Pointer-to-pointer is used to implement zero-copy buffers.
* See \ref USBD_ZeroCopy for more details on zero-copy concept.
* \param[in, out] len Amount of data to be sent back to host.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len);
/**
* Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a SET_COMM_FEATURE set request.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.
* \param[in] buffer Pointer to the settings buffer for the specified communication feature.
* \param[in] len Length of the request buffer.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len);
/**
* Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a GET_ENCAPSULATED_RESPONSE request.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.
* \param[in, out] buffer Pointer to a pointer of data buffer containing current settings
* for the communication feature.
* Pointer-to-pointer is used to implement zero-copy buffers.
* \param[in, out] len Amount of data to be sent back to host.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len);
/**
* Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a CLEAR_COMM_FEATURE request. In the call-back the application
* should Clears the settings for a particular communication feature.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature);
/**
* Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a SET_CONTROL_LINE_STATE request. RS-232 signal used to tell the DCE
* device the DTE device is now present
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] state The state value uses bitmap values defined in usbcdc11.pdf,
* section 6.2.14, Table 51.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state);
/**
* Abstract control model(ACM) subclass specific SEND_BREAK request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a SEND_BREAK request.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] mstime Duration of Break signal in milliseconds. If mstime is FFFFh, then
* the application should send break until another SendBreak request is received
* with the wValue of 0000h.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t mstime);
/**
* Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function.
*
* This function is provided by the application software. This function gets called
* when host sends a SET_LINE_CODING request. The application should configure the device
* per DTE rate, stop-bits, parity, and number-of-character bits settings provided in
* command buffer. See usbcdc11.pdf, section 6.2.13, table 50 for detail of the command buffer.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] line_coding Pointer to the CDC_LINE_CODING command buffer.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding);
/**
* Optional Communication Device Class specific INTERRUPT IN endpoint handler.
*
* The application software should provide the INT IN endpoint handler.
* Applications should transfer data depending on the communication protocol type set in descriptors.
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*CDC_InterruptEP_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
/**
* Optional user override-able function to replace the default CDC class handler.
*
* The application software could override the default EP0 class handler with their
* own by providing the handler function address as this data member of the parameter
* structure. Application which like the default handler should set this data member
* to zero before calling the USBD_CDC_API::Init().
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*CDC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
} USBD_CDC_INIT_PARAM_T;
/** \brief CDC class API functions structure.
* \ingroup USBD_CDC
*
* This module exposes functions which interact directly with USB device controller hardware.
*
*/
typedef struct USBD_CDC_API
{
/** \fn uint32_t GetMemSize(USBD_CDC_INIT_PARAM_T* param)
* Function to determine the memory required by the CDC function driver module.
*
* This function is called by application layer before calling pUsbApi->CDC->Init(), to allocate memory used
* by CDC function driver module. The application should allocate the memory which is accessible by USB
* controller/DMA controller.
* \note Some memory areas are not accessible by all bus masters.
*
* \param[in] param Structure containing CDC function driver module initialization parameters.
* \return Returns the required memory size in bytes.
*/
uint32_t (*GetMemSize)(USBD_CDC_INIT_PARAM_T* param);
/** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param)
* Function to initialize CDC function driver module.
*
* This function is called by application layer to initialize CDC function driver module.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in, out] param Structure containing CDC function driver module initialization parameters.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte
* aligned or smaller than required.
* \retval ERR_API_INVALID_PARAM2 Either CDC_Write() or CDC_Read() or
* CDC_Verify() callbacks are not defined.
* \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.
* \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed.
*/
ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC);
/** \fn ErrorCode_t SendNotification(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data)
* Function to send CDC class notifications to host.
*
* This function is called by application layer to send CDC class notifications to host.
* See usbcdc11.pdf, section 6.3, Table 67 for various notification types the CDC device can send.
* \note The current version of the driver only supports following notifications allowed by ACM subclass:
* CDC_NOTIFICATION_NETWORK_CONNECTION, CDC_RESPONSE_AVAILABLE, CDC_NOTIFICATION_SERIAL_STATE.
* \n
* For all other notifications application should construct the notification buffer appropriately
* and call hw->USB_WriteEP() for interrupt endpoint associated with the interface.
*
* \param[in] hCdc Handle to CDC function driver.
* \param[in] bNotification Notification type allowed by ACM subclass. Should be CDC_NOTIFICATION_NETWORK_CONNECTION,
* CDC_RESPONSE_AVAILABLE or CDC_NOTIFICATION_SERIAL_STATE. For all other types ERR_API_INVALID_PARAM2
* is returned. See usbcdc11.pdf, section 3.6.2.1, table 5.
* \param[in] data Data associated with notification.
* \n For CDC_NOTIFICATION_NETWORK_CONNECTION a non-zero data value is interpreted as connected state.
* \n For CDC_RESPONSE_AVAILABLE this parameter is ignored.
* \n For CDC_NOTIFICATION_SERIAL_STATE the data should use bitmap values defined in usbcdc11.pdf,
* section 6.3.5, Table 69.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_API_INVALID_PARAM2 If unsupported notification type is passed.
*
*/
ErrorCode_t (*SendNotification)(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data);
} USBD_CDC_API_T;
/*-----------------------------------------------------------------------------
* Private functions & structures prototypes
*-----------------------------------------------------------------------------*/
/** @cond ADVANCED_API */
typedef struct _CDC_CTRL_T
{
USB_CORE_CTRL_T* pUsbCtrl;
/* notification buffer */
uint8_t notice_buf[12];
CDC_LINE_CODING line_coding;
uint8_t pad0;
uint8_t cif_num; /* control interface number */
uint8_t dif_num; /* data interface number */
uint8_t epin_num; /* BULK IN endpoint number */
uint8_t epout_num; /* BULK OUT endpoint number */
uint8_t epint_num; /* Interrupt IN endpoint number */
uint8_t pad[3];
/* user defined functions */
ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len);
ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len);
ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len);
ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len);
ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature);
ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state);
ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t state);
ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding);
/* virtual functions */
ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);
ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);
} USB_CDC_CTRL_T;
/* structure used by old ROM drivers, needed for workaround */
typedef struct _CDC0_CTRL_T {
USB_CORE_CTRL_T *pUsbCtrl;
/* notification buffer */
uint8_t notice_buf[12];
CDC_LINE_CODING line_coding;
uint8_t cif_num; /* control interface number */
uint8_t dif_num; /* data interface number */
uint8_t epin_num; /* BULK IN endpoint number */
uint8_t epout_num; /* BULK OUT endpoint number */
uint8_t epint_num; /* Interrupt IN endpoint number */
/* user defined functions */
ErrorCode_t (*SendEncpsCmd)(USBD_HANDLE_T hCDC, uint8_t *buffer, uint16_t len);
ErrorCode_t (*GetEncpsResp)(USBD_HANDLE_T hCDC, uint8_t * *buffer, uint16_t *len);
ErrorCode_t (*SetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t *buffer, uint16_t len);
ErrorCode_t (*GetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t * *pBuffer, uint16_t *len);
ErrorCode_t (*ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature);
ErrorCode_t (*SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state);
ErrorCode_t (*SendBreak)(USBD_HANDLE_T hCDC, uint16_t state);
ErrorCode_t (*SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding);
/* virtual functions */
ErrorCode_t (*CIC_GetRequest)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t * *pBuffer, uint16_t *length);
ErrorCode_t (*CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t * *pBuffer, uint16_t length);
} USB_CDC0_CTRL_T;
typedef ErrorCode_t (*CIC_SetRequest_t)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t * *pBuffer, uint16_t length);
/** @cond DIRECT_API */
extern uint32_t mwCDC_GetMemSize(USBD_CDC_INIT_PARAM_T* param);
extern ErrorCode_t mwCDC_init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC);
extern ErrorCode_t mwCDC_SendNotification (USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data);
/** @endcond */
/** @endcond */
#endif /* __CDCUSER_H__ */

585
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_core.h Normal file
View File

@ -0,0 +1,585 @@
/***********************************************************************
* $Id:: mw_usbd_core.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB core controller structure definitions and function prototypes.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __MW_USBD_CORE_H__
#define __MW_USBD_CORE_H__
#include "error.h"
#include "usbd.h"
#include "app_usbd_cfg.h"
/** \file
* \brief ROM API for USB device stack.
*
* Definition of functions exported by core layer of ROM based USB device stack.
*
*/
/** \ingroup Group_USBD
* @defgroup USBD_Core USB Core Layer
* \section Sec_CoreModDescription Module Description
* The USB Core Layer implements the device abstraction defined in the <em> Universal Serial Bus Specification, </em>
* for applications to interact with the USB device interface on the device. The software in this layer responds to
* standard requests and returns standard descriptors. In current stack the Init() routine part of
* \ref USBD_HW_API_T structure initializes both hardware layer and core layer.
*/
/* function pointer types */
/** \ingroup USBD_Core
* \typedef USB_CB_T
* \brief USB device stack's event callback function type.
*
* The USB device stack exposes several event triggers through callback to application layer. The
* application layer can register methods to be called when such USB event happens.
*
* \param[in] hUsb Handle to the USB device stack.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx Other error conditions.
*
*/
typedef ErrorCode_t (*USB_CB_T) (USBD_HANDLE_T hUsb);
/** \ingroup USBD_Core
* \typedef USB_PARAM_CB_T
* \brief USB device stack's event callback function type.
*
* The USB device stack exposes several event triggers through callback to application layer. The
* application layer can register methods to be called when such USB event happens.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] param1 Extra information related to the event.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
typedef ErrorCode_t (*USB_PARAM_CB_T) (USBD_HANDLE_T hUsb, uint32_t param1);
/** \ingroup USBD_Core
* \typedef USB_EP_HANDLER_T
* \brief USBD setup request and endpoint event handler type.
*
* The application layer should define the custom class's EP0 handler with function signature.
* The stack calls all the registered class handlers on any EP0 event before going through default
* handling of the event. This gives the class handlers to implement class specific request handlers
* and also to override the default stack handling for a particular event targeted to the interface.
* If an event is not handled by the callback the function should return ERR_USBD_UNHANDLED. For all
* other return codes the stack assumes that callback has taken care of the event and hence will not
* process the event any further and issues a STALL condition on EP0 indicating error to the host.
* \n
* For endpoint interrupt handler the return value is ignored by the stack.
* \n
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
typedef ErrorCode_t (*USB_EP_HANDLER_T)(USBD_HANDLE_T hUsb, void* data, uint32_t event);
/** \ingroup USBD_Core
* \brief USB descriptors data structure.
* \ingroup USBD_Core
*
* \details This structure is used as part of USB device stack initialization
* parameter structure \ref USBD_API_INIT_PARAM_T. This structure contains
* pointers to various descriptor arrays needed by the stack. These descriptors
* are reported to USB host as part of enumerations process.
*
* \note All descriptor pointers assigned in this structure should be on 4 byte
* aligned address boundary.
*/
typedef struct _USB_CORE_DESCS_T
{
uint8_t *device_desc; /**< Pointer to USB device descriptor */
uint8_t *string_desc; /**< Pointer to array of USB string descriptors */
uint8_t *full_speed_desc; /**< Pointer to USB device configuration descriptor
* when device is operating in full speed mode.
*/
uint8_t *high_speed_desc; /**< Pointer to USB device configuration descriptor
* when device is operating in high speed mode. For
* full-speed only implementation this pointer should
* be same as full_speed_desc.
*/
uint8_t *device_qualifier; /**< Pointer to USB device qualifier descriptor. For
* full-speed only implementation this pointer should
* be set to null (0).
*/
} USB_CORE_DESCS_T;
/** \brief USB device stack initialization parameter data structure.
* \ingroup USBD_Core
*
* \details This data structure is used to pass initialization parameters to the
* USB device stack's init function.
*
*/
typedef struct USBD_API_INIT_PARAM
{
uint32_t usb_reg_base; /**< USB device controller's base register address. */
uint32_t mem_base; /**< Base memory location from where the stack can allocate
data and buffers. \note The memory address set in this field
should be accessible by USB DMA controller. Also this value
should be aligned on 2048 byte boundary.
*/
uint32_t mem_size; /**< The size of memory buffer which stack can use.
\note The \em mem_size should be greater than the size
returned by USBD_HW_API::GetMemSize() routine.*/
uint8_t max_num_ep; /**< max number of endpoints supported by the USB device
controller instance (specified by \em usb_reg_base field)
to which this instance of stack is attached.
*/
uint8_t pad0[3];
/* USB Device Events Callback Functions */
/** Event for USB interface reset. This event fires when the USB host requests that the device
* reset its interface. This event fires after the control endpoint has been automatically
* configured by the library.
* \n
* \note This event is called from USB_ISR context and hence is time-critical. Having delays in this
* callback will prevent the device from enumerating correctly or operate properly.
*
*/
USB_CB_T USB_Reset_Event;
/** Event for USB suspend. This event fires when the USB host suspends the device by halting its
* transmission of Start Of Frame pulses to the device. This is generally hooked in order to move
* the device over to a low power state until the host wakes up the device.
* \n
* \note This event is called from USB_ISR context and hence is time-critical. Having delays in this
* callback will cause other system issues.
*/
USB_CB_T USB_Suspend_Event;
/** Event for USB wake up or resume. This event fires when a the USB device interface is suspended
* and the host wakes up the device by supplying Start Of Frame pulses. This is generally
* hooked to pull the user application out of a low power state and back into normal operating
* mode.
* \n
* \note This event is called from USB_ISR context and hence is time-critical. Having delays in this
* callback will cause other system issues.
*
*/
USB_CB_T USB_Resume_Event;
/** Reserved parameter should be set to zero. */
USB_CB_T reserved_sbz;
/** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB
* frame, once per millisecond in full-speed mode or once per 125 microseconds in high-speed mode,
* and is synchronized to the USB bus.
*
* This event is time-critical; it is run once per millisecond (full-speed mode) and thus long handlers
* will significantly degrade device performance. This event should only be enabled when needed to
* reduce device wake-ups.
*
* \note This event is not normally active - it must be manually enabled and disabled via the USB interrupt
* register.
* \n\n
*/
USB_CB_T USB_SOF_Event;
/** Event for remote wake-up configuration, when enabled. This event fires when the USB host
* request the device to configure itself for remote wake-up capability. The USB host sends
* this request to device which report remote wake-up capable in their device descriptors,
* before going to low-power state. The application layer should implement this callback if
* they have any special on board circuit to trigger remote wake up event. Also application
* can use this callback to differentiate the following SUSPEND event is caused by cable plug-out
* or host SUSPEND request. The device can wake-up host only after receiving this callback and
* remote wake-up feature is enabled by host. To signal remote wake-up the device has to generate
* resume signaling on bus by calling usapi.hw->WakeUp() routine.
*
* \n\n
* \param[in] hUsb Handle to the USB device stack.
* \param[in] param1 When 0 - Clear the wake-up configuration, 1 - Enable the wake-up configuration.
* \return The call back should return \ref ErrorCode_t type to indicate success or error condition.
*/
USB_PARAM_CB_T USB_WakeUpCfg;
/** Reserved parameter should be set to zero. */
USB_PARAM_CB_T USB_Power_Event;
/** Event for error condition. This event fires when USB device controller detect
* an error condition in the system.
*
* \n\n
* \param[in] hUsb Handle to the USB device stack.
* \param[in] param1 USB device interrupt status register.
* \return The call back should return \ref ErrorCode_t type to indicate success or error condition.
*/
USB_PARAM_CB_T USB_Error_Event;
/* USB Core Events Callback Functions */
/** Event for USB configuration number changed. This event fires when a the USB host changes the
* selected configuration number. On receiving configuration change request from host, the stack
* enables/configures the endpoints needed by the new configuration before calling this callback
* function.
* \n
* \note This event is called from USB_ISR context and hence is time-critical. Having delays in this
* callback will prevent the device from enumerating correctly or operate properly.
*
*/
USB_CB_T USB_Configure_Event;
/** Event for USB interface setting changed. This event fires when a the USB host changes the
* interface setting to one of alternate interface settings. On receiving interface change
* request from host, the stack enables/configures the endpoints needed by the new alternate
* interface setting before calling this callback function.
* \n
* \note This event is called from USB_ISR context and hence is time-critical. Having delays in this
* callback will prevent the device from enumerating correctly or operate properly.
*
*/
USB_CB_T USB_Interface_Event;
/** Event for USB feature changed. This event fires when a the USB host send set/clear feature
* request. The stack handles this request for USB_FEATURE_REMOTE_WAKEUP, USB_FEATURE_TEST_MODE
* and USB_FEATURE_ENDPOINT_STALL features only. On receiving feature request from host, the
* stack handle the request appropriately and then calls this callback function.
* \n
* \note This event is called from USB_ISR context and hence is time-critical. Having delays in this
* callback will prevent the device from enumerating correctly or operate properly.
*
*/
USB_CB_T USB_Feature_Event;
/* cache and MMU translation functions */
/** Reserved parameter for future use. should be set to zero. */
uint32_t (* virt_to_phys)(void* vaddr);
/** Reserved parameter for future use. should be set to zero. */
void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr);
} USBD_API_INIT_PARAM_T;
/** \brief USBD stack Core API functions structure.
* \ingroup USBD_Core
*
* \details This module exposes functions which interact directly with USB device stack's core layer.
* The application layer uses this component when it has to implement custom class function driver or
* standard class function driver which is not part of the current USB device stack.
* The functions exposed by this interface are to register class specific EP0 handlers and corresponding
* utility functions to manipulate EP0 state machine of the stack. This interface also exposes
* function to register custom endpoint interrupt handler.
*
*/
typedef struct USBD_CORE_API
{
/** \fn ErrorCode_t RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data)
* Function to register class specific EP0 event handler with USB device stack.
*
* The application layer uses this function when it has to register the custom class's EP0 handler.
* The stack calls all the registered class handlers on any EP0 event before going through default
* handling of the event. This gives the class handlers to implement class specific request handlers
* and also to override the default stack handling for a particular event targeted to the interface.
* Check \ref USB_EP_HANDLER_T for more details on how the callback function should be implemented. Also
* application layer could use this function to register EP0 handler which responds to vendor specific
* requests.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] pfn Class specific EP0 handler function.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) The number of class handlers registered is
greater than the number of handlers allowed by the stack.
*
*/
ErrorCode_t (*RegisterClassHandler)(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);
/** \fn ErrorCode_t RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data)
* Function to register interrupt/event handler for the requested endpoint with USB device stack.
*
* The application layer uses this function to register the endpoint event handler.
* The stack calls all the registered endpoint handlers when
* - USB_EVT_OUT or USB_EVT_OUT_NAK events happen for OUT endpoint.
* - USB_EVT_IN or USB_EVT_IN_NAK events happen for IN endpoint.
* Check USB_EP_HANDLER_T for more details on how the callback function should be implemented.
* \note By default endpoint _NAK events are not enabled. Application should call \ref USBD_HW_API_T::EnableEvent
* for the corresponding endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] ep_index Endpoint index. Computed as
* - For OUT endpoints = 2 * endpoint number eg. for EP2_OUT it is 4.
* - For IN endopoints = (2 * endpoint number) + 1 eg. for EP2_IN it is 5.
* \param[in] pfn Endpoint event handler function.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_API_INVALID_PARAM2 ep_index is outside the boundary ( < 2 * USBD_API_INIT_PARAM_T::max_num_ep).
*
*/
ErrorCode_t (*RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);
/** \fn void SetupStage(USBD_HANDLE_T hUsb)
* Function to set EP0 state machine in setup state.
*
* This function is called by USB stack and the application layer to
* set the EP0 state machine in setup state. This function will read
* the setup packet received from USB host into stack's buffer.
* \n
* \note This interface is provided to users to invoke this function in other
* scenarios which are not handle by current stack. In most user applications
* this function is not called directly.Also this function can be used by
* users who are selectively modifying the USB device stack's standard handlers
* through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*SetupStage )(USBD_HANDLE_T hUsb);
/** \fn void DataInStage(USBD_HANDLE_T hUsb)
* Function to set EP0 state machine in data_in state.
*
* This function is called by USB stack and the application layer to
* set the EP0 state machine in data_in state. This function will write
* the data present in EP0Data buffer to EP0 FIFO for transmission to host.
* \n
* \note This interface is provided to users to invoke this function in other
* scenarios which are not handle by current stack. In most user applications
* this function is not called directly.Also this function can be used by
* users who are selectively modifying the USB device stack's standard handlers
* through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*DataInStage)(USBD_HANDLE_T hUsb);
/** \fn void DataOutStage(USBD_HANDLE_T hUsb)
* Function to set EP0 state machine in data_out state.
*
* This function is called by USB stack and the application layer to
* set the EP0 state machine in data_out state. This function will read
* the control data (EP0 out packets) received from USB host into EP0Data buffer.
* \n
* \note This interface is provided to users to invoke this function in other
* scenarios which are not handle by current stack. In most user applications
* this function is not called directly.Also this function can be used by
* users who are selectively modifying the USB device stack's standard handlers
* through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*DataOutStage)(USBD_HANDLE_T hUsb);
/** \fn void StatusInStage(USBD_HANDLE_T hUsb)
* Function to set EP0 state machine in status_in state.
*
* This function is called by USB stack and the application layer to
* set the EP0 state machine in status_in state. This function will send
* zero length IN packet on EP0 to host, indicating positive status.
* \n
* \note This interface is provided to users to invoke this function in other
* scenarios which are not handle by current stack. In most user applications
* this function is not called directly.Also this function can be used by
* users who are selectively modifying the USB device stack's standard handlers
* through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*StatusInStage)(USBD_HANDLE_T hUsb);
/** \fn void StatusOutStage(USBD_HANDLE_T hUsb)
* Function to set EP0 state machine in status_out state.
*
* This function is called by USB stack and the application layer to
* set the EP0 state machine in status_out state. This function will read
* the zero length OUT packet received from USB host on EP0.
* \n
* \note This interface is provided to users to invoke this function in other
* scenarios which are not handle by current stack. In most user applications
* this function is not called directly.Also this function can be used by
* users who are selectively modifying the USB device stack's standard handlers
* through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*StatusOutStage)(USBD_HANDLE_T hUsb);
/** \fn void StallEp0(USBD_HANDLE_T hUsb)
* Function to set EP0 state machine in stall state.
*
* This function is called by USB stack and the application layer to
* generate STALL signaling on EP0 endpoint. This function will also
* reset the EP0Data buffer.
* \n
* \note This interface is provided to users to invoke this function in other
* scenarios which are not handle by current stack. In most user applications
* this function is not called directly.Also this function can be used by
* users who are selectively modifying the USB device stack's standard handlers
* through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*StallEp0)(USBD_HANDLE_T hUsb);
} USBD_CORE_API_T;
/*-----------------------------------------------------------------------------
* Private functions & structures prototypes
*-----------------------------------------------------------------------------*/
/** @cond ADVANCED_API */
/* forward declaration */
struct _USB_CORE_CTRL_T;
typedef struct _USB_CORE_CTRL_T USB_CORE_CTRL_T;
/* USB device Speed status defines */
#define USB_FULL_SPEED 0
#define USB_HIGH_SPEED 1
/* USB Endpoint Data Structure */
typedef struct _USB_EP_DATA
{
uint8_t *pData;
uint16_t Count;
uint16_t pad0;
} USB_EP_DATA;
/* USB core controller data structure */
struct _USB_CORE_CTRL_T
{
/* override-able function pointers ~ c++ style virtual functions*/
USB_CB_T USB_EvtSetupHandler;
USB_CB_T USB_EvtOutHandler;
USB_PARAM_CB_T USB_ReqVendor;
USB_CB_T USB_ReqGetStatus;
USB_CB_T USB_ReqGetDescriptor;
USB_CB_T USB_ReqGetConfiguration;
USB_CB_T USB_ReqSetConfiguration;
USB_CB_T USB_ReqGetInterface;
USB_CB_T USB_ReqSetInterface;
USB_PARAM_CB_T USB_ReqSetClrFeature;
/* USB Device Events Callback Functions */
USB_CB_T USB_Reset_Event;
USB_CB_T USB_Suspend_Event;
USB_CB_T USB_Resume_Event;
USB_CB_T USB_SOF_Event;
USB_PARAM_CB_T USB_Power_Event;
USB_PARAM_CB_T USB_Error_Event;
USB_PARAM_CB_T USB_WakeUpCfg;
/* USB Core Events Callback Functions */
USB_CB_T USB_Configure_Event;
USB_CB_T USB_Interface_Event;
USB_CB_T USB_Feature_Event;
/* cache and MMU translation functions */
uint32_t (* virt_to_phys)(void* vaddr);
void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr);
/* event handlers for endpoints. */
USB_EP_HANDLER_T ep_event_hdlr[2 * USB_MAX_EP_NUM];
void* ep_hdlr_data[2 * USB_MAX_EP_NUM];
/* USB class handlers */
USB_EP_HANDLER_T ep0_hdlr_cb[USB_MAX_IF_NUM];
void* ep0_cb_data[USB_MAX_IF_NUM];
uint8_t num_ep0_hdlrs;
/* USB Core data Variables */
uint8_t max_num_ep; /* max number of endpoints supported by the HW */
uint8_t device_speed;
uint8_t num_interfaces;
uint8_t device_addr;
uint8_t config_value;
uint16_t device_status;
uint8_t *device_desc;
uint8_t *string_desc;
uint8_t *full_speed_desc;
uint8_t *high_speed_desc;
uint8_t *device_qualifier;
uint32_t ep_mask;
uint32_t ep_halt;
uint32_t ep_stall;
uint8_t alt_setting[USB_MAX_IF_NUM];
/* HW driver data pointer */
void* hw_data;
/* USB Endpoint 0 Data Info */
USB_EP_DATA EP0Data;
/* USB Endpoint 0 Buffer */
//ALIGNED(4)
uint8_t EP0Buf[64];
/* USB Setup Packet */
//ALIGNED(4)
USB_SETUP_PACKET SetupPacket;
};
/* USB Core Functions */
extern void mwUSB_InitCore(USB_CORE_CTRL_T* pCtrl, USB_CORE_DESCS_T* pdescr, USBD_API_INIT_PARAM_T* param);
extern void mwUSB_ResetCore(USBD_HANDLE_T hUsb);
/* inline functions */
static INLINE void USB_SetSpeedMode(USB_CORE_CTRL_T* pCtrl, uint8_t mode)
{
pCtrl->device_speed = mode;
}
static INLINE bool USB_IsConfigured(USBD_HANDLE_T hUsb)
{
USB_CORE_CTRL_T* pCtrl = (USB_CORE_CTRL_T*) hUsb;
return (bool) (pCtrl->config_value != 0);
}
/** @cond DIRECT_API */
/* midleware API */
extern ErrorCode_t mwUSB_RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);
extern ErrorCode_t mwUSB_RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);
extern void mwUSB_SetupStage (USBD_HANDLE_T hUsb);
extern void mwUSB_DataInStage(USBD_HANDLE_T hUsb);
extern void mwUSB_DataOutStage(USBD_HANDLE_T hUsb);
extern void mwUSB_StatusInStage(USBD_HANDLE_T hUsb);
extern void mwUSB_StatusOutStage(USBD_HANDLE_T hUsb);
extern void mwUSB_StallEp0(USBD_HANDLE_T hUsb);
extern ErrorCode_t mwUSB_RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);
extern ErrorCode_t mwUSB_RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);
extern void mwUSB_SetupStage (USBD_HANDLE_T hUsb);
extern void mwUSB_DataInStage(USBD_HANDLE_T hUsb);
extern void mwUSB_DataOutStage(USBD_HANDLE_T hUsb);
extern void mwUSB_StatusInStage(USBD_HANDLE_T hUsb);
extern void mwUSB_StatusOutStage(USBD_HANDLE_T hUsb);
extern void mwUSB_StallEp0(USBD_HANDLE_T hUsb);
/** @endcond */
/** @endcond */
#endif /* __MW_USBD_CORE_H__ */

48
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_desc.h Normal file
View File

@ -0,0 +1,48 @@
/***********************************************************************
* $Id:: mw_usbd_desc.h 165 2011-04-14 17:41:11Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB Descriptors Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __USBDESC_H__
#define __USBDESC_H__
#include "usbd.h"
#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)
#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF)
#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))
#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))
#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))
#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))
#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))
#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))
//#define HID_DESC_SIZE (sizeof(HID_DESCRIPTOR))
//#define HID_REPORT_DESC_SIZE (sizeof(HID_ReportDescriptor))
extern const uint8_t HID_ReportDescriptor[];
extern const uint16_t HID_ReportDescSize;
extern const uint16_t HID_DescOffset;
#endif /* __USBDESC_H__ */

120
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_dfu.h Normal file
View File

@ -0,0 +1,120 @@
/***********************************************************************
* $Id:: mw_usbd_dfu.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* Device Firmware Upgrade (DFU) module.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __MW_USBD_DFU_H__
#define __MW_USBD_DFU_H__
#include "usbd.h"
/** \file
* \brief Device Firmware Upgrade (DFU) class descriptors.
*
* Definition of DFU class descriptors and their bit defines.
*
*/
/**
* If USB device is only DFU capable, DFU Interface number is always 0.
* if USB device is (DFU + Other Class (Audio/Mass Storage/HID), DFU
* Interface number should also be 0 in this implementation.
*/
#define USB_DFU_IF_NUM 0x0
#define USB_DFU_DESCRIPTOR_TYPE 0x21
#define USB_DFU_DESCRIPTOR_SIZE 9
#define USB_DFU_SUBCLASS 0x01
/* DFU class-specific requests (Section 3, DFU Rev 1.1) */
#define USB_REQ_DFU_DETACH 0x00
#define USB_REQ_DFU_DNLOAD 0x01
#define USB_REQ_DFU_UPLOAD 0x02
#define USB_REQ_DFU_GETSTATUS 0x03
#define USB_REQ_DFU_CLRSTATUS 0x04
#define USB_REQ_DFU_GETSTATE 0x05
#define USB_REQ_DFU_ABORT 0x06
#define DFU_STATUS_OK 0x00
#define DFU_STATUS_errTARGET 0x01
#define DFU_STATUS_errFILE 0x02
#define DFU_STATUS_errWRITE 0x03
#define DFU_STATUS_errERASE 0x04
#define DFU_STATUS_errCHECK_ERASED 0x05
#define DFU_STATUS_errPROG 0x06
#define DFU_STATUS_errVERIFY 0x07
#define DFU_STATUS_errADDRESS 0x08
#define DFU_STATUS_errNOTDONE 0x09
#define DFU_STATUS_errFIRMWARE 0x0a
#define DFU_STATUS_errVENDOR 0x0b
#define DFU_STATUS_errUSBR 0x0c
#define DFU_STATUS_errPOR 0x0d
#define DFU_STATUS_errUNKNOWN 0x0e
#define DFU_STATUS_errSTALLEDPKT 0x0f
enum dfu_state {
DFU_STATE_appIDLE = 0,
DFU_STATE_appDETACH = 1,
DFU_STATE_dfuIDLE = 2,
DFU_STATE_dfuDNLOAD_SYNC = 3,
DFU_STATE_dfuDNBUSY = 4,
DFU_STATE_dfuDNLOAD_IDLE = 5,
DFU_STATE_dfuMANIFEST_SYNC = 6,
DFU_STATE_dfuMANIFEST = 7,
DFU_STATE_dfuMANIFEST_WAIT_RST= 8,
DFU_STATE_dfuUPLOAD_IDLE = 9,
DFU_STATE_dfuERROR = 10
};
#define DFU_EP0_NONE 0
#define DFU_EP0_UNHANDLED 1
#define DFU_EP0_STALL 2
#define DFU_EP0_ZLP 3
#define DFU_EP0_DATA 4
#define USB_DFU_CAN_DOWNLOAD (1 << 0)
#define USB_DFU_CAN_UPLOAD (1 << 1)
#define USB_DFU_MANIFEST_TOL (1 << 2)
#define USB_DFU_WILL_DETACH (1 << 3)
PRE_PACK struct POST_PACK _USB_DFU_FUNC_DESCRIPTOR {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bmAttributes;
uint16_t wDetachTimeOut;
uint16_t wTransferSize;
uint16_t bcdDFUVersion;
};
typedef struct _USB_DFU_FUNC_DESCRIPTOR USB_DFU_FUNC_DESCRIPTOR;
PRE_PACK struct POST_PACK _DFU_STATUS {
uint8_t bStatus;
uint8_t bwPollTimeout[3];
uint8_t bState;
uint8_t iString;
};
typedef struct _DFU_STATUS DFU_STATUS_T;
#define DFU_FUNC_DESC_SIZE sizeof(USB_DFU_FUNC_DESCRIPTOR)
#define DFU_GET_STATUS_SIZE 0x6
#endif /* __MW_USBD_DFU_H__ */

270
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_dfuuser.h Normal file
View File

@ -0,0 +1,270 @@
/***********************************************************************
* $Id:: mw_usbd_dfuuser.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* Device Firmware Upgrade Class Custom User Module Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __DFUUSER_H__
#define __DFUUSER_H__
#include "usbd.h"
#include "usbd_dfu.h"
#include "usbd_core.h"
/** \file
* \brief Device Firmware Upgrade (DFU) API structures and function prototypes.
*
* Definition of functions exported by ROM based DFU function driver.
*
*/
/** \ingroup Group_USBD
* @defgroup USBD_DFU Device Firmware Upgrade (DFU) Class Function Driver
* \section Sec_MSCModDescription Module Description
* DFU Class Function Driver module. This module contains an internal implementation of the USB DFU Class.
* User applications can use this class driver instead of implementing the DFU class manually
* via the low-level USBD_HW and USBD_Core APIs.
*
* This module is designed to simplify the user code by exposing only the required interface needed to interface with
* Devices using the USB DFU Class.
*/
/** \brief USB descriptors data structure.
* \ingroup USBD_DFU
*
* \details This module exposes functions which interact directly with USB device stack's core layer.
* The application layer uses this component when it has to implement custom class function driver or
* standard class function driver which is not part of the current USB device stack.
* The functions exposed by this interface are to register class specific EP0 handlers and corresponding
* utility functions to manipulate EP0 state machine of the stack. This interface also exposes
* function to register custom endpoint interrupt handler.
*
*/
typedef struct USBD_DFU_INIT_PARAM
{
/* memory allocation params */
uint32_t mem_base; /**< Base memory location from where the stack can allocate
data and buffers. \note The memory address set in this field
should be accessible by USB DMA controller. Also this value
should be aligned on 4 byte boundary.
*/
uint32_t mem_size; /**< The size of memory buffer which stack can use.
\note The \em mem_size should be greater than the size
returned by USBD_DFU_API::GetMemSize() routine.*/
/* DFU paramas */
uint16_t wTransferSize; /**< DFU transfer block size in number of bytes.
This value should match the value set in DFU descriptor
provided as part of the descriptor array
(\em high_speed_desc) passed to Init() through
\ref USB_CORE_DESCS_T structure. */
uint16_t pad;
/** Pointer to the DFU interface descriptor within the descriptor
* array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T
* structure.
*/
uint8_t* intf_desc;
/* user defined functions */
/**
* DFU Write callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a write command. For application using zero-copy buffer scheme
* this function is called for the first time with \em length parameter set to 0.
* The application code should update the buffer pointer.
*
* \param[in] block_num Destination start address.
* \param[in, out] src Pointer to a pointer to the source of data. Pointer-to-pointer
* is used to implement zero-copy buffers. See \ref USBD_ZeroCopy
* for more details on zero-copy concept.
* \param[out] bwPollTimeout Pointer to a 3 byte buffer which the callback implementer
* should fill with the amount of minimum time, in milliseconds,
* that the host should wait before sending a subsequent
* DFU_GETSTATUS request.
* \param[in] length Number of bytes to be written.
* \return Returns DFU_STATUS_ values defined in mw_usbd_dfu.h.
*
*/
uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout);
/**
* DFU Read callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a read command.
*
* \param[in] block_num Destination start address.
* \param[in, out] dst Pointer to a pointer to the source of data. Pointer-to-pointer
* is used to implement zero-copy buffers. See \ref USBD_ZeroCopy
* for more details on zero-copy concept.
* \param[in] length Amount of data copied to destination buffer.
* \return Returns
* - DFU_STATUS_ values defined in mw_usbd_dfu.h to return error conditions.
* - 0 if there is no more data to be read. Stack will send EOF frame and set
* DFU state-machine to dfuIdle state.
* - length of the data copied, should be greater than or equal to 16. If the data copied
* is less than DFU \em wTransferSize the stack will send EOF frame and
* goes to dfuIdle state.
*
*/
uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length);
/**
* DFU done callback function.
*
* This function is provided by the application software. This function gets called
* after firmware download completes.
*
* \return Nothing.
*
*/
void (*DFU_Done)(void);
/**
* DFU detach callback function.
*
* This function is provided by the application software. This function gets called
* after USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH
* bit in DFU descriptor should define this function. As part of this function
* application can call Connect() routine to disconnect and then connect back with
* host. For application which rely on WinUSB based host application should use this
* feature since USB reset can be invoked only by kernel drivers on Windows host.
* By implementing this feature host doen't have to issue reset instead the device
* has to do it automatically by disconnect and connect procedure.
*
* \param[in] hUsb Handle DFU control structure.
* \return Nothing.
*
*/
void (*DFU_Detach)(USBD_HANDLE_T hUsb);
/**
* Optional user override-able function to replace the default DFU class handler.
*
* The application software could override the default EP0 class handler with their
* own by providing the handler function address as this data member of the parameter
* structure. Application which like the default handler should set this data member
* to zero before calling the USBD_DFU_API::Init().
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*DFU_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
} USBD_DFU_INIT_PARAM_T;
/** \brief DFU class API functions structure.
* \ingroup USBD_DFU
*
* This module exposes functions which interact directly with USB device controller hardware.
*
*/
typedef struct USBD_DFU_API
{
/** \fn uint32_t GetMemSize(USBD_DFU_INIT_PARAM_T* param)
* Function to determine the memory required by the DFU function driver module.
*
* This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used
* by DFU function driver module. The application should allocate the memory which is accessible by USB
* controller/DMA controller.
* \note Some memory areas are not accessible by all bus masters.
*
* \param[in] param Structure containing DFU function driver module initialization parameters.
* \return Returns the required memory size in bytes.
*/
uint32_t (*GetMemSize)(USBD_DFU_INIT_PARAM_T* param);
/** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param)
* Function to initialize DFU function driver module.
*
* This function is called by application layer to initialize DFU function driver module.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in, out] param Structure containing DFU function driver module initialization parameters.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte aligned or smaller than required.
* \retval ERR_API_INVALID_PARAM2 Either DFU_Write() or DFU_Done() or DFU_Read() call-backs are not defined.
* \retval ERR_USBD_BAD_DESC
* - USB_DFU_DESCRIPTOR_TYPE is not defined immediately after
* interface descriptor.
* - wTransferSize in descriptor doesn't match the value passed
* in param->wTransferSize.
* - DFU_Detach() is not defined while USB_DFU_WILL_DETACH is set
* in DFU descriptor.
* \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.
*/
ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state);
} USBD_DFU_API_T;
/*-----------------------------------------------------------------------------
* Private functions & structures prototypes
*-----------------------------------------------------------------------------*/
/** @cond ADVANCED_API */
typedef struct _USBD_DFU_CTRL_T
{
/*ALIGNED(4)*/ DFU_STATUS_T dfu_req_get_status;
uint16_t pad;
uint8_t dfu_state;
uint8_t dfu_status;
uint8_t download_done;
uint8_t if_num; /* interface number */
uint8_t* xfr_buf;
USB_DFU_FUNC_DESCRIPTOR* dfu_desc;
USB_CORE_CTRL_T* pUsbCtrl;
/* user defined functions */
/* return DFU_STATUS_ values defined in mw_usbd_dfu.h */
uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout);
/* return
* DFU_STATUS_ : values defined in mw_usbd_dfu.h in case of errors
* 0 : If end of memory reached
* length : Amount of data copied to destination buffer
*/
uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length);
/* callback called after download is finished */
void (*DFU_Done)(void);
/* callback called after USB_REQ_DFU_DETACH is recived */
void (*DFU_Detach)(USBD_HANDLE_T hUsb);
} USBD_DFU_CTRL_T;
/** @cond DIRECT_API */
uint32_t mwDFU_GetMemSize(USBD_DFU_INIT_PARAM_T* param);
extern ErrorCode_t mwDFU_init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state);
/** @endcond */
/** @endcond */
#endif /* __DFUUSER_H__ */

430
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_hid.h Normal file
View File

@ -0,0 +1,430 @@
/***********************************************************************
* $Id: mw_usbd_hid.h.rca 1.2 Tue Nov 1 11:45:07 2011 nlv09221 Experimental $
*
* Project: USB device ROM Stack
*
* Description:
* HID Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __HID_H__
#define __HID_H__
#include "usbd.h"
/** \file
* \brief Common definitions and declarations for the library USB HID Class driver.
*
* Common definitions and declarations for the library USB HID Class driver.
* \addtogroup USBD_HID
* @{
*/
/** HID Subclass Codes
* @{
*/
/** Descriptor Subclass value indicating that the device or interface does not implement a HID boot protocol. */
#define HID_SUBCLASS_NONE 0x00
/** Descriptor Subclass value indicating that the device or interface implements a HID boot protocol. */
#define HID_SUBCLASS_BOOT 0x01
/** @} */
/** HID Protocol Codes
* @{
*/
/** Descriptor Protocol value indicating that the device or interface does not belong to a HID boot protocol. */
#define HID_PROTOCOL_NONE 0x00
/** Descriptor Protocol value indicating that the device or interface belongs to the Keyboard HID boot protocol. */
#define HID_PROTOCOL_KEYBOARD 0x01
/** Descriptor Protocol value indicating that the device or interface belongs to the Mouse HID boot protocol. */
#define HID_PROTOCOL_MOUSE 0x02
/** @} */
/** Descriptor Types
* @{
*/
/** Descriptor header type value, to indicate a HID class HID descriptor. */
#define HID_HID_DESCRIPTOR_TYPE 0x21
/** Descriptor header type value, to indicate a HID class HID report descriptor. */
#define HID_REPORT_DESCRIPTOR_TYPE 0x22
/** Descriptor header type value, to indicate a HID class HID Physical descriptor. */
#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23
/** @} */
/** \brief HID class-specific HID Descriptor.
*
* Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID
* specification for details on the structure elements.
*
*/
PRE_PACK struct POST_PACK _HID_DESCRIPTOR {
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of HID descriptor. */
uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. */
uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */
uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */
PRE_PACK struct POST_PACK _HID_DESCRIPTOR_LIST {
uint8_t bDescriptorType; /**< Type of HID report. */
uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */
} DescriptorList[1]; /**< Array of one or more descriptors */
} ;
/** HID class-specific HID Descriptor. */
typedef struct _HID_DESCRIPTOR HID_DESCRIPTOR;
#define HID_DESC_SIZE sizeof(HID_DESCRIPTOR)
/** HID Request Codes
* @{
*/
#define HID_REQUEST_GET_REPORT 0x01
#define HID_REQUEST_GET_IDLE 0x02
#define HID_REQUEST_GET_PROTOCOL 0x03
#define HID_REQUEST_SET_REPORT 0x09
#define HID_REQUEST_SET_IDLE 0x0A
#define HID_REQUEST_SET_PROTOCOL 0x0B
/** @} */
/** HID Report Types
* @{
*/
#define HID_REPORT_INPUT 0x01
#define HID_REPORT_OUTPUT 0x02
#define HID_REPORT_FEATURE 0x03
/** @} */
/** Usage Pages
* @{
*/
#define HID_USAGE_PAGE_UNDEFINED 0x00
#define HID_USAGE_PAGE_GENERIC 0x01
#define HID_USAGE_PAGE_SIMULATION 0x02
#define HID_USAGE_PAGE_VR 0x03
#define HID_USAGE_PAGE_SPORT 0x04
#define HID_USAGE_PAGE_GAME 0x05
#define HID_USAGE_PAGE_DEV_CONTROLS 0x06
#define HID_USAGE_PAGE_KEYBOARD 0x07
#define HID_USAGE_PAGE_LED 0x08
#define HID_USAGE_PAGE_BUTTON 0x09
#define HID_USAGE_PAGE_ORDINAL 0x0A
#define HID_USAGE_PAGE_TELEPHONY 0x0B
#define HID_USAGE_PAGE_CONSUMER 0x0C
#define HID_USAGE_PAGE_DIGITIZER 0x0D
#define HID_USAGE_PAGE_UNICODE 0x10
#define HID_USAGE_PAGE_ALPHANUMERIC 0x14
/** @} */
/** Generic Desktop Page (0x01)
* @{
*/
#define HID_USAGE_GENERIC_POINTER 0x01
#define HID_USAGE_GENERIC_MOUSE 0x02
#define HID_USAGE_GENERIC_JOYSTICK 0x04
#define HID_USAGE_GENERIC_GAMEPAD 0x05
#define HID_USAGE_GENERIC_KEYBOARD 0x06
#define HID_USAGE_GENERIC_KEYPAD 0x07
#define HID_USAGE_GENERIC_X 0x30
#define HID_USAGE_GENERIC_Y 0x31
#define HID_USAGE_GENERIC_Z 0x32
#define HID_USAGE_GENERIC_RX 0x33
#define HID_USAGE_GENERIC_RY 0x34
#define HID_USAGE_GENERIC_RZ 0x35
#define HID_USAGE_GENERIC_SLIDER 0x36
#define HID_USAGE_GENERIC_DIAL 0x37
#define HID_USAGE_GENERIC_WHEEL 0x38
#define HID_USAGE_GENERIC_HATSWITCH 0x39
#define HID_USAGE_GENERIC_COUNTED_BUFFER 0x3A
#define HID_USAGE_GENERIC_BYTE_COUNT 0x3B
#define HID_USAGE_GENERIC_MOTION_WAKEUP 0x3C
#define HID_USAGE_GENERIC_VX 0x40
#define HID_USAGE_GENERIC_VY 0x41
#define HID_USAGE_GENERIC_VZ 0x42
#define HID_USAGE_GENERIC_VBRX 0x43
#define HID_USAGE_GENERIC_VBRY 0x44
#define HID_USAGE_GENERIC_VBRZ 0x45
#define HID_USAGE_GENERIC_VNO 0x46
#define HID_USAGE_GENERIC_SYSTEM_CTL 0x80
#define HID_USAGE_GENERIC_SYSCTL_POWER 0x81
#define HID_USAGE_GENERIC_SYSCTL_SLEEP 0x82
#define HID_USAGE_GENERIC_SYSCTL_WAKE 0x83
#define HID_USAGE_GENERIC_SYSCTL_CONTEXT_MENU 0x84
#define HID_USAGE_GENERIC_SYSCTL_MAIN_MENU 0x85
#define HID_USAGE_GENERIC_SYSCTL_APP_MENU 0x86
#define HID_USAGE_GENERIC_SYSCTL_HELP_MENU 0x87
#define HID_USAGE_GENERIC_SYSCTL_MENU_EXIT 0x88
#define HID_USAGE_GENERIC_SYSCTL_MENU_SELECT 0x89
#define HID_USAGE_GENERIC_SYSCTL_MENU_RIGHT 0x8A
#define HID_USAGE_GENERIC_SYSCTL_MENU_LEFT 0x8B
#define HID_USAGE_GENERIC_SYSCTL_MENU_UP 0x8C
#define HID_USAGE_GENERIC_SYSCTL_MENU_DOWN 0x8D
/** @} */
/** Simulation Controls Page (0x02)
* @{
*/
#define HID_USAGE_SIMULATION_RUDDER 0xBA
#define HID_USAGE_SIMULATION_THROTTLE 0xBB
/** @} */
/* Virtual Reality Controls Page (0x03) */
/* ... */
/* Sport Controls Page (0x04) */
/* ... */
/* Game Controls Page (0x05) */
/* ... */
/* Generic Device Controls Page (0x06) */
/* ... */
/** Keyboard/Keypad Page (0x07)
* @{
*/
/** Error "keys" */
#define HID_USAGE_KEYBOARD_NOEVENT 0x00
#define HID_USAGE_KEYBOARD_ROLLOVER 0x01
#define HID_USAGE_KEYBOARD_POSTFAIL 0x02
#define HID_USAGE_KEYBOARD_UNDEFINED 0x03
/** Letters */
#define HID_USAGE_KEYBOARD_aA 0x04
#define HID_USAGE_KEYBOARD_zZ 0x1D
/** Numbers */
#define HID_USAGE_KEYBOARD_ONE 0x1E
#define HID_USAGE_KEYBOARD_ZERO 0x27
#define HID_USAGE_KEYBOARD_RETURN 0x28
#define HID_USAGE_KEYBOARD_ESCAPE 0x29
#define HID_USAGE_KEYBOARD_DELETE 0x2A
/** Funtion keys */
#define HID_USAGE_KEYBOARD_F1 0x3A
#define HID_USAGE_KEYBOARD_F12 0x45
#define HID_USAGE_KEYBOARD_PRINT_SCREEN 0x46
/** Modifier Keys */
#define HID_USAGE_KEYBOARD_LCTRL 0xE0
#define HID_USAGE_KEYBOARD_LSHFT 0xE1
#define HID_USAGE_KEYBOARD_LALT 0xE2
#define HID_USAGE_KEYBOARD_LGUI 0xE3
#define HID_USAGE_KEYBOARD_RCTRL 0xE4
#define HID_USAGE_KEYBOARD_RSHFT 0xE5
#define HID_USAGE_KEYBOARD_RALT 0xE6
#define HID_USAGE_KEYBOARD_RGUI 0xE7
#define HID_USAGE_KEYBOARD_SCROLL_LOCK 0x47
#define HID_USAGE_KEYBOARD_NUM_LOCK 0x53
#define HID_USAGE_KEYBOARD_CAPS_LOCK 0x39
/** @} */
/* ... */
/** LED Page (0x08)
* @{
*/
#define HID_USAGE_LED_NUM_LOCK 0x01
#define HID_USAGE_LED_CAPS_LOCK 0x02
#define HID_USAGE_LED_SCROLL_LOCK 0x03
#define HID_USAGE_LED_COMPOSE 0x04
#define HID_USAGE_LED_KANA 0x05
#define HID_USAGE_LED_POWER 0x06
#define HID_USAGE_LED_SHIFT 0x07
#define HID_USAGE_LED_DO_NOT_DISTURB 0x08
#define HID_USAGE_LED_MUTE 0x09
#define HID_USAGE_LED_TONE_ENABLE 0x0A
#define HID_USAGE_LED_HIGH_CUT_FILTER 0x0B
#define HID_USAGE_LED_LOW_CUT_FILTER 0x0C
#define HID_USAGE_LED_EQUALIZER_ENABLE 0x0D
#define HID_USAGE_LED_SOUND_FIELD_ON 0x0E
#define HID_USAGE_LED_SURROUND_FIELD_ON 0x0F
#define HID_USAGE_LED_REPEAT 0x10
#define HID_USAGE_LED_STEREO 0x11
#define HID_USAGE_LED_SAMPLING_RATE_DETECT 0x12
#define HID_USAGE_LED_SPINNING 0x13
#define HID_USAGE_LED_CAV 0x14
#define HID_USAGE_LED_CLV 0x15
#define HID_USAGE_LED_RECORDING_FORMAT_DET 0x16
#define HID_USAGE_LED_OFF_HOOK 0x17
#define HID_USAGE_LED_RING 0x18
#define HID_USAGE_LED_MESSAGE_WAITING 0x19
#define HID_USAGE_LED_DATA_MODE 0x1A
#define HID_USAGE_LED_BATTERY_OPERATION 0x1B
#define HID_USAGE_LED_BATTERY_OK 0x1C
#define HID_USAGE_LED_BATTERY_LOW 0x1D
#define HID_USAGE_LED_SPEAKER 0x1E
#define HID_USAGE_LED_HEAD_SET 0x1F
#define HID_USAGE_LED_HOLD 0x20
#define HID_USAGE_LED_MICROPHONE 0x21
#define HID_USAGE_LED_COVERAGE 0x22
#define HID_USAGE_LED_NIGHT_MODE 0x23
#define HID_USAGE_LED_SEND_CALLS 0x24
#define HID_USAGE_LED_CALL_PICKUP 0x25
#define HID_USAGE_LED_CONFERENCE 0x26
#define HID_USAGE_LED_STAND_BY 0x27
#define HID_USAGE_LED_CAMERA_ON 0x28
#define HID_USAGE_LED_CAMERA_OFF 0x29
#define HID_USAGE_LED_ON_LINE 0x2A
#define HID_USAGE_LED_OFF_LINE 0x2B
#define HID_USAGE_LED_BUSY 0x2C
#define HID_USAGE_LED_READY 0x2D
#define HID_USAGE_LED_PAPER_OUT 0x2E
#define HID_USAGE_LED_PAPER_JAM 0x2F
#define HID_USAGE_LED_REMOTE 0x30
#define HID_USAGE_LED_FORWARD 0x31
#define HID_USAGE_LED_REVERSE 0x32
#define HID_USAGE_LED_STOP 0x33
#define HID_USAGE_LED_REWIND 0x34
#define HID_USAGE_LED_FAST_FORWARD 0x35
#define HID_USAGE_LED_PLAY 0x36
#define HID_USAGE_LED_PAUSE 0x37
#define HID_USAGE_LED_RECORD 0x38
#define HID_USAGE_LED_ERROR 0x39
#define HID_USAGE_LED_SELECTED_INDICATOR 0x3A
#define HID_USAGE_LED_IN_USE_INDICATOR 0x3B
#define HID_USAGE_LED_MULTI_MODE_INDICATOR 0x3C
#define HID_USAGE_LED_INDICATOR_ON 0x3D
#define HID_USAGE_LED_INDICATOR_FLASH 0x3E
#define HID_USAGE_LED_INDICATOR_SLOW_BLINK 0x3F
#define HID_USAGE_LED_INDICATOR_FAST_BLINK 0x40
#define HID_USAGE_LED_INDICATOR_OFF 0x41
#define HID_USAGE_LED_FLASH_ON_TIME 0x42
#define HID_USAGE_LED_SLOW_BLINK_ON_TIME 0x43
#define HID_USAGE_LED_SLOW_BLINK_OFF_TIME 0x44
#define HID_USAGE_LED_FAST_BLINK_ON_TIME 0x45
#define HID_USAGE_LED_FAST_BLINK_OFF_TIME 0x46
#define HID_USAGE_LED_INDICATOR_COLOR 0x47
#define HID_USAGE_LED_RED 0x48
#define HID_USAGE_LED_GREEN 0x49
#define HID_USAGE_LED_AMBER 0x4A
#define HID_USAGE_LED_GENERIC_INDICATOR 0x4B
/** @} */
/* Button Page (0x09)
*/
/* There is no need to label these usages. */
/* Ordinal Page (0x0A)
*/
/* There is no need to label these usages. */
/** Telephony Device Page (0x0B)
* @{
*/
#define HID_USAGE_TELEPHONY_PHONE 0x01
#define HID_USAGE_TELEPHONY_ANSWERING_MACHINE 0x02
#define HID_USAGE_TELEPHONY_MESSAGE_CONTROLS 0x03
#define HID_USAGE_TELEPHONY_HANDSET 0x04
#define HID_USAGE_TELEPHONY_HEADSET 0x05
#define HID_USAGE_TELEPHONY_KEYPAD 0x06
#define HID_USAGE_TELEPHONY_PROGRAMMABLE_BUTTON 0x07
/** @} */
/* ... */
/** Consumer Page (0x0C)
* @{
*/
#define HID_USAGE_CONSUMER_CONTROL 0x01
#define HID_USAGE_CONSUMER_FAST_FORWARD 0xB3
#define HID_USAGE_CONSUMER_REWIND 0xB4
#define HID_USAGE_CONSUMER_PLAY_PAUSE 0xCD
#define HID_USAGE_CONSUMER_VOLUME_INCREMENT 0xE9
#define HID_USAGE_CONSUMER_VOLUME_DECREMENT 0xEA
/** @} */
/* ... */
/* and others ... */
/** HID Report Item Macros
* @{
*/
/** Main Items */
#define HID_Input(x) 0x81,x
#define HID_Output(x) 0x91,x
#define HID_Feature(x) 0xB1,x
#define HID_Collection(x) 0xA1,x
#define HID_EndCollection 0xC0
/** Data (Input, Output, Feature) */
#define HID_Data 0<<0
#define HID_Constant 1<<0
#define HID_Array 0<<1
#define HID_Variable 1<<1
#define HID_Absolute 0<<2
#define HID_Relative 1<<2
#define HID_NoWrap 0<<3
#define HID_Wrap 1<<3
#define HID_Linear 0<<4
#define HID_NonLinear 1<<4
#define HID_PreferredState 0<<5
#define HID_NoPreferred 1<<5
#define HID_NoNullPosition 0<<6
#define HID_NullState 1<<6
#define HID_NonVolatile 0<<7
#define HID_Volatile 1<<7
/** Collection Data */
#define HID_Physical 0x00
#define HID_Application 0x01
#define HID_Logical 0x02
#define HID_Report 0x03
#define HID_NamedArray 0x04
#define HID_UsageSwitch 0x05
#define HID_UsageModifier 0x06
/** Global Items */
#define HID_UsagePage(x) 0x05,x
#define HID_UsagePageVendor(x) 0x06,x,0xFF
#define HID_LogicalMin(x) 0x15,x
#define HID_LogicalMinS(x) 0x16,(x&0xFF),((x>>8)&0xFF)
#define HID_LogicalMinL(x) 0x17,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
#define HID_LogicalMax(x) 0x25,x
#define HID_LogicalMaxS(x) 0x26,(x&0xFF),((x>>8)&0xFF)
#define HID_LogicalMaxL(x) 0x27,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
#define HID_PhysicalMin(x) 0x35,x
#define HID_PhysicalMinS(x) 0x36,(x&0xFF),((x>>8)&0xFF)
#define HID_PhysicalMinL(x) 0x37,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
#define HID_PhysicalMax(x) 0x45,x
#define HID_PhysicalMaxS(x) 0x46,(x&0xFF),((x>>8)&0xFF)
#define HID_PhysicalMaxL(x) 0x47,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
#define HID_UnitExponent(x) 0x55,x
#define HID_Unit(x) 0x65,x
#define HID_UnitS(x) 0x66,(x&0xFF),((x>>8)&0xFF)
#define HID_UnitL(x) 0x67,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
#define HID_ReportSize(x) 0x75,x
#define HID_ReportID(x) 0x85,x
#define HID_ReportCount(x) 0x95,x
#define HID_Push 0xA0
#define HID_Pop 0xB0
/** Local Items */
#define HID_Usage(x) 0x09,x
#define HID_UsageMin(x) 0x19,x
#define HID_UsageMax(x) 0x29,x
/** @} */
/** @} */
#endif /* __HID_H__ */

421
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_hiduser.h Normal file
View File

@ -0,0 +1,421 @@
/***********************************************************************
* $Id:: mw_usbd_hiduser.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* HID Custom User Module Definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __HIDUSER_H__
#define __HIDUSER_H__
#include "usbd.h"
#include "usbd_hid.h"
#include "usbd_core.h"
/** \file
* \brief Human Interface Device (HID) API structures and function prototypes.
*
* Definition of functions exported by ROM based HID function driver.
*
*/
/** \ingroup Group_USBD
* @defgroup USBD_HID HID Class Function Driver
* \section Sec_HIDModDescription Module Description
* HID Class Function Driver module. This module contains an internal implementation of the USB HID Class.
* User applications can use this class driver instead of implementing the HID class manually
* via the low-level HW and core APIs.
*
* This module is designed to simplify the user code by exposing only the required interface needed to interface with
* Devices using the USB HID Class.
*/
/** \brief HID report descriptor data structure.
* \ingroup USBD_HID
*
* \details This structure is used as part of HID function driver initialization
* parameter structure \ref USBD_HID_INIT_PARAM. This structure contains
* details of a report type supported by the application. An application
* can support multiple report types as a single HID device. The application
* should define this report type data structure per report it supports and
* the array of report types to USBD_HID_API::init() through \ref USBD_HID_INIT_PARAM
* structure.
*
* \note All descriptor pointers assigned in this structure should be on 4 byte
* aligned address boundary.
*
*/
typedef struct _HID_REPORT_T {
uint16_t len; /**< Size of the report descriptor in bytes. */
uint8_t idle_time; /**< This value is used by stack to respond to Set_Idle &
GET_Idle requests for the specified report ID. The value
of this field specified the rate at which duplicate reports
are generated for the specified Report ID. For example, a
device with two input reports could specify an idle rate of
20 milliseconds for report ID 1 and 500 milliseconds for
report ID 2.
*/
uint8_t __pad; /**< Padding space. */
uint8_t* desc; /**< Report descriptor. */
} USB_HID_REPORT_T;
/** \brief USB descriptors data structure.
* \ingroup USBD_HID
*
* \details This module exposes functions which interact directly with USB device stack's core layer.
* The application layer uses this component when it has to implement custom class function driver or
* standard class function driver which is not part of the current USB device stack.
* The functions exposed by this interface are to register class specific EP0 handlers and corresponding
* utility functions to manipulate EP0 state machine of the stack. This interface also exposes
* function to register custom endpoint interrupt handler.
*
*/
typedef struct USBD_HID_INIT_PARAM
{
/* memory allocation params */
uint32_t mem_base; /**< Base memory location from where the stack can allocate
data and buffers. \note The memory address set in this field
should be accessible by USB DMA controller. Also this value
should be aligned on 4 byte boundary.
*/
uint32_t mem_size; /**< The size of memory buffer which stack can use.
\note The \em mem_size should be greater than the size
returned by USBD_HID_API::GetMemSize() routine.*/
/* HID paramas */
uint8_t max_reports; /**< Number of HID reports supported by this instance
of HID class driver.
*/
uint8_t pad[3];
uint8_t* intf_desc; /**< Pointer to the HID interface descriptor within the
descriptor array (\em high_speed_desc) passed to Init()
through \ref USB_CORE_DESCS_T structure.
*/
USB_HID_REPORT_T* report_data; /**< Pointer to an array of HID report descriptor
data structure (\ref USB_HID_REPORT_T). The number
of elements in the array should be same a \em max_reports
value. The stack uses this array to respond to
requests received for various HID report descriptor
information. \note This array should be of global scope.
*/
/* user defined functions */
/* required functions */
/**
* HID get report callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a HID_REQUEST_GET_REPORT request. The setup packet data (\em pSetup)
* is passed to the callback so that application can extract the report ID, report
* type and other information need to generate the report. \note HID reports are sent
* via interrupt IN endpoint also. This function is called only when report request
* is received on control endpoint. Application should implement \em HID_EpIn_Hdlr to
* send reports to host via interrupt IN endpoint.
*
*
* \param[in] hHid Handle to HID function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in, out] pBuffer Pointer to a pointer of data buffer containing report data.
* Pointer-to-pointer is used to implement zero-copy buffers.
* See \ref USBD_ZeroCopy for more details on zero-copy concept.
* \param[in] length Amount of data copied to destination buffer.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);
/**
* HID set report callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a HID_REQUEST_SET_REPORT request. The setup packet data (\em pSetup)
* is passed to the callback so that application can extract the report ID, report
* type and other information need to modify the report. An application might choose
* to ignore input Set_Report requests as meaningless. Alternatively these reports
* could be used to reset the origin of a control (that is, current position should
* report zero).
*
* \param[in] hHid Handle to HID function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in, out] pBuffer Pointer to a pointer of data buffer containing report data.
* Pointer-to-pointer is used to implement zero-copy buffers.
* See \ref USBD_ZeroCopy for more details on zero-copy concept.
* \param[in] length Amount of data copied to destination buffer.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);
/* optional functions */
/**
* Optional callback function to handle HID_GetPhysDesc request.
*
* The application software could provide this callback HID_GetPhysDesc handler to
* handle get physical descriptor requests sent by the host. When host requests
* Physical Descriptor set 0, application should return a special descriptor
* identifying the number of descriptor sets and their sizes. A Get_Descriptor
* request with the Physical Index equal to 1 should return the first Physical
* Descriptor set. A device could possibly have alternate uses for its items.
* These can be enumerated by issuing subsequent Get_Descriptor requests while
* incrementing the Descriptor Index. A device should return the last descriptor
* set to requests with an index greater than the last number defined in the HID
* descriptor.
* \note Applications which don't have physical descriptor should set this data member
* to zero before calling the USBD_HID_API::Init().
* \n
*
* \param[in] hHid Handle to HID function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in] pBuf Pointer to a pointer of data buffer containing physical descriptor
* data. If the physical descriptor is in USB accessible memory area
* application could just update the pointer or else it should copy
* the descriptor to the address pointed by this pointer.
* \param[in] length Amount of data copied to destination buffer or descriptor length.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);
/**
* Optional callback function to handle HID_REQUEST_SET_IDLE request.
*
* The application software could provide this callback to handle HID_REQUEST_SET_IDLE
* requests sent by the host. This callback is provided to applications to adjust
* timers associated with various reports, which are sent to host over interrupt
* endpoint. The setup packet data (\em pSetup) is passed to the callback so that
* application can extract the report ID, report type and other information need
* to modify the report's idle time.
* \note Applications which don't send reports on Interrupt endpoint or don't
* have idle time between reports should set this data member to zero before
* calling the USBD_HID_API::Init().
* \n
*
* \param[in] hHid Handle to HID function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in] idleTime Idle time to be set for the specified report.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime);
/**
* Optional callback function to handle HID_REQUEST_SET_PROTOCOL request.
*
* The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL
* requests sent by the host. This callback is provided to applications to adjust
* modes of their code between boot mode and report mode.
* \note Applications which don't support protocol modes should set this data member
* to zero before calling the USBD_HID_API::Init().
* \n
*
* \param[in] hHid Handle to HID function driver.
* \param[in] pSetup Pointer to setup packet received from host.
* \param[in] protocol Protocol mode.
* 0 = Boot Protocol
* 1 = Report Protocol
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol);
/**
* Optional Interrupt IN endpoint event handler.
*
* The application software could provide Interrupt IN endpoint event handler.
* Application which send reports to host on interrupt endpoint should provide
* an endpoint event handler through this data member. This data member is
* ignored if the interface descriptor \em intf_desc doesn't have any IN interrupt
* endpoint descriptor associated.
* \n
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Handle to HID function driver.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should return \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_EpIn_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
/**
* Optional Interrupt OUT endpoint event handler.
*
* The application software could provide Interrupt OUT endpoint event handler.
* Application which receives reports from host on interrupt endpoint should provide
* an endpoint event handler through this data member. This data member is
* ignored if the interface descriptor \em intf_desc doesn't have any OUT interrupt
* endpoint descriptor associated.
* \n
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Handle to HID function driver.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should return \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_EpOut_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
/* user override-able function */
/**
* Optional user override-able function to replace the default HID_GetReportDesc handler.
*
* The application software could override the default HID_GetReportDesc handler with their
* own by providing the handler function address as this data member of the parameter
* structure. Application which like the default handler should set this data member
* to zero before calling the USBD_HID_API::Init() and also provide report data array
* \em report_data field.
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);
/**
* Optional user override-able function to replace the default HID class handler.
*
* The application software could override the default EP0 class handler with their
* own by providing the handler function address as this data member of the parameter
* structure. Application which like the default handler should set this data member
* to zero before calling the USBD_HID_API::Init().
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*HID_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
} USBD_HID_INIT_PARAM_T;
/** \brief HID class API functions structure.
* \ingroup USBD_HID
*
* This structure contains pointers to all the function exposed by HID function driver module.
*
*/
typedef struct USBD_HID_API
{
/** \fn uint32_t GetMemSize(USBD_HID_INIT_PARAM_T* param)
* Function to determine the memory required by the HID function driver module.
*
* This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used
* by HID function driver module. The application should allocate the memory which is accessible by USB
* controller/DMA controller.
* \note Some memory areas are not accessible by all bus masters.
*
* \param[in] param Structure containing HID function driver module initialization parameters.
* \return Returns the required memory size in bytes.
*/
uint32_t (*GetMemSize)(USBD_HID_INIT_PARAM_T* param);
/** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param)
* Function to initialize HID function driver module.
*
* This function is called by application layer to initialize HID function driver
* module. On successful initialization the function returns a handle to HID
* function driver module in passed param structure.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in, out] param Structure containing HID function driver module
* initialization parameters.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte
* aligned or smaller than required.
* \retval ERR_API_INVALID_PARAM2 Either HID_GetReport() or HID_SetReport()
* callback are not defined.
* \retval ERR_USBD_BAD_DESC HID_HID_DESCRIPTOR_TYPE is not defined
* immediately after interface descriptor.
* \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.
* \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed.
*/
ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param);
} USBD_HID_API_T;
/*-----------------------------------------------------------------------------
* Private functions & structures prototypes
*-----------------------------------------------------------------------------*/
/** @cond ADVANCED_API */
typedef struct _HID_CTRL_T {
/* pointer to controller */
USB_CORE_CTRL_T* pUsbCtrl;
/* descriptor pointers */
uint8_t* hid_desc;
USB_HID_REPORT_T* report_data;
uint8_t protocol;
uint8_t if_num; /* interface number */
uint8_t epin_adr; /* IN interrupt endpoint */
uint8_t epout_adr; /* OUT interrupt endpoint */
/* user defined functions */
ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);
ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);
ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);
ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime);
ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol);
/* virtual overridable functions */
ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);
}USB_HID_CTRL_T;
/** @cond DIRECT_API */
extern uint32_t mwHID_GetMemSize(USBD_HID_INIT_PARAM_T* param);
extern ErrorCode_t mwHID_init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param);
/** @endcond */
/** @endcond */
#endif /* __HIDUSER_H__ */

457
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_hw.h Normal file
View File

@ -0,0 +1,457 @@
/***********************************************************************
* $Id:: mw_usbd_hw.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* USB Hardware Function prototypes.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __USBHW_H__
#define __USBHW_H__
#include "error.h"
#include "usbd.h"
#include "usbd_core.h"
/** \file
* \brief USB Hardware Function prototypes.
*
* Definition of functions exported by ROM based Device Controller Driver (DCD).
*
*/
/** \ingroup Group_USBD
* @defgroup USBD_HW USB Device Controller Driver
* \section Sec_HWModDescription Module Description
* The Device Controller Driver Layer implements the routines to deal directly with the hardware.
*/
/** \ingroup USBD_HW
* USB Endpoint/class handler Callback Events.
*
*/
enum USBD_EVENT_T {
USB_EVT_SETUP =1, /**< 1 Setup Packet received */
USB_EVT_OUT, /**< 2 OUT Packet received */
USB_EVT_IN, /**< 3 IN Packet sent */
USB_EVT_OUT_NAK, /**< 4 OUT Packet - Not Acknowledged */
USB_EVT_IN_NAK, /**< 5 IN Packet - Not Acknowledged */
USB_EVT_OUT_STALL, /**< 6 OUT Packet - Stalled */
USB_EVT_IN_STALL, /**< 7 IN Packet - Stalled */
USB_EVT_OUT_DMA_EOT, /**< 8 DMA OUT EP - End of Transfer */
USB_EVT_IN_DMA_EOT, /**< 9 DMA IN EP - End of Transfer */
USB_EVT_OUT_DMA_NDR, /**< 10 DMA OUT EP - New Descriptor Request */
USB_EVT_IN_DMA_NDR, /**< 11 DMA IN EP - New Descriptor Request */
USB_EVT_OUT_DMA_ERR, /**< 12 DMA OUT EP - Error */
USB_EVT_IN_DMA_ERR, /**< 13 DMA IN EP - Error */
USB_EVT_RESET, /**< 14 Reset event recieved */
USB_EVT_SOF, /**< 15 Start of Frame event */
USB_EVT_DEV_STATE, /**< 16 Device status events */
USB_EVT_DEV_ERROR /**< 17 Device error events */
};
/**
* \brief Hardware API functions structure.
* \ingroup USBD_HW
*
* This module exposes functions which interact directly with USB device controller hardware.
*
*/
typedef struct USBD_HW_API
{
/** \fn uint32_t GetMemSize(USBD_API_INIT_PARAM_T* param)
* Function to determine the memory required by the USB device stack's DCD and core layers.
*
* This function is called by application layer before calling pUsbApi->hw->Init(), to allocate memory used
* by DCD and core layers. The application should allocate the memory which is accessible by USB
* controller/DMA controller.
* \note Some memory areas are not accessible by all bus masters.
*
* \param[in] param Structure containing USB device stack initialization parameters.
* \return Returns the required memory size in bytes.
*/
uint32_t (*GetMemSize)(USBD_API_INIT_PARAM_T* param);
/** \fn ErrorCode_t Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param)
* Function to initialize USB device stack's DCD and core layers.
*
* This function is called by application layer to initialize USB hardware and core layers.
* On successful initialization the function returns a handle to USB device stack which should
* be passed to the rest of the functions.
*
* \param[in,out] phUsb Pointer to the USB device stack handle of type USBD_HANDLE_T.
* \param[in] pDesc Structure containing pointers to various descriptor arrays needed by the stack.
* These descriptors are reported to USB host as part of enumerations process.
* \param[in] param Structure containing USB device stack initialization parameters.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK(0) On success
* \retval ERR_USBD_BAD_MEM_BUF(0x0004000b) When insufficient memory buffer is passed or memory
* is not aligned on 2048 boundary.
*/
ErrorCode_t (*Init)(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param);
/** \fn void Connect(USBD_HANDLE_T hUsb, uint32_t con)
* Function to make USB device visible/invisible on the USB bus.
*
* This function is called after the USB initialization. This function uses the soft connect
* feature to make the device visible on the USB bus. This function is called only after the
* application is ready to handle the USB data. The enumeration process is started by the
* host after the device detection. The driver handles the enumeration process according to
* the USB descriptors passed in the USB initialization function.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] con States whether to connect (1) or to disconnect (0).
* \return Nothing.
*/
void (*Connect)(USBD_HANDLE_T hUsb, uint32_t con);
/** \fn void ISR(USBD_HANDLE_T hUsb)
* Function to USB device controller interrupt events.
*
* When the user application is active the interrupt handlers are mapped in the user flash
* space. The user application must provide an interrupt handler for the USB interrupt and
* call this function in the interrupt handler routine. The driver interrupt handler takes
* appropriate action according to the data received on the USB bus.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*ISR)(USBD_HANDLE_T hUsb);
/** \fn void Reset(USBD_HANDLE_T hUsb)
* Function to Reset USB device stack and hardware controller.
*
* Reset USB device stack and hardware controller. Disables all endpoints except EP0.
* Clears all pending interrupts and resets endpoint transfer queues.
* This function is called internally by pUsbApi->hw->init() and from reset event.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*Reset)(USBD_HANDLE_T hUsb);
/** \fn void ForceFullSpeed(USBD_HANDLE_T hUsb, uint32_t cfg)
* Function to force high speed USB device to operate in full speed mode.
*
* This function is useful for testing the behavior of current device when connected
* to a full speed only hosts.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] cfg When 1 - set force full-speed or
* 0 - clear force full-speed.
* \return Nothing.
*/
void (*ForceFullSpeed )(USBD_HANDLE_T hUsb, uint32_t cfg);
/** \fn void WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg)
* Function to configure USB device controller to wake-up host on remote events.
*
* This function is called by application layer to configure the USB device controller
* to wakeup on remote events. It is recommended to call this function from users's
* USB_WakeUpCfg() callback routine registered with stack.
* \note User's USB_WakeUpCfg() is registered with stack by setting the USB_WakeUpCfg member
* of USBD_API_INIT_PARAM_T structure before calling pUsbApi->hw->Init() routine.
* Certain USB device controllers needed to keep some clocks always on to generate
* resume signaling through pUsbApi->hw->WakeUp(). This hook is provided to support
* such controllers. In most controllers cases this is an empty routine.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] cfg When 1 - Configure controller to wake on remote events or
* 0 - Configure controller not to wake on remote events.
* \return Nothing.
*/
void (*WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg);
/** \fn void SetAddress(USBD_HANDLE_T hUsb, uint32_t adr)
* Function to set USB address assigned by host in device controller hardware.
*
* This function is called automatically when USB_REQUEST_SET_ADDRESS request is received
* by the stack from USB host.
* This interface is provided to users to invoke this function in other scenarios which are not
* handle by current stack. In most user applications this function is not called directly.
* Also this function can be used by users who are selectively modifying the USB device stack's
* standard handlers through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] adr USB bus Address to which the device controller should respond. Usually
* assigned by the USB host.
* \return Nothing.
*/
void (*SetAddress)(USBD_HANDLE_T hUsb, uint32_t adr);
/** \fn void Configure(USBD_HANDLE_T hUsb, uint32_t cfg)
* Function to configure device controller hardware with selected configuration.
*
* This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received
* by the stack from USB host.
* This interface is provided to users to invoke this function in other scenarios which are not
* handle by current stack. In most user applications this function is not called directly.
* Also this function can be used by users who are selectively modifying the USB device stack's
* standard handlers through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] cfg Configuration index.
* \return Nothing.
*/
void (*Configure)(USBD_HANDLE_T hUsb, uint32_t cfg);
/** \fn void ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD)
* Function to configure USB Endpoint according to descriptor.
*
* This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received
* by the stack from USB host. All the endpoints associated with the selected configuration
* are configured.
* This interface is provided to users to invoke this function in other scenarios which are not
* handle by current stack. In most user applications this function is not called directly.
* Also this function can be used by users who are selectively modifying the USB device stack's
* standard handlers through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] pEPD Endpoint descriptor structure defined in USB 2.0 specification.
* \return Nothing.
*/
void (*ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD);
/** \fn void DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir)
* Function to set direction for USB control endpoint EP0.
*
* This function is called automatically by the stack on need basis.
* This interface is provided to users to invoke this function in other scenarios which are not
* handle by current stack. In most user applications this function is not called directly.
* Also this function can be used by users who are selectively modifying the USB device stack's
* standard handlers through callback interface exposed by the stack.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] cfg When 1 - Set EP0 in IN transfer mode
* 0 - Set EP0 in OUT transfer mode
* \return Nothing.
*/
void (*DirCtrlEP)(USBD_HANDLE_T hUsb, uint32_t dir);
/** \fn void EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)
* Function to enable selected USB endpoint.
*
* This function enables interrupts on selected endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \return Nothing.
*/
void (*EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);
/** \fn void DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)
* Function to disable selected USB endpoint.
*
* This function disables interrupts on selected endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \return Nothing.
*/
void (*DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);
/** \fn void ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum)
* Function to reset selected USB endpoint.
*
* This function flushes the endpoint buffers and resets data toggle logic.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \return Nothing.
*/
void (*ResetEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);
/** \fn void SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum)
* Function to STALL selected USB endpoint.
*
* Generates STALL signaling for requested endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \return Nothing.
*/
void (*SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);
/** \fn void ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum)
* Function to clear STALL state for the requested endpoint.
*
* This function clears STALL state for the requested endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \return Nothing.
*/
void (*ClrStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);
/** \fn ErrorCode_t SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode)
* Function to set high speed USB device controller in requested test mode.
*
* USB-IF requires the high speed device to be put in various test modes
* for electrical testing. This USB device stack calls this function whenever
* it receives USB_REQUEST_CLEAR_FEATURE request for USB_FEATURE_TEST_MODE.
* Users can put the device in test mode by directly calling this function.
* Returns ERR_USBD_INVALID_REQ when device controller is full-speed only.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] mode Test mode defined in USB 2.0 electrical testing specification.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK(0) - On success
* \retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid test mode or
* Device controller is full-speed only.
*/
ErrorCode_t (*SetTestMode)(USBD_HANDLE_T hUsb, uint8_t mode);
/** \fn uint32_t ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData)
* Function to read data received on the requested endpoint.
*
* This function is called by USB stack and the application layer to read the data
* received on the requested endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \param[in,out] pData Pointer to the data buffer where data is to be copied.
* \return Returns the number of bytes copied to the buffer.
*/
uint32_t (*ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData);
/** \fn uint32_t ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len)
* Function to queue read request on the specified endpoint.
*
* This function is called by USB stack and the application layer to queue a read request
* on the specified endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \param[in,out] pData Pointer to the data buffer where data is to be copied. This buffer
* address should be accessible by USB DMA master.
* \param[in] len Length of the buffer passed.
* \return Returns the length of the requested buffer.
*/
uint32_t (*ReadReqEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len);
/** \fn uint32_t ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData)
* Function to read setup packet data received on the requested endpoint.
*
* This function is called by USB stack and the application layer to read setup packet data
* received on the requested endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP0_IN is represented by 0x80 number.
* \param[in,out] pData Pointer to the data buffer where data is to be copied.
* \return Returns the number of bytes copied to the buffer.
*/
uint32_t (*ReadSetupPkt)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData);
/** \fn uint32_t WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt)
* Function to write data to be sent on the requested endpoint.
*
* This function is called by USB stack and the application layer to send data
* on the requested endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number as per USB specification.
* ie. An EP1_IN is represented by 0x81 number.
* \param[in] pData Pointer to the data buffer from where data is to be copied.
* \param[in] cnt Number of bytes to write.
* \return Returns the number of bytes written.
*/
uint32_t (*WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt);
/** \fn void WakeUp(USBD_HANDLE_T hUsb)
* Function to generate resume signaling on bus for remote host wakeup.
*
* This function is called by application layer to remotely wakeup host controller
* when system is in suspend state. Application should indicate this remote wakeup
* capability by setting USB_CONFIG_REMOTE_WAKEUP in bmAttributes of Configuration
* Descriptor. Also this routine will generate resume signalling only if host
* enables USB_FEATURE_REMOTE_WAKEUP by sending SET_FEATURE request before suspending
* the bus.
*
* \param[in] hUsb Handle to the USB device stack.
* \return Nothing.
*/
void (*WakeUp)(USBD_HANDLE_T hUsb);
/** \fn void EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable)
* Function to enable/disable selected USB event.
*
* This function enables interrupts on selected endpoint.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] EPNum Endpoint number corresponding to the event.
* ie. An EP1_IN is represented by 0x81 number. For device events
* set this param to 0x0.
* \param[in] event_type Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \param[in] enable 1 - enable event, 0 - disable event.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK(0) - On success
* \retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid event type.
*/
ErrorCode_t (*EnableEvent)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable);
} USBD_HW_API_T;
/*-----------------------------------------------------------------------------
* Private functions & structures prototypes used by stack internally
*-----------------------------------------------------------------------------*/
/** @cond DIRECT_API */
/* Driver functions */
uint32_t hwUSB_GetMemSize(USBD_API_INIT_PARAM_T* param);
ErrorCode_t hwUSB_Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param);
void hwUSB_Connect(USBD_HANDLE_T hUsb, uint32_t con);
void hwUSB_ISR(USBD_HANDLE_T hUsb);
/* USB Hardware Functions */
extern void hwUSB_Reset(USBD_HANDLE_T hUsb);
extern void hwUSB_ForceFullSpeed (USBD_HANDLE_T hUsb, uint32_t con);
extern void hwUSB_WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg);
extern void hwUSB_SetAddress(USBD_HANDLE_T hUsb, uint32_t adr);
extern void hwUSB_Configure(USBD_HANDLE_T hUsb, uint32_t cfg);
extern void hwUSB_ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD);
extern void hwUSB_DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir);
extern void hwUSB_EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum);
extern void hwUSB_DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum);
extern void hwUSB_ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum);
extern void hwUSB_SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum);
extern void hwUSB_ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum);
extern ErrorCode_t hwUSB_SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode); /* for FS only devices return ERR_USBD_INVALID_REQ */
extern uint32_t hwUSB_ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData);
extern uint32_t hwUSB_ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len);
extern uint32_t hwUSB_ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t, uint32_t *);
extern uint32_t hwUSB_WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt);
/* generate resume signaling on the bus */
extern void hwUSB_WakeUp(USBD_HANDLE_T hUsb);
extern ErrorCode_t hwUSB_EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable);
/* TODO implement following routines
- function to program TD and queue them to ep Qh
*/
/** @endcond */
#endif /* __USBHW_H__ */

119
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_msc.h Normal file
View File

@ -0,0 +1,119 @@
/***********************************************************************
* $Id:: mw_usbd_msc.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* Mass Storage Class definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __MSC_H__
#define __MSC_H__
#include "usbd.h"
/** \file
* \brief Mass Storage class (MSC) descriptors.
*
* Definition of MSC class descriptors and their bit defines.
*
*/
/* MSC Subclass Codes */
#define MSC_SUBCLASS_RBC 0x01
#define MSC_SUBCLASS_SFF8020I_MMC2 0x02
#define MSC_SUBCLASS_QIC157 0x03
#define MSC_SUBCLASS_UFI 0x04
#define MSC_SUBCLASS_SFF8070I 0x05
#define MSC_SUBCLASS_SCSI 0x06
/* MSC Protocol Codes */
#define MSC_PROTOCOL_CBI_INT 0x00
#define MSC_PROTOCOL_CBI_NOINT 0x01
#define MSC_PROTOCOL_BULK_ONLY 0x50
/* MSC Request Codes */
#define MSC_REQUEST_RESET 0xFF
#define MSC_REQUEST_GET_MAX_LUN 0xFE
/* MSC Bulk-only Stage */
#define MSC_BS_CBW 0 /* Command Block Wrapper */
#define MSC_BS_DATA_OUT 1 /* Data Out Phase */
#define MSC_BS_DATA_IN 2 /* Data In Phase */
#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */
#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */
#define MSC_BS_CSW 5 /* Command Status Wrapper */
#define MSC_BS_ERROR 6 /* Error */
/* Bulk-only Command Block Wrapper */
PRE_PACK struct POST_PACK _MSC_CBW
{
uint32_t dSignature;
uint32_t dTag;
uint32_t dDataLength;
uint8_t bmFlags;
uint8_t bLUN;
uint8_t bCBLength;
uint8_t CB[16];
} ;
typedef struct _MSC_CBW MSC_CBW;
/* Bulk-only Command Status Wrapper */
PRE_PACK struct POST_PACK _MSC_CSW
{
uint32_t dSignature;
uint32_t dTag;
uint32_t dDataResidue;
uint8_t bStatus;
} ;
typedef struct _MSC_CSW MSC_CSW;
#define MSC_CBW_Signature 0x43425355
#define MSC_CSW_Signature 0x53425355
/* CSW Status Definitions */
#define CSW_CMD_PASSED 0x00
#define CSW_CMD_FAILED 0x01
#define CSW_PHASE_ERROR 0x02
/* SCSI Commands */
#define SCSI_TEST_UNIT_READY 0x00
#define SCSI_REQUEST_SENSE 0x03
#define SCSI_FORMAT_UNIT 0x04
#define SCSI_INQUIRY 0x12
#define SCSI_MODE_SELECT6 0x15
#define SCSI_MODE_SENSE6 0x1A
#define SCSI_START_STOP_UNIT 0x1B
#define SCSI_MEDIA_REMOVAL 0x1E
#define SCSI_READ_FORMAT_CAPACITIES 0x23
#define SCSI_READ_CAPACITY 0x25
#define SCSI_READ10 0x28
#define SCSI_WRITE10 0x2A
#define SCSI_VERIFY10 0x2F
#define SCSI_READ12 0xA8
#define SCSI_WRITE12 0xAA
#define SCSI_MODE_SELECT10 0x55
#define SCSI_MODE_SENSE10 0x5A
#endif /* __MSC_H__ */

270
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_mscuser.h Normal file
View File

@ -0,0 +1,270 @@
/***********************************************************************
* $Id:: mw_usbd_mscuser.h 577 2012-11-20 01:42:04Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* Mass Storage Class Custom User Module definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __MSCUSER_H__
#define __MSCUSER_H__
#include "error.h"
#include "usbd.h"
#include "usbd_msc.h"
#include "usbd_core.h"
#include "app_usbd_cfg.h"
/** \file
* \brief Mass Storage Class (MSC) API structures and function prototypes.
*
* Definition of functions exported by ROM based MSC function driver.
*
*/
/** \ingroup Group_USBD
* @defgroup USBD_MSC Mass Storage Class (MSC) Function Driver
* \section Sec_MSCModDescription Module Description
* MSC Class Function Driver module. This module contains an internal implementation of the USB MSC Class.
* User applications can use this class driver instead of implementing the MSC class manually
* via the low-level USBD_HW and USBD_Core APIs.
*
* This module is designed to simplify the user code by exposing only the required interface needed to interface with
* Devices using the USB MSC Class.
*/
/** \brief Mass Storage class function driver initialization parameter data structure.
* \ingroup USBD_MSC
*
* \details This data structure is used to pass initialization parameters to the
* Mass Storage class function driver's init function.
*
*/
typedef struct USBD_MSC_INIT_PARAM
{
/* memory allocation params */
uint32_t mem_base; /**< Base memory location from where the stack can allocate
data and buffers. \note The memory address set in this field
should be accessible by USB DMA controller. Also this value
should be aligned on 4 byte boundary.
*/
uint32_t mem_size; /**< The size of memory buffer which stack can use.
\note The \em mem_size should be greater than the size
returned by USBD_MSC_API::GetMemSize() routine.*/
/* mass storage params */
uint8_t* InquiryStr; /**< Pointer to the 28 character string. This string is
sent in response to the SCSI Inquiry command. \note The data
pointed by the pointer should be of global scope.
*/
uint32_t BlockCount; /**< Number of blocks present in the mass storage device */
uint32_t BlockSize; /**< Block size in number of bytes */
uint32_t MemorySize; /**< Memory size in number of bytes */
/** Pointer to the interface descriptor within the descriptor
* array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T
* structure. The stack assumes both HS and FS use same BULK endpoints.
*/
uint8_t* intf_desc;
/* user defined functions */
/**
* MSC Write callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a write command.
*
* \param[in] offset Destination start address.
* \param[in, out] src Pointer to a pointer to the source of data. Pointer-to-pointer
* is used to implement zero-copy buffers. See \ref USBD_ZeroCopy
* for more details on zero-copy concept.
* \param[in] length Number of bytes to be written.
* \return Nothing.
*
*/
void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length, uint32_t high_offset);
/**
* MSC Read callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a read command.
*
* \param[in] offset Source start address.
* \param[in, out] dst Pointer to a pointer to the source of data. The MSC function drivers
* implemented in stack are written with zero-copy model. Meaning the stack doesn't make an
* extra copy of buffer before writing/reading data from USB hardware FIFO. Hence the
* parameter is pointer to a pointer containing address buffer (<em>uint8_t** dst</em>).
* So that the user application can update the buffer pointer instead of copying data to
* address pointed by the parameter. /note The updated buffer address should be accessible
* by USB DMA master. If user doesn't want to use zero-copy model, then the user should copy
* data to the address pointed by the passed buffer pointer parameter and shouldn't change
* the address value. See \ref USBD_ZeroCopy for more details on zero-copy concept.
* \param[in] length Number of bytes to be read.
* \return Nothing.
*
*/
void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length, uint32_t high_offset);
/**
* MSC Verify callback function.
*
* This function is provided by the application software. This function gets called
* when host sends a verify command. The callback function should compare the buffer
* with the destination memory at the requested offset and
*
* \param[in] offset Destination start address.
* \param[in] buf Buffer containing the data sent by the host.
* \param[in] length Number of bytes to verify.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK If data in the buffer matches the data at destination
* \retval ERR_FAILED At least one byte is different.
*
*/
ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t buf[], uint32_t length, uint32_t high_offset);
/**
* Optional callback function to optimize MSC_Write buffer transfer.
*
* This function is provided by the application software. This function gets called
* when host sends SCSI_WRITE10/SCSI_WRITE12 command. The callback function should
* update the \em buff_adr pointer so that the stack transfers the data directly
* to the target buffer. /note The updated buffer address should be accessible
* by USB DMA master. If user doesn't want to use zero-copy model, then the user
* should not update the buffer pointer. See \ref USBD_ZeroCopy for more details
* on zero-copy concept.
*
* \param[in] offset Destination start address.
* \param[in,out] buf Buffer containing the data sent by the host.
* \param[in] length Number of bytes to write.
* \return Nothing.
*
*/
void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length, uint32_t high_offset);
/**
* Optional user override-able function to replace the default MSC class handler.
*
* The application software could override the default EP0 class handler with their
* own by providing the handler function address as this data member of the parameter
* structure. Application which like the default handler should set this data member
* to zero before calling the USBD_MSC_API::Init().
* \n
* \note
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in] data Pointer to the data which will be passed when callback function is called by the stack.
* \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.
* \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success.
* \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.
* \retval ERR_USBD_xxx For other error conditions.
*
*/
ErrorCode_t (*MSC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
uint64_t MemorySize64;
} USBD_MSC_INIT_PARAM_T;
/** \brief MSC class API functions structure.
* \ingroup USBD_MSC
*
* This module exposes functions which interact directly with USB device controller hardware.
*
*/
typedef struct USBD_MSC_API
{
/** \fn uint32_t GetMemSize(USBD_MSC_INIT_PARAM_T* param)
* Function to determine the memory required by the MSC function driver module.
*
* This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used
* by MSC function driver module. The application should allocate the memory which is accessible by USB
* controller/DMA controller.
* \note Some memory areas are not accessible by all bus masters.
*
* \param[in] param Structure containing MSC function driver module initialization parameters.
* \return Returns the required memory size in bytes.
*/
uint32_t (*GetMemSize)(USBD_MSC_INIT_PARAM_T* param);
/** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param)
* Function to initialize MSC function driver module.
*
* This function is called by application layer to initialize MSC function driver module.
*
* \param[in] hUsb Handle to the USB device stack.
* \param[in, out] param Structure containing MSC function driver module initialization parameters.
* \return Returns \ref ErrorCode_t type to indicate success or error condition.
* \retval LPC_OK On success
* \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte
* aligned or smaller than required.
* \retval ERR_API_INVALID_PARAM2 Either MSC_Write() or MSC_Read() or
* MSC_Verify() callbacks are not defined.
* \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.
* \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed.
*/
ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param);
} USBD_MSC_API_T;
/*-----------------------------------------------------------------------------
* Private functions & structures prototypes
*-----------------------------------------------------------------------------*/
/** @cond ADVANCED_API */
typedef struct _MSC_CTRL_T
{
/* If it's a USB HS, the max packet is 512, if it's USB FS,
the max packet is 64. Use 512 for both HS and FS. */
/*ALIGNED(4)*/ uint8_t BulkBuf[USB_HS_MAX_BULK_PACKET]; /* Bulk In/Out Buffer */
/*ALIGNED(4)*/MSC_CBW CBW; /* Command Block Wrapper */
/*ALIGNED(4)*/MSC_CSW CSW; /* Command Status Wrapper */
USB_CORE_CTRL_T* pUsbCtrl;
uint64_t Offset; /* R/W Offset */
uint32_t Length; /* R/W Length */
uint32_t BulkLen; /* Bulk In/Out Length */
uint8_t* rx_buf;
uint8_t BulkStage; /* Bulk Stage */
uint8_t if_num; /* interface number */
uint8_t epin_num; /* BULK IN endpoint number */
uint8_t epout_num; /* BULK OUT endpoint number */
uint32_t MemOK; /* Memory OK */
uint8_t* InquiryStr;
uint32_t BlockCount;
uint32_t BlockSize;
uint64_t MemorySize;
/* user defined functions */
void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length, uint32_t high_offset);
void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length, uint32_t high_offset);
ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t src[], uint32_t length, uint32_t high_offset);
/* optional call back for MSC_Write optimization */
void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length, uint32_t high_offset);
}USB_MSC_CTRL_T;
/** @cond DIRECT_API */
extern uint32_t mwMSC_GetMemSize(USBD_MSC_INIT_PARAM_T* param);
extern ErrorCode_t mwMSC_init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param);
/** @endcond */
/** @endcond */
#endif /* __MSCUSER_H__ */

92
hw/mcu/nxp/lpc_chip_175x_6x/inc/usbd/usbd_rom_api.h Normal file
View File

@ -0,0 +1,92 @@
/***********************************************************************
* $Id:: mw_usbd_rom_api.h 331 2012-08-09 18:54:34Z usb10131 $
*
* Project: USB device ROM Stack
*
* Description:
* ROM API Module definitions.
*
***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __MW_USBD_ROM_API_H
#define __MW_USBD_ROM_API_H
/** \file
* \brief ROM API for USB device stack.
*
* Definition of functions exported by ROM based USB device stack.
*
*/
#include "error.h"
#include "usbd.h"
#include "usbd_hw.h"
#include "usbd_core.h"
#include "usbd_mscuser.h"
#include "usbd_dfuuser.h"
#include "usbd_hiduser.h"
#include "usbd_cdcuser.h"
/** \brief Main USBD API functions structure.
* \ingroup Group_USBD
*
* This structure contains pointer to various USB Device stack's sub-module
* function tables. This structure is used as main entry point to access
* various methods (grouped in sub-modules) exposed by ROM based USB device
* stack.
*
*/
typedef struct USBD_API
{
const USBD_HW_API_T* hw; /**< Pointer to function table which exposes functions
which interact directly with USB device stack's core
layer.*/
const USBD_CORE_API_T* core; /**< Pointer to function table which exposes functions
which interact directly with USB device controller
hardware.*/
const USBD_MSC_API_T* msc; /**< Pointer to function table which exposes functions
provided by MSC function driver module.
*/
const USBD_DFU_API_T* dfu; /**< Pointer to function table which exposes functions
provided by DFU function driver module.
*/
const USBD_HID_API_T* hid; /**< Pointer to function table which exposes functions
provided by HID function driver module.
*/
const USBD_CDC_API_T* cdc; /**< Pointer to function table which exposes functions
provided by CDC-ACM function driver module.
*/
const uint32_t* reserved6; /**< Reserved for future function driver module.
*/
const uint32_t version; /**< Version identifier of USB ROM stack. The version is
defined as 0x0CHDMhCC where each nibble represents version
number of the corresponding component.
CC - 7:0 - 8bit core version number
h - 11:8 - 4bit hardware interface version number
M - 15:12 - 4bit MSC class module version number
D - 19:16 - 4bit DFU class module version number
H - 23:20 - 4bit HID class module version number
C - 27:24 - 4bit CDC class module version number
H - 31:28 - 4bit reserved
*/
} USBD_API_T;
/* Applications using USBD ROM API should define this instance. The pointer should be assigned a value computed based on chip definitions. */
extern const USBD_API_T* g_pUsbApi;
#define USBD_API g_pUsbApi
#endif /*__MW_USBD_ROM_API_H*/

276
hw/mcu/nxp/lpc_chip_175x_6x/inc/wwdt_17xx_40xx.h Normal file
View File

@ -0,0 +1,276 @@
/*
* @brief LPC17xx/40xx WWDT driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __WWDT_17XX_40XX_H_
#define __WWDT_17XX_40XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup WWDT_17XX_40XX CHIP: LPC17xx/40xx Windowed Watchdog driver
* @ingroup CHIP_17XX_40XX_Drivers
* @{
*/
#if !defined(CHIP_LPC175X_6X)
#define WATCHDOG_WINDOW_SUPPORT
#endif
#if defined(CHIP_LPC175X_6X)
#define WATCHDOG_CLKSEL_SUPPORT
#endif
/** WDT oscillator frequency value */
#define WDT_OSC (500000 / 4) /*!< Dedicated oscillator that provides a 500 kHz clock to Watchdog timer*/
/**
* @brief Windowed Watchdog register block structure
*/
typedef struct { /*!< WWDT Structure */
__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */
__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
#ifdef WATCHDOG_CLKSEL_SUPPORT
__IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
#else
__I uint32_t RESERVED0;
#endif
#ifdef WATCHDOG_WINDOW_SUPPORT
__IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
__IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */
#endif
} LPC_WWDT_T;
/**
* @brief Watchdog Mode register definitions
*/
/** Watchdog Mode Bitmask */
#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F)
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0))
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1))
/** WWDT time out flag bit */
#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2))
/** WDT Time Out flag bit */
#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3))
#if !defined(CHIP_LPC175X_6X)
/** WWDT Protect flag bit */
#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4))
#endif
/**
* @brief Initialize the Watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
/**
* @brief Shutdown the Watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) {}
/**
* @brief Set WDT timeout constant value used for feed
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
* @return none
*/
STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->TC = timeout;
}
/**
* @brief Feed watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
* @note If this function isn't called, a watchdog timer warning will occur.
* After the warning, a timeout will occur if a feed has happened.
*/
STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)
{
pWWDT->FEED = 0xAA;
pWWDT->FEED = 0x55;
}
#if defined(WATCHDOG_WINDOW_SUPPORT)
/**
* @brief Set WWDT warning interrupt
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT warning in ticks, between 0 and 1023
* @return None
* @note This is the number of ticks after the watchdog interrupt that the
* warning interrupt will be generated.
*/
STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->WARNINT = timeout;
}
/**
* @brief Set WWDT window time
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
* @return None
* @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
* function and this function, with this function defining the last tick before the
* watchdog window interrupt occurs.
*/
STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->WINDOW = timeout;
}
#endif
/**
* @brief Enable watchdog timer options
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param options : An or'ed set of options of values
* WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
* @return None
* @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
* WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
* are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot
* be unset.
*/
STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)
{
pWWDT->MOD |= options;
}
/**
* @brief Disable/clear watchdog timer options
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param options : An or'ed set of options of values
* WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
* @return None
* @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
* WWDT_WDMOD_WDTOF).
*/
STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)
{
pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;
}
/**
* @brief Enable WWDT activity
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)
{
Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);
Chip_WWDT_Feed(pWWDT);
}
/**
* @brief Read WWDT status flag
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return Watchdog status, an Or'ed value of WWDT_WDMOD_*
*/
STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)
{
return pWWDT->MOD;
}
/**
* @brief Clear WWDT interrupt status flags
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param status : Or'ed value of status flag(s) that you want to clear, should be:
* - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
* - WWDT_WDMOD_WDINT: Clear watchdog warning flag
* @return None
*/
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status);
/**
* @brief Get the current value of WDT
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return current value of WDT
*/
STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)
{
return pWWDT->TV;
}
#if defined(WATCHDOG_CLKSEL_SUPPORT)
/**
* @brief Watchdog Timer Clock Source Selection register definitions
*/
/** Clock source select bitmask */
#define WWDT_CLKSEL_BITMASK ((uint32_t) 0x10000003)
/** Clock source select */
#define WWDT_CLKSEL_SOURCE(n) ((uint32_t) (n & 0x03))
/** Lock the clock source selection */
#define WWDT_CLKSEL_LOCK ((uint32_t) (1 << 31))
/**
* @brief Watchdog Clock Source definitions
*/
typedef enum {
WWDT_CLKSRC_IRC = WWDT_CLKSEL_SOURCE(0), /*!< Internal RC oscillator */
#if defined(CHIP_LPC175X_6X)
WWDT_CLKSRC_WATCHDOG_PCLK = WWDT_CLKSEL_SOURCE(1), /*!< APB peripheral clock (watchdog pclk) */
WWDT_CLKSRC_RTC_CLK = WWDT_CLKSEL_SOURCE(2), /*!< RTC oscillator (rtc_clk) */
#else
WWDT_CLKSRC_WATCHDOG_WDOSC = WWDT_CLKSEL_SOURCE(1), /*!< Watchdog oscillator (WDOSC) */
#endif
} CHIP_WWDT_CLK_SRC_T;
/**
* @brief Get the current value of WDT
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param wdtClkSrc : Selected watchdog clock source
* @return Nothing
*/
STATIC INLINE void Chip_WWDT_SelClockSource(LPC_WWDT_T *pWWDT, CHIP_WWDT_CLK_SRC_T wdtClkSrc)
{
pWWDT->CLKSEL = wdtClkSrc & WWDT_CLKSEL_BITMASK;
}
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __WWDT_17XX_40XX_H_ */

256
hw/mcu/nxp/lpc_chip_175x_6x/src/adc_17xx_40xx.c Normal file
View File

@ -0,0 +1,256 @@
/*
* @brief LPC17xx/40xx A/D conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Get the number of clock for a full conversion */
STATIC INLINE uint8_t getFullConvClk(void)
{
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
return 31;
#elif defined(CHIP_LPC175X_6X)
return 65;
#else
return 0;
#endif
}
/* Get divider value */
STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
{
uint32_t adcBlockFreq;
uint32_t fullAdcRate;
uint8_t div;
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
A/D converter, which should be less than or equal to 4.5MHz.
A fully conversion requires (bits_accuracy+1) of these clocks.
ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
ADC rate = ADC clock / (the number of clocks required for each conversion);
*/
#if defined(CHIP_LPC175X_6X)
adcBlockFreq = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_ADC);
#else
adcBlockFreq = Chip_Clock_GetPeripheralClockRate();
#endif
#if defined(ADC_ACC_12BITS)
fullAdcRate = adcRate * getFullConvClk();
#else
if (burstMode) {
fullAdcRate = adcRate * clks;
}
else {
fullAdcRate = adcRate * getFullConvClk();
}
#endif
/* Get the round value by fomular: (2*A + B)/(2*B) */
div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
return div;
}
/* Set start mode for ADC */
void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode)
{
uint32_t temp;
temp = pADC->CR & (~ADC_CR_START_MASK);
pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode));
}
/* Get the ADC value */
Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
uint32_t temp;
temp = pADC->DR[channel];
if (!ADC_DR_DONE(temp)) {
return ERROR;
}
/* if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */
/* return ERROR; */
*data = (uint16_t) ADC_DR_RESULT(temp);
return SUCCESS;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the ADC peripheral and the ADC setup structure to default value */
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup)
{
uint8_t div;
uint32_t cr = 0;
uint32_t clk;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
#if defined(ADC_TRIM_SUPPORT)
pADC->ADTRM = 0xF00;
#endif
pADC->INTEN = 0; /* Disable all interrupts */
cr |= ADC_CR_PDN;
ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE;
ADCSetup->bitsAccuracy = 0; /* LPC17xx/40xx doesn't support this setting */
clk = 0;
ADCSetup->burstMode = false;
div = getClkDiv(pADC, false, ADCSetup->adcRate, clk);
cr |= ADC_CR_CLKDIV(div);
#if !defined(ADC_ACC_12BITS)
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
#endif /*defined(ADC_ACC_12BITS)*/
pADC->CR = cr;
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0x00000100;
pADC->CR = 0;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
}
/* Get the ADC value */
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
return readAdcVal(pADC, channel, data);
}
/* Get ADC Channel status from ADC data register */
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
{
switch (StatusType) {
case ADC_DR_DONE_STAT:
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_OVERRUN_STAT:
channel += 8;
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_ADINT_STAT:
return pADC->STAT >> 16 ? SET : RESET;
default:
break;
}
return RESET;
}
/* Enable/Disable interrupt for ADC channel */
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->INTEN |= (1UL << channel);
}
else {
pADC->INTEN &= (~(1UL << channel));
}
}
/* Select the mode starting the AD conversion */
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption)
{
if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
if (EdgeOption) {
pADC->CR |= ADC_CR_EDGE;
}
else {
pADC->CR &= ~ADC_CR_EDGE;
}
}
setStartMode(pADC, (uint8_t) mode);
}
/* Set the ADC Sample rate */
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate)
{
uint8_t div;
uint32_t cr;
cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK);
ADCSetup->adcRate = rate;
div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy));
cr |= ADC_CR_CLKDIV(div);
#if !defined(ADC_ACC_12BITS)
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
#endif /*defined(ADC_ACC_12BITS)*/
pADC->CR = cr;
}
/* Enable or disable the ADC channel on ADC peripheral */
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->CR |= ADC_CR_CH_SEL(channel);
}
else {
pADC->CR &= ~ADC_CR_START_MASK;
pADC->CR &= ~ADC_CR_CH_SEL(channel);
}
}
/* Enable burst mode */
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
setStartMode(pADC, ADC_NO_START);
if (NewState == DISABLE) {
pADC->CR &= ~ADC_CR_BURST;
}
else {
pADC->CR |= ADC_CR_BURST;
}
}
/* Read the ADC value and convert it to 8bits value */
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data)
{
uint16_t temp;
Status rt;
rt = readAdcVal(pADC, channel, &temp);
*data = (uint8_t) temp;
return rt;
}

1507
hw/mcu/nxp/lpc_chip_175x_6x/src/can_17xx_40xx.c Normal file
View File

File diff suppressed because it is too large Load Diff

110
hw/mcu/nxp/lpc_chip_175x_6x/src/chip_17xx_40xx.c Normal file
View File

@ -0,0 +1,110 @@
/*
* @brief LPC17xx/40xx Miscellaneous chip specific functions
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/* System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock;
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Update system core clock rate, should be called if the system has
a clock rate change */
void SystemCoreClockUpdate(void)
{
/* CPU core speed */
SystemCoreClock = Chip_Clock_GetSystemClockRate();
}
/* Sets up USB PLL, all needed clocks and enables USB PHY on the chip. USB pins which are
muxed to different pads are not initialized here. This routine assumes that the XTAL
OSC is enabled and running prior to this call. */
void Chip_USB_Init(void)
{
#if defined(CHIP_LPC175X_6X)
/* Setup USB PLL1 for a 48MHz clock
Input clock rate (FIN) is main oscillator = 12MHz
PLL1 Output = USBCLK = 48MHz = FIN * MSEL, so MSEL = 4.
FCCO = USBCLK = USBCLK * 2 * P. It must be between 156 MHz to 320 MHz.
so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1); /* Multiply by 4, Divide by 2 */
/* Use PLL1 output as USB Clock Source */
/* Enable PLL1 */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
/* Wait for PLL1 to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
/* Connect PLL1 */
Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT);
/* Wait for PLL1 to be connected */
while (!Chip_Clock_IsUSBPLLConnected()) {}
#else
/* Select XTAL as clock source for USB block and divider as 1 */
LPC_SYSCTL->USBCLKSEL = 0x1;
/* Setup USB PLL1 for a 48MHz clock
Input clock rate (FIN) is main oscillator = 12MHz
PLL output = 48MHz = FIN * MSEL, so MSEL = 4
FCCO must be between 156 MHz to 320 MHz, where FCCO = PLL output * 2 * P,
so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1);
/* Wait for USB PLL to lock */
while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0) {}
/* Select PLL1/USBPLL as clock source for USB block and divider as 1 */
LPC_SYSCTL->USBCLKSEL = (SYSCTL_USBCLKSRC_USBPLL << 8) | 0x01;
#endif /* defined(CHIP_LPC175X_6X) */
/* Enable AHB clock to the USB block and USB RAM. */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
}

516
hw/mcu/nxp/lpc_chip_175x_6x/src/clock_17xx_40xx.c Normal file
View File

@ -0,0 +1,516 @@
/*
* @brief LPC17xx/40xx System and Control driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Enables or connects a PLL */
void Chip_Clock_EnablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags) {
uint32_t temp;
temp = LPC_SYSCTL->PLL[PLLNum].PLLCON;
temp |= flags;
LPC_SYSCTL->PLL[PLLNum].PLLCON = temp;
Chip_Clock_FeedPLL(PLLNum);
}
/* Disables or disconnects a PLL */
void Chip_Clock_DisablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags) {
uint32_t temp;
temp = LPC_SYSCTL->PLL[PLLNum].PLLCON;
temp &= ~flags;
LPC_SYSCTL->PLL[PLLNum].PLLCON = temp;
Chip_Clock_FeedPLL(PLLNum);
}
/* Sets up a PLL */
void Chip_Clock_SetupPLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t msel, uint32_t psel) {
uint32_t PLLcfg;
#if defined(CHIP_LPC175X_6X)
/* PLL0 and PLL1 are slightly different */
if (PLLNum == SYSCTL_MAIN_PLL) {
PLLcfg = (msel) | (psel << 16);
}
else {
PLLcfg = (msel) | (psel << 5);
}
#else
PLLcfg = (msel) | (psel << 5);
#endif
LPC_SYSCTL->PLL[PLLNum].PLLCFG = PLLcfg;
LPC_SYSCTL->PLL[PLLNum].PLLCON = 0x1;
Chip_Clock_FeedPLL(PLLNum);
}
/* Enables power and clocking for a peripheral */
void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk) {
uint32_t bs = (uint32_t) clk;
#if defined(CHIP_LPC40XX)
if (bs >= 32) {
LPC_SYSCTL->PCONP1 |= (1 << (bs - 32));
}
else {
LPC_SYSCTL->PCONP |= (1 << bs);
}
#else
LPC_SYSCTL->PCONP |= (1 << bs);
#endif
}
/* Disables power and clocking for a peripheral */
void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk) {
uint32_t bs = (uint32_t) clk;
#if defined(CHIP_LPC40XX)
if (bs >= 32) {
LPC_SYSCTL->PCONP1 &= ~(1 << (bs - 32));
}
else {
LPC_SYSCTL->PCONP |= ~(1 << bs);
}
#else
LPC_SYSCTL->PCONP |= ~(1 << bs);
#endif
}
/* Returns power enables state for a peripheral */
bool Chip_Clock_IsPeripheralClockEnabled(CHIP_SYSCTL_CLOCK_T clk)
{
uint32_t bs = (uint32_t) clk;
#if defined(CHIP_LPC40XX)
if (bs >= 32) {
bs = LPC_SYSCTL->PCONP1 & (1 << (bs - 32));
}
else {
bs = LPC_SYSCTL->PCONP & (1 << bs);
}
#else
bs = LPC_SYSCTL->PCONP & (1 << bs);
#endif
return (bool) (bs != 0);
}
/* Sets the current CPU clock source */
void Chip_Clock_SetCPUClockSource(CHIP_SYSCTL_CCLKSRC_T src)
{
#if defined(CHIP_LPC175X_6X)
/* LPC175x/6x CPU clock source is based on PLL connect status */
if (src == SYSCTL_CCLKSRC_MAINPLL) {
/* Connect PLL0 */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
else {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
#else
/* LPC177x/8x and 407x/8x CPU clock source is based on CCLKSEL */
if (src == SYSCTL_CCLKSRC_MAINPLL) {
/* Connect PLL0 */
LPC_SYSCTL->CCLKSEL |= (1 << 8);
}
else {
LPC_SYSCTL->CCLKSEL &= ~(1 << 8);
}
#endif
}
/* Returns the current CPU clock source */
CHIP_SYSCTL_CCLKSRC_T Chip_Clock_GetCPUClockSource(void)
{
CHIP_SYSCTL_CCLKSRC_T src;
#if defined(CHIP_LPC175X_6X)
/* LPC175x/6x CPU clock source is based on PLL connect status */
if (Chip_Clock_IsMainPLLConnected()) {
src = SYSCTL_CCLKSRC_MAINPLL;
}
else {
src = SYSCTL_CCLKSRC_SYSCLK;
}
#else
/* LPC177x/8x and 407x/8x CPU clock source is based on CCLKSEL */
if (LPC_SYSCTL->CCLKSEL & (1 << 8)) {
src = SYSCTL_CCLKSRC_MAINPLL;
}
else {
src = SYSCTL_CCLKSRC_SYSCLK;
}
#endif
return src;
}
/* Selects the CPU clock divider */
void Chip_Clock_SetCPUClockDiv(uint32_t div)
{
#if defined(CHIP_LPC175X_6X)
LPC_SYSCTL->CCLKSEL = div;
#else
uint32_t temp;
/* Save state of CPU clock source bit */
temp = LPC_SYSCTL->CCLKSEL & (1 << 8);
LPC_SYSCTL->CCLKSEL = temp | div;
#endif
}
/* Gets the CPU clock divider */
uint32_t Chip_Clock_GetCPUClockDiv(void)
{
#if defined(CHIP_LPC175X_6X)
return (LPC_SYSCTL->CCLKSEL & 0xFF) + 1;
#else
return LPC_SYSCTL->CCLKSEL & 0x1F;
#endif
}
#if !defined(CHIP_LPC175X_6X)
/* Selects the USB clock divider source */
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src)
{
uint32_t temp;
/* Mask out current source, but keep divider */
temp = LPC_SYSCTL->USBCLKSEL & ~(0x3 << 8);
LPC_SYSCTL->USBCLKSEL = temp | (((uint32_t) src) << 8);
}
#endif
/* Sets the USB clock divider */
void Chip_Clock_SetUSBClockDiv(uint32_t div)
{
uint32_t temp;
/* Mask out current divider */
#if defined(CHIP_LPC175X_6X)
temp = LPC_SYSCTL->USBCLKSEL & ~(0xF);
#else
temp = LPC_SYSCTL->USBCLKSEL & ~(0x1F);
#endif
LPC_SYSCTL->USBCLKSEL = temp | div;
}
/* Gets the USB clock divider */
uint32_t Chip_Clock_GetUSBClockDiv(void)
{
#if defined(CHIP_LPC175X_6X)
return (LPC_SYSCTL->USBCLKSEL & 0xF) + 1;
#else
return (LPC_SYSCTL->USBCLKSEL & 0x1F) + 1;
#endif
}
#if defined(CHIP_LPC175X_6X)
/* Selects a clock divider for a peripheral */
void Chip_Clock_SetPCLKDiv(CHIP_SYSCTL_PCLK_T clk, CHIP_SYSCTL_CLKDIV_T div)
{
uint32_t temp, bitIndex, regIndex = (uint32_t) clk;
/* Get register array index and clock index into the register */
bitIndex = ((regIndex % 16) * 2);
regIndex = regIndex / 16;
/* Mask and update register */
temp = LPC_SYSCTL->PCLKSEL[regIndex] & ~(0x3 << bitIndex);
temp |= (((uint32_t) div) << bitIndex);
LPC_SYSCTL->PCLKSEL[regIndex] = temp;
}
/* Gets a clock divider for a peripheral */
uint32_t Chip_Clock_GetPCLKDiv(CHIP_SYSCTL_PCLK_T clk)
{
uint32_t div = 1, bitIndex, regIndex = ((uint32_t) clk) * 2;
/* Get register array index and clock index into the register */
bitIndex = regIndex % 32;
regIndex = regIndex / 32;
/* Mask and update register */
div = LPC_SYSCTL->PCLKSEL[regIndex];
div = (div >> bitIndex) & 0x3;
if (div == SYSCTL_CLKDIV_4) {
div = 4;
}
else if (div == SYSCTL_CLKDIV_1) {
div = 1;
}
else if (div == SYSCTL_CLKDIV_2) {
div = 2;
}
else {
/* Special case for CAN clock divider */
if ((clk == SYSCTL_PCLK_CAN1) || (clk == SYSCTL_PCLK_CAN2) || (clk == SYSCTL_PCLK_ACF)) {
div = 6;
}
else {
div = 8;
}
}
return div;
}
#endif
/* Selects a source clock and divider rate for the CLKOUT pin */
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src,
uint32_t div)
{
uint32_t temp;
temp = LPC_SYSCTL->CLKOUTCFG & ~0x1FF;
temp |= ((uint32_t) src) | ((div - 1) << 4);
LPC_SYSCTL->CLKOUTCFG = temp;
}
/* Returns the current SYSCLK clock rate */
uint32_t Chip_Clock_GetSYSCLKRate(void)
{
/* Determine clock input rate to SYSCLK based on input selection */
switch (Chip_Clock_GetMainPLLSource()) {
case (uint32_t) SYSCTL_PLLCLKSRC_IRC:
return Chip_Clock_GetIntOscRate();
case (uint32_t) SYSCTL_PLLCLKSRC_MAINOSC:
return Chip_Clock_GetMainOscRate();
#if defined(CHIP_LPC175X_6X)
case (uint32_t) SYSCTL_PLLCLKSRC_RTC:
return Chip_Clock_GetRTCOscRate();
#endif
}
return 0;
}
/* Returns the main PLL output clock rate */
uint32_t Chip_Clock_GetMainPLLOutClockRate(void)
{
uint32_t clkhr = 0;
#if defined(CHIP_LPC175X_6X)
/* Only valid if enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
uint32_t msel, nsel;
/* PLL0 rate is (FIN * 2 * MSEL) / NSEL, get MSEL and NSEL */
msel = 1 + (LPC_SYSCTL->PLL[SYSCTL_MAIN_PLL].PLLCFG & 0x7FFF);
nsel = 1 + ((LPC_SYSCTL->PLL[SYSCTL_MAIN_PLL].PLLCFG >> 16) & 0xFF);
clkhr = (Chip_Clock_GetMainPLLInClockRate() * 2 * msel) / nsel;
}
#else
if (Chip_Clock_IsMainPLLEnabled()) {
uint32_t msel;
/* PLL0 rate is (FIN * MSEL) */
msel = 1 + (LPC_SYSCTL->PLL[SYSCTL_MAIN_PLL].PLLCFG & 0x1F);
clkhr = (Chip_Clock_GetMainPLLInClockRate() * msel);
}
#endif
return (uint32_t) clkhr;
}
/* Get USB output clock rate */
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
{
uint32_t clkhr = 0;
/* Only valid if enabled */
if (Chip_Clock_IsUSBPLLEnabled()) {
uint32_t msel;
/* PLL1 input clock (FIN) is always main oscillator */
/* PLL1 rate is (FIN * MSEL) */
msel = 1 + (LPC_SYSCTL->PLL[SYSCTL_USB_PLL].PLLCFG & 0x1F);
clkhr = (Chip_Clock_GetUSBPLLInClockRate() * msel);
}
return (uint32_t) clkhr;
}
/* Get the main clock rate */
/* On 175x/6x devices, this is the input clock to the CPU divider.
Additionally, on 177x/8x and 407x/8x devices, this is also the
input clock to the peripheral divider. */
uint32_t Chip_Clock_GetMainClockRate(void)
{
switch (Chip_Clock_GetCPUClockSource()) {
case SYSCTL_CCLKSRC_MAINPLL:
return Chip_Clock_GetMainPLLOutClockRate();
case SYSCTL_CCLKSRC_SYSCLK:
return Chip_Clock_GetSYSCLKRate();
default:
return 0;
}
}
/* Get CCLK rate */
uint32_t Chip_Clock_GetSystemClockRate(void)
{
return Chip_Clock_GetMainClockRate() / Chip_Clock_GetCPUClockDiv();
}
/* Returns the USB clock (USB_CLK) rate */
uint32_t Chip_Clock_GetUSBClockRate(void)
{
uint32_t div, clkrate;
#if defined(CHIP_LPC175X_6X)
/* The USB clock rate is derived from PLL1 or PLL0 */
if (Chip_Clock_IsUSBPLLConnected()) {
/* Use PLL1 clock for USB source with divider of 1 */
clkrate = Chip_Clock_GetUSBPLLOutClockRate();
div = 1;
}
else {
clkrate = Chip_Clock_GetMainClockRate();
div = Chip_Clock_GetUSBClockDiv();
}
#else
/* Get clock from source drving USB */
switch (Chip_Clock_GetUSBClockSource()) {
case SYSCTL_USBCLKSRC_SYSCLK:
default:
clkrate = Chip_Clock_GetSYSCLKRate();
break;
case SYSCTL_USBCLKSRC_MAINPLL:
clkrate = Chip_Clock_GetMainPLLOutClockRate();
break;
case SYSCTL_USBCLKSRC_USBPLL:
clkrate = Chip_Clock_GetUSBPLLOutClockRate();
break;
}
div = Chip_Clock_GetUSBClockDiv();
#endif
return clkrate / div;
}
#if !defined(CHIP_LPC175X_6X)
/* Selects the SPIFI clock divider source */
void Chip_Clock_SetSPIFIClockSource(CHIP_SYSCTL_SPIFICLKSRC_T src)
{
uint32_t temp;
/* Mask out current source, but keep divider */
temp = LPC_SYSCTL->SPIFICLKSEL & ~(0x3 << 8);
LPC_SYSCTL->SPIFICLKSEL = temp | (((uint32_t) src) << 8);
}
/* Sets the SPIFI clock divider */
void Chip_Clock_SetSPIFIClockDiv(uint32_t div)
{
uint32_t temp;
/* Mask out current divider */
temp = LPC_SYSCTL->SPIFICLKSEL & ~(0x1F);
LPC_SYSCTL->SPIFICLKSEL = temp | div;
}
/* Returns the SPIFI clock rate */
uint32_t Chip_Clock_GetSPIFIClockRate(void)
{
uint32_t div, clkrate;
/* Get clock from source drving USB */
switch (Chip_Clock_GetSPIFIClockSource()) {
case SYSCTL_SPIFICLKSRC_SYSCLK:
default:
clkrate = Chip_Clock_GetSYSCLKRate();
break;
case SYSCTL_SPIFICLKSRC_MAINPLL:
clkrate = Chip_Clock_GetMainPLLOutClockRate();
break;
case SYSCTL_SPIFICLKSRC_USBPLL:
clkrate = Chip_Clock_GetUSBPLLOutClockRate();
break;
}
div = Chip_Clock_GetSPIFIClockDiv();
return clkrate / div;
}
#endif
#if defined(CHIP_LPC175X_6X)
/* Returns the clock rate for a peripheral */
uint32_t Chip_Clock_GetPeripheralClockRate(CHIP_SYSCTL_PCLK_T clk) {
/* 175x/6x clock is derived from CPU clock with CPU divider */
return Chip_Clock_GetSystemClockRate() / Chip_Clock_GetPCLKDiv(clk);
}
#else
/* Returns the clock rate for all peripherals */
uint32_t Chip_Clock_GetPeripheralClockRate(void)
{
uint32_t clkrate = 0, div;
/* Get divider, a divider of 0 means the clock is disabled */
div = Chip_Clock_GetPCLKDiv();
if (div != 0) {
/* Derived from periperhal clock input and peripheral clock divider */
clkrate = Chip_Clock_GetMainClockRate() / div;
}
return clkrate;
}
#endif

64
hw/mcu/nxp/lpc_chip_175x_6x/src/cmp_17xx_40xx.c Normal file
View File

@ -0,0 +1,64 @@
/*
* @brief LPC17xx/40xx Comparator driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC40XX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the CMP */
void Chip_CMP_Init(void)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_CMP);
}
/* De-initializes the CMP */
void Chip_CMP_DeInit(void)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_CMP);
}
#endif /* defined(CHIP_LPC40XX) */

110
hw/mcu/nxp/lpc_chip_175x_6x/src/crc_17xx_40xx.c Normal file
View File

@ -0,0 +1,110 @@
/*
* @brief LPC17xx/40xx Cyclic Redundancy Check (CRC) Engine driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Sets up the CRC engine with defaults based on the polynomial to be used */
void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly)
{
switch (poly) {
case CRC_POLY_CRC16:
LPC_CRC->MODE = MODE_CFG_CRC16;
LPC_CRC->SEED = CRC_SEED_CRC16;
break;
case CRC_POLY_CRC32:
LPC_CRC->MODE = MODE_CFG_CRC32;
LPC_CRC->SEED = CRC_SEED_CRC32;
break;
case CRC_POLY_CCITT:
default:
LPC_CRC->MODE = MODE_CFG_CCITT;
LPC_CRC->SEED = CRC_SEED_CCITT;
break;
}
}
/* configure CRC engine and compute CCITT checksum from 8-bit data */
uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes)
{
Chip_CRC_UseDefaultConfig(CRC_POLY_CCITT);
while (bytes > 0) {
Chip_CRC_Write8(*data);
data++;
bytes--;
}
return Chip_CRC_Sum();
}
/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */
uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords)
{
Chip_CRC_UseDefaultConfig(CRC_POLY_CRC16);
while (hwords > 0) {
Chip_CRC_Write16(*data);
data++;
hwords--;
}
return Chip_CRC_Sum();
}
/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */
uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words)
{
Chip_CRC_UseDefaultConfig(CRC_POLY_CRC32);
while (words > 0) {
Chip_CRC_Write32(*data);
data++;
words--;
}
return Chip_CRC_Sum();
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */

84
hw/mcu/nxp/lpc_chip_175x_6x/src/dac_17xx_40xx.c Normal file
View File

@ -0,0 +1,84 @@
/*
* @brief LPC17xx/40xx D/A conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the DAC peripheral */
void Chip_DAC_Init(LPC_DAC_T *pDAC)
{
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
Chip_SYSCTL_PeriphReset(SYSCTL_RESET_DAC);
#endif
/* Set maximum update rate 1MHz */
Chip_DAC_SetBias(pDAC, DAC_MAX_UPDATE_RATE_1MHz);
}
/* Shutdown DAC peripheral */
void Chip_DAC_DeInit(LPC_DAC_T *pDAC)
{}
/* Update value to DAC buffer*/
void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value)
{
uint32_t tmp;
tmp = pDAC->CR & DAC_BIAS_EN;
tmp |= DAC_VALUE(dac_value);
/* Update value */
pDAC->CR = tmp;
}
/* Set Maximum update rate for DAC */
void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias)
{
pDAC->CR &= ~DAC_BIAS_EN;
if (bias == DAC_MAX_UPDATE_RATE_400kHz) {
pDAC->CR |= DAC_BIAS_EN;
}
}

258
hw/mcu/nxp/lpc_chip_175x_6x/src/eeprom_17xx_40xx.c Normal file
View File

@ -0,0 +1,258 @@
/*
* @brief LPC17xx/40xx EEPROM driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Setup EEPROM clock */
STATIC void setClkDiv(LPC_EEPROM_T *pEEPROM)
{
uint32_t clk;
/* Setup EEPROM timing to 375KHz based on PCLK rate */
clk = Chip_Clock_GetSystemClockRate();
/* Set EEPROM clock divide value*/
pEEPROM->CLKDIV = clk / 375000 - 1;
}
/* Setup EEPROM clock */
STATIC void setWaitState(LPC_EEPROM_T *pEEPROM)
{
uint32_t val, clk;
/* Setup EEPROM timing to 375KHz based on PCLK rate */
clk = Chip_Clock_GetSystemClockRate();
/* Setup EEPROM wait states to 15, 35, 35nS */
val = ((((clk / 1000000) * 15) / 1000) + 1);
val |= (((((clk / 1000000) * 55) / 1000) + 1) << 8);
val |= (((((clk / 1000000) * 35) / 1000) + 1) << 16);
Chip_EEPROM_SetWaitState(pEEPROM, val);
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the EEPROM peripheral with specified parameter */
void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM)
{
Chip_EEPROM_DisablePowerDown(pEEPROM);
setClkDiv(pEEPROM);
setWaitState(pEEPROM);
}
/* Wait for interrupt */
void Chip_EEPROM_WaitForIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
{
uint32_t status;
while (1) {
status = Chip_EEPROM_GetIntStatus(pEEPROM);
if ((status & mask) == mask) {
break;
}
}
Chip_EEPROM_ClearIntStatus(pEEPROM, mask);
}
/* Erase data in page register */
void Chip_EEPROM_ErasePageRegister(LPC_EEPROM_T *pEEPROM)
{
uint32_t i = 0;
Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_32BITS_WRITE);
Chip_EEPROM_SetAddr(pEEPROM, 0, 0);
for (i = 0; i < EEPROM_PAGE_SIZE; i += 4) {
Chip_EEPROM_WriteData(pEEPROM, 0);
Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
}
}
/* Write data to page register */
uint32_t Chip_EEPROM_WritePageRegister(LPC_EEPROM_T *pEEPROM, uint16_t pageOffset,
uint8_t *pData, uint8_t wsize, uint32_t byteNum)
{
uint32_t i = 0;
uint32_t mask = (1 << (8 * wsize)) - 1;
Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
if (wsize == 1) {
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_8BITS_WRITE);
}
else if (wsize == 2) {
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_16BITS_WRITE);
}
else {
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_32BITS_WRITE);
}
Chip_EEPROM_SetAddr(pEEPROM, 0, pageOffset);
for (i = 0; i < byteNum; i += wsize) {
Chip_EEPROM_WriteData(pEEPROM, (*(uint32_t *) (&pData[i])) & mask);
Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
}
return i;
}
/* Write data from page register to non-volatile memory */
void Chip_EEPROM_EraseProgramPage(LPC_EEPROM_T *pEEPROM, uint16_t pageAddr)
{
Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_CMD_ERASE_PRG_PAGE);
Chip_EEPROM_SetAddr(pEEPROM, pageAddr, 0);
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_ERASE_PRG_PAGE);
Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFPROG);
}
/* Read data from non-volatile memory */
uint32_t Chip_EEPROM_ReadPage(LPC_EEPROM_T *pEEPROM,
uint16_t pageOffset,
uint16_t pageAddr,
uint8_t *pData,
uint8_t rsize,
uint32_t byteNum)
{
uint32_t i;
uint32_t mask = (1 << (8 * rsize)) - 1;
Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
Chip_EEPROM_SetAddr(pEEPROM, pageAddr, pageOffset);
if (rsize == 1) {
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_8BITS_READ | EEPROM_CMD_RDPREFETCH);
}
else if (rsize == 2) {
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_16BITS_READ | EEPROM_CMD_RDPREFETCH);
}
else {
Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_32BITS_READ | EEPROM_CMD_RDPREFETCH);
}
/* read and store data in buffer */
for (i = 0; i < byteNum; i += rsize) {
(*(uint32_t *) (&pData[i]) ) &= ~mask;
(*(uint32_t *) (&pData[i]) ) |= (Chip_EEPROM_ReadData(pEEPROM) & mask);
Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
}
return i;
}
/* Write data to EEPROM at specific address */
Status Chip_EEPROM_Write(LPC_EEPROM_T *pEEPROM,
uint16_t pageOffset,
uint16_t pageAddr,
void *pData,
EEPROM_RWSIZE_T wsize,
uint32_t byteNum)
{
uint32_t wTotalByteNum = 0;
uint32_t wOffset = (pageOffset & (EEPROM_PAGE_SIZE - 1));
uint32_t wByteNum = EEPROM_PAGE_SIZE - wOffset;
while (byteNum) {
if (wByteNum > byteNum) {
wByteNum = byteNum;
}
/* update data to page register */
Chip_EEPROM_WritePageRegister(pEEPROM, wOffset,
&((uint8_t *) pData)[wTotalByteNum], (uint8_t) wsize, wByteNum);
Chip_EEPROM_EraseProgramPage(pEEPROM, pageAddr);
wTotalByteNum += wByteNum;
byteNum -= wByteNum;
/* Change to next page */
pageAddr++;
wOffset = 0;
wByteNum = EEPROM_PAGE_SIZE;
}
return SUCCESS;
}
/* Read data to EEPROM at specific address */
void Chip_EEPROM_Read(LPC_EEPROM_T *pEEPROM,
uint16_t pageOffset,
uint16_t pageAddr,
void *pData,
EEPROM_RWSIZE_T rsize,
uint32_t byteNum)
{
uint32_t rTotalByteNum = 0;
uint32_t rOffset = (pageOffset & (EEPROM_PAGE_SIZE - 1));
uint32_t rByteNum = EEPROM_PAGE_SIZE - rOffset;
/* read and store data in buffer */
while (byteNum) {
if (rByteNum > byteNum) {
rByteNum = byteNum;
}
/* update data to page register */
Chip_EEPROM_ReadPage(pEEPROM, rOffset, pageAddr,
&((uint8_t *) pData)[rTotalByteNum], (uint8_t) rsize, rByteNum);
rTotalByteNum += rByteNum;
byteNum -= rByteNum;
/* Change to next page */
pageAddr++;
rOffset = 0;
rByteNum = EEPROM_PAGE_SIZE;
}
}
/* Erase a page at the specific address */
void Chip_EEPROM_Erase(LPC_EEPROM_T *pEEPROM, uint16_t pageAddr)
{
Chip_EEPROM_ErasePageRegister(pEEPROM);
Chip_EEPROM_EraseProgramPage(pEEPROM, pageAddr);
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */

282
hw/mcu/nxp/lpc_chip_175x_6x/src/emc_17xx_40xx.c Normal file
View File

@ -0,0 +1,282 @@
/*
* @brief LPC17xx/40xx EMC driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* DIV function with result rounded up */
#define EMC_DIV_ROUND_UP(x, y) ((x + y - 1) / y)
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
#ifndef EMC_SUPPORT_ONLY_PL172
/* Get ARM External Memory Controller Version */
STATIC uint32_t getARMPeripheralID(void)
{
uint32_t *RegAdd;
RegAdd = (uint32_t *) ((uint32_t) LPC_EMC + 0xFE0);
return (RegAdd[0] & 0xFF) | ((RegAdd[1] & 0xFF) << 8) |
((RegAdd[2] & 0xFF) << 16) | (RegAdd[3] << 24);
}
#endif
/* Calculate Clock Count from Timing Unit(nanoseconds) */
STATIC uint32_t convertTimmingParam(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust)
{
uint32_t temp;
if (input_ns < 0) {
return (-input_ns) >> 8;
}
temp = EMC_Clock / 1000000; /* MHz calculation */
temp = temp * input_ns / 1000;
/* round up */
temp += 0xFF;
/* convert to simple integer number format */
temp >>= 8;
if (temp > adjust) {
return temp - adjust;
}
return 0;
}
/* Get Dynamic Memory Device Colum len */
STATIC uint32_t getColsLen(uint32_t DynConfig)
{
uint32_t DevBusWidth;
DevBusWidth = (DynConfig >> EMC_DYN_CONFIG_DEV_BUS_BIT) & 0x03;
if (DevBusWidth == 2) {
return 8;
}
else if (DevBusWidth == 1) {
return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 8;
}
else if (DevBusWidth == 0) {
return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 9;
}
return 0;
}
/* Initializes the Dynamic Controller according to the specified parameters
in the IP_EMC_DYN_CONFIG_T */
void initDynMem(LPC_EMC_T *pEMC, IP_EMC_DYN_CONFIG_T *Dynamic_Config, uint32_t EMC_Clock)
{
uint32_t ChipSelect, tmpclk;
int i;
for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + (ChipSelect << 5));
EMC_Reg_add->DYNAMICRASCAS0 = Dynamic_Config->DevConfig[ChipSelect].RAS |
((Dynamic_Config->DevConfig[ChipSelect].ModeRegister <<
(8 - EMC_DYN_MODE_CAS_BIT)) & 0xF00);
EMC_Reg_add->DYNAMICCONFIG0 = Dynamic_Config->DevConfig[ChipSelect].DynConfig;
}
pEMC->DYNAMICREADCONFIG = Dynamic_Config->ReadConfig; /* Read strategy */
pEMC->DYNAMICRP = convertTimmingParam(EMC_Clock, Dynamic_Config->tRP, 1);
pEMC->DYNAMICRAS = convertTimmingParam(EMC_Clock, Dynamic_Config->tRAS, 1);
pEMC->DYNAMICSREX = convertTimmingParam(EMC_Clock, Dynamic_Config->tSREX, 1);
pEMC->DYNAMICAPR = convertTimmingParam(EMC_Clock, Dynamic_Config->tAPR, 1);
pEMC->DYNAMICDAL = convertTimmingParam(EMC_Clock, Dynamic_Config->tDAL, 0);
pEMC->DYNAMICWR = convertTimmingParam(EMC_Clock, Dynamic_Config->tWR, 1);
pEMC->DYNAMICRC = convertTimmingParam(EMC_Clock, Dynamic_Config->tRC, 1);
pEMC->DYNAMICRFC = convertTimmingParam(EMC_Clock, Dynamic_Config->tRFC, 1);
pEMC->DYNAMICXSR = convertTimmingParam(EMC_Clock, Dynamic_Config->tXSR, 1);
pEMC->DYNAMICRRD = convertTimmingParam(EMC_Clock, Dynamic_Config->tRRD, 1);
pEMC->DYNAMICMRD = convertTimmingParam(EMC_Clock, Dynamic_Config->tMRD, 1);
/* TIM_Waitus(100); */
/*FIXME: if Timer driver is ready, it should replace below "for" delay technic */
for (i = 0; i < 1000; i++) { /* wait 100us */
}
pEMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
/* TIM_Waitus(200); */ /* wait 200us */
/*FIXME: if Timer driver is ready, it should replace below "for" delay technic */
for (i = 0; i < 1000; i++) {}
pEMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
pEMC->DYNAMICREFRESH = 2; /* ( 2 * 16 ) -> 32 clock cycles */
/* FIXME: TIM_Waitus(200); */ /* wait 200us */
for (i = 0; i < 80; i++) {}
tmpclk = EMC_DIV_ROUND_UP(convertTimmingParam(EMC_Clock, Dynamic_Config->RefreshPeriod, 0), 16);
pEMC->DYNAMICREFRESH = tmpclk;
pEMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
/*uint32_t burst_length;*/
uint32_t DynAddr;
uint8_t Col_len;
Col_len = getColsLen(Dynamic_Config->DevConfig[ChipSelect].DynConfig);
/* get bus wide: if 32bit, len is 4 else if 16bit len is 2 */
/* burst_length = 1 << ((((Dynamic_Config->DynConfig[ChipSelect] >> 14) & 1)^1) +1); */
if (Dynamic_Config->DevConfig[ChipSelect].DynConfig & (1 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)) {
/*32bit bus */
/*burst_length = 2;*/
Col_len += 2;
}
else {
/*burst_length = 4;*/
Col_len += 1;
}
DynAddr = Dynamic_Config->DevConfig[ChipSelect].BaseAddr;
if (DynAddr != 0) {
uint32_t temp;
uint32_t ModeRegister;
ModeRegister = Dynamic_Config->DevConfig[ChipSelect].ModeRegister;
temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len)));
temp = temp;
}
}
pEMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */
/* enable buffers */
pEMC->DYNAMICCONFIG0 |= 1 << 19;
pEMC->DYNAMICCONFIG1 |= 1 << 19;
pEMC->DYNAMICCONFIG2 |= 1 << 19;
pEMC->DYNAMICCONFIG3 |= 1 << 19;
}
/* Initializes the Static Controller according to the specified parameters
* in the IP_EMC_STATIC_CONFIG_T
*/
void initStaticMem(LPC_EMC_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock)
{
LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5));
EMC_Reg_add->STATICCONFIG0 = Static_Config->Config;
EMC_Reg_add->STATICWAITWEN0 = convertTimmingParam(EMC_Clock, Static_Config->WaitWen, 1);
EMC_Reg_add->STATICWAITOEN0 = convertTimmingParam(EMC_Clock, Static_Config->WaitOen, 0);
EMC_Reg_add->STATICWAITRD0 = convertTimmingParam(EMC_Clock, Static_Config->WaitRd, 1);
EMC_Reg_add->STATICWAITPAG0 = convertTimmingParam(EMC_Clock, Static_Config->WaitPage, 1);
EMC_Reg_add->STATICWAITWR0 = convertTimmingParam(EMC_Clock, Static_Config->WaitWr, 2);
EMC_Reg_add->STATICWAITTURN0 = convertTimmingParam(EMC_Clock, Static_Config->WaitTurn, 1);
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Dyanmic memory setup */
void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config)
{
uint32_t ClkFreq;
/* Note clocks must be enabled prior to this call */
ClkFreq = Chip_Clock_GetEMCClockRate();
initDynMem(LPC_EMC, Dynamic_Config, ClkFreq);
}
/* Enable Dynamic Memory Controller */
void Chip_EMC_Dynamic_Enable(uint8_t Enable)
{
if (Enable) {
LPC_EMC->DYNAMICCONTROL |= EMC_DYN_CONTROL_ENABLE;
}
else {
LPC_EMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE;
}
}
/* Static memory setup */
void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config)
{
uint32_t ClkFreq;
/* Note clocks must be enabled prior to this call */
ClkFreq = Chip_Clock_GetEMCClockRate();
initStaticMem(LPC_EMC, Static_Config, ClkFreq);
}
/* Mirror CS1 to CS0 and DYCS0 */
void Chip_EMC_Mirror(uint8_t Enable)
{
if (Enable) {
LPC_EMC->CONTROL |= 1 << 1;
}
else {
LPC_EMC->CONTROL &= ~(1 << 1);
}
}
/* Enable EMC */
void Chip_EMC_Enable(uint8_t Enable)
{
if (Enable) {
LPC_EMC->CONTROL |= 1;
}
else {
LPC_EMC->CONTROL &= ~(1);
}
}
/* Set EMC LowPower Mode */
void Chip_EMC_LowPowerMode(uint8_t Enable)
{
if (Enable) {
LPC_EMC->CONTROL |= 1 << 2;
}
else {
LPC_EMC->CONTROL &= ~(1 << 2);
}
}
/* Initialize EMC */
void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
{
LPC_EMC->CONFIG = (EndianMode ? 1 : 0) | ((ClockRatio ? 1 : 0) << 8);
/* Enable EMC 001 Normal Memory Map, No low power mode */
LPC_EMC->CONTROL = (Enable ? 1 : 0);
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */

289
hw/mcu/nxp/lpc_chip_175x_6x/src/enet_17xx_40xx.c Normal file
View File

@ -0,0 +1,289 @@
/*
* @brief LPC17xx/40xx ethernet driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Saved address for PHY and clock divider */
STATIC uint32_t phyAddr;
/* Divider index values for the MII PHY clock */
STATIC const uint8_t EnetClkDiv[] = {4, 6, 8, 10, 14, 20, 28, 36, 40, 44,
48, 52, 56, 60, 64};
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC INLINE void resetENET(LPC_ENET_T *pENET)
{
volatile uint32_t i;
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
Chip_SYSCTL_PeriphReset(SYSCTL_RESET_ENET);
#endif
/* Reset ethernet peripheral */
Chip_ENET_Reset(pENET);
for (i = 0; i < 100; i++) {}
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Basic Ethernet interface initialization */
void Chip_ENET_Init(LPC_ENET_T *pENET, bool useRMII)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ENET);
resetENET(pENET);
/* Initial MAC configuration for full duplex,
100Mbps, inter-frame gap use default values */
pENET->MAC.MAC1 = ENET_MAC1_PARF;
pENET->MAC.MAC2 = ENET_MAC2_FULLDUPLEX | ENET_MAC2_CRCEN | ENET_MAC2_PADCRCEN;
if (useRMII) {
pENET->CONTROL.COMMAND = ENET_COMMAND_FULLDUPLEX | ENET_COMMAND_PASSRUNTFRAME | ENET_COMMAND_RMII;
}
else {
pENET->CONTROL.COMMAND = ENET_COMMAND_FULLDUPLEX | ENET_COMMAND_PASSRUNTFRAME;
}
pENET->MAC.IPGT = ENET_IPGT_FULLDUPLEX;
pENET->MAC.IPGR = ENET_IPGR_P2_DEF;
pENET->MAC.SUPP = ENET_SUPP_100Mbps_SPEED;
pENET->MAC.MAXF = ENET_ETH_MAX_FLEN;
pENET->MAC.CLRT = ENET_CLRT_DEF;
/* Setup default filter */
pENET->CONTROL.COMMAND |= ENET_COMMAND_PASSRXFILTER;
/* Clear all MAC interrupts */
pENET->MODULE_CONTROL.INTCLEAR = 0xFFFF;
/* Disable MAC interrupts */
pENET->MODULE_CONTROL.INTENABLE = 0;
}
/* Ethernet interface shutdown */
void Chip_ENET_DeInit(LPC_ENET_T *pENET)
{
/* Disable packet reception */
pENET->MAC.MAC1 &= ~ENET_MAC1_RXENABLE;
pENET->CONTROL.COMMAND = 0;
/* Clear all MAC interrupts */
pENET->MODULE_CONTROL.INTCLEAR = 0xFFFF;
/* Disable MAC interrupts */
pENET->MODULE_CONTROL.INTENABLE = 0;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ENET);
}
/* Sets up the PHY link clock divider and PHY address */
void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
{
/* Save clock divider and PHY address in MII address register */
phyAddr = ENET_MADR_PHYADDR(addr);
/* Write to MII configuration register and reset */
pENET->MAC.MCFG = ENET_MCFG_CLOCKSEL(div) | ENET_MCFG_RES_MII;
/* release reset */
pENET->MAC.MCFG &= ~(ENET_MCFG_RES_MII);
}
/* Find the divider index for a desired MII clock rate */
uint32_t Chip_ENET_FindMIIDiv(LPC_ENET_T *pENET, uint32_t clockRate)
{
uint32_t tmp, divIdx = 0;
/* Find desired divider value */
tmp = Chip_Clock_GetENETClockRate() / clockRate;
/* Determine divider index from desired divider */
for (divIdx = 0; divIdx < (sizeof(EnetClkDiv) / sizeof(EnetClkDiv[0])); divIdx++) {
/* Closest index, but not higher than desired rate */
if (EnetClkDiv[divIdx] >= tmp) {
return divIdx;
}
}
/* Use maximum divider index */
return (sizeof(EnetClkDiv) / sizeof(EnetClkDiv[0])) - 1;
}
/* Starts a PHY write via the MII */
void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
{
/* Write value at PHY address and register */
pENET->MAC.MCMD = 0;
pENET->MAC.MADR = phyAddr | ENET_MADR_REGADDR(reg);
pENET->MAC.MWTD = data;
}
/*Starts a PHY read via the MII */
void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg)
{
/* Read value at PHY address and register */
pENET->MAC.MADR = phyAddr | ENET_MADR_REGADDR(reg);
pENET->MAC.MCMD = ENET_MCMD_READ;
}
/* Read MII data */
uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET)
{
pENET->MAC.MCMD = 0;
return pENET->MAC.MRDD;
}
/* Sets full duplex for the ENET interface */
void Chip_ENET_SetFullDuplex(LPC_ENET_T *pENET)
{
pENET->MAC.MAC2 |= ENET_MAC2_FULLDUPLEX;
pENET->CONTROL.COMMAND |= ENET_COMMAND_FULLDUPLEX;
pENET->MAC.IPGT = ENET_IPGT_FULLDUPLEX;
}
/* Sets half duplex for the ENET interface */
void Chip_ENET_SetHalfDuplex(LPC_ENET_T *pENET)
{
pENET->MAC.MAC2 &= ~ENET_MAC2_FULLDUPLEX;
pENET->CONTROL.COMMAND &= ~ENET_COMMAND_FULLDUPLEX;
pENET->MAC.IPGT = ENET_IPGT_HALFDUPLEX;
}
/* Configures the initial ethernet transmit descriptors */
void Chip_ENET_InitTxDescriptors(LPC_ENET_T *pENET,
ENET_TXDESC_T *pDescs,
ENET_TXSTAT_T *pStatus,
uint32_t descNum)
{
/* Setup descriptor list base addresses */
pENET->CONTROL.TX.DESCRIPTOR = (uint32_t) pDescs;
pENET->CONTROL.TX.DESCRIPTORNUMBER = descNum - 1;
pENET->CONTROL.TX.STATUS = (uint32_t) pStatus;
pENET->CONTROL.TX.PRODUCEINDEX = 0;
}
/* Configures the initial ethernet receive descriptors */
void Chip_ENET_InitRxDescriptors(LPC_ENET_T *pENET,
ENET_RXDESC_T *pDescs,
ENET_RXSTAT_T *pStatus,
uint32_t descNum)
{
/* Setup descriptor list base addresses */
pENET->CONTROL.RX.DESCRIPTOR = (uint32_t) pDescs;
pENET->CONTROL.RX.DESCRIPTORNUMBER = descNum - 1;
pENET->CONTROL.RX.STATUS = (uint32_t) pStatus;
pENET->CONTROL.RX.CONSUMEINDEX = 0;
}
/* Get status for the descriptor list */
ENET_BUFF_STATUS_T Chip_ENET_GetBufferStatus(LPC_ENET_T *pENET,
uint16_t produceIndex,
uint16_t consumeIndex,
uint16_t buffSize)
{
/* Empty descriptor list */
if (consumeIndex == produceIndex) {
return ENET_BUFF_EMPTY;
}
/* Full descriptor list */
if ((consumeIndex == 0) &&
(produceIndex == (buffSize - 1))) {
return ENET_BUFF_FULL;
}
/* Wrap-around, full descriptor list */
if (consumeIndex == (produceIndex + 1)) {
return ENET_BUFF_FULL;
}
return ENET_BUFF_PARTIAL_FULL;
}
/* Get the number of descriptor filled */
uint32_t Chip_ENET_GetFillDescNum(LPC_ENET_T *pENET, uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
{
/* Empty descriptor list */
if (consumeIndex == produceIndex) {
return 0;
}
if (consumeIndex > produceIndex) {
return (buffSize - consumeIndex) + produceIndex;
}
return produceIndex - consumeIndex;
}
/* Increase the current Tx Produce Descriptor Index */
uint16_t Chip_ENET_IncTXProduceIndex(LPC_ENET_T *pENET)
{
/* Get current TX produce index */
uint32_t idx = pENET->CONTROL.TX.PRODUCEINDEX;
/* Start frame transmission by incrementing descriptor */
idx++;
if (idx > pENET->CONTROL.TX.DESCRIPTORNUMBER) {
idx = 0;
}
pENET->CONTROL.TX.PRODUCEINDEX = idx;
return idx;
}
/* Increase the current Rx Consume Descriptor Index */
uint16_t Chip_ENET_IncRXConsumeIndex(LPC_ENET_T *pENET)
{
/* Get current RX consume index */
uint32_t idx = pENET->CONTROL.RX.CONSUMEINDEX;
/* Consume descriptor */
idx++;
if (idx > pENET->CONTROL.RX.DESCRIPTORNUMBER) {
idx = 0;
}
pENET->CONTROL.RX.CONSUMEINDEX = idx;
return idx;
}

704
hw/mcu/nxp/lpc_chip_175x_6x/src/gpdma_17xx_40xx.c Normal file
View File

@ -0,0 +1,704 @@
/*
* @brief LPC17xx/40xx GPDMA driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Channel array to monitor free channel */
static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS];
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/* Optimized Peripheral Source and Destination burst size (177x_8x,407x_8x) */
static const uint8_t GPDMA_LUTPerBurst[] = {
0, /* Reserved */
GPDMA_BSIZE_8, /* SD Card */
GPDMA_BSIZE_4, /* SSP0 Tx */
GPDMA_BSIZE_4, /* SSP0 Rx */
GPDMA_BSIZE_4, /* SSP1 Tx */
GPDMA_BSIZE_4, /* SSP1 Rx */
GPDMA_BSIZE_4, /* SSP2 Tx */
GPDMA_BSIZE_4, /* SSP2 Rx */
GPDMA_BSIZE_1, /* ADC */
GPDMA_BSIZE_1, /* DAC */
GPDMA_BSIZE_1, /* UART0 Tx */
GPDMA_BSIZE_1, /* UART0 Rx */
GPDMA_BSIZE_1, /* UART1 Tx */
GPDMA_BSIZE_1, /* UART1 Rx */
GPDMA_BSIZE_1, /* UART2 Tx */
GPDMA_BSIZE_1, /* UART2 Rx */
GPDMA_BSIZE_1, /* MAT0.0 */
GPDMA_BSIZE_1, /* MAT0.1 */
GPDMA_BSIZE_1, /* MAT1.0 */
GPDMA_BSIZE_1, /* MAT1.1 */
GPDMA_BSIZE_1, /* MAT2.0 */
GPDMA_BSIZE_1, /* MAT2.1 */
GPDMA_BSIZE_32, /* I2S channel 0 */
GPDMA_BSIZE_32, /* I2S channel 1 */
0, /* Reserved */
0, /* Reserved */
GPDMA_BSIZE_1, /* UART3 Tx */
GPDMA_BSIZE_1, /* UART3 Rx */
GPDMA_BSIZE_1, /* UART4 Tx */
GPDMA_BSIZE_1, /* UART4 Rx */
GPDMA_BSIZE_1, /* MAT3.0 */
GPDMA_BSIZE_1, /* MAT3.1 */
};
/* Optimized Peripheral Source and Destination transfer width (177x_8x,407x_8x) */
static const uint8_t GPDMA_LUTPerWid[] = {
0, /* Reserved */
GPDMA_WIDTH_WORD, /* SD Card */
GPDMA_WIDTH_BYTE, /* SSP0 Tx */
GPDMA_WIDTH_BYTE, /* SSP0 Rx */
GPDMA_WIDTH_BYTE, /* SSP1 Tx */
GPDMA_WIDTH_BYTE, /* SSP1 Rx */
GPDMA_WIDTH_BYTE, /* SSP2 Tx */
GPDMA_WIDTH_BYTE, /* SSP2 Rx */
GPDMA_WIDTH_WORD, /* ADC */
GPDMA_WIDTH_HALFWORD, /* DAC */
GPDMA_WIDTH_BYTE, /* UART0 Tx */
GPDMA_WIDTH_BYTE, /* UART0 Rx */
GPDMA_WIDTH_BYTE, /* UART1 Tx */
GPDMA_WIDTH_BYTE, /* UART1 Rx */
GPDMA_WIDTH_BYTE, /* UART2 Tx */
GPDMA_WIDTH_BYTE, /* UART2 Rx */
GPDMA_WIDTH_WORD, /* MAT0.0 */
GPDMA_WIDTH_WORD, /* MAT0.1 */
GPDMA_WIDTH_WORD, /* MAT1.0 */
GPDMA_WIDTH_WORD, /* MAT1.1 */
GPDMA_WIDTH_WORD, /* MAT2.0 */
GPDMA_WIDTH_WORD, /* MAT2.1 */
GPDMA_WIDTH_WORD, /* I2S channel 0 */
GPDMA_WIDTH_WORD, /* I2S channel 1 */
0, /* Reserved */
0, /* Reserved */
GPDMA_WIDTH_BYTE, /* UART3 Tx */
GPDMA_WIDTH_BYTE, /* UART3 Rx */
GPDMA_WIDTH_BYTE, /* UART4 Tx */
GPDMA_WIDTH_BYTE, /* UART4 Rx */
GPDMA_WIDTH_WORD, /* MAT3.0 */
GPDMA_WIDTH_WORD, /* MAT3.1 */
};
/* Lookup Table of Connection Type matched with (177x_8x,407x_8x) Peripheral Data (FIFO) register base address */
volatile static const void *GPDMA_LUTPerAddr[] = {
0, /* Reserved */
(&LPC_SDC->FIFO), /* SD Card */
(&LPC_SSP0->DR), /* SSP0 Tx */
(&LPC_SSP0->DR), /* SSP0 Rx */
(&LPC_SSP1->DR), /* SSP1 Tx */
(&LPC_SSP1->DR), /* SSP1 Rx */
(&LPC_SSP2->DR), /* SSP2 Tx */
(&LPC_SSP2->DR), /* SSP2 Rx */
(&LPC_ADC->GDR), /* ADC */
(&LPC_DAC->CR), /* DAC */
(&LPC_UART0-> /*RBTHDLR.*/ THR), /* UART0 Tx */
(&LPC_UART0-> /*RBTHDLR.*/ RBR), /* UART0 Rx */
(&LPC_UART1-> /*RBTHDLR.*/ THR), /* UART1 Tx */
(&LPC_UART1-> /*RBTHDLR.*/ RBR), /* UART1 Rx */
(&LPC_UART2-> /*RBTHDLR.*/ THR), /* UART2 Tx */
(&LPC_UART2-> /*RBTHDLR.*/ RBR), /* UART2 Rx */
(&LPC_TIMER0->MR[0]), /* MAT0.0 */
(&LPC_TIMER0->MR[1]), /* MAT0.1 */
(&LPC_TIMER1->MR[0]), /* MAT1.0 */
(&LPC_TIMER1->MR[1]), /* MAT1.1 */
(&LPC_TIMER2->MR[0]), /* MAT2.0 */
(&LPC_TIMER2->MR[1]), /* MAT2.1 */
(&LPC_I2S->TXFIFO), /* I2S Tx */
(&LPC_I2S->RXFIFO), /* I2S Rx */
0, /* Reverse */
0, /* Reverse */
(&LPC_UART3-> /*RBTHDLR.*/ THR), /* UART3 Tx */
(&LPC_UART3-> /*RBTHDLR.*/ RBR), /* UART3 Rx */
(&LPC_UART4-> /*RBTHDLR.*/ THR), /* UART4 Tx */
(&LPC_UART4-> /*RBTHDLR.*/ RBR), /* UART4 Rx */
(&LPC_TIMER3->MR[0]), /* MAT3.0 */
(&LPC_TIMER3->MR[1]) /* MAT3.1 */
};
#elif defined(CHIP_LPC175X_6X)
const uint8_t GPDMA_LUTPerBurst[] = {
GPDMA_BSIZE_4, // SSP0 Tx
GPDMA_BSIZE_4, // SSP0 Rx
GPDMA_BSIZE_4, // SSP1 Tx
GPDMA_BSIZE_4, // SSP1 Rx
GPDMA_BSIZE_1, // ADC
GPDMA_BSIZE_32, // I2S channel 0
GPDMA_BSIZE_32, // I2S channel 1
GPDMA_BSIZE_1, // DAC
GPDMA_BSIZE_1, // UART0 Tx
GPDMA_BSIZE_1, // UART0 Rx
GPDMA_BSIZE_1, // UART1 Tx
GPDMA_BSIZE_1, // UART1 Rx
GPDMA_BSIZE_1, // UART2 Tx
GPDMA_BSIZE_1, // UART2 Rx
GPDMA_BSIZE_1, // UART3 Tx
GPDMA_BSIZE_1, // UART3 Rx
GPDMA_BSIZE_1, // MAT0.0
GPDMA_BSIZE_1, // MAT0.1
GPDMA_BSIZE_1, // MAT1.0
GPDMA_BSIZE_1, // MAT1.1
GPDMA_BSIZE_1, // MAT2.0
GPDMA_BSIZE_1, // MAT2.1
GPDMA_BSIZE_1, // MAT3.0
GPDMA_BSIZE_1 // MAT3.1
};
/**
* @brief Optimized Peripheral Source and Destination transfer width
*/
const uint8_t GPDMA_LUTPerWid[] = {
GPDMA_WIDTH_BYTE, // SSP0 Tx
GPDMA_WIDTH_BYTE, // SSP0 Rx
GPDMA_WIDTH_BYTE, // SSP1 Tx
GPDMA_WIDTH_BYTE, // SSP1 Rx
GPDMA_WIDTH_WORD, // ADC
GPDMA_WIDTH_WORD, // I2S channel 0
GPDMA_WIDTH_WORD, // I2S channel 1
GPDMA_WIDTH_HALFWORD, // DAC
GPDMA_WIDTH_BYTE, // UART0 Tx
GPDMA_WIDTH_BYTE, // UART0 Rx
GPDMA_WIDTH_BYTE, // UART1 Tx
GPDMA_WIDTH_BYTE, // UART1 Rx
GPDMA_WIDTH_BYTE, // UART2 Tx
GPDMA_WIDTH_BYTE, // UART2 Rx
GPDMA_WIDTH_BYTE, // UART3 Tx
GPDMA_WIDTH_BYTE, // UART3 Rx
GPDMA_WIDTH_WORD, // MAT0.0
GPDMA_WIDTH_WORD, // MAT0.1
GPDMA_WIDTH_WORD, // MAT1.0
GPDMA_WIDTH_WORD, // MAT1.1
GPDMA_WIDTH_WORD, // MAT2.0
GPDMA_WIDTH_WORD, // MAT2.1
GPDMA_WIDTH_WORD, // MAT3.0
GPDMA_WIDTH_WORD // MAT3.1
};
/**
* @brief Peripheral Source and Destination address
*/
volatile const void *GPDMA_LUTPerAddr[] = {
(&LPC_SSP0->DR), // SSP0 Tx
(&LPC_SSP0->DR), // SSP0 Rx
(&LPC_SSP1->DR), // SSP1 Tx
(&LPC_SSP1->DR), // SSP1 Rx
(&LPC_ADC->GDR), // ADC
(&LPC_I2S->TXFIFO), // I2S Tx
(&LPC_I2S->RXFIFO), // I2S Rx
(&LPC_DAC->CR), // DAC
(&LPC_UART0-> /*RBTHDLR.*/ THR), // UART0 Tx
(&LPC_UART0-> /*RBTHDLR.*/ RBR), // UART0 Rx
(&LPC_UART1-> /*RBTHDLR.*/ THR), // UART1 Tx
(&LPC_UART1-> /*RBTHDLR.*/ RBR), // UART1 Rx
(&LPC_UART2-> /*RBTHDLR.*/ THR), // UART2 Tx
(&LPC_UART2-> /*RBTHDLR.*/ RBR), // UART2 Rx
(&LPC_UART3-> /*RBTHDLR.*/ THR), // UART3 Tx
(&LPC_UART3-> /*RBTHDLR.*/ RBR), // UART3 Rx
(&LPC_TIMER0->MR[0]), // MAT0.0
(&LPC_TIMER0->MR[1]), // MAT0.1
(&LPC_TIMER1->MR[0]), // MAT1.0
(&LPC_TIMER1->MR[1]), // MAT1.1
(&LPC_TIMER2->MR[0]), // MAT2.0
(&LPC_TIMER2->MR[1]), // MAT2.1
(&LPC_TIMER3->MR[0]), // MAT3.0
(&LPC_TIMER3->MR[1]) // MAT3.1
};
#endif
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Control which set of peripherals is connected to the DMA controller */
STATIC uint8_t configDMAMux(uint32_t gpdma_peripheral_connection_number)
{
#if defined(CHIP_LPC175X_6X)
if (gpdma_peripheral_connection_number > 15) {
LPC_SYSCTL->DMAREQSEL |= (1 << (gpdma_peripheral_connection_number - 16));
return gpdma_peripheral_connection_number - 8;
}
else {
if (gpdma_peripheral_connection_number > 7) {
LPC_SYSCTL->DMAREQSEL &= ~(1 << (gpdma_peripheral_connection_number - 8));
}
return gpdma_peripheral_connection_number;
}
#elif defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
if (gpdma_peripheral_connection_number > 15) {
LPC_SYSCTL->DMAREQSEL |= (1 << (gpdma_peripheral_connection_number - 16));
return gpdma_peripheral_connection_number - 16;
}
else {
LPC_SYSCTL->DMAREQSEL &= ~(1 << (gpdma_peripheral_connection_number));
return gpdma_peripheral_connection_number;
}
#endif
}
uint32_t makeCtrlWord(const GPDMA_CH_CFG_T *GPDMAChannelConfig,
uint32_t GPDMA_LUTPerBurstSrcConn,
uint32_t GPDMA_LUTPerBurstDstConn,
uint32_t GPDMA_LUTPerWidSrcConn,
uint32_t GPDMA_LUTPerWidDstConn)
{
uint32_t ctrl_word = 0;
switch (GPDMAChannelConfig->TransferType) {
/* Memory to memory */
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
ctrl_word = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize((4UL)) /**< Burst size = 32 */
| GPDMA_DMACCxControl_DBSize((4UL)) /**< Burst size = 32 */
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth)
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth)
| GPDMA_DMACCxControl_SI
| GPDMA_DMACCxControl_DI
| GPDMA_DMACCxControl_I;
break;
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn)
| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn)
| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
| GPDMA_DMACCxControl_DestTransUseAHBMaster1
| GPDMA_DMACCxControl_SI
| GPDMA_DMACCxControl_I;
break;
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn)
| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn)
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1
| GPDMA_DMACCxControl_DI
| GPDMA_DMACCxControl_I;
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1
| GPDMA_DMACCxControl_DestTransUseAHBMaster1
| GPDMA_DMACCxControl_I;
break;
/* Do not support any more transfer type, return ERROR */
default:
return ERROR;
}
return ctrl_word;
}
/* Set up the DPDMA according to the specification configuration details */
Status setupChannel(LPC_GPDMA_T *pGPDMA,
GPDMA_CH_CFG_T *GPDMAChannelConfig,
uint32_t CtrlWord,
uint32_t LinkListItem,
uint8_t SrcPeripheral,
uint8_t DstPeripheral)
{
GPDMA_CH_T *pDMAch;
if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) {
/* This channel is enabled, return ERROR, need to release this channel first */
return ERROR;
}
/* Get Channel pointer */
pDMAch = (GPDMA_CH_T *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]);
/* Reset the Interrupt status */
pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
/* Assign Linker List Item value */
pDMAch->LLI = LinkListItem;
/* Enable DMA channels, little endian */
pGPDMA->CONFIG = GPDMA_DMACConfig_E;
while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {}
pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr;
pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr;
/* Configure DMA Channel, enable Error Counter and Terminate counter */
pDMAch->CONFIG = GPDMA_DMACCxConfig_IE
| GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/
| GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType)
| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
| GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);
pDMAch->CONTROL = CtrlWord;
return SUCCESS;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the GPDMA */
void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA)
{
uint8_t i;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPDMA);
/* Reset all channel configuration register */
for (i = 8; i > 0; i--) {
pGPDMA->CH[i - 1].CONFIG = 0;
}
/* Clear all DMA interrupt and error flag */
pGPDMA->INTTCCLEAR = 0xFF;
pGPDMA->INTERRCLR = 0xFF;
/* Reset all channels are free */
for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++) {
ChannelHandlerArray[i].ChannelStatus = DISABLE;
}
}
/* Shutdown the GPDMA */
void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPDMA);
}
/* Stop a stream DMA transfer */
void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum)
{
Chip_GPDMA_ChannelCmd(pGPDMA, (ChannelNum), DISABLE);
if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTTC, ChannelNum)) {
/* Clear terminate counter Interrupt pending */
Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTTC, ChannelNum);
}
if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTERR, ChannelNum)) {
/* Clear terminate counter Interrupt pending */
Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTERR, ChannelNum);
}
ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE;
}
/* The GPDMA stream interrupt status checking */
Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum)
{
if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INT, ChannelNum)) {
/* Check counter terminal status */
if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTTC, ChannelNum)) {
/* Clear terminate counter Interrupt pending */
Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTTC, ChannelNum);
return SUCCESS;
}
/* Check error terminal status */
if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTERR, ChannelNum)) {
/* Clear error counter Interrupt pending */
Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTERR, ChannelNum);
return ERROR;
}
}
return ERROR;
}
int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
GPDMA_CH_CFG_T *GPDMACfg,
uint8_t ChannelNum,
uint32_t src,
uint32_t dst,
uint32_t Size,
GPDMA_FLOW_CONTROL_T TransferType)
{
int rval = -1;
GPDMACfg->ChannelNum = ChannelNum;
GPDMACfg->TransferType = TransferType;
GPDMACfg->TransferSize = Size;
switch (TransferType) {
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
GPDMACfg->SrcAddr = (uint32_t) src;
GPDMACfg->DstAddr = (uint32_t) dst;
rval = 3;
GPDMACfg->TransferWidth = GPDMA_WIDTH_WORD;
GPDMACfg->TransferSize = Size / 4;
break;
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
GPDMACfg->SrcAddr = (uint32_t) src;
rval = 1;
GPDMACfg->DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
break;
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
GPDMACfg->SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
GPDMACfg->DstAddr = (uint32_t) dst;
rval = 2;
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
GPDMACfg->SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
GPDMACfg->DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
rval = 0;
break;
default:
break;
}
return rval;
}
/* Read the status from different registers according to the type */
IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel)
{
/**
* TODO check the channel <=8 type is exited
*/
switch (type) {
case GPDMA_STAT_INT:/* check status of DMA channel interrupts */
return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF)));
case GPDMA_STAT_INTTC: /* check terminal count interrupt request status for DMA */
return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF)));
case GPDMA_STAT_INTERR: /* check interrupt status for DMA channels */
return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF)));
case GPDMA_STAT_RAWINTTC: /* check status of the terminal count interrupt for DMA channels */
return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF)));
case GPDMA_STAT_RAWINTERR: /* check status of the error interrupt for DMA channels */
return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF)));
default:/* check enable status for DMA channels */
return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF)));
}
}
/* Clear the Interrupt Flag from different registers according to the type */
void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel)
{
if (type == GPDMA_STATCLR_INTTC) {
/* clears the terminal count interrupt request on DMA channel */
pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF));
}
else {
/* clear the error interrupt request */
pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF));
}
}
/* Enable or Disable the GPDMA Channel */
void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
{
GPDMA_CH_T *pDMAch;
/* Get Channel pointer */
pDMAch = (GPDMA_CH_T *) &(pGPDMA->CH[channelNum]);
if (NewState == ENABLE) {
pDMAch->CONFIG |= GPDMA_DMACCxConfig_E;
}
else {
pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E;
}
}
/* Do a DMA transfer M2M, M2P,P2M or P2P */
Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum,
uint32_t src,
uint32_t dst,
GPDMA_FLOW_CONTROL_T TransferType,
uint32_t Size)
{
GPDMA_CH_CFG_T GPDMACfg;
uint8_t SrcPeripheral = 0, DstPeripheral = 0;
uint32_t cwrd;
int ret;
ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, Size, TransferType);
if (ret < 0) {
return ERROR;
}
/* Adjust src/dst index if they are memory */
if (ret & 1) {
src = 0;
}
else {
SrcPeripheral = configDMAMux(src);
}
if (ret & 2) {
dst = 0;
}
else {
DstPeripheral = configDMAMux(dst);
}
cwrd = makeCtrlWord(&GPDMACfg,
(uint32_t) GPDMA_LUTPerBurst[src],
(uint32_t) GPDMA_LUTPerBurst[dst],
(uint32_t) GPDMA_LUTPerWid[src],
(uint32_t) GPDMA_LUTPerWid[dst]);
if (setupChannel(pGPDMA, &GPDMACfg, cwrd, 0, SrcPeripheral, DstPeripheral) == ERROR) {
return ERROR;
}
/* Start the Channel */
Chip_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE);
return SUCCESS;
}
Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
DMA_TransferDescriptor_t *DMADescriptor,
uint32_t src,
uint32_t dst,
uint32_t Size,
GPDMA_FLOW_CONTROL_T TransferType,
const DMA_TransferDescriptor_t *NextDescriptor)
{
int ret;
GPDMA_CH_CFG_T GPDMACfg;
ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, 0, src, dst, Size, TransferType);
if (ret < 0) {
return ERROR;
}
/* Adjust src/dst index if they are memory */
if (ret & 1) {
src = 0;
}
if (ret & 2) {
dst = 0;
}
DMADescriptor->src = GPDMACfg.SrcAddr;
DMADescriptor->dst = GPDMACfg.DstAddr;
DMADescriptor->lli = (uint32_t) NextDescriptor;
DMADescriptor->ctrl = makeCtrlWord(&GPDMACfg,
(uint32_t) GPDMA_LUTPerBurst[src],
(uint32_t) GPDMA_LUTPerBurst[dst],
(uint32_t) GPDMA_LUTPerWid[src],
(uint32_t) GPDMA_LUTPerWid[dst]);
/* By default set interrupt only for last transfer */
if (NextDescriptor) {
DMADescriptor->ctrl &= ~GPDMA_DMACCxControl_I;
}
return SUCCESS;
}
/* Do a DMA scatter-gather transfer M2M, M2P,P2M or P2P using DMA descriptors */
Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
uint8_t ChannelNum,
const DMA_TransferDescriptor_t *DMADescriptor,
GPDMA_FLOW_CONTROL_T TransferType)
{
const DMA_TransferDescriptor_t *dsc = DMADescriptor;
GPDMA_CH_CFG_T GPDMACfg;
uint8_t SrcPeripheral = 0, DstPeripheral = 0;
uint32_t src = DMADescriptor->src, dst = DMADescriptor->dst;
int ret;
ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, 0, TransferType);
if (ret < 0) {
return ERROR;
}
/* Adjust src/dst index if they are memory */
if (ret & 1) {
src = 0;
}
else {
SrcPeripheral = configDMAMux(src);
}
if (ret & 2) {
dst = 0;
}
else {
DstPeripheral = configDMAMux(dst);
}
if (setupChannel(pGPDMA, &GPDMACfg, dsc->ctrl, dsc->lli, SrcPeripheral, DstPeripheral) == ERROR) {
return ERROR;
}
/* Start the Channel */
Chip_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE);
return SUCCESS;
}
/* Get a free GPDMA channel for one DMA connection */
uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA,
uint32_t PeripheralConnection_ID)
{
uint8_t temp = 0;
for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++) {
if (!Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_ENABLED_CH,
temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) {
ChannelHandlerArray[temp].ChannelStatus = ENABLE;
return temp;
}
}
return 0;
}

46
hw/mcu/nxp/lpc_chip_175x_6x/src/gpio_17xx_40xx.c Normal file
View File

@ -0,0 +1,46 @@
/*
* @brief LPC17xx/40xx GPIO driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/

46
hw/mcu/nxp/lpc_chip_175x_6x/src/gpioint_17xx_40xx.c Normal file
View File

@ -0,0 +1,46 @@
/*
* @brief LPC17xx/40xx GPIO Interrupt driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/

561
hw/mcu/nxp/lpc_chip_175x_6x/src/i2c_17xx_40xx.c Normal file
View File

@ -0,0 +1,561 @@
/*
* @brief LPC17xx/40xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Control flags */
#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
#define LPC_I2Cx(id) ((i2c[id].ip))
#define SLAVE_ACTIVE(iic) (((iic)->flags & 0xFF00) != 0)
#ifdef CHIP_LPC175X_6X
static const CHIP_SYSCTL_PCLK_T I2C_PeriphClk[I2C_NUM_INTERFACE] = {
SYSCTL_PCLK_I2C0,
SYSCTL_PCLK_I2C1,
SYSCTL_PCLK_I2C2
};
#endif
/* I2C common interface structure */
struct i2c_interface {
LPC_I2C_T *ip; /* IP base address of the I2C device */
CHIP_SYSCTL_CLOCK_T clk; /* Clock used by I2C */
I2C_EVENTHANDLER_T mEvent; /* Current active Master event handler */
I2C_EVENTHANDLER_T sEvent; /* Slave transfer events */
I2C_XFER_T *mXfer; /* Current active xfer pointer */
I2C_XFER_T *sXfer; /* Pointer to store xfer when bus is busy */
uint32_t flags; /* Flags used by I2C master and slave */
};
/* Slave interface structure */
struct i2c_slave_interface {
I2C_XFER_T *xfer;
I2C_EVENTHANDLER_T event;
};
/* I2C interfaces */
static struct i2c_interface i2c[I2C_NUM_INTERFACE] = {
{LPC_I2C0, SYSCTL_CLOCK_I2C0, Chip_I2C_EventHandler, NULL, NULL, NULL, 0},
{LPC_I2C1, SYSCTL_CLOCK_I2C1, Chip_I2C_EventHandler, NULL, NULL, NULL, 0},
{LPC_I2C2, SYSCTL_CLOCK_I2C2, Chip_I2C_EventHandler, NULL, NULL, NULL, 0}
};
static struct i2c_slave_interface i2c_slave[I2C_NUM_INTERFACE][I2C_SLAVE_NUM_INTERFACE];
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC INLINE void enableClk(I2C_ID_T id)
{
Chip_Clock_EnablePeriphClock(i2c[id].clk);
}
STATIC INLINE void disableClk(I2C_ID_T id)
{
Chip_Clock_DisablePeriphClock(i2c[id].clk);
}
/* Get the ADC Clock Rate */
STATIC INLINE uint32_t getClkRate(I2C_ID_T id)
{
#if defined(CHIP_LPC175X_6X)
return Chip_Clock_GetPeripheralClockRate(I2C_PeriphClk[id]);
#else
return Chip_Clock_GetPeripheralClockRate();
#endif
}
/* Enable I2C and start master transfer */
STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}
/* Enable I2C and enable slave transfers */
STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
}
/* Check if I2C bus is free */
STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C)
{
return !(pI2C->CONSET & I2C_CON_STO);
}
/* Get current state of the I2C peripheral */
STATIC INLINE int getCurState(LPC_I2C_T *pI2C)
{
return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
}
/* Check if the active state belongs to master mode*/
STATIC INLINE int isMasterState(LPC_I2C_T *pI2C)
{
return getCurState(pI2C) < 0x60;
}
/* Set OWN slave address for specific slave ID */
STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
{
uint32_t index = (uint32_t) sid - 1;
pI2C->MASK[index] = mask;
if (sid == I2C_SLAVE_0) {
pI2C->ADR0 = addr;
}
else {
volatile uint32_t *abase = &pI2C->ADR1;
abase[index - 1] = addr;
}
}
/* Match the slave address */
STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask)
{
mask |= 1;
return (addr1 & ~mask) == (addr2 & ~mask);
}
/* Get the index of the active slave */
STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr)
{
if (!(slaveAddr >> 1)) {
return I2C_SLAVE_GENERAL; /* General call address */
}
if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) {
return I2C_SLAVE_0;
}
if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) {
return I2C_SLAVE_1;
}
if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) {
return I2C_SLAVE_2;
}
if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) {
return I2C_SLAVE_3;
}
/* If everything is fine the code should never come here */
return I2C_SLAVE_GENERAL;
}
/* Master transfer state change handler handler */
int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
switch (getCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
break;
/* Tx handling */
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
if (!xfer->txSz) {
cclr &= ~(xfer->rxSz ? I2C_CON_STA : I2C_CON_STO);
}
else {
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
}
break;
/* Rx handling */
case 0x58: /* Data Received and NACK sent */
cclr &= ~I2C_CON_STO;
case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
case 0x40: /* SLA+R sent and ACK received */
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
/* NAK Handling */
case 0x20: /* SLA+W sent NAK received */
case 0x30: /* DATA sent NAK received */
case 0x48: /* SLA+R sent NAK received */
xfer->status = I2C_STATUS_NAK;
cclr &= ~I2C_CON_STO;
break;
case 0x38: /* Arbitration lost */
xfer->status = I2C_STATUS_ARBLOST;
break;
/* Bus Error */
case 0x00:
xfer->status = I2C_STATUS_BUSERR;
cclr &= ~I2C_CON_STO;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
/* If stopped return 0 */
if (!(cclr & I2C_CON_STO) || (xfer->status == I2C_STATUS_ARBLOST)) {
if (xfer->status == I2C_STATUS_BUSY) {
xfer->status = I2C_STATUS_DONE;
}
return 0;
}
return 1;
}
/* Find the slave address of SLA+W or SLA+R */
I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C)
{
switch (getCurState(pI2C)) {
case 0x60:
case 0x68:
case 0x70:
case 0x78:
case 0xA8:
case 0xB0:
return lookupSlaveIndex(pI2C, pI2C->DAT);
}
/* If everything is fine code should never come here */
return I2C_SLAVE_GENERAL;
}
/* Slave state machine handler */
int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
int ret = RET_SLAVE_BUSY;
xfer->status = I2C_STATUS_BUSY;
switch (getCurState(pI2C)) {
case 0x80: /* SLA: Data received + ACK sent */
case 0x90: /* GC: Data received + ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
ret = RET_SLAVE_RX;
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
case 0x60: /* Own SLA+W received */
case 0x68: /* Own SLA+W received after losing arbitration */
case 0x70: /* GC+W received */
case 0x78: /* GC+W received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1;
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
case 0xA8: /* SLA+R received */
case 0xB0: /* SLA+R received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1;
case 0xB8: /* DATA sent and ACK received */
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
if (xfer->txSz > 0) {
cclr &= ~I2C_CON_AA;
}
ret = RET_SLAVE_TX;
break;
case 0xC0: /* Data transmitted and NAK received */
case 0xC8: /* Last data transmitted and ACK received */
case 0x88: /* SLA: Data received + NAK sent */
case 0x98: /* GC: Data received + NAK sent */
case 0xA0: /* STOP/Repeated START condition received */
ret = RET_SLAVE_IDLE;
cclr &= ~I2C_CON_AA;
xfer->status = I2C_STATUS_DONE;
if (xfer->slaveAddr & 1) {
cclr &= ~I2C_CON_STA;
}
break;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
return ret;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Chip event handler interrupt based */
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Wait for the status to change */
while (*stat == I2C_STATUS_BUSY) {}
}
/* Chip polling event handler */
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Call the state change handler till xfer is done */
while (*stat == I2C_STATUS_BUSY) {
if (Chip_I2C_IsStateChanged(id)) {
Chip_I2C_MasterStateHandler(id);
}
}
}
/* Initializes the LPC_I2C peripheral with specified parameter */
void Chip_I2C_Init(I2C_ID_T id)
{
enableClk(id);
/* Set I2C operation to default */
LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
}
/* De-initializes the I2C peripheral registers to their default reset values */
void Chip_I2C_DeInit(I2C_ID_T id)
{
/* Disable I2C control */
LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
disableClk(id);
}
/* Set up clock rate for LPC_I2C peripheral */
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate)
{
uint32_t SCLValue;
SCLValue = (getClkRate(id) / clockrate);
LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1);
LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH);
}
/* Get current clock rate for LPC_I2C peripheral */
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id)
{
return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL);
}
/* Set the master event handler */
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event)
{
struct i2c_interface *iic = &i2c[id];
if (!iic->mXfer) {
iic->mEvent = event;
}
return iic->mEvent == event;
}
/* Get the master event handler */
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id)
{
return i2c[id].mEvent;
}
/* Transmit and Receive data in master mode */
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer)
{
struct i2c_interface *iic = &i2c[id];
iic->mEvent(id, I2C_EVENT_LOCK);
xfer->status = I2C_STATUS_BUSY;
iic->mXfer = xfer;
/* If slave xfer not in progress */
if (!iic->sXfer) {
startMasterXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_WAIT);
iic->mXfer = 0;
/* Wait for stop condition to appear on bus */
while (!isI2CBusFree(iic->ip)) {}
/* Start slave if one is active */
if (SLAVE_ACTIVE(iic)) {
startSlaverXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_UNLOCK);
return (int) xfer->status;
}
/* Master tx only */
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = buff;
xfer.txSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.txSz;
}
/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
* This function is useful for communicating with the I2C slave registers
*/
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = &cmd;
xfer.txSz = 1;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
/* Sequential master read */
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
/* Check if master state is active */
int Chip_I2C_IsMasterActive(I2C_ID_T id)
{
return isMasterState(i2c[id].ip);
}
/* State change handler for master transfer */
void Chip_I2C_MasterStateHandler(I2C_ID_T id)
{
if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) {
i2c[id].mEvent(id, I2C_EVENT_DONE);
}
}
/* Setup slave function */
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask)
{
struct i2c_interface *iic = &i2c[id];
struct i2c_slave_interface *si2c = &i2c_slave[id][sid];
si2c->xfer = xfer;
si2c->event = event;
/* Set up the slave address */
if (sid != I2C_SLAVE_GENERAL) {
setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask);
}
if (!SLAVE_ACTIVE(iic) && !iic->mXfer) {
startSlaverXfer(iic->ip);
}
iic->flags |= 1 << (sid + 8);
}
/* I2C Slave event handler */
void Chip_I2C_SlaveStateHandler(I2C_ID_T id)
{
int ret;
struct i2c_interface *iic = &i2c[id];
/* Get the currently addressed slave */
if (!iic->sXfer) {
struct i2c_slave_interface *si2c;
I2C_SLAVE_ID sid = getSlaveIndex(iic->ip);
si2c = &i2c_slave[id][sid];
iic->sXfer = si2c->xfer;
iic->sEvent = si2c->event;
}
iic->sXfer->slaveAddr |= iic->mXfer != 0;
ret = handleSlaveXferState(iic->ip, iic->sXfer);
if (ret) {
if (iic->sXfer->status == I2C_STATUS_DONE) {
iic->sXfer = 0;
}
iic->sEvent(id, (I2C_EVENT_T) ret);
}
}
/* Disable I2C device */
void Chip_I2C_Disable(I2C_ID_T id)
{
LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC;
}
/* State change checking */
int Chip_I2C_IsStateChanged(I2C_ID_T id)
{
return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0;
}

260
hw/mcu/nxp/lpc_chip_175x_6x/src/i2s_17xx_40xx.c Normal file
View File

@ -0,0 +1,260 @@
/*
* @brief LPC17xx/40xx I2S driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Get divider value */
STATIC Status getClkDiv(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format, uint16_t *pxDiv, uint16_t *pyDiv, uint32_t *pN)
{
uint32_t pClk;
uint32_t x, y;
uint64_t divider;
uint16_t dif;
uint16_t xDiv = 0, yDiv = 0;
uint32_t N;
uint16_t err, ErrorOptimal = 0xFFFF;
#if defined(CHIP_LPC175X_6X)
pClk = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_I2S);
#else
pClk = Chip_Clock_GetPeripheralClockRate();
#endif
/* divider is a fixed point number with 16 fractional bits */
divider = (((uint64_t) (format->SampleRate) * 2 * (format->WordWidth) * 2) << 16) / pClk;
/* find N that make x/y <= 1 -> divider <= 2^16 */
for (N = 64; N > 0; N--) {
if ((divider * N) < (1 << 16)) {
break;
}
}
if (N == 0) {
return ERROR;
}
divider *= N;
for (y = 255; y > 0; y--) {
x = y * divider;
if (x & (0xFF000000)) {
continue;
}
dif = x & 0xFFFF;
if (dif > 0x8000) {
err = 0x10000 - dif;
}
else {
err = dif;
}
if (err == 0) {
yDiv = y;
break;
}
else if (err < ErrorOptimal) {
ErrorOptimal = err;
yDiv = y;
}
}
xDiv = ((uint64_t) yDiv * (format->SampleRate) * 2 * (format->WordWidth) * N * 2) / pClk;
if (xDiv >= 256) {
xDiv = 0xFF;
}
if (xDiv == 0) {
xDiv = 1;
}
*pxDiv = xDiv;
*pyDiv = yDiv;
*pN = N;
return SUCCESS;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the I2S interface */
void Chip_I2S_Init(LPC_I2S_T *pI2S)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2S);
}
/* Shutdown I2S */
void Chip_I2S_DeInit(LPC_I2S_T *pI2S)
{
pI2S->DAI = 0x07E1;
pI2S->DAO = 0x87E1;
pI2S->IRQ = 0;
pI2S->TXMODE = 0;
pI2S->RXMODE = 0;
pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] = 0;
pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] = 0;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_I2S);
}
/* Configure I2S for Audio Format input */
Status Chip_I2S_TxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format)
{
uint32_t temp;
uint16_t xDiv, yDiv;
uint32_t N;
if (getClkDiv(pI2S, format, &xDiv, &yDiv, &N) == ERROR) {
return ERROR;
}
temp = pI2S->DAO & (~(I2S_DAO_WORDWIDTH_MASK | I2S_DAO_MONO | I2S_DAO_SLAVE | I2S_DAO_WS_HALFPERIOD_MASK));
if (format->WordWidth <= 8) {
temp |= I2S_WORDWIDTH_8;
}
else if (format->WordWidth <= 16) {
temp |= I2S_WORDWIDTH_16;
}
else {
temp |= I2S_WORDWIDTH_32;
}
temp |= (format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO;
temp |= I2S_MASTER_MODE;
temp |= I2S_DAO_WS_HALFPERIOD(format->WordWidth - 1);
pI2S->DAO = temp;
pI2S->TXMODE = I2S_TXMODE_CLKSEL(0);
pI2S->TXBITRATE = N - 1;
pI2S->TXRATE = yDiv | (xDiv << 8);
return SUCCESS;
}
/* Configure I2S for Audio Format input */
Status Chip_I2S_RxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format)
{
uint32_t temp;
uint16_t xDiv, yDiv;
uint32_t N;
if (getClkDiv(pI2S, format, &xDiv, &yDiv, &N) == ERROR) {
return ERROR;
}
temp = pI2S->DAI & (~(I2S_DAI_WORDWIDTH_MASK | I2S_DAI_MONO | I2S_DAI_SLAVE | I2S_DAI_WS_HALFPERIOD_MASK));
if (format->WordWidth <= 8) {
temp |= I2S_WORDWIDTH_8;
}
else if (format->WordWidth <= 16) {
temp |= I2S_WORDWIDTH_16;
}
else {
temp |= I2S_WORDWIDTH_32;
}
temp |= (format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO;
temp |= I2S_MASTER_MODE;
temp |= I2S_DAI_WS_HALFPERIOD(format->WordWidth - 1);
pI2S->DAI = temp;
pI2S->RXMODE = I2S_RXMODE_CLKSEL(0);
pI2S->RXBITRATE = N - 1;
pI2S->RXRATE = yDiv | (xDiv << 8);
return SUCCESS;
}
/* Enable/Disable Interrupt with a specific FIFO depth */
void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth)
{
uint32_t temp;
depth &= 0x0F;
if (newState == ENABLE) {
pI2S->IRQ |= 0x02;
}
else {
pI2S->IRQ &= (~0x02);
}
temp = pI2S->IRQ & (~I2S_IRQ_TX_DEPTH_MASK);
pI2S->IRQ = temp | (I2S_IRQ_TX_DEPTH(depth));
}
/* Enable/Disable Interrupt with a specific FIFO depth */
void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth)
{
uint32_t temp;
depth &= 0x0F;
if (newState == ENABLE) {
pI2S->IRQ |= 0x01;
}
else {
pI2S->IRQ &= (~0x01);
}
temp = pI2S->IRQ & (~I2S_IRQ_RX_DEPTH_MASK);
pI2S->IRQ = temp | (I2S_IRQ_RX_DEPTH(depth));
}
/* Enable/Disable DMA with a specific FIFO depth */
void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S,
I2S_DMA_CHANNEL_T dmaNum,
FunctionalState newState,
uint8_t depth)
{
/* Set FIFO Level */
pI2S->DMA[dmaNum] &= ~(0x0F << 16);
pI2S->DMA[dmaNum] |= depth << 16;
/* Enable/Disable I2S transmit*/
if (newState == ENABLE) {
pI2S->DMA[dmaNum] |= 0x02;
}
else {
pI2S->DMA[dmaNum] &= ~0x02;
}
}
/* Enable/Disable DMA with a specific FIFO depth */
void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S,
I2S_DMA_CHANNEL_T dmaNum,
FunctionalState newState,
uint8_t depth)
{
/* Set FIFO Level */
pI2S->DMA[dmaNum] &= ~(0x0F << 8);
pI2S->DMA[dmaNum] |= depth << 8;
/* Enable/Disable I2S Receive */
if (newState == ENABLE) {
pI2S->DMA[dmaNum] |= 0x01;
}
else {
pI2S->DMA[dmaNum] &= ~0x01;
}
}

175
hw/mcu/nxp/lpc_chip_175x_6x/src/iap.c Normal file
View File

@ -0,0 +1,175 @@
/*
* @brief Common FLASH support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Prepare sector for write operation */
uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector)
{
uint32_t command[5], result[4];
command[0] = IAP_PREWRRITE_CMD;
command[1] = strSector;
command[2] = endSector;
iap_entry(command, result);
return result[0];
}
/* Copy RAM to flash */
uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt)
{
uint32_t command[5], result[4];
command[0] = IAP_WRISECTOR_CMD;
command[1] = dstAdd;
command[2] = (uint32_t) srcAdd;
command[3] = byteswrt;
command[4] = SystemCoreClock / 1000;
iap_entry(command, result);
return result[0];
}
/* Erase sector */
uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector)
{
uint32_t command[5], result[4];
command[0] = IAP_ERSSECTOR_CMD;
command[1] = strSector;
command[2] = endSector;
command[3] = SystemCoreClock / 1000;
iap_entry(command, result);
return result[0];
}
/* Blank check sector */
uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector)
{
uint32_t command[5], result[4];
command[0] = IAP_BLANK_CHECK_SECTOR_CMD;
command[1] = strSector;
command[2] = endSector;
iap_entry(command, result);
return result[0];
}
/* Read part identification number */
uint32_t Chip_IAP_ReadPID()
{
uint32_t command[5], result[4];
command[0] = IAP_REPID_CMD;
iap_entry(command, result);
return result[1];
}
/* Read boot code version number */
uint8_t Chip_IAP_ReadBootCode()
{
uint32_t command[5], result[4];
command[0] = IAP_READ_BOOT_CODE_CMD;
iap_entry(command, result);
return result[0];
}
/* IAP compare */
uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp)
{
uint32_t command[5], result[4];
command[0] = IAP_COMPARE_CMD;
command[1] = dstAdd;
command[2] = srcAdd;
command[3] = bytescmp;
iap_entry(command, result);
return result[0];
}
/* Reinvoke ISP */
uint8_t Chip_IAP_ReinvokeISP()
{
uint32_t command[5], result[4];
command[0] = IAP_REINVOKE_ISP_CMD;
iap_entry(command, result);
return result[0];
}
/* Read the unique ID */
uint32_t Chip_IAP_ReadUID()
{
uint32_t command[5], result[4];
command[0] = IAP_READ_UID_CMD;
iap_entry(command, result);
return result[1];
}
/* Erase page */
uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage)
{
uint32_t command[5], result[4];
command[0] = IAP_ERASE_PAGE_CMD;
command[1] = strPage;
command[2] = endPage;
command[3] = SystemCoreClock / 1000;
iap_entry(command, result);
return result[0];
}

83
hw/mcu/nxp/lpc_chip_175x_6x/src/iocon_17xx_40xx.c Normal file
View File

@ -0,0 +1,83 @@
/*
* @brief LPC17xx/40xx IOCON driver
*
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#if defined(CHIP_LPC175X_6X)
/* Sets I/O Control pin mux */
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
{
Chip_IOCON_PinMux(pIOCON, port, pin,
/* mode is in bits 3:2 */
modefunc >> 2,
/* func is in bits 1:0 */
modefunc & 3 );
}
/* Setup pin modes and function */
void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t mode, uint8_t func)
{
uint8_t reg, bitPos;
uint32_t temp;
bitPos = IOCON_BIT_INDEX(pin);
reg = IOCON_REG_INDEX(port,pin);
temp = pIOCON->PINSEL[reg] & ~(0x03UL << bitPos);
pIOCON->PINSEL[reg] = temp | (func << bitPos);
temp = pIOCON->PINMODE[reg] & ~(0x03UL << bitPos);
pIOCON->PINMODE[reg] = temp | (mode << bitPos);
}
#endif /* defined(CHIP_LPC175X_6X) */
/* Set all I/O Control pin muxing */
void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength)
{
uint32_t ix;
for (ix = 0; ix < arrayLength; ix++ ) {
Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].pingrp, pinArray[ix].pinnum, pinArray[ix].modefunc);
}
}

210
hw/mcu/nxp/lpc_chip_175x_6x/src/lcd_17xx_40xx.c Normal file
View File

@ -0,0 +1,210 @@
/*
* @brief LCD chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
static LCD_CURSOR_SIZE_OPT_T LCD_Cursor_Size = LCD_CURSOR_64x64;
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the LCD controller */
void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_CONFIG_T *LCD_ConfigStruct)
{
uint32_t i, regValue, *pPal;
uint32_t pcd;
/* Enable LCD Clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_LCD);
/* disable the display */
pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
/* Setting LCD_TIMH register */
regValue = ( ((((LCD_ConfigStruct->PPL / 16) - 1) & 0x3F) << 2)
| (( (LCD_ConfigStruct->HSW - 1) & 0xFF) << 8)
| (( (LCD_ConfigStruct->HFP - 1) & 0xFF) << 16)
| (( (LCD_ConfigStruct->HBP - 1) & 0xFF) << 24) );
pLCD->TIMH = regValue;
/* Setting LCD_TIMV register */
regValue = ((((LCD_ConfigStruct->LPP - 1) & 0x3FF) << 0)
| (((LCD_ConfigStruct->VSW - 1) & 0x03F) << 10)
| (((LCD_ConfigStruct->VFP - 1) & 0x0FF) << 16)
| (((LCD_ConfigStruct->VBP - 1) & 0x0FF) << 24) );
pLCD->TIMV = regValue;
/* Generate the clock and signal polarity control word */
regValue = 0;
regValue = (((LCD_ConfigStruct->ACB - 1) & 0x1F) << 6);
regValue |= (LCD_ConfigStruct->IOE & 1) << 14;
regValue |= (LCD_ConfigStruct->IPC & 1) << 13;
regValue |= (LCD_ConfigStruct->IHS & 1) << 12;
regValue |= (LCD_ConfigStruct->IVS & 1) << 11;
/* Compute clocks per line based on panel type */
switch (LCD_ConfigStruct->LCD) {
case LCD_MONO_4:
regValue |= ((((LCD_ConfigStruct->PPL / 4) - 1) & 0x3FF) << 16);
break;
case LCD_MONO_8:
regValue |= ((((LCD_ConfigStruct->PPL / 8) - 1) & 0x3FF) << 16);
break;
case LCD_CSTN:
regValue |= (((((LCD_ConfigStruct->PPL * 3) / 8) - 1) & 0x3FF) << 16);
break;
case LCD_TFT:
default:
regValue |= /*1<<26 |*/ (((LCD_ConfigStruct->PPL - 1) & 0x3FF) << 16);
}
/* panel clock divisor */
pcd = 5;// LCD_ConfigStruct->pcd; /* TODO: should be calculated from LCDDCLK */
pcd &= 0x3FF;
regValue |= ((pcd >> 5) << 27) | ((pcd) & 0x1F);
pLCD->POL = regValue;
/* disable interrupts */
pLCD->INTMSK = 0;
/* set bits per pixel */
regValue = LCD_ConfigStruct->BPP << 1;
/* set color format RGB */
regValue |= LCD_ConfigStruct->color_format << 8;
regValue |= LCD_ConfigStruct->LCD << 4;
if (LCD_ConfigStruct->Dual == 1) {
regValue |= 1 << 7;
}
pLCD->CTRL = regValue;
/* clear palette */
pPal = (uint32_t *) (&(pLCD->PAL));
for (i = 0; i < 128; i++) {
*pPal = 0;
pPal++;
}
}
/* Shutdown the LCD controller */
void Chip_LCD_DeInit(LPC_LCD_T *pLCD)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_LCD);
}
/* Configure Cursor */
void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync)
{
LCD_Cursor_Size = cursor_size;
pLCD->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size;
}
/* Write Cursor Image into Internal Cursor Image Buffer */
void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image)
{
int i, j;
uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image;
/* Check if Cursor Size was configured as 32x32 or 64x64*/
if (LCD_Cursor_Size == LCD_CURSOR_32x32) {
i = cursor_num * 64;
j = i + 64;
}
else {
i = 0;
j = 256;
}
fifoptr = (void *) &(pLCD->CRSR_IMG[0]);
/* Copy Cursor Image content to FIFO */
for (; i < j; i++) {
*fifoptr = *crsr_ptr;
crsr_ptr++;
fifoptr++;
}
}
/* Load LCD Palette */
void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette)
{
LCD_PALETTE_ENTRY_T pal_entry, *ptr_pal_entry;
uint8_t i, *pal_ptr;
/* This function supports loading of the color palette from
the C file generated by the bmp2c utility. It expects the
palette to be passed as an array of 32-bit BGR entries having
the following format:
2:0 - Not used
7:3 - Blue
10:8 - Not used
15:11 - Green
18:16 - Not used
23:19 - Red
31:24 - Not used
arg = pointer to input palette table address */
ptr_pal_entry = &pal_entry;
pal_ptr = (uint8_t *) palette;
/* 256 entry in the palette table */
for (i = 0; i < 256 / 2; i++) {
pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */
pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */
pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */
pal_ptr++; /* skip over the unused byte */
/* do the most significant halfword of the palette */
pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */
pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */
pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */
pal_ptr++; /* skip over the unused byte */
pLCD->PAL[i] = *((uint32_t *) ptr_pal_entry);
}
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */

118
hw/mcu/nxp/lpc_chip_175x_6x/src/pmu_17xx_40xx.c Normal file
View File

@ -0,0 +1,118 @@
/*
* @brief LPC15xx PMU chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Enter MCU Sleep mode */
void Chip_PMU_SleepState(LPC_PMU_T *pPMU)
{
/* Select Sleep/Deep Sleep mode */
pPMU->PCON &= ~(PMU_PCON_PM1_FLAG | PMU_PCON_PM0_FLAG);
/* Clearing SLEEPDEEP bit in SCR makes it Sleep mode */
SCB->SCR &= ~(1UL << SCB_SCR_SLEEPDEEP_Pos);
/* Enter sleep mode */
__WFI();
}
/* Enter MCU Deep Sleep mode */
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU)
{
/* Select Sleep/Deep Sleep mode */
pPMU->PCON &= ~(PMU_PCON_PM1_FLAG | PMU_PCON_PM0_FLAG);
/* Setting SLEEPDEEP bit in SCR makes it Deep Sleep mode */
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
/* Enter sleep mode */
__WFI();
}
/* Enter MCU Power down mode */
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU)
{
/* Select power down mode */
pPMU->PCON = (pPMU->PCON & ~PMU_PCON_PM1_FLAG) | PMU_PCON_PM0_FLAG;
/* Setting SLEEPDEEP bit in SCR makes it power down mode */
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
/* Enter sleep mode */
__WFI();
}
/* Enter MCU Deep Power down mode */
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU)
{
/* Select deep power down mode */
pPMU->PCON |= PMU_PCON_PM1_FLAG | PMU_PCON_PM0_FLAG;
/* Setting SLEEPDEEP bit in SCR makes it deep power down mode */
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
/* Enter sleep mode */
__WFI();
}
/* Put some of the peripheral in sleep mode */
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode)
{
if (SleepMode == PMU_MCU_DEEP_SLEEP) {
Chip_PMU_DeepSleepState(pPMU);
}
else if (SleepMode == PMU_MCU_POWER_DOWN) {
Chip_PMU_PowerDownState(pPMU);
}
else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
Chip_PMU_DeepPowerDownState(pPMU);
}
else {
/* PMU_MCU_SLEEP */
Chip_PMU_SleepState(pPMU);
}
}

167
hw/mcu/nxp/lpc_chip_175x_6x/src/ring_buffer.c Normal file
View File

@ -0,0 +1,167 @@
/*
* @brief Common ring buffer support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include <string.h>
#include "ring_buffer.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1))
#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1))
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize ring buffer */
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
{
RingBuff->data = buffer;
RingBuff->count = count;
RingBuff->itemSz = itemSize;
RingBuff->head = RingBuff->tail = 0;
return 1;
}
/* Insert a single item into Ring Buffer */
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, RingBuff->itemSz);
RingBuff->head++;
return 1;
}
/* Insert multiple items into Ring Buffer */
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num)
{
uint8_t *ptr = RingBuff->data;
int cnt1, cnt2;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
/* Calculate the segment lengths */
cnt1 = cnt2 = RingBuffer_GetFree(RingBuff);
if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count)
cnt1 = RingBuff->count - RB_INDH(RingBuff);
cnt2 -= cnt1;
cnt1 = MIN(cnt1, num);
num -= cnt1;
cnt2 = MIN(cnt2, num);
num -= cnt2;
/* Write segment 1 */
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, cnt1 * RingBuff->itemSz);
RingBuff->head += cnt1;
/* Write segment 2 */
ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz;
data = (const uint8_t *) data + cnt1 * RingBuff->itemSz;
memcpy(ptr, data, cnt2 * RingBuff->itemSz);
RingBuff->head += cnt2;
return cnt1 + cnt2;
}
/* Pop single item from Ring Buffer */
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot pop when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, RingBuff->itemSz);
RingBuff->tail++;
return 1;
}
/* Pop multiple items from Ring buffer */
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num)
{
uint8_t *ptr = RingBuff->data;
int cnt1, cnt2;
/* We cannot insert when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
/* Calculate the segment lengths */
cnt1 = cnt2 = RingBuffer_GetCount(RingBuff);
if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count)
cnt1 = RingBuff->count - RB_INDT(RingBuff);
cnt2 -= cnt1;
cnt1 = MIN(cnt1, num);
num -= cnt1;
cnt2 = MIN(cnt2, num);
num -= cnt2;
/* Write segment 1 */
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, cnt1 * RingBuff->itemSz);
RingBuff->tail += cnt1;
/* Write segment 2 */
ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz;
data = (uint8_t *) data + cnt1 * RingBuff->itemSz;
memcpy(data, ptr, cnt2 * RingBuff->itemSz);
RingBuff->tail += cnt2;
return cnt1 + cnt2;
}

100
hw/mcu/nxp/lpc_chip_175x_6x/src/ritimer_17xx_40xx.c Normal file
View File

@ -0,0 +1,100 @@
/*
* @brief LPC17xx/40xx RITimer driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC175X_6X)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the RIT */
void Chip_RIT_Init(LPC_RITIMER_T *pRITimer)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RIT);
pRITimer->COMPVAL = 0xFFFFFFFF;
pRITimer->MASK = 0x00000000;
pRITimer->CTRL = 0x0C;
pRITimer->COUNTER = 0x00000000;
}
/* DeInitialize the RIT */
void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer)
{
Chip_RIT_Init(pRITimer);
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_RIT);
}
/* Set timer interval value */
void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval)
{
uint32_t cmp_value;
/* Determine aapproximate compare value based on clock rate and passed interval */
cmp_value = (Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_RIT) / 1000) * time_interval;
/* Set timer compare value */
Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
/* Set timer enable clear bit to clear timer to 0 whenever
counter value equals the contents of RICOMPVAL */
Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR);
}
/* Check whether interrupt is pending */
IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)
{
uint8_t result;
if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) {
result = SET;
}
else {
return RESET;
}
return (IntStatus) result;
}
#endif /* defined(CHIP_LPC175X_6X) */

221
hw/mcu/nxp/lpc_chip_175x_6x/src/rtc_17xx_40xx.c Normal file
View File

@ -0,0 +1,221 @@
/*
* @brief LPC17xx/40xx RTC chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the RTC peripheral */
void Chip_RTC_Init(LPC_RTC_T *pRTC)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RTC);
/* Disable RTC */
Chip_RTC_Enable(pRTC, DISABLE);
/* Disable Calibration */
Chip_RTC_CalibCounterCmd(pRTC, DISABLE);
/* Reset RTC Clock */
Chip_RTC_ResetClockTickCounter(pRTC);
/* Clear counter increment and alarm interrupt */
pRTC->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF;
while (pRTC->ILR != 0) {}
/* Clear all register to be default */
pRTC->CIIR = 0x00;
pRTC->AMR = 0xFF;
pRTC->CALIBRATION = 0x00;
}
/*De-initialize the RTC peripheral */
void Chip_RTC_DeInit(LPC_RTC_T *pRTC)
{
pRTC->CCR = 0x00;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_RTC);
}
/* Reset clock tick counter in the RTC peripheral */
void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC)
{
do {
/* Reset RTC clock*/
pRTC->CCR |= RTC_CCR_CTCRST;
} while ((pRTC->CCR & RTC_CCR_CTCRST) != RTC_CCR_CTCRST);
do {
/* Finish resetting RTC clock */
pRTC->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;
} while (pRTC->CCR & RTC_CCR_CTCRST);
}
/* Start/Stop RTC peripheral */
void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState)
{
if (NewState == ENABLE) {
do {
pRTC->CCR |= RTC_CCR_CLKEN;
} while ((pRTC->CCR & RTC_CCR_CLKEN) == 0);
}
else {
pRTC->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
}
}
/* Enable/Disable Counter increment interrupt for a time type in the RTC peripheral */
void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState)
{
if (NewState == ENABLE) {
pRTC->CIIR |= cntrMask;
}
else {
pRTC->CIIR &= (~cntrMask) & RTC_AMR_CIIR_BITMASK;
while (pRTC->CIIR & cntrMask) {}
}
}
/* Enable/Disable Alarm interrupt for a time type in the RTC peripheral */
void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState)
{
if (NewState == ENABLE) {
pRTC->AMR &= (~alarmMask) & RTC_AMR_CIIR_BITMASK;
}
else {
pRTC->AMR |= (alarmMask);
while ((pRTC->AMR & alarmMask) == 0) {}
}
}
/* Set full time in the RTC peripheral */
void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
{
RTC_TIMEINDEX_T i;
uint32_t ccr_val = pRTC->CCR;
/* Temporarily disable */
if (ccr_val & RTC_CCR_CLKEN) {
pRTC->CCR = ccr_val & (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
}
/* Date time setting */
for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
pRTC->TIME[i] = pFullTime->time[i];
}
/* Restore to old setting */
pRTC->CCR = ccr_val;
}
/* Get full time from the RTC peripheral */
void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
{
RTC_TIMEINDEX_T i;
uint32_t secs = 0xFF;
/* Read full time, but verify second tick didn't change during the read. If
it did, re-read the time again so it will be consistent across all fields. */
while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) {
secs = pFullTime->time[RTC_TIMETYPE_SECOND] = pRTC->TIME[RTC_TIMETYPE_SECOND];
for (i = RTC_TIMETYPE_MINUTE; i < RTC_TIMETYPE_LAST; i++) {
pFullTime->time[i] = pRTC->TIME[i];
}
}
}
/* Set full alarm time in the RTC peripheral */
void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
{
RTC_TIMEINDEX_T i;
for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
pRTC->ALRM[i] = pFullTime->time[i];
}
}
/* Get full alarm time in the RTC peripheral */
void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
{
RTC_TIMEINDEX_T i;
for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
pFullTime->time[i] = pRTC->ALRM[i];
}
}
/* Enable/Disable calibration counter in the RTC peripheral */
void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState)
{
if (NewState == ENABLE) {
do {
pRTC->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;
} while (pRTC->CCR & RTC_CCR_CCALEN);
}
else {
pRTC->CCR |= RTC_CCR_CCALEN;
}
}
#if RTC_EV_SUPPORT
/* Get first timestamp value */
void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp)
{
pTimeStamp->sec = RTC_ER_TIMESTAMP_SEC(pRTC->ERFIRSTSTAMP[ch]);
pTimeStamp->min = RTC_ER_TIMESTAMP_MIN(pRTC->ERFIRSTSTAMP[ch]);
pTimeStamp->hour = RTC_ER_TIMESTAMP_HOUR(pRTC->ERFIRSTSTAMP[ch]);
pTimeStamp->dayofyear = RTC_ER_TIMESTAMP_DOY(pRTC->ERFIRSTSTAMP[ch]);
}
/* Get last timestamp value */
void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp)
{
pTimeStamp->sec = RTC_ER_TIMESTAMP_SEC(pRTC->ERLASTSTAMP[ch]);
pTimeStamp->min = RTC_ER_TIMESTAMP_MIN(pRTC->ERLASTSTAMP[ch]);
pTimeStamp->hour = RTC_ER_TIMESTAMP_HOUR(pRTC->ERLASTSTAMP[ch]);
pTimeStamp->dayofyear = RTC_ER_TIMESTAMP_DOY(pRTC->ERLASTSTAMP[ch]);
}
#endif /*RTC_EV_SUPPORT*/

247
hw/mcu/nxp/lpc_chip_175x_6x/src/sdc_17xx_40xx.c Normal file
View File

@ -0,0 +1,247 @@
/*
* @brief SD Card Interface registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
static void writeDelay(void)
{
volatile uint8_t i;
for ( i = 0; i < 0x10; i++ ) { /* delay 3MCLK + 2PCLK */
}
}
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Set power state of SDC peripheral */
void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag)
{
pSDC->POWER = SDC_PWR_CTRL(pwrMode) | flag;
writeDelay();
}
/* Set clock divider for SDC peripheral */
void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div)
{
uint32_t temp;
temp = (pSDC->CLOCK & (~SDC_CLOCK_CLKDIV_BITMASK));
pSDC->CLOCK = temp | (SDC_CLOCK_CLKDIV(div));
writeDelay();
}
/* Clock control for SDC peripheral*/
void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
FunctionalState NewState)
{
if (NewState) {
pSDC->CLOCK |= (1 << ctrlType);
}
else {
pSDC->CLOCK &= (~(1 << ctrlType));
}
writeDelay();
}
/* Initialize SDC peripheral */
static void SDC_Init(LPC_SDC_T *pSDC)
{
/* Disable SD_CLK */
Chip_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, DISABLE);
/* Power-off */
Chip_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
writeDelay();
/* Disable all interrupts */
pSDC->MASK0 = 0;
/*Setting for timeout problem */
pSDC->DATATIMER = 0x1FFFFFFF;
pSDC->COMMAND = 0;
writeDelay();
pSDC->DATACTRL = 0;
writeDelay();
/* clear all pending interrupts */
pSDC->CLEAR = SDC_CLEAR_ALL;
}
/* Initializes the SDC card controller */
void Chip_SDC_Init(LPC_SDC_T *pSDC)
{
uint32_t i = 0;
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SDC);
Chip_SYSCTL_PeriphReset(SYSCTL_RESET_PCSDC);
/* Initialize GPDMA controller */
Chip_GPDMA_Init(LPC_GPDMA);
/* Initialize SDC peripheral */
SDC_Init(pSDC);
/* Power-up SDC Peripheral */
Chip_SDC_PowerControl(pSDC, SDC_POWER_UP, 0);
/* delays for the supply output is stable*/
for ( i = 0; i < 0x80000; i++ ) {}
Chip_SDC_SetClock(pSDC, SDC_IDENT_CLOCK_RATE);
Chip_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, ENABLE);
/* Power-on SDC Interface */
Chip_SDC_PowerControl(pSDC, SDC_POWER_ON, 0);
}
/* Set Command Info */
void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg)
{
/* Clear status register */
pSDC->CLEAR = SDC_CLEAR_ALL;
/* Set the argument first, finally command */
pSDC->ARGUMENT = Arg;
/* Write command value, enable the command */
pSDC->COMMAND = Cmd | SDC_COMMAND_ENABLE;
writeDelay();
}
/* Reset Command Info */
void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC)
{
pSDC->CLEAR = SDC_CLEAR_ALL;
pSDC->ARGUMENT = 0xFFFFFFFF;
pSDC->COMMAND = 0;
writeDelay();
}
/* Get Command response */
void Chip_SDC_GetResp(LPC_SDC_T *pSDC, SDC_RESP_T *pResp)
{
uint8_t i;
pResp->CmdIndex = SDC_RESPCOMMAND_VAL(pSDC->RESPCMD);
for (i = 0; i < SDC_CARDSTATUS_BYTENUM; i++) {
pResp->Data[i] = pSDC->RESPONSE[i];
}
}
/* Setup Data Transfer Information */
void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer)
{
uint32_t DataCtrl = 0;
pSDC->DATATIMER = pTransfer->Timeout;
pSDC->DATALENGTH = pTransfer->BlockNum * SDC_DATACTRL_BLOCKSIZE_VAL(pTransfer->BlockSize);
DataCtrl = SDC_DATACTRL_ENABLE;
DataCtrl |= ((uint32_t) pTransfer->Dir) | ((uint32_t) pTransfer->Mode) | SDC_DATACTRL_BLOCKSIZE(
pTransfer->BlockSize);
if (pTransfer->DMAUsed) {
DataCtrl |= SDC_DATACTRL_DMA_ENABLE;
}
pSDC->DATACTRL = DataCtrl;
writeDelay();
}
/* Write data to FIFO */
void Chip_SDC_WriteFIFO(LPC_SDC_T *pSDC, uint32_t *pSrc, bool bFirstHalf)
{
uint8_t start = 0, end = 7;
if (!bFirstHalf) {
start += 8;
end += 8;
}
for (; start <= end; start++) {
pSDC->FIFO[start] = *pSrc;
pSrc++;
}
}
/* Read data from FIFO */
void Chip_SDC_ReadFIFO(LPC_SDC_T *pSDC, uint32_t *pDst, bool bFirstHalf)
{
uint8_t start = 0, end = 7;
if (!bFirstHalf) {
start += 8;
end += 8;
}
for (; start <= end; start++) {
*pDst = pSDC->FIFO[start];
pDst++;
}
}
/* Set SD_CLK Clock */
void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq)
{
uint32_t PClk;
uint32_t ClkValue = 0;
PClk = Chip_Clock_GetPeripheralClockRate();
ClkValue = (PClk + 2 * freq - 1) / (2 * freq);
if (ClkValue > 0) {
ClkValue -= 1;
}
Chip_SDC_SetClockDiv(pSDC, ClkValue);
}
/* Shutdown the SDC card controller */
void Chip_SDC_DeInit(LPC_SDC_T *pSDC)
{
/* Power-off */
Chip_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SDC);
}
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC4XX) */

1196
hw/mcu/nxp/lpc_chip_175x_6x/src/sdmmc_17xx_40xx.c Normal file
View File

File diff suppressed because it is too large Load Diff

227
hw/mcu/nxp/lpc_chip_175x_6x/src/spi_17xx_40xx.c Normal file
View File

@ -0,0 +1,227 @@
/*
* @brief LPC17xx/40xx SPI driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC175X_6X)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Execute callback function */
STATIC void executeCallback(LPC_SPI_T *pSPI, SPI_CALLBACK_T pfunc)
{
if (pfunc) {
(pfunc) ();
}
}
/* Write byte(s) to FIFO buffer */
STATIC void writeData(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint32_t num_bytes)
{
uint16_t data2write = 0xFFFF;
if ( pXfSetup->pTxData) {
data2write = pXfSetup->pTxData[pXfSetup->cnt];
if (num_bytes == 2) {
data2write |= pXfSetup->pTxData[pXfSetup->cnt + 1] << 8;
}
}
Chip_SPI_SendFrame(pSPI, data2write);
}
/* Read byte(s) from FIFO buffer */
STATIC void readData(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint16_t rDat, uint32_t num_bytes)
{
rDat = Chip_SPI_ReceiveFrame(pSPI);
if (pXfSetup->pRxData) {
pXfSetup->pRxData[pXfSetup->cnt] = rDat;
if (num_bytes == 2) {
pXfSetup->pRxData[pXfSetup->cnt + 1] = rDat >> 8;
}
}
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* SPI Polling Read/Write in blocking mode */
uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
{
uint32_t status;
uint16_t rDat = 0x0000;
uint8_t bytes = 1;
/* Clear status */
Chip_SPI_Int_FlushData(pSPI);
if (Chip_SPI_GetDataSize(pSPI) != SPI_BITS_8) {
bytes = 2;
}
executeCallback(pSPI, pXfSetup->fnBefTransfer);
while (pXfSetup->cnt < pXfSetup->length) {
executeCallback(pSPI, pXfSetup->fnBefFrame);
/* write data to buffer */
writeData(pSPI, pXfSetup, bytes);
/* Wait for transfer completes */
while (1) {
status = Chip_SPI_GetStatus(pSPI);
/* Check error */
if (status & SPI_SR_ERROR) {
goto rw_end;
}
if (status & SPI_SR_SPIF) {
break;
}
}
executeCallback(pSPI, pXfSetup->fnAftFrame);
/* Read data*/
readData(pSPI, pXfSetup, rDat, bytes);
pXfSetup->cnt += bytes;
}
rw_end:
executeCallback(pSPI, pXfSetup->fnAftTransfer);
return pXfSetup->cnt;
}
/* Clean all data in RX FIFO of SPI */
void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI)
{
volatile uint32_t tmp;
Chip_SPI_GetStatus(pSPI);
tmp = Chip_SPI_ReceiveFrame(pSPI);
Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF);
}
/* SPI Interrupt Read/Write with 8-bit frame width */
Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint8_t bytes)
{
uint32_t status;
uint16_t rDat = 0x0000;
status = Chip_SPI_GetStatus(pSPI);
/* Check error status */
if (status & SPI_SR_ERROR) {
return ERROR;
}
Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF);
if (status & SPI_SR_SPIF) {
executeCallback(pSPI, pXfSetup->fnAftFrame);
if (pXfSetup->cnt < pXfSetup->length) {
/* read data */
readData(pSPI, pXfSetup, rDat, bytes);
pXfSetup->cnt += bytes;
}
}
if (pXfSetup->cnt < pXfSetup->length) {
executeCallback(pSPI, pXfSetup->fnBefFrame);
/* Write data */
writeData(pSPI, pXfSetup, bytes);
}
else {
executeCallback(pSPI, pXfSetup->fnAftTransfer);
}
return SUCCESS;
}
/* SPI Interrupt Read/Write with 8-bit frame width */
Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
{
return Chip_SPI_Int_RWFrames(pSPI, pXfSetup, 1);
}
/* SPI Interrupt Read/Write with 16-bit frame width */
Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
{
return Chip_SPI_Int_RWFrames(pSPI, pXfSetup, 2);
}
/* Set the clock frequency for SPI interface */
void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate)
{
uint32_t spiClk, counter;
/* Get SPI clock rate */
spiClk = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_SPI);
counter = spiClk / bitRate;
if (counter < 8) {
counter = 8;
}
counter = ((counter + 1) / 2) * 2;
if (counter > 254) {
counter = 254;
}
Chip_SPI_SetClockCounter(pSPI, counter);
}
/* Initialize the SPI */
void Chip_SPI_Init(LPC_SPI_T *pSPI)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SPI);
Chip_SPI_SetMode(pSPI, SPI_MODE_MASTER);
pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | SPI_BITS_8 | SPI_CLOCK_CPHA0_CPOL0 | SPI_DATA_MSB_FIRST;
Chip_SPI_SetBitRate(pSPI, 400000);
}
/* De-initializes the SPI peripheral */
void Chip_SPI_DeInit(LPC_SPI_T *pSPI)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SPI);
}
#endif /* defined(CHIP_LPC175X_6X) */

478
hw/mcu/nxp/lpc_chip_175x_6x/src/ssp_17xx_40xx.c Normal file
View File

@ -0,0 +1,478 @@
/*
* @brief LPC17xx/40xx SSP driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data +
xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFFFF);
}
xf_setup->tx_cnt += 2;
}
/** SSP macro: write 1 bytes to FIFO buffer */
STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFF);
}
xf_setup->tx_cnt++;
}
/** SSP macro: read 1 bytes from FIFO buffer */
STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt += 2;
}
}
/** SSP macro: read 2 bytes from FIFO buffer */
STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt++;
}
}
/* Returns clock for the peripheral block */
STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_CLOCK_T clkSSP;
if (pSSP == LPC_SSP1) {
clkSSP = SYSCTL_CLOCK_SSP1;
}
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
else if (pSSP == LPC_SSP2) {
clkSSP = SYSCTL_CLOCK_SSP2;
}
#endif
else {
clkSSP = SYSCTL_CLOCK_SSP0;
}
return clkSSP;
}
#if defined(CHIP_LPC175X_6X)
/* Returns clock ID for the peripheral block */
STATIC CHIP_SYSCTL_PCLK_T Chip_SSP_GetClkIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_PCLK_T clkSSP;
if (pSSP == LPC_SSP0) {
clkSSP = SYSCTL_PCLK_SSP0;
}
else {
clkSSP = SYSCTL_PCLK_SSP1;
}
return clkSSP;
}
#endif
/*****************************************************************************
* Public functions
****************************************************************************/
/*Set up output clocks per bit for SSP bus*/
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
{
uint32_t temp;
temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
pSSP->CPSR = prescale;
}
/* SSP Polling Read/Write in blocking mode */
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
/* write data to buffer */
if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
SSP_Write2BFifo(pSSP, xf_setup);
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read2BFifo(pSSP, xf_setup);
}
}
else {
while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
/* write data to buffer */
if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
SSP_Write1BFifo(pSSP, xf_setup);
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read1BFifo(pSSP, xf_setup);
}
}
if (xf_setup->tx_data) {
return xf_setup->tx_cnt;
}
else if (xf_setup->rx_data) {
return xf_setup->rx_cnt;
}
return 0;
}
/* SSP Polling Write in blocking mode */
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t tx_cnt = 0, rx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *wdata16;
wdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, *wdata16);
wdata16++;
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
rx_cnt += 2;
}
}
}
else {
uint8_t *wdata8;
wdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, *wdata8);
wdata8++;
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
rx_cnt++;
}
}
}
return tx_cnt;
}
/* SSP Polling Read in blocking mode */
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t rx_cnt = 0, tx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *rdata16;
rdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
rdata16++;
rx_cnt += 2;
}
}
}
else {
uint8_t *rdata8;
rdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
rdata8++;
rx_cnt++;
}
}
}
return rx_cnt;
}
/* Clean all data in RX FIFO of SSP */
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
{
if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
}
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
}
/* SSP Interrupt Read/Write with 8-bit frame width */
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
/* check if RX FIFO contains data */
SSP_Read1BFifo(pSSP, xf_setup);
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
/* Write data to buffer */
SSP_Write1BFifo(pSSP, xf_setup);
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read1BFifo(pSSP, xf_setup);
}
return SUCCESS;
}
return ERROR;
}
/* SSP Interrupt Read/Write with 16-bit frame width */
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
/* check if RX FIFO contains data */
SSP_Read2BFifo(pSSP, xf_setup);
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
/* Write data to buffer */
SSP_Write2BFifo(pSSP, xf_setup);
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read2BFifo(pSSP, xf_setup);
}
return SUCCESS;
}
return ERROR;
}
/* Set the SSP operating modes, master or slave */
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
{
if (master) {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
}
else {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
}
}
/* Set the clock frequency for SSP interface */
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
{
uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
#if defined(CHIP_LPC175X_6X)
ssp_clk = Chip_Clock_GetPeripheralClockRate(Chip_SSP_GetClkIndex(pSSP));
#else
ssp_clk = Chip_Clock_GetPeripheralClockRate();
#endif
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > bitRate) {
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > bitRate) {
cr0_div++;
if (cr0_div > 0xFF) {
cr0_div = 0;
prescale += 2;
}
}
}
Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
}
/* Initialize the SSP */
void Chip_SSP_Init(LPC_SSP_T *pSSP)
{
Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
Chip_SSP_SetBitRate(pSSP, 100000);
}
/* De-initializes the SSP peripheral */
void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
{
Chip_SSP_Disable(pSSP);
Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
}

110
hw/mcu/nxp/lpc_chip_175x_6x/src/stopwatch_17xx_40xx.c Normal file
View File

@ -0,0 +1,110 @@
/*
* @brief LPC17xx_40xx specific stopwatch implementation
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#include "stopwatch.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Precompute these to optimize runtime */
static uint32_t ticksPerSecond;
static uint32_t ticksPerMs;
static uint32_t ticksPerUs;
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize stopwatch */
void StopWatch_Init(void)
{
/* Use timer 1. Set prescaler to divide by 8, should give ticks at 3.75 MHz.
That gives a useable stopwatch measurement range of about 19 minutes
(if system clock is running at 120 MHz). */
const uint32_t prescaleDivisor = 8;
Chip_TIMER_Init(LPC_TIMER1);
Chip_TIMER_PrescaleSet(LPC_TIMER1, prescaleDivisor - 1);
Chip_TIMER_Enable(LPC_TIMER1);
/* Pre-compute tick rate. Note that peripheral clock supplied to the
timer includes a fixed divide by 4. */
ticksPerSecond = Chip_Clock_GetSystemClockRate() / prescaleDivisor / 4;
ticksPerMs = ticksPerSecond / 1000;
ticksPerUs = ticksPerSecond / 1000000;
}
/* Start a stopwatch */
uint32_t StopWatch_Start(void)
{
/* Return the current timer count. */
return Chip_TIMER_ReadCount(LPC_TIMER1);
}
/* Returns number of ticks per second of the stopwatch timer */
uint32_t StopWatch_TicksPerSecond(void)
{
return ticksPerSecond;
}
/* Converts from stopwatch ticks to mS. */
uint32_t StopWatch_TicksToMs(uint32_t ticks)
{
return ticks / ticksPerMs;
}
/* Converts from stopwatch ticks to uS. */
uint32_t StopWatch_TicksToUs(uint32_t ticks)
{
return ticks / ticksPerUs;
}
/* Converts from mS to stopwatch ticks. */
uint32_t StopWatch_MsToTicks(uint32_t mS)
{
return mS * ticksPerMs;
}
/* Converts from uS to stopwatch ticks. */
uint32_t StopWatch_UsToTicks(uint32_t uS)
{
return uS * ticksPerUs;
}

70
hw/mcu/nxp/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c Normal file
View File

@ -0,0 +1,70 @@
/*
* @brief LPC17xx/40xx System and Control driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Returns and clears the current sleep mode entry flags */
uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags) {
uint32_t savedFlags = LPC_SYSCTL->PCON;
LPC_SYSCTL->PCON = flags;
return savedFlags & (SYSCTL_PD_SMFLAG | SYSCTL_PD_DSFLAG |
SYSCTL_PD_PDFLAG | SYSCTL_PD_DPDFLAG);
}
#if !defined(CHIP_LPC175X_6X)
/* Resets a peripheral */
void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph)
{
uint32_t bitIndex, regIndex = (uint32_t) periph;
/* Get register array index and clock index into the register */
bitIndex = (regIndex % 32);
regIndex = regIndex / 32;
/* Reset peripheral */
LPC_SYSCTL->RSTCON[regIndex] = (1 << bitIndex);
LPC_SYSCTL->RSTCON[regIndex] &= ~(1 << bitIndex);
}
#endif /*!defined(CHIP_LPC175X_6X)*/

178
hw/mcu/nxp/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c Normal file
View File

@ -0,0 +1,178 @@
/*
* @brief LPC17xx/40xx Chip specific SystemInit
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#if defined(CHIP_LPC175X_6X)
void Chip_SetupIrcClocking(void)
{
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* FCCO = ((44+1) * 2 * 4MHz) / (0+1) = 360MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 44, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(2);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
void Chip_SetupXtalClocking(void)
{
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Set PLL0 Source to Crystal Oscillator */
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = ((15+1) * 2 * 12MHz) / (0+1) = 384MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 15, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
/* 384MHz / (3+1) = 96MHz */
Chip_Clock_SetCPUClockDiv(3);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
#endif
#if (defined(CHIP_LPC177X_8X) | defined(CHIP_LPC40XX))
/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(void)
{
/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* It is safe to switch the PLL Source to IRC */
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
/* Fout = FCCO / ((0+1) * 2) = 120MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(1);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
Chip_Clock_SetPCLKDiv(2);
}
/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* It is safe to switch the PLL Source to Crystal Oscillator */
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
/* Fout = FCCO / ((0+1) * 2) = 120MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(1);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
Chip_Clock_SetPCLKDiv(2);
}
#endif
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
/* Setup Chip clocking */
Chip_SetupIrcClocking();
}

116
hw/mcu/nxp/lpc_chip_175x_6x/src/timer_17xx_40xx.c Normal file
View File

@ -0,0 +1,116 @@
/*
* @brief LPC17xx/40xx 16/32-bit Timer/PWM driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Returns clock for the peripheral block */
STATIC CHIP_SYSCTL_CLOCK_T Chip_Timer_GetClockIndex(LPC_TIMER_T *pTMR)
{
CHIP_SYSCTL_CLOCK_T clkTMR;
if (pTMR == LPC_TIMER1) {
clkTMR = SYSCTL_CLOCK_TIMER1;
}
else if (pTMR == LPC_TIMER2) {
clkTMR = SYSCTL_CLOCK_TIMER2;
}
else if (pTMR == LPC_TIMER3) {
clkTMR = SYSCTL_CLOCK_TIMER3;
}
else {
clkTMR = SYSCTL_CLOCK_TIMER0;
}
return clkTMR;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize a timer */
void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
{
Chip_Clock_EnablePeriphClock(Chip_Timer_GetClockIndex(pTMR));
}
/* Shutdown a timer */
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
{
Chip_Clock_DisablePeriphClock(Chip_Timer_GetClockIndex(pTMR));
}
/* Resets the timer terminal and prescale counts to 0 */
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
{
uint32_t reg;
/* Disable timer, set terminal count to non-0 */
reg = pTMR->TCR;
pTMR->TCR = 0;
pTMR->TC = 1;
/* Reset timer counter */
pTMR->TCR = TIMER_RESET;
/* Wait for terminal count to clear */
while (pTMR->TC != 0) {}
/* Restore timer state */
pTMR->TCR = reg;
}
/* Sets external match control (MATn.matchnum) pin control */
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
{
uint32_t mask, reg;
/* Clear bits corresponding to selected match register */
mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2)));
reg = pTMR->EMR &= ~mask;
/* Set new configuration for selected match register */
pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) |
(((uint32_t) matchState) << (4 + (matchnum * 2)));
}

533
hw/mcu/nxp/lpc_chip_175x_6x/src/uart_17xx_40xx.c Normal file
View File

@ -0,0 +1,533 @@
/*
* @brief LPC11xx UART chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Autobaud status flag */
STATIC volatile FlagStatus ABsyncSts = RESET;
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Returns clock for the peripheral block */
STATIC CHIP_SYSCTL_CLOCK_T Chip_UART_GetClockIndex(LPC_USART_T *pUART)
{
CHIP_SYSCTL_CLOCK_T clkUART;
if (pUART == LPC_UART1) {
clkUART = SYSCTL_CLOCK_UART1;
}
else if (pUART == LPC_UART2) {
clkUART = SYSCTL_CLOCK_UART2;
}
else if (pUART == LPC_UART3) {
clkUART = SYSCTL_CLOCK_UART3;
}
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
else if (pUART == LPC_UART4) {
clkUART = SYSCTL_CLOCK_UART4;
}
#endif
else {
clkUART = SYSCTL_CLOCK_UART0;
}
return clkUART;
}
/* UART Autobaud command interrupt handler */
STATIC void Chip_UART_ABIntHandler(LPC_USART_T *pUART)
{
/* Handle End Of Autobaud interrupt */
if((Chip_UART_ReadIntIDReg(pUART) & UART_IIR_ABEO_INT) != 0) {
Chip_UART_SetAutoBaudReg(pUART, UART_ACR_ABEOINT_CLR);
Chip_UART_IntDisable(pUART, UART_IER_ABEOINT);
if (ABsyncSts == RESET) {
ABsyncSts = SET;
}
}
/* Handle Autobaud Timeout interrupt */
if((Chip_UART_ReadIntIDReg(pUART) & UART_IIR_ABTO_INT) != 0) {
Chip_UART_SetAutoBaudReg(pUART, UART_ACR_ABTOINT_CLR);
Chip_UART_IntDisable(pUART, UART_IER_ABTOINT);
}
}
#if defined(CHIP_LPC175X_6X)
/* Returns clock ID for the peripheral block */
STATIC CHIP_SYSCTL_PCLK_T Chip_UART_GetClkIndex(LPC_USART_T *pUART)
{
CHIP_SYSCTL_PCLK_T clkUART;
if (pUART == LPC_UART1) {
clkUART = SYSCTL_PCLK_UART1;
}
else if (pUART == LPC_UART2) {
clkUART = SYSCTL_PCLK_UART2;
}
else if (pUART == LPC_UART3) {
clkUART = SYSCTL_PCLK_UART3;
}
else {
clkUART = SYSCTL_PCLK_UART0;
}
return clkUART;
}
#endif
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the pUART peripheral */
void Chip_UART_Init(LPC_USART_T *pUART)
{
uint32_t tmp;
(void) tmp;
/* Enable UART clocking. UART base clock(s) must already be enabled */
Chip_Clock_EnablePeriphClock(Chip_UART_GetClockIndex(pUART));
/* Enable FIFOs by default, reset them */
Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS));
/* Disable Tx */
Chip_UART_TXDisable(pUART);
/* Disable interrupts */
pUART->IER = 0;
/* Set LCR to default state */
pUART->LCR = 0;
/* Set ACR to default state */
pUART->ACR = 0;
/* Set RS485 control to default state */
pUART->RS485CTRL = 0;
/* Set RS485 delay timer to default state */
pUART->RS485DLY = 0;
/* Set RS485 addr match to default state */
pUART->RS485ADRMATCH = 0;
/* Clear MCR */
if (pUART == LPC_UART1) {
/* Set Modem Control to default state */
pUART->MCR = 0;
/*Dummy Reading to Clear Status */
tmp = pUART->MSR;
}
/* Default 8N1, with DLAB disabled */
Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS));
/* Disable fractional divider */
pUART->FDR = 0x10;
}
/* De-initializes the pUART peripheral */
void Chip_UART_DeInit(LPC_USART_T *pUART)
{
/* Disable Tx */
Chip_UART_TXDisable(pUART);
/* Disable clock */
Chip_Clock_DisablePeriphClock(Chip_UART_GetClockIndex(pUART));
}
/* Enable transmission on UART TxD pin */
void Chip_UART_TXEnable(LPC_USART_T *pUART)
{
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
if(pUART == LPC_UART4) {
pUART->TER2 = UART_TER2_TXEN;
}
else {
#endif
pUART->TER1 = UART_TER1_TXEN;
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
}
#endif
}
/* Disable transmission on UART TxD pin */
void Chip_UART_TXDisable(LPC_USART_T *pUART)
{
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
if(pUART == LPC_UART4) {
pUART->TER2 = 0;
}
else {
#endif
pUART->TER1 = 0;
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
}
#endif
}
/* Transmit a byte array through the UART peripheral (non-blocking) */
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
{
int sent = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((sent < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) {
Chip_UART_SendByte(pUART, *p8);
p8++;
sent++;
}
return sent;
}
/* Check whether if UART is busy or not */
FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART)
{
if (pUART->LSR & UART_LSR_TEMT) {
return RESET;
}
else {
return SET;
}
}
/* Transmit a byte array through the UART peripheral (blocking) */
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes)
{
int pass, sent = 0;
uint8_t *p8 = (uint8_t *) data;
while (numBytes > 0) {
pass = Chip_UART_Send(pUART, p8, numBytes);
numBytes -= pass;
sent += pass;
p8 += pass;
}
return sent;
}
/* Read data through the UART peripheral (non-blocking) */
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
{
int readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((readBytes < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) {
*p8 = Chip_UART_ReadByte(pUART);
p8++;
readBytes++;
}
return readBytes;
}
/* Read data through the UART peripheral (blocking) */
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes)
{
int pass, readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
while (readBytes < numBytes) {
pass = Chip_UART_Read(pUART, p8, numBytes);
numBytes -= pass;
readBytes += pass;
p8 += pass;
}
return readBytes;
}
/* Determines and sets best dividers to get a target bit rate */
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t div, divh, divl, clkin;
/* Determine UART clock in rate without FDR */
#if defined(CHIP_LPC175X_6X)
clkin = Chip_Clock_GetPeripheralClockRate(Chip_UART_GetClkIndex(pUART));
#else
clkin = Chip_Clock_GetPeripheralClockRate();
#endif
div = clkin / (baudrate * 16);
/* High and low halves of the divider */
divh = div / 256;
divl = div - (divh * 256);
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, divl, divh);
Chip_UART_DisableDivisorAccess(pUART);
/* Fractional FDR already setup for 1 in UART init */
return clkin / div;
}
/* UART receive-only interrupt handler for ring buffers */
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
/* New data will be ignored if data not popped in time */
while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) {
uint8_t ch = Chip_UART_ReadByte(pUART);
RingBuffer_Insert(pRB, &ch);
}
}
/* UART transmit-only interrupt handler for ring buffers */
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
uint8_t ch;
/* Fill FIFO until full or until TX ring buffer is empty */
while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 &&
RingBuffer_Pop(pRB, &ch)) {
Chip_UART_SendByte(pUART, ch);
}
}
/* Populate a transmit ring buffer and start UART transmit */
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
{
uint32_t ret;
uint8_t *p8 = (uint8_t *) data;
/* Don't let UART transmit ring buffer change in the UART IRQ handler */
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
/* Move as much data as possible into transmit ring buffer */
ret = RingBuffer_InsertMult(pRB, p8, bytes);
Chip_UART_TXIntHandlerRB(pUART, pRB);
/* Add additional data to transmit ring buffer if possible */
ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
/* Enable UART transmit interrupt */
Chip_UART_IntEnable(pUART, UART_IER_THREINT);
return ret;
}
/* Copy data from a receive ring buffer */
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes)
{
(void) pUART;
return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes);
}
/* UART receive/transmit interrupt handler for ring buffers */
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if (pUART->IER & UART_IER_THREINT) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
/* Handle Autobaud interrupts */
Chip_UART_ABIntHandler(pUART);
}
/* Determines and sets best dividers to get a target baud rate */
uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t uClk;
uint32_t actualRate = 0, d, m, bestd, bestm, tmp;
uint32_t current_error, best_error;
uint64_t best_divisor, divisor;
uint32_t recalcbaud;
/* Get Clock rate */
#if defined(CHIP_LPC175X_6X)
uClk = Chip_Clock_GetPeripheralClockRate(Chip_UART_GetClkIndex(pUART));
#else
uClk = Chip_Clock_GetPeripheralClockRate();
#endif
/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
* The formula is :
* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
* It involves floating point calculations. That's the reason the formulae are adjusted with
* Multiply and divide method.*/
/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
best_error = 0xFFFFFFFF;/* Worst case */
bestd = 0;
bestm = 0;
best_divisor = 0;
for (m = 1; m <= 15; m++) {
for (d = 0; d < m; d++) {
/* The result here is a fixed point number. The integer portion is in the upper 32 bits.
* The fractional portion is in the lower 32 bits.
*/
divisor = ((uint64_t) uClk << 28) * m / (baudrate * (m + d));
/* The fractional portion is the error. */
current_error = divisor & 0xFFFFFFFF;
/* Snag the integer portion of the divisor. */
tmp = divisor >> 32;
/* If closer to the next divisor... */
if (current_error > ((uint32_t) 1 << 31)) {
/* Increment to the next divisor... */
tmp++;
/* Now the error is the distance to the next divisor... */
current_error = -current_error;
}
/* Can't use a divisor that's less than 1 or more than 65535. */
if ((tmp < 1) || (tmp > 65535)) {
/* Out of range */
continue;
}
/* Also, if fractional divider is enabled can't use a divisor that is less than 3. */
if ((d != 0) && (tmp < 3)) {
/* Out of range */
continue;
}
/* Do we have a new best? */
if (current_error < best_error) {
best_error = current_error;
best_divisor = tmp;
bestd = d;
bestm = m;
/* If error is 0, that's perfect. We're done. */
if (best_error == 0) {
break;
}
}
} /* for (d) */
/* If error is 0, that's perfect. We're done. */
if (best_error == 0) {
break;
}
} /* for (m) */
if (best_divisor == 0) {
/* can not find best match */
return 0;
}
recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
/* reuse best_error to evaluate baud error */
if (baudrate > recalcbaud) {
best_error = baudrate - recalcbaud;
}
else {
best_error = recalcbaud - baudrate;
}
best_error = (best_error * 100) / baudrate;
/* Update UART registers */
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, UART_LOAD_DLL(best_divisor), UART_LOAD_DLM(best_divisor));
Chip_UART_DisableDivisorAccess(pUART);
/* Set best fractional divider */
pUART->FDR = (UART_FDR_MULVAL(bestm) | UART_FDR_DIVADDVAL(bestd));
/* Return actual baud rate */
actualRate = recalcbaud;
return actualRate;
}
/* UART interrupt service routine */
FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART)
{
(void) pUART;
return ABsyncSts;
}
/* Start/Stop Auto Baudrate activity */
void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart, FunctionalState NewState)
{
uint32_t tmp = 0;
if (NewState == ENABLE) {
/* Clear DLL and DLM value */
pUART->LCR |= UART_LCR_DLAB_EN;
pUART->DLL = 0;
pUART->DLM = 0;
pUART->LCR &= ~UART_LCR_DLAB_EN;
/* FDR value must be reset to default value */
pUART->FDR = 0x10;
if (mode == UART_ACR_MODE1) {
tmp = UART_ACR_START | UART_ACR_MODE;
}
else {
tmp = UART_ACR_START;
}
if (autorestart == true) {
tmp |= UART_ACR_AUTO_RESTART;
}
pUART->ACR = tmp;
}
else {
pUART->ACR = 0;
}
}

72
hw/mcu/nxp/lpc_chip_175x_6x/src/wwdt_17xx_40xx.c Normal file
View File

@ -0,0 +1,72 @@
/*
* @brief LPC17xx/40xx WWDT chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the Watchdog timer */
void Chip_WWDT_Init(LPC_WWDT_T *pWWDT)
{
/* Disable watchdog */
pWWDT->MOD = 0;
pWWDT->TC = 0xFF;
#if defined(WATCHDOG_WINDOW_SUPPORT)
pWWDT->WARNINT = 0xFFFF;
pWWDT->WINDOW = 0xFFFFFF;
#endif
}
/* Clear WWDT interrupt status flags */
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
{
if (status & WWDT_WDMOD_WDTOF) {
pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK;
}
if (status & WWDT_WDMOD_WDINT) {
pWWDT->MOD |= WWDT_WDMOD_WDINT;
}
}