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Merge pull request #1077 from hathach/st-synopsy-compliance
St synopsy compliance
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Ha Thach
GitHub
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5f141a4c13
@ -96,6 +96,9 @@
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#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
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#include "synopsys_common.h"
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// for remote wakeup delay
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#define __NOP() __asm volatile ("nop")
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// These numbers are the same for the whole GD32VF103 family.
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#define OTG_FS_IRQn 86
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#define EP_MAX_FS 4
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@ -213,17 +216,18 @@ static void bus_reset(uint8_t rhport)
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tu_memclr(xfer_status, sizeof(xfer_status));
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_out_ep_closed = false;
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// clear device address
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dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
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// 1. NAK for all OUT endpoints
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for(uint8_t n = 0; n < EP_MAX; n++) {
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out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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}
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// clear device address
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dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
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// TODO should probably assign value when reset rather than OR
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dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
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dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
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dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
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// 2. Un-mask interrupt bits
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dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
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dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
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dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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@ -307,8 +311,6 @@ static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
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// Turnaround timeout depends on the MCU clock
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uint32_t turnaround;
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TU_LOG_INT(2, SystemCoreClock);
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if ( SystemCoreClock >= 32000000U )
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turnaround = 0x6U;
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else if ( SystemCoreClock >= 27500000U )
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@ -556,13 +558,34 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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}
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static void remote_wakeup_delay(void)
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{
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// try to delay for 1 ms
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uint32_t count = SystemCoreClock / 1000;
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while ( count-- )
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{
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__NOP();
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}
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}
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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// TODO must manually clear this bit after 1-15 ms
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// USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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// dev->DCTL |= USB_OTG_DCTL_RWUSIG;
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USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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// set remote wakeup
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dev->DCTL |= USB_OTG_DCTL_RWUSIG;
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// enable SOF to detect bus resume
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usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
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usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
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// Per specs: remote wakeup signal bit must be clear within 1-15ms
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remote_wakeup_delay();
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dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
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}
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void dcd_connect(uint8_t rhport)
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@ -618,8 +641,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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usb_otg->GRXFSIZ = sz;
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}
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out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
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(desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
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out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
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(desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
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(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
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(desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
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dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
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@ -661,7 +685,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
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(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
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(desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
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(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
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(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
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(desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos);
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dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
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@ -670,10 +694,32 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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return true;
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}
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// Close all non-control endpoints, cancel all pending transfers if any.
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void dcd_edpt_close_all (uint8_t rhport)
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{
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(void) rhport;
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// TODO implement dcd_edpt_close_all()
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// USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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// Disable non-control interrupt
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dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
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for(uint8_t n = 1; n < EP_MAX; n++)
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{
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// disable OUT endpoint
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out_ep[n].DOEPCTL = 0;
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xfer_status[n][TUSB_DIR_OUT].max_size = 0;
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// disable IN endpoint
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in_ep[n].DIEPCTL = 0;
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xfer_status[n][TUSB_DIR_IN].max_size = 0;
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}
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// reset allocated fifo IN
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_allocated_fifo_words_tx = 16;
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}
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bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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@ -835,22 +881,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// Clear stall and reset data toggle
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if(dir == TUSB_DIR_IN) {
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in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
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uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> USB_OTG_DIEPCTL_EPTYP_Pos;
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// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints.
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if(eptype == 2 || eptype == 3) {
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in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
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}
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in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
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} else {
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out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
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uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> USB_OTG_DOEPCTL_EPTYP_Pos;
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// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints.
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if(eptype == 2 || eptype == 3) {
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out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
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}
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out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
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}
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}
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@ -1087,7 +1124,7 @@ void dcd_int_handler(uint8_t rhport)
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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uint32_t int_status = usb_otg->GINTSTS;
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uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
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if(int_status & USB_OTG_GINTSTS_USBRST)
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{
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@ -1120,6 +1157,9 @@ void dcd_int_handler(uint8_t rhport)
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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// TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
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// if(int_status & USB_OTG_GINTSTS_DISCINT)
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if(int_status & USB_OTG_GINTSTS_OTGINT)
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{
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// OTG INT bit is read-only
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@ -1133,13 +1173,15 @@ void dcd_int_handler(uint8_t rhport)
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usb_otg->GOTGINT = otg_int;
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}
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#if USE_SOF
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if(int_status & USB_OTG_GINTSTS_SOF)
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{
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usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
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// Disable SOF interrupt since currently only used for remote wakeup detection
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usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
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dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
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}
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#endif
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// RxFIFO non-empty interrupt handling.
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if(int_status & USB_OTG_GINTSTS_RXFLVL)
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@ -1153,8 +1195,7 @@ void dcd_int_handler(uint8_t rhport)
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do
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{
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handle_rxflvl_ints(rhport, out_ep);
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int_status = usb_otg->GINTSTS;
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} while(int_status & USB_OTG_GINTSTS_RXFLVL);
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} while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
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// Manage RX FIFO size
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if (_out_ep_closed)
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