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Change hcd_edpt_xfer to send at the next SOF
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cc06a3585e
commit
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@ -268,7 +268,7 @@ static void suspend_transfer(int pipenum, buffer_descriptor_t *bd)
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{
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pipe_state_t *pipe = &_hcd.pipe[pipenum];
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pipe->buffer = bd->addr;
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pipe->data = bd->data;
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pipe->data = bd->data ^ 1;
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if (TUSB_XFER_INTERRUPT == pipe->xfer) {
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_hcd.pending |= TU_BIT(pipenum);
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KHCI->INTEN |= USB_ISTAT_SOFTOK_MASK;
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@ -309,7 +309,6 @@ static void process_tokdne(uint8_t rhport)
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result = XFER_RESULT_SUCCESS;
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break;
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case TOK_PID_NAK:
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case TOK_PID_ERR:
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suspend_transfer(pipenum, bd);
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next_pipenum = select_next_pipenum(pipenum);
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if (0 <= next_pipenum)
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@ -318,6 +317,7 @@ static void process_tokdne(uint8_t rhport)
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case TOK_PID_STALL:
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result = XFER_RESULT_STALLED;
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break;
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case TOK_PID_ERR: /* mismatch toggle bit */
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case TOK_PID_BUSTO:
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result = XFER_RESULT_FAILED;
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break;
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@ -535,6 +535,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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return true;
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}
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/* The address of buffer must be aligned to 4 byte boundary. And it must be at least 4 bytes long.
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* DMA writes data in 4 byte unit */
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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(void)rhport;
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@ -545,15 +547,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(pipenum)));
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unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
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unsigned const wip = _hcd.in_progress;
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NVIC_DisableIRQ(USB0_IRQn);
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pipe_state_t *pipe = &_hcd.pipe[pipenum];
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pipe->buffer = buffer;
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pipe->length = buflen;
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pipe->remaining = buflen;
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_hcd.in_progress = wip | TU_BIT(pipenum);
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if (0 == (wip & ~_hcd.pending))
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resume_transfer(pipenum);
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_hcd.in_progress |= TU_BIT(pipenum);
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_hcd.pending |= TU_BIT(pipenum); /* Send at the next Frame */
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KHCI->INTEN |= USB_ISTAT_SOFTOK_MASK;
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if (ie) NVIC_EnableIRQ(USB0_IRQn);
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return true;
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}
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