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correct memory placement for lpc13. CDC work well

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hathach 2018-12-03 16:23:38 +07:00
parent f9ae8fa5d2
commit 786b04e19d
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GPG Key ID: 2FA891220FBFD581
3 changed files with 6 additions and 1 deletions
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1
examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
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@ -3,4 +3,5 @@
<MemorySegment name="FLASH" start="0x00000000" size="0x00010000" access="ReadOnly" />
<MemorySegment name="RAM" start="0x10000000" size="0x00002000" access="Read/Write" />
<MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" />
<MemorySegment name="RAM3" start="0x20004000" size="0x00000800" access="Read/Write" />
</root>

4
examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml
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@ -34,4 +34,8 @@
<ProgramSection alignment="4" load="No" name=".data2_run" />
<ProgramSection alignment="4" load="No" name=".bss2" />
</MemorySegment>
<MemorySegment name="$(RAM3_NAME:RAM3)">
<ProgramSection alignment="4" load="No" name=".data3_run" />
<ProgramSection alignment="4" load="No" name=".bss3" />
</MemorySegment>
</Root>

2
examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
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@ -17,7 +17,7 @@
arm_target_debug_interface_type="ADIv5"
arm_target_device_name="LPC1347"
arm_target_interface_type="SWD"
c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX"
c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss3&quot;)));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))"
c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/lpc_chip_13xx/inc"
debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml"
debug_target_connection="J-Link"