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Merge pull request #2865 from HiFiPhile/rt1170

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RT1170 enhancements
This commit is contained in:
Ha Thach 2024-12-18 16:07:21 +07:00 committed by GitHub
commit 7c1afa837a
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GPG Key ID: B5690EEEBB952194
61 changed files with 1370 additions and 1047 deletions
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12
.gitignore vendored
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@ -1,16 +1,20 @@
html
latex
*.a
*.d
*.o
*.P
*.map
*.axf
*.bin
*.elf
*.env
*.ind
*.log
*.map
*.obj
*.jlink
*.emSession
*.elf
*.ind
.env
*.ninja*
.settings/
.vscode/
.gdb_history

2
examples/device/audio_test_multi_rate/src/main.c
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@ -85,7 +85,7 @@ audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1];
// Audio test data
CFG_TUSB_MEM_ALIGN uint8_t test_buffer_audio[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
CFG_TUD_MEM_ALIGN uint8_t test_buffer_audio[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
uint16_t startVal = 0;
void led_blinking_task(void);

1
hw/bsp/broadcom_32bit/family.cmake
View File

@ -106,5 +106,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/broadcom_64bit/family.cmake
View File

@ -113,5 +113,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/f1c100s/family.cmake
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@ -110,5 +110,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

15
hw/bsp/family_support.cmake
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@ -300,10 +300,17 @@ endfunction()
# Add bin/hex output
function(family_add_bin_hex TARGET)
add_custom_command(TARGET ${TARGET} POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
VERBATIM)
if (CMAKE_C_COMPILER_ID STREQUAL "IAR")
add_custom_command(TARGET ${TARGET} POST_BUILD
COMMAND ${CMAKE_OBJCOPY} --bin $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
COMMAND ${CMAKE_OBJCOPY} --ihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
VERBATIM)
else()
add_custom_command(TARGET ${TARGET} POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
VERBATIM)
endif()
endfunction()
# Add uf2 output

1
hw/bsp/gd32vf103/family.cmake
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@ -117,5 +117,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

17
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake
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@ -1,8 +1,17 @@
set(MCU_VARIANT MIMXRT1176)
set(MCU_CORE _cm7)
set(JLINK_DEVICE MIMXRT1176xxxA_M7)
set(PYOCD_TARGET mimxrt1170_cm7)
if (M4 STREQUAL "1")
set(MCU_CORE _cm4)
set(JLINK_CORE _M4)
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld)
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
else ()
set(MCU_CORE _cm7)
set(JLINK_CORE _M7)
endif()
set(JLINK_DEVICE MIMXRT1176xxxA${JLINK_CORE})
set(PYOCD_TARGET mimxrt1170${MCU_CORE})
set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK)
function(update_board TARGET)
@ -10,7 +19,7 @@ function(update_board TARGET)
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbmimxrt1170_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1176DVMAA_cm7
CPU_MIMXRT1176DVMAA${MCU_CORE}
BOARD_TUD_RHPORT=0
BOARD_TUH_RHPORT=1
)

18
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk
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@ -1,12 +1,22 @@
CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7
MCU_VARIANT = MIMXRT1176
MCU_CORE = _cm7
ifeq ($(M4), 1)
MCU_CORE = _cm4
JLINK_CORE = _M4
CPU_CORE = cortex-m4
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_ram.ld
else
MCU_CORE = _cm7
JLINK_CORE = _M7
endif
CFLAGS += -DCPU_MIMXRT1176DVMAA$(MCU_CORE)
# For flash-jlink target
JLINK_DEVICE = MIMXRT1176xxxA_M7
JLINK_DEVICE = MIMXRT1176xxxA$(JLINK_CORE)
# For flash-pyocd target
PYOCD_TARGET = mimxrt1170_cm7
PYOCD_TARGET = mimxrt1170$(MCU_CORE)
BOARD_TUD_RHPORT = 0
BOARD_TUH_RHPORT = 1

14
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
View File

@ -11,11 +11,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v12.0
product: Clocks v14.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 14.0.1
processor_version: 16.3.0
board: MIMXRT1170-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@ -335,7 +335,6 @@ void BOARD_BootClockRUN(void)
/* Init OSC RC 400M */
CLOCK_OSC_EnableOscRc400M();
CLOCK_OSC_GateOscRc400M(false);
/* Init OSC RC 48M */
CLOCK_OSC_EnableOsc48M(true);
@ -349,22 +348,29 @@ void BOARD_BootClockRUN(void)
{
}
/* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
/* Switch core M7 clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
#endif
/* Switch core M7 systick clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
/* Switch core M4 clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
/* Switch the Bus_Lpsr clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);

2
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h
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@ -48,7 +48,7 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IEE__IEE_RT1170, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */

15
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
View File

@ -6,11 +6,11 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v14.0
product: Pins v16.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 14.0.1
processor_version: 16.3.0
board: MIMXRT1170-EVKB
external_user_signals: {}
pin_labels:
@ -90,7 +90,7 @@ void BOARD_InitPins(void) {
IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull / Keep Select Field: Pull Disable
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
@ -99,7 +99,7 @@ void BOARD_InitPins(void) {
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull / Keep Select Field: Pull Disable
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
@ -108,22 +108,19 @@ void BOARD_InitPins(void) {
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull / Keep Select Field: Pull Disable
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */
0x0EU); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high driver
Pull / Keep Select Field: Pull Enable
0x0EU); /* Pull / Keep Select Field: Pull Enable
Pull Up / Down Config. Field: Weak pull up
Open Drain SNVS Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

2
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
View File

@ -46,7 +46,7 @@ void BOARD_InitBootPins(void);
#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
/* WAKEUP (coord T8), USER_BUTTON */
/* WAKEUP (coord T8), USER_BUTTON/SW7 */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO13 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */

13
hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_14 http://mcuxpresso.nxp.com/XSD/mex_configuration_14.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="14" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_14" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_16 http://mcuxpresso.nxp.com/XSD/mex_configuration_16.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="16" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_16" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1176xxxxx</processor>
<package>MIMXRT1176DVMAA</package>
@ -19,18 +19,17 @@
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="14.0" enabled="true" update_project_code="true">
<pins name="Pins" version="16.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>14.0.1</processor_version>
<processor_version>16.3.0</processor_version>
<pin_labels>
<pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED;USER_LED"/>
</pin_labels>
<external_user_signals>
<routingDetailsColumns/>
<properties/>
</external_user_signals>
<power_domains/>
@ -44,7 +43,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@ -104,13 +103,13 @@
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="12.0" enabled="true" update_project_code="true">
<clocks name="Clocks" version="14.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>14.0.1</processor_version>
<processor_version>16.3.0</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">

447
hw/bsp/imxrt/family.c
View File

@ -31,23 +31,36 @@
// Suppress warning caused by mcu driver
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
#include "fsl_clock.h"
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_iomuxc.h"
#include "fsl_clock.h"
#include "fsl_lpuart.h"
#include "fsl_ocotp.h"
#ifdef __GNUC__
#pragma GCC diagnostic pop
#pragma GCC diagnostic pop
#endif
/* --- Note about USB buffer RAM ---
For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default)
Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU():
- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
- (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N
For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used:
- __NCACHE_REGION_SIZE is defined by the linker script by default
- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
*/
static void BOARD_ConfigMPU(void);
// needed by fsl_flexspi_nor_boot
TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 };
TU_ATTR_USED const uint8_t dcd_data[] = {0x00};
//--------------------------------------------------------------------+
//
@ -59,20 +72,20 @@ TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 };
#endif
static void init_usb_phy(uint8_t usb_id) {
USBPHY_Type* usb_phy;
USBPHY_Type *usb_phy;
if (usb_id == 0) {
usb_phy = USBPHY1;
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
}
#ifdef USBPHY2
#ifdef USBPHY2
else if (usb_id == 1) {
usb_phy = USBPHY2;
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
}
#endif
#endif
else {
return;
}
@ -91,13 +104,8 @@ static void init_usb_phy(uint8_t usb_id) {
usb_phy->TX = phytx;
}
void board_init(void)
{
// make sure the dcache is on.
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache();
#endif
void board_init(void) {
BOARD_ConfigMPU();
BOARD_InitPins();
BOARD_BootClockRUN();
SystemCoreClockUpdate();
@ -113,9 +121,9 @@ void board_init(void)
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#ifdef USBPHY2
#ifdef USBPHY2
NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
#endif
#endif
board_led_write(true);
@ -127,16 +135,16 @@ void board_init(void)
uart_config.enableTx = true;
uart_config.enableRx = true;
if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT) ) {
if (kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT)) {
// failed to init uart, probably baudrate is not supported
// TU_BREAKPOINT();
}
//------------- USB -------------//
// Note: RT105x RT106x and later have dual USB controllers.
init_usb_phy(0); // USB0
init_usb_phy(0);// USB0
#ifdef USBPHY2
init_usb_phy(1); // USB1
init_usb_phy(1);// USB1
#endif
}
@ -166,18 +174,18 @@ uint32_t board_button_read(void) {
size_t board_get_unique_id(uint8_t id[], size_t max_len) {
(void) max_len;
#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
#else
#else
OCOTP_Init(OCOTP, 0u);
#endif
#endif
// Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
// into 8 bit wide destination, avoiding punning.
for (int i = 0; i < 4; ++i) {
uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1);
for (int j = 0; j < 4; j++) {
id[i*4+j] = wr & 0xff;
id[i * 4 + j] = wr & 0xff;
wr >>= 8;
}
}
@ -186,7 +194,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
return 16;
}
int board_uart_read(uint8_t* buf, int len) {
int board_uart_read(uint8_t *buf, int len) {
int count = 0;
while (count < len) {
@ -209,8 +217,8 @@ int board_uart_read(uint8_t* buf, int len) {
return count;
}
int board_uart_write(void const * buf, int len) {
LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len);
int board_uart_write(void const *buf, int len) {
LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len);
return len;
}
@ -237,9 +245,390 @@ TU_ATTR_UNUSED void _start(void) {
}
#ifdef __clang__
void _exit (int __status) {
void _exit(int __status) {
while (1) {}
}
#endif
#endif
//--------------------------------------------------------------------
// MPU configuration
//--------------------------------------------------------------------
#if __CORTEX_M == 7
static void BOARD_ConfigMPU(void) {
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
#if defined(__USE_SHMEM)
extern uint32_t __base_rpmsg_sh_mem;
extern uint32_t __top_rpmsg_sh_mem;
uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem);
uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart;
#else
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
#endif
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
uint32_t size = (uint32_t) __NCACHE_REGION_SIZE;
#endif
volatile uint32_t i = 0;
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
SCB_DisableICache();
}
#endif
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
SCB_DisableDCache();
}
#endif
/* Disable MPU */
ARM_MPU_Disable();
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outer cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/
/*
* Add default region to deny access to whole address space to workaround speculative prefetch.
* Refer to Arm errata 1013783-B for more details.
*
*/
/* Region 0 setting: Instruction access disabled, No data access permission. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
/* Region 6 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 7 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
#else
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
#endif
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
#endif
#ifdef USE_SDRAM
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
/* Region 9 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
#else
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
#endif
#endif
while ((size >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}
/* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
/* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
/* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
/* Enable I cache and D cache */
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
SCB_EnableDCache();
#endif
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
SCB_EnableICache();
#endif
}
#elif __CORTEX_M == 4
void BOARD_ConfigMPU(void) {
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE;
#endif
#if defined(__USE_SHMEM)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
/* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base;
uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
#elif defined(__MCUXPRESSO)
extern uint32_t __base_rpmsg_sh_mem;
extern uint32_t __top_rpmsg_sh_mem;
uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem);
uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __RPMSG_SH_MEM_START[];
extern uint32_t __RPMSG_SH_MEM_SIZE[];
uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START;
uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE;
#endif
#endif
uint32_t i = 0;
/* Only config non-cacheable region on system bus */
assert(nonCacheStart >= 0x20000000);
/* Disable code bus cache */
if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) {
/* Enable the processor code bus to push all modified lines. */
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
/* Now disable the cache. */
LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
}
/* Disable system bus cache */
if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) {
/* Enable the processor system bus to push all modified lines. */
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
/* Now disable the cache. */
LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
}
/* Disable MPU */
ARM_MPU_Disable();
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
/* Region 0 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 1 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
/* Region 2 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
while ((nonCacheSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % nonCacheSize));
assert(nonCacheSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 3 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#if defined(__USE_SHMEM)
i = 0;
while ((rpmsgShmemSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(rpmsgShmemStart % rpmsgShmemSize));
assert(rpmsgShmemSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 4 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#endif
#else
while ((nonCacheSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % nonCacheSize));
assert(nonCacheSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 0 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#if defined(__USE_SHMEM)
i = 0;
while ((rpmsgShmemSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(rpmsgShmemStart % rpmsgShmemSize));
assert(rpmsgShmemSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 1 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#endif
#endif
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
/* Enables the processor system bus to invalidate all lines in both ways.
and Initiate the processor system bus cache command. */
LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the cache command completes */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
/* Now enable the system bus cache. */
LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
/* Enables the processor code bus to invalidate all lines in both ways.
and Initiate the processor code bus code cache command. */
LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
/* Now enable the code bus cache. */
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
}
#endif

25
hw/bsp/imxrt/family.cmake
View File

@ -8,7 +8,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE})
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
endif ()
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
@ -25,13 +27,13 @@ function(add_board_target BOARD_TARGET)
# LD_FILE and STARTUP_FILE can be defined in board.cmake
if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld)
#set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf)
endif ()
set(LD_FILE_Clang ${LD_FILE_GNU})
if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S)
#set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S)
set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s)
endif ()
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
@ -58,13 +60,21 @@ function(add_board_target BOARD_TARGET)
endif()
endforeach()
target_compile_definitions(${BOARD_TARGET} PUBLIC
__ARMVFP__=0
__ARMFPV5__=0
XIP_EXTERNAL_FLASH=1
XIP_BOOT_HEADER_ENABLE=1
__STARTUP_CLEAR_BSS
CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\"NonCacheable\"\)\)\)
)
if (NOT M4 STREQUAL "1")
target_compile_definitions(${BOARD_TARGET} PUBLIC
__ARMVFP__=0
__ARMFPV5__=0
XIP_EXTERNAL_FLASH=1
XIP_BOOT_HEADER_ENABLE=1
)
endif ()
target_include_directories(${BOARD_TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
@ -140,6 +150,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})

11
hw/bsp/imxrt/family.mk
View File

@ -8,13 +8,18 @@ CPU_CORE ?= cortex-m7
MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE}
MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
CFLAGS += \
-D__STARTUP_CLEAR_BSS \
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \
-DCFG_TUSB_MEM_SECTION='__attribute__((section("NonCacheable")))' \
ifneq ($(M4), 1)
CFLAGS += \
-D__ARMVFP__=0 \
-D__ARMFPV5__=0 \
-D__STARTUP_CLEAR_BSS \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX
-DXIP_BOOT_HEADER_ENABLE=1
endif
ifdef BOARD_TUD_RHPORT
CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT)

1
hw/bsp/kinetis_k/family.cmake
View File

@ -108,6 +108,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
if (DEFINED TEENSY_MCU)

2
hw/bsp/kinetis_k32l2/family.cmake
View File

@ -104,9 +104,9 @@ function(family_configure_example TARGET RTOS)
# Flashing
family_flash_jlink(${TARGET})
family_add_bin_hex(${TARGET})
if (DEFINED TEENSY_MCU)
family_add_bin_hex(${TARGET})
family_flash_teensy(${TARGET})
endif ()
endfunction()

1
hw/bsp/kinetis_kl/family.cmake
View File

@ -107,5 +107,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/lpc11/family.cmake
View File

@ -100,6 +100,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
endfunction()

1
hw/bsp/lpc13/family.cmake
View File

@ -97,6 +97,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
endfunction()

1
hw/bsp/lpc15/family.cmake
View File

@ -99,6 +99,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
endfunction()

1
hw/bsp/lpc17/family.cmake
View File

@ -98,6 +98,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
endfunction()

1
hw/bsp/lpc18/family.cmake
View File

@ -96,5 +96,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/lpc40/family.cmake
View File

@ -99,6 +99,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
endfunction()

1
hw/bsp/lpc43/family.cmake
View File

@ -104,5 +104,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/lpc51/family.cmake
View File

@ -116,6 +116,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})

1
hw/bsp/lpc54/family.cmake
View File

@ -149,6 +149,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})

1
hw/bsp/lpc55/family.cmake
View File

@ -150,6 +150,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})

1
hw/bsp/max32650/family.cmake
View File

@ -147,6 +147,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
family_flash_openocd_adi(${TARGET})

1
hw/bsp/max32666/family.cmake
View File

@ -142,6 +142,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
family_flash_openocd_adi(${TARGET})
endfunction()

1
hw/bsp/max32690/family.cmake
View File

@ -147,6 +147,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
family_flash_openocd_adi(${TARGET})
endfunction()

1
hw/bsp/max78002/family.cmake
View File

@ -148,6 +148,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
family_flash_msdk(${TARGET})
endfunction()

1
hw/bsp/mcx/family.cmake
View File

@ -125,6 +125,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})

1
hw/bsp/mm32/family.cmake
View File

@ -97,5 +97,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/nrf/family.cmake
View File

@ -141,6 +141,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
# family_flash_adafruit_nrfutil(${TARGET})
endfunction()

2
hw/bsp/ra/family.cmake
View File

@ -160,9 +160,9 @@ function(family_configure_example TARGET RTOS)
# Flashing
family_flash_jlink(${TARGET})
family_add_bin_hex(${TARGET})
if (DEFINED DFU_UTIL_VID_PID)
family_add_bin_hex(${TARGET})
family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID})
endif ()
endfunction()

1
hw/bsp/stm32c0/family.cmake
View File

@ -113,6 +113,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
family_flash_stlink(${TARGET})
#family_flash_openocd(${TARGET})

1
hw/bsp/stm32f0/family.cmake
View File

@ -110,6 +110,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32f1/family.cmake
View File

@ -109,6 +109,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32f2/family.cmake
View File

@ -111,6 +111,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32f3/family.cmake
View File

@ -107,6 +107,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32f4/family.cmake
View File

@ -137,6 +137,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32f7/family.cmake
View File

@ -139,6 +139,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32g0/family.cmake
View File

@ -112,6 +112,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
family_flash_stlink(${TARGET})
#family_flash_openocd(${TARGET})

1
hw/bsp/stm32g4/family.cmake
View File

@ -108,6 +108,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32h5/family.cmake
View File

@ -112,6 +112,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32h7/family.cmake
View File

@ -144,6 +144,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32l0/family.cmake
View File

@ -111,6 +111,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32l4/family.cmake
View File

@ -114,6 +114,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32u5/family.cmake
View File

@ -115,6 +115,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/stm32wb/family.cmake
View File

@ -114,6 +114,7 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_stlink(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1
hw/bsp/xmc4000/family.cmake
View File

@ -95,5 +95,6 @@ function(family_configure_example TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
endfunction()

1701
src/class/audio/audio_device.c
View File

File diff suppressed because it is too large Load Diff

3
src/class/audio/audio_device.h
View File

@ -203,6 +203,9 @@
#define CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP 0 // Feedback - 0 or 1
#endif
// Audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74)
#define CFG_TUD_AUDIO_INTERRUPT_EP_SZ 6
// Use software encoding/decoding
// The software coding feature of the driver is not mandatory. It is useful if, for instance, you have two I2S streams which need to be interleaved

8
src/common/tusb_mcu.h
View File

@ -108,12 +108,20 @@
#define TUP_DCD_ENDPOINT_MAX 16
#elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
#include "fsl_device_registers.h"
#define TUP_USBIP_CHIPIDEA_HS
#define TUP_USBIP_EHCI
#define TUP_DCD_ENDPOINT_MAX 8
#define TUP_RHPORT_HIGHSPEED 1
#if __CORTEX_M == 7
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
#endif
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
#define TUP_USBIP_CHIPIDEA_FS
#define TUP_USBIP_CHIPIDEA_FS_KINETIS

25
src/portable/chipidea/ci_hs/ci_hs_imxrt.h
View File

@ -56,14 +56,23 @@ static const ci_hs_controller_t _ci_controller[] =
#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
//------------- DCD -------------//
#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
//------------- HCD -------------//
#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
//------------- DCache -------------//
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
#if __CORTEX_M == 7
TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) {
size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE;
}
return size;
}
TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
return !(0x20000000 <= addr && addr < 0x20100000);
}
@ -72,6 +81,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, ui
const uintptr_t addr32 = (uintptr_t) addr;
if (imxrt_is_cache_mem(addr32)) {
TU_ASSERT(tu_is_aligned32(addr32));
data_size = round_up_to_cache_line_size(data_size);
SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
}
return true;
@ -84,6 +94,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* add
// *very* careful when we do it. If we're not aligned, then we risk resetting
// values back to their RAM state.
TU_ASSERT(tu_is_aligned32(addr32));
data_size = round_up_to_cache_line_size(data_size);
SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
}
return true;
@ -93,9 +104,15 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void cons
const uintptr_t addr32 = (uintptr_t) addr;
if (imxrt_is_cache_mem(addr32)) {
TU_ASSERT(tu_is_aligned32(addr32));
data_size = round_up_to_cache_line_size(data_size);
SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
}
return true;
}
#elif __CORTEX_M == 4
#error "Secondary M4 core's cache controller is not supported yet."
#endif
#endif
#endif

29
src/portable/chipidea/ci_hs/dcd_ci_hs.c
View File

@ -34,17 +34,19 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
#include "ci_hs_imxrt.h"
bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean(addr, data_size);
}
#if CFG_TUD_MEM_DCACHE_ENABLE
bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean(addr, data_size);
}
bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_invalidate(addr, data_size);
}
bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_invalidate(addr, data_size);
}
bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean_invalidate(addr, data_size);
}
bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean_invalidate(addr, data_size);
}
#endif
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h"
@ -311,9 +313,7 @@ void dcd_sof_enable(uint8_t rhport, bool en)
static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
{
// Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
// address to 32-byte boundaries. Buffer must be word aligned
dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes);
tu_memclr(p_qtd, sizeof(dcd_qtd_t));
@ -479,7 +479,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
return true;
}
#if !CFG_TUD_MEM_DCACHE_ENABLE
// fifo has to be aligned to 4k boundary
// It's incompatible with dcache enabled transfer, since neither address nor size is aligned to cache line
bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
{
uint8_t const epnum = tu_edpt_number(ep_addr);
@ -525,8 +527,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
page++;
}
}
dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
}
else
{
@ -541,6 +541,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
return true;
}
#endif
//--------------------------------------------------------------------+
// ISR

2
src/portable/chipidea/ci_hs/hcd_ci_hs.c
View File

@ -42,6 +42,7 @@
#include "ci_hs_imxrt.h"
#if CFG_TUH_MEM_DCACHE_ENABLE
bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean(addr, data_size);
}
@ -53,6 +54,7 @@ bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean_invalidate(addr, data_size);
}
#endif
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)

13
tools/build.py
View File

@ -110,12 +110,13 @@ def cmake_board(board, toolchain, build_flags_on):
f'-DTOOLCHAIN={toolchain} {build_flags}')
if rcmd.returncode == 0:
cmd = f"cmake --build {build_dir}"
# Due to IAR capability, limit parallel build to 4 (medium+) or 6 (large) docker
if toolchain == 'iar' and os.getenv('CIRCLECI'):
if 'large' in os.getenv('CIRCLE_JOB'):
cmd += ' --parallel 6'
else:
cmd += ' --parallel 4'
# circleci docker return $nproc as 36 core, limit parallel according to resource class. Required for IAR, also prevent crashed/killed by docker
if os.getenv('CIRCLECI'):
resource_class = { 'small': 1, 'medium': 2, 'medium+': 3, 'large': 4 }
for rc in resource_class:
if rc in os.getenv('CIRCLE_JOB'):
cmd += f' --parallel {resource_class[rc]}'
break
rcmd = run_cmd(cmd)
ret[0 if rcmd.returncode == 0 else 1] += 1