mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-31 05:52:55 +08:00
more hcd clean up
This commit is contained in:
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c696812cad
commit
80398cb4cb
@ -334,10 +334,10 @@ bool tusb_dcd_edpt_busy(uint8_t port, uint8_t edpt_addr)
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}
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// add only, controller virtually cannot know
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static tusb_error_t pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
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static bool pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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uint8_t qtd_idx = qtd_find_free(port);
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ASSERT(qtd_idx != 0, TUSB_ERROR_DCD_NOT_ENOUGH_QTD);
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TU_ASSERT(qtd_idx != 0);
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dcd_data_t* p_dcd = dcd_data_ptr[port];
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dcd_qhd_t * p_qhd = &p_dcd->qhd[ed_idx];
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@ -349,7 +349,7 @@ static tusb_error_t pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, u
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{
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if ( p_qhd->list_qtd_idx[free_slot] == 0 ) break; // found free slot
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}
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ASSERT(free_slot < DCD_QTD_PER_QHD_MAX, TUSB_ERROR_DCD_NOT_ENOUGH_QTD);
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TU_ASSERT(free_slot < DCD_QTD_PER_QHD_MAX);
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p_qhd->list_qtd_idx[free_slot] = qtd_idx; // add new qtd to qhd's array list
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@ -359,20 +359,20 @@ static tusb_error_t pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, u
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if ( free_slot > 0 ) p_dcd->qtd[ p_qhd->list_qtd_idx[free_slot-1] ].next = (uint32_t) p_qtd;
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return TUSB_ERROR_NONE;
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return true;
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}
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tusb_error_t tusb_dcd_edpt_queue_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes)
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bool tusb_dcd_edpt_queue_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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uint8_t ep_idx = edpt_addr2phy(edpt_addr);
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return pipe_add_xfer(port, ep_idx, buffer, total_bytes, false);
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}
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tusb_error_t tusb_dcd_edpt_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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bool tusb_dcd_edpt_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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uint8_t ep_idx = edpt_addr2phy(edpt_addr);
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ASSERT_STATUS ( pipe_add_xfer(port, ep_idx, buffer, total_bytes, int_on_complete) );
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VERIFY ( pipe_add_xfer(port, ep_idx, buffer, total_bytes, int_on_complete) );
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dcd_qhd_t* p_qhd = &dcd_data_ptr[port]->qhd[ ep_idx ];
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dcd_qtd_t* p_qtd = &dcd_data_ptr[port]->qtd[ p_qhd->list_qtd_idx[0] ];
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@ -381,7 +381,7 @@ tusb_error_t tusb_dcd_edpt_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buff
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LPC_USB[port]->ENDPTPRIME = BIT_( edpt_phy2pos(ep_idx) ) ;
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return TUSB_ERROR_NONE;
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return true;
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}
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//------------- Device Controller Driver's Interrupt Handler -------------//
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@ -195,7 +195,7 @@ tusb_error_t cdcd_open(uint8_t port, tusb_descriptor_interface_t const * p_inter
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p_cdc->interface_number = p_interface_desc->bInterfaceNumber;
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// Prepare for incoming data
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tusb_dcd_edpt_xfer(port, p_cdc->edpt_addr[CDC_PIPE_DATA_OUT], _tmp_rx_buf, sizeof(_tmp_rx_buf), true);
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_cdc->edpt_addr[CDC_PIPE_DATA_OUT], _tmp_rx_buf, sizeof(_tmp_rx_buf), true), TUSB_ERROR_DCD_EDPT_XFER);
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return TUSB_ERROR_NONE;
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@ -269,7 +269,7 @@ tusb_error_t cdcd_xfer_cb(uint8_t port, uint8_t edpt_addr, tusb_event_t event, u
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fifo_write_n(&_rx_ff, _tmp_rx_buf, xferred_bytes);
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// preparing for next
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tusb_dcd_edpt_xfer(port, p_cdc->edpt_addr[CDC_PIPE_DATA_OUT], _tmp_rx_buf, sizeof(_tmp_rx_buf), true);
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TU_ASSERT(tusb_dcd_edpt_xfer(port, p_cdc->edpt_addr[CDC_PIPE_DATA_OUT], _tmp_rx_buf, sizeof(_tmp_rx_buf), true), TUSB_ERROR_DCD_EDPT_XFER);
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// fire callback
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tud_cdc_rx_cb(port);
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@ -288,7 +288,7 @@ void cdcd_sof(uint8_t port)
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{
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uint16_t count = fifo_read_n(&_tx_ff, _tmp_tx_buf, sizeof(_tmp_tx_buf));
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tusb_dcd_edpt_xfer(port, edpt, _tmp_tx_buf, count, false);
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TU_ASSERT( tusb_dcd_edpt_xfer(port, edpt, _tmp_tx_buf, count, false), TUSB_ERROR_DCD_EDPT_XFER);
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}
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}
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@ -114,11 +114,11 @@ bool tud_hid_keyboard_busy(uint8_t port)
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tusb_error_t tud_hid_keyboard_send(uint8_t port, hid_keyboard_report_t const *p_report)
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{
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ASSERT(tud_mounted(), TUSB_ERROR_USBD_DEVICE_NOT_CONFIGURED);
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VERIFY(tud_mounted(), TUSB_ERROR_USBD_DEVICE_NOT_CONFIGURED);
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hidd_interface_t * p_kbd = &keyboardd_data; // TODO &keyboardd_data[port];
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ASSERT_STATUS( tusb_dcd_edpt_xfer(port, p_kbd->edpt_addr, (void*) p_report, sizeof(hid_keyboard_report_t), true) ) ;
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_kbd->edpt_addr, (void*) p_report, sizeof(hid_keyboard_report_t), true), TUSB_ERROR_DCD_EDPT_XFER ) ;
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return TUSB_ERROR_NONE;
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}
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@ -137,11 +137,11 @@ bool tud_hid_mouse_is_busy(uint8_t port)
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tusb_error_t tud_hid_mouse_send(uint8_t port, hid_mouse_report_t const *p_report)
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{
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ASSERT(tud_mounted(), TUSB_ERROR_USBD_DEVICE_NOT_CONFIGURED);
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VERIFY(tud_mounted(), TUSB_ERROR_USBD_DEVICE_NOT_CONFIGURED);
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hidd_interface_t * p_mouse = &moused_data; // TODO &keyboardd_data[port];
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ASSERT_STATUS( tusb_dcd_edpt_xfer(port, p_mouse->edpt_addr, (void*) p_report, sizeof(hid_mouse_report_t), true) ) ;
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_mouse->edpt_addr, (void*) p_report, sizeof(hid_mouse_report_t), true), TUSB_ERROR_DCD_EDPT_XFER ) ;
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return TUSB_ERROR_NONE;
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}
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@ -116,7 +116,7 @@ tusb_error_t mscd_open(uint8_t port, tusb_descriptor_interface_t const * p_inter
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(*p_length) += sizeof(tusb_descriptor_interface_t) + 2*sizeof(tusb_descriptor_endpoint_t);
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//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
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ASSERT_STATUS( tusb_dcd_edpt_xfer(port, p_msc->edpt_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->edpt_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cmd_block_wrapper_t), true), TUSB_ERROR_DCD_EDPT_XFER );
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return TUSB_ERROR_NONE;
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}
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@ -197,7 +197,7 @@ tusb_error_t mscd_xfer_cb(uint8_t port, uint8_t edpt_addr, tusb_event_t event, u
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}else
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{
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memcpy(p_msc->scsi_data, p_buffer, actual_length);
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ASSERT_STATUS( tusb_dcd_edpt_queue_xfer(port, edpt_data, p_msc->scsi_data, actual_length ) );
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TU_ASSERT( tusb_dcd_edpt_queue_xfer(port, edpt_data, p_msc->scsi_data, actual_length), TUSB_ERROR_DCD_EDPT_XFER );
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}
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}
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}
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@ -213,10 +213,10 @@ tusb_error_t mscd_xfer_cb(uint8_t port, uint8_t edpt_addr, tusb_event_t event, u
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// Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
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if (!is_waiting_read10_write10)
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{
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ASSERT_STATUS( tusb_dcd_edpt_xfer(port, p_msc->edpt_in , (uint8_t*) p_csw, sizeof(msc_cmd_status_wrapper_t), false) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->edpt_in , (uint8_t*) p_csw, sizeof(msc_cmd_status_wrapper_t), false), TUSB_ERROR_DCD_EDPT_XFER );
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//------------- Queue the next CBW -------------//
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ASSERT_STATUS( tusb_dcd_edpt_xfer(port, p_msc->edpt_out, (uint8_t*) p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->edpt_out, (uint8_t*) p_cbw, sizeof(msc_cmd_block_wrapper_t), true), TUSB_ERROR_DCD_EDPT_XFER );
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}
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return TUSB_ERROR_NONE;
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@ -252,7 +252,7 @@ static bool read10_write10_data_xfer(uint8_t port, mscd_interface_t* p_msc)
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return true;
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} else if (xferred_block < block_count)
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{
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ASSERT_STATUS( tusb_dcd_edpt_xfer(port, edpt_addr, p_buffer, xferred_byte, true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, edpt_addr, p_buffer, xferred_byte, true), TUSB_ERROR_DCD_EDPT_XFER );
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// adjust lba, block_count, xfer_bytes for the next call
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p_readwrite->lba = __n2be(lba+xferred_block);
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@ -263,7 +263,7 @@ static bool read10_write10_data_xfer(uint8_t port, mscd_interface_t* p_msc)
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}else
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{
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p_csw->status = MSC_CSW_STATUS_PASSED;
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ASSERT_STATUS( tusb_dcd_edpt_queue_xfer(port, edpt_addr, p_buffer, xferred_byte) );
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TU_ASSERT( tusb_dcd_edpt_queue_xfer(port, edpt_addr, p_buffer, xferred_byte), TUSB_ERROR_DCD_EDPT_XFER );
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return true;
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}
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}
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@ -86,6 +86,7 @@
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ENTRY(TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT )\
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ENTRY(TUSB_ERROR_DCD_NOT_ENOUGH_QTD )\
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ENTRY(TUSB_ERROR_DCD_OPEN_PIPE_FAILED )\
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ENTRY(TUSB_ERROR_DCD_EDPT_XFER )\
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ENTRY(TUSB_ERROR_NOT_SUPPORTED_YET )\
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ENTRY(TUSB_ERROR_USBD_DEVICE_NOT_CONFIGURED )\
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ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY )\
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@ -88,7 +88,7 @@ typedef enum
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TUSB_DESC_DEBUG = 0x0A ,
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TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B ,
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TUSB_DESC_CLASS_SPECIFIC = 0x24
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}tusb_std_descriptor_type_t;
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}tusb_desc_type_t;
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typedef enum
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{
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@ -60,11 +60,11 @@
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// VERIFY Helper
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//--------------------------------------------------------------------+
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#if TUSB_CFG_DEBUG >= 1
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// #define VERIFY_MESS(format, ...) cprintf("[%08ld] %s: %d: verify failed\n", get_millis(), __func__, __LINE__)
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#define VERIFY_MESS(_status) printf("%s: %d: verify failed, error = %s\n", __PRETTY_FUNCTION__, __LINE__, TUSB_ErrorStr[_status]);
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// #define _VERIFY_MESS(format, ...) cprintf("[%08ld] %s: %d: verify failed\n", get_millis(), __func__, __LINE__)
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#define _VERIFY_MESS(_status) printf("%s: %d: verify failed, error = %s\n", __PRETTY_FUNCTION__, __LINE__, TUSB_ErrorStr[_status]);
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#define _ASSERT_MESS() printf("%s: %d: assert failed\n", __PRETTY_FUNCTION__, __LINE__);
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#else
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#define VERIFY_MESS(_status)
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#define _VERIFY_MESS(_status)
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#define _ASSERT_MESS()
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#endif
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@ -82,13 +82,13 @@
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#define VERIFY_STS_1ARGS(sts) \
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do { \
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uint32_t _status = (uint32_t)(sts); \
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if ( 0 != _status ) { VERIFY_MESS(_status) return _status; } \
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if ( 0 != _status ) { _VERIFY_MESS(_status) return _status; } \
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} while(0)
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#define VERIFY_STS_2ARGS(sts, _error) \
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do { \
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uint32_t _status = (uint32_t)(sts); \
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if ( 0 != _status ) { VERIFY_MESS(_status) return _error; }\
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if ( 0 != _status ) { _VERIFY_MESS(_status) return _error; }\
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} while(0)
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/**
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@ -106,13 +106,13 @@
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#define VERIFY_STS_HDLR_2ARGS(sts, _handler) \
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do { \
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uint32_t _status = (uint32_t)(sts); \
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if ( 0 != _status ) { VERIFY_MESS(_status) _handler; return _status; }\
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if ( 0 != _status ) { _VERIFY_MESS(_status) _handler; return _status; }\
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} while(0)
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#define VERIFY_STS_HDLR_3ARGS(sts, _handler, _error) \
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do { \
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uint32_t _status = (uint32_t)(sts); \
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if ( 0 != _status ) { VERIFY_MESS(_status) _handler; return _error; }\
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if ( 0 != _status ) { _VERIFY_MESS(_status) _handler; return _error; }\
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} while(0)
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#define VERIFY_STATUS_HDLR(...) GET_4TH_ARG(__VA_ARGS__, VERIFY_STS_HDLR_3ARGS, VERIFY_STS_HDLR_2ARGS)(__VA_ARGS__)
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@ -401,7 +401,7 @@ static tusb_error_t usbd_set_configure_received(uint8_t port, uint8_t config_num
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static tusb_error_t get_descriptor(uint8_t port, tusb_control_request_t const * const p_request, uint8_t const ** pp_buffer, uint16_t * p_length)
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{
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tusb_std_descriptor_type_t const desc_type = (tusb_std_descriptor_type_t) u16_high_u8(p_request->wValue);
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tusb_desc_type_t const desc_type = (tusb_desc_type_t) u16_high_u8(p_request->wValue);
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uint8_t const desc_index = u16_low_u8( p_request->wValue );
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uint8_t const * p_data = NULL ;
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@ -62,37 +62,38 @@ typedef enum
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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bool tusb_dcd_init (uint8_t port);
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void tusb_dcd_connect (uint8_t port);
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void tusb_dcd_disconnect (uint8_t port);
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void tusb_dcd_set_address (uint8_t port, uint8_t dev_addr);
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void tusb_dcd_set_config (uint8_t port, uint8_t config_num);
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bool tusb_dcd_init (uint8_t port);
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void tusb_dcd_connect (uint8_t port);
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void tusb_dcd_disconnect (uint8_t port);
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void tusb_dcd_set_address (uint8_t port, uint8_t dev_addr);
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void tusb_dcd_set_config (uint8_t port, uint8_t config_num);
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/*------------------------------------------------------------------*/
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/* Event Function
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* Called by DCD to notify USBD
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*------------------------------------------------------------------*/
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void tusb_dcd_bus_event(uint8_t port, usbd_bus_event_type_t bus_event);
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void tusb_dcd_setup_received(uint8_t port, uint8_t const* p_request);
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void tusb_dcd_xfer_complete(uint8_t port, uint8_t edpt_addr, uint32_t xferred_bytes, bool succeeded);
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void tusb_dcd_bus_event (uint8_t port, usbd_bus_event_type_t bus_event);
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void tusb_dcd_setup_received (uint8_t port, uint8_t const* p_request);
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void tusb_dcd_xfer_complete (uint8_t port, uint8_t edpt_addr, uint32_t xferred_bytes, bool succeeded);
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/*------------------------------------------------------------------*/
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/* Endpoint API
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*------------------------------------------------------------------*/
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//------------- Control Endpoint -------------//
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bool tusb_dcd_control_xfer(uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete);
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void tusb_dcd_control_stall(uint8_t port);
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bool tusb_dcd_control_xfer (uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete);
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void tusb_dcd_control_stall (uint8_t port);
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//------------- Other Endpoints -------------//
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bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc);
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tusb_error_t tusb_dcd_edpt_queue_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes); // only queue, not transferring yet
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tusb_error_t tusb_dcd_edpt_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete);
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bool tusb_dcd_edpt_open (uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc);
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bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete);
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bool tusb_dcd_edpt_queue_xfer (uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes); // only queue, not transferring yet
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bool tusb_dcd_edpt_busy(uint8_t port, uint8_t edpt_addr);
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void tusb_dcd_edpt_stall (uint8_t port, uint8_t edpt_addr);
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void tusb_dcd_edpt_clear_stall (uint8_t port, uint8_t edpt_addr);
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void tusb_dcd_edpt_stall(uint8_t port, uint8_t edpt_addr);
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void tusb_dcd_edpt_clear_stall(uint8_t port, uint8_t edpt_addr);
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// TODO may remove
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bool tusb_dcd_edpt_busy (uint8_t port, uint8_t edpt_addr);
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#ifdef __cplusplus
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}
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