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- move CMSIS & driver lib for lpc13u to codebase bsp/lpc13xx

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- change descriptor.c/h able to build device example
This commit is contained in:
hathach 2013-05-23 13:22:46 +07:00
parent d7ae21203c
commit 8cb7818bcc
50 changed files with 5307 additions and 257 deletions
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2
demos/bsp/boards/board.h
View File

@ -84,7 +84,7 @@
#elif BOARD == BOARD_NGX4330
#include "ngx/board_ngx4330.h"
#elif BOARD == BOARD_LPCXPRESSO1347
#include "board_lpcxpresso1347.h"
#include "lpcxpresso/board_lpcxpresso1347.h"
#elif BOARD == BOARD_AT86RF2XX
#include "board_at86rf2xx.h"
#elif BOARD == BOARD_EA4357

2
demos/bsp/boards/board_lpcxpresso1347.c → demos/bsp/boards/lpcxpresso/board_lpcxpresso1347.c
View File

@ -36,7 +36,7 @@
*/
/**************************************************************************/
#include "board.h"
#include "../board.h"
#if BOARD == BOARD_LPCXPRESSO1347

4
demos/bsp/boards/board_lpcxpresso1347.h → demos/bsp/boards/lpcxpresso/board_lpcxpresso1347.h
View File

@ -57,8 +57,8 @@
#endif
#include "LPC13Uxx.h"
#include "lpc13uxx/gpio.h"
#include "lpc13uxx/uart.h"
#include "lpc13uxx/LPC13Uxx_DriverLib/inc/gpio.h"
#include "lpc13uxx/LPC13Uxx_DriverLib/inc/uart.h"
#define CFG_LED_PORT (0)
#define CFG_LED_PIN (7)

2
demos/bsp/boards/board_at86rf2xx.c → demos/bsp/boards/microbuilder/board_at86rf2xx.c
View File

@ -36,7 +36,7 @@
*/
/**************************************************************************/
#include "board.h"
#include "../board.h"
#if BOARD == BOARD_AT86RF2XX

0
demos/bsp/boards/board_at86rf2xx.h → demos/bsp/boards/microbuilder/board_at86rf2xx.h
View File

414
demos/bsp/lpc13uxx/CMSISv2p10_LPC13Uxx/.cproject Normal file
View File

@ -0,0 +1,414 @@
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&lt;Properties property_0="" property_1="" property_3="NXP" property_4="LPC1347" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&#13;
&lt;info chip="LPC1347" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
&lt;chip&gt;&#13;
&lt;name&gt;LPC1347&lt;/name&gt;&#13;
&lt;family&gt;LPC13xx (12bit ADC)&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x40064000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&#13;
&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;</projectStorage>
</storageModule>
</cproject>

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/****************************************************************************************************//**
* @file LPC13Uxx.h
*
*
*
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* default LPC13Uxx Device Series
*
* @version V0.1
* @date 18. Jan 2012
*
* @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
*
* from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
* created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
*
*******************************************************************************************************/
/** @addtogroup NXP
* @{
*/
/** @addtogroup LPC13Uxx
* @{
*/
#ifndef __LPC13UXX_H__
#define __LPC13UXX_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/* Interrupt Number Definition */
typedef enum {
// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
GINT0_IRQn = 8, /*!< 8 GINT0 */
GINT1_IRQn = 9, /*!< 9 GINT1 */
Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
SSP1_IRQn = 14, /*!< 14 SSP1 */
I2C_IRQn = 15, /*!< 15 I2C */
CT16B0_IRQn = 16, /*!< 16 CT16B0 */
CT16B1_IRQn = 17, /*!< 17 CT16B1 */
CT32B0_IRQn = 18, /*!< 18 CT32B0 */
CT32B1_IRQn = 19, /*!< 19 CT32B1 */
SSP0_IRQn = 20, /*!< 20 SSP0 */
USART_IRQn = 21, /*!< 21 USART */
USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ADC_IRQn = 24, /*!< 24 ADC */
WDT_IRQn = 25, /*!< 25 WDT */
BOD_IRQn = 26, /*!< 26 BOD */
FMC_IRQn = 27, /*!< 27 FMC */
Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
/** @addtogroup Device_Peripheral_Registers
* @{
*/
// ------------------------------------------------------------------------------------------------
// ----- I2C -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40000000) I2C Structure */
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
union{
__IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
struct{
__IO uint32_t ADR1;
__IO uint32_t ADR2;
__IO uint32_t ADR3;
};
};
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
union{
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
struct{
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
};
};
} LPC_I2C_Type;
// ------------------------------------------------------------------------------------------------
// ----- WWDT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40004000) WWDT Structure */
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
__O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
} LPC_WWDT_Type;
// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40008000) USART Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union {
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__I uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
__I uint32_t RESERVED1;
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
} LPC_USART_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT16B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
__IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B0_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT16B1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B1_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT32B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B0_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT32B1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B1_Type;
// ------------------------------------------------------------------------------------------------
// ----- ADC -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4001C000) ADC Structure */
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__I uint32_t RESERVED0[1];
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
union{
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
struct{
__I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
__I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
__I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
__I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
__I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
__I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
__I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
__I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
};
};
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
} LPC_ADC_Type;
// ------------------------------------------------------------------------------------------------
// ----- PMU -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40038000) PMU Structure */
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
union{
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
struct{
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
};
};
__IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
} LPC_PMU_Type;
// ------------------------------------------------------------------------------------------------
// ----- FLASHCTRL -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
__I uint32_t RESERVED2[1];
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
__I uint32_t RESERVED3[1001];
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
__I uint32_t RESERVED4[1];
__O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
} LPC_FLASHCTRL_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
} LPC_SSP0_Type;
// ------------------------------------------------------------------------------------------------
// ----- IOCON -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40044000) IOCON Structure */
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
__IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
__IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
__IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
__IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
__IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
__IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
__IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
__IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
__IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
__IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
__IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
__IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
__IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
__IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
__IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
} LPC_IOCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- SYSCON -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
__I uint32_t RESERVED0[2];
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
__I uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
__I uint32_t RESERVED3;
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
__I uint32_t RESERVED4[9];
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
__I uint32_t RESERVED5;
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
__I uint32_t RESERVED6;
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
__I uint32_t RESERVED7[4];
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
__I uint32_t RESERVED8[3];
__IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
__IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
__I uint32_t RESERVED9[3];
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
__I uint32_t RESERVED10;
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
__I uint32_t RESERVED11[5];
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
__I uint32_t RESERVED12;
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
__I uint32_t RESERVED13[5];
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
__I uint32_t RESERVED14[18];
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
__I uint32_t RESERVED15[6];
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
__IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
__I uint32_t RESERVED16[25];
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
__I uint32_t RESERVED17[3];
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
__I uint32_t RESERVED18[6];
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
__I uint32_t RESERVED19[111];
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
} LPC_SYSCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PIN_INT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
__O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
__O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
__O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
} LPC_GPIO_PIN_INT_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40058000) SSP1 Structure */
__IO uint32_t CR0; /*!< (@ 0x40058000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40058004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40058008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4005800C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40058010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40058014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40058018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4005801C) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< (@ 0x40058020) SSPICR Interrupt Clear Register */
} LPC_SSP1_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INT0_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
__IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INT1_Type;
// ------------------------------------------------------------------------------------------------
// ----- Repetitive Interrupt Timer (RIT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
__IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
__IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
__IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
__IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
__IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
__IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
__I uint32_t RESERVED0[1];
__IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
} LPC_RITIMER_Type;
// ------------------------------------------------------------------------------------------------
// ----- USB -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40020000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
} LPC_USB_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PORT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
union {
struct {
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
};
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
};
__I uint32_t RESERVED0[1008];
union {
struct {
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
};
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
};
__I uint32_t RESERVED1[960];
__IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
__I uint32_t RESERVED2[30];
__IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
__I uint32_t RESERVED3[30];
__IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
__I uint32_t RESERVED4[30];
__IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
__I uint32_t RESERVED5[30];
__IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
__I uint32_t RESERVED6[30];
__O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
__I uint32_t RESERVED7[30];
__O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
} LPC_GPIO_Type;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
// ------------------------------------------------------------------------------------------------
// ----- Peripheral memory map -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C_BASE (0x40000000)
#define LPC_WWDT_BASE (0x40004000)
#define LPC_USART_BASE (0x40008000)
#define LPC_CT16B0_BASE (0x4000C000)
#define LPC_CT16B1_BASE (0x40010000)
#define LPC_CT32B0_BASE (0x40014000)
#define LPC_CT32B1_BASE (0x40018000)
#define LPC_ADC_BASE (0x4001C000)
#define LPC_PMU_BASE (0x40038000)
#define LPC_FLASHCTRL_BASE (0x4003C000)
#define LPC_SSP0_BASE (0x40040000)
#define LPC_IOCON_BASE (0x40044000)
#define LPC_SYSCON_BASE (0x40048000)
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
#define LPC_SSP1_BASE (0x40058000)
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
#define LPC_RITIMER_BASE (0x40064000)
#define LPC_USB_BASE (0x40080000)
#define LPC_GPIO_BASE (0x50000000)
// ------------------------------------------------------------------------------------------------
// ----- Peripheral declaration -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
#define LPC_CT16B1 ((LPC_CT16B1_Type *) LPC_CT16B1_BASE)
#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
#define LPC_CT32B1 ((LPC_CT32B1_Type *) LPC_CT32B1_BASE)
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP1_Type *) LPC_SSP1_BASE)
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group (null) */
/** @} */ /* End of group h1usf */
#ifdef __cplusplus
}
#endif
#endif // __LPC13UXX_H__

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10
* @date 26. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

0
demos/bsp/lpc13uxx/power_api.h → demos/bsp/lpc13uxx/CMSISv2p10_LPC13Uxx/inc/power_api.h
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64
demos/bsp/lpc13uxx/CMSISv2p10_LPC13Uxx/inc/system_LPC13Uxx.h Normal file
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/**************************************************************************//**
* @file system_LPC13Uxx.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
* for the NXP LPC13Uxx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC13Uxx_H
#define __SYSTEM_LPC13Uxx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC13Uxx_H */

32
demos/bsp/lpc13uxx/CMSISv2p10_LPC13Uxx/liblinks.xml Normal file
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<!-- liblinks.xml
Code Red Technologies "Smart update wizard" script file
When executed on a particular application project, will
add appropriate links to the specified library project.
Note that this script assumes that the application project
contains the standard 'Debug' and 'Release' build
configurations.
-->
<project name="" update="true">
<setting id="all.compiler.inc">
<value>${workspace_loc:/CMSISv2p10_LPC13Uxx/inc}</value>
</setting>
<setting id="all.compiler.def">
<value>__USE_CMSIS=CMSISv2p10_LPC13Uxx</value>
</setting>
<setting id="linker.libs">
<value>CMSISv2p10_LPC13Uxx</value>
</setting>
<setting id="linker.paths" buildType="Debug">
<value>${workspace_loc:/CMSISv2p10_LPC13Uxx/Debug}</value>
</setting>
<setting id="linker.paths" buildType="Release">
<value>${workspace_loc:/CMSISv2p10_LPC13Uxx/Release}</value>
</setting>
<requires msg="Library project `CMSISv2p10_LPC13Uxx` not found">
<value>CMSISv2p10_LPC13Uxx</value>
</requires>
</project>

437
demos/bsp/lpc13uxx/CMSISv2p10_LPC13Uxx/src/system_LPC13Uxx.c Normal file
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/******************************************************************************
* @file system_LPC13Uxx.c
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC13xx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC13Uxx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Oscillator Control Register (SYSOSCCTRL)
// <o1.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o1.9> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
//
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
// <o2.0..4> DIVSEL: Select Divider for Fclkana
// <i> wdt_osc_clk = Fclkana/ (2 <20> (1 + DIVSEL))
// <0-31>
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
// <0=> Undefined
// <1=> 0.5 MHz
// <2=> 0.8 MHz
// <3=> 1.1 MHz
// <4=> 1.4 MHz
// <5=> 1.6 MHz
// <6=> 1.8 MHz
// <7=> 2.0 MHz
// <8=> 2.2 MHz
// <9=> 2.4 MHz
// <10=> 2.6 MHz
// <11=> 2.7 MHz
// <12=> 2.9 MHz
// <13=> 3.1 MHz
// <14=> 3.2 MHz
// <15=> 3.4 MHz
// </h>
//
// <h> System PLL Control Register (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o3.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o3.5..6> PSEL: Post Divider Selection
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
//
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
// <o4.0..1> SEL: System PLL Clock Source
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> Main Clock Source Select Register (MAINCLKSEL)
// <o5.0..1> SEL: Clock Source for Main Clock
// <0=> IRC Oscillator
// <1=> Input Clock to System PLL
// <2=> WDT Oscillator
// <3=> System PLL Clock Out
// </h>
//
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
// <o6.0..7> DIV: System AHB Clock Divider
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
// </h>
//
// <h> USB PLL Control Register (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o7.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o7.5..6> PSEL: Post Divider Selection
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
//
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
// <o8.0..1> SEL: USB PLL Clock Source
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> USB Clock Source Select Register (USBCLKSEL)
// <o9.0..1> SEL: System PLL Clock Source
// <0=> USB PLL out
// <1=> Main clock
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> USB Clock Divider Register (USBCLKDIV)
// <o10.0..7> DIV: USB Clock Divider
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
// </h>
// </e>
*/
#define CLOCK_SETUP 1
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
#error "WDTOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
#error "MAINCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (12000000UL) /* Oscillator frequency */
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
#if (CLOCK_SETUP) /* Clock Setup */
#if (__FREQSEL == 0)
#define __WDT_OSC_CLK ( 0) /* undefined */
#elif (__FREQSEL == 1)
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
#elif (__FREQSEL == 2)
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
#elif (__FREQSEL == 3)
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
#elif (__FREQSEL == 4)
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
#elif (__FREQSEL == 5)
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
#elif (__FREQSEL == 6)
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
#elif (__FREQSEL == 7)
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
#elif (__FREQSEL == 8)
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
#elif (__FREQSEL == 9)
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
#elif (__FREQSEL == 10)
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
#elif (__FREQSEL == 11)
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
#elif (__FREQSEL == 12)
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
#elif (__FREQSEL == 13)
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
#elif (__FREQSEL == 14)
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
#else
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
#endif
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#else
#define __SYS_PLLCLKIN (0)
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSEL_Val & 0x03) == 0)
#define __MAIN_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSEL_Val & 0x03) == 1)
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSEL_Val & 0x03) == 2)
#if (__FREQSEL == 0)
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
#else
#define __MAIN_CLOCK (__WDT_OSC_CLK)
#endif
#elif ((MAINCLKSEL_Val & 0x03) == 3)
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
#else
#define __MAIN_CLOCK (0)
#endif
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif // CLOCK_SETUP
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t wdt_osc = 0;
/* Determine clock frequency according to clock register values */
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
case 0: wdt_osc = 0; break;
case 1: wdt_osc = 500000; break;
case 2: wdt_osc = 800000; break;
case 3: wdt_osc = 1100000; break;
case 4: wdt_osc = 1400000; break;
case 5: wdt_osc = 1600000; break;
case 6: wdt_osc = 1800000; break;
case 7: wdt_osc = 2000000; break;
case 8: wdt_osc = 2200000; break;
case 9: wdt_osc = 2400000; break;
case 10: wdt_osc = 2600000; break;
case 11: wdt_osc = 2700000; break;
case 12: wdt_osc = 2900000; break;
case 13: wdt_osc = 3100000; break;
case 14: wdt_osc = 3200000; break;
case 15: wdt_osc = 3400000; break;
}
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* WDT Oscillator */
SystemCoreClock = wdt_osc;
break;
case 3: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
SystemCoreClock = __IRC_OSC_CLK;
} else {
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
}
break;
case 1: /* System oscillator */
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
SystemCoreClock = __SYS_OSC_CLK;
} else {
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
}
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void) {
volatile uint32_t i;
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
for (i = 0; i < 200; i++) __NOP();
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
#if (((MAINCLKSEL_Val & 0x03) == 2) )
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
for (i = 0; i < 200; i++) __NOP();
#endif
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
#endif
#endif
/* System clock to the IOCON needs to be enabled or
most of the I/O related peripherals won't work. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
}

417
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<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
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</storageModule>
<storageModule moduleId="com.crt.config">
<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_0="" property_1="" property_3="NXP" property_4="LPC1347" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&#13;
&lt;info chip="LPC1347" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
&lt;chip&gt;&#13;
&lt;name&gt;LPC1347&lt;/name&gt;&#13;
&lt;family&gt;LPC13Uxx&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x40064000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&#13;
&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpc13U_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;</projectStorage>
</storageModule>
</cproject>

83
demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/.project Normal file
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@ -0,0 +1,83 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>LPC13Uxx_DriverLib</name>
<comment></comment>
<projects>
<project>CMSISv2p10_LPC13Uxx</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
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<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
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<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildLocation</key>
<value>${workspace_loc:/LPC13Uxx_DriverLib/Debug}</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
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</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

0
demos/bsp/lpc13uxx/clkconfig.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/clkconfig.h
View File

0
demos/bsp/lpc13uxx/gpio.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/gpio.h
View File

0
demos/bsp/lpc13uxx/nmi.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/nmi.h
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88
demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/power_api.h Normal file
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@ -0,0 +1,88 @@
/****************************************************************************
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
* Project: NXP LPC13Uxx software example
*
* Description:
* Power API Header File for NXP LPC13Uxx Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __LPC13UXX_POWER_API_H__
#define __LPC13UXX_POWER_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#define PWRROMD_PRESENT
#define USBROMD_PRESENT
#ifdef USBROMD_PRESENT
#include "mw_usbd_rom_api.h"
#endif
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
#ifdef USBROMD_PRESENT
const USBD_API_T * pUSBD;
#else
const unsigned p_usbd;
#endif /* USBROMD_PRESENT */
const unsigned p_clib;
const unsigned p_cand;
#ifdef PWRROMD_PRESENT
const PWRD * pPWRD;
#else
const unsigned p_pwrd;
#endif /* PWRROMD_PRESENT */
const unsigned p_dev1;
const unsigned p_dev2;
const unsigned p_dev3;
const unsigned p_dev4;
} ROM;
//PLL setup related definitions
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
//power setup elated definitions
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
#define MAX_CLOCK_KHZ_PARAM 50000
#ifdef __cplusplus
}
#endif
#endif /* __LPC13UXX_POWER_API_H__ */

0
demos/bsp/lpc13uxx/timer16.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/timer16.h
View File

0
demos/bsp/lpc13uxx/timer32.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/timer32.h
View File

0
demos/bsp/lpc13uxx/type.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/type.h
View File

0
demos/bsp/lpc13uxx/uart.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/uart.h
View File

0
demos/bsp/lpc13uxx/usart.h → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc/usart.h
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32
demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/liblinks.xml Normal file
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@ -0,0 +1,32 @@
<!-- liblinks.xml
Code Red Technologies "Smart update wizard" script file
When executed on a particular application project, will
add appropriate links to the specified library project.
Note that this script assumes that the application project
contains the standard 'Debug' and 'Release' build
configurations.
-->
<project name="" update="true">
<setting id="all.compiler.inc">
<value>${workspace_loc:/LPC13Uxx_DriverLib/inc}</value>
</setting>
<setting id="all.compiler.def">
<value>__USE_LPC13Uxx_DriverLib</value>
</setting>
<setting id="linker.libs">
<value>LPC13Uxx_DriverLib</value>
</setting>
<setting id="linker.paths" buildType="Debug">
<value>${workspace_loc:/LPC13Uxx_DriverLib/Debug}</value>
</setting>
<setting id="linker.paths" buildType="Release">
<value>${workspace_loc:/LPC13Uxx_DriverLib/Release}</value>
</setting>
<requires msg="Library project `LPC13Uxx_DriverLib` not found">
<value>LPC13Uxx_DriverLib</value>
</requires>
</project>

0
demos/bsp/lpc13uxx/Serial.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/Serial.c
View File

0
demos/bsp/lpc13uxx/clkconfig.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/clkconfig.c
View File

0
demos/bsp/lpc13uxx/gpio.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/gpio.c
View File

0
demos/bsp/lpc13uxx/nmi.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/nmi.c
View File

0
demos/bsp/lpc13uxx/timer16.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/timer16.c
View File

0
demos/bsp/lpc13uxx/timer32.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/timer32.c
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0
demos/bsp/lpc13uxx/uart.c → demos/bsp/lpc13uxx/LPC13Uxx_DriverLib/src/uart.c
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15
demos/device/keyboard/.cproject
View File

@ -41,7 +41,8 @@
</option>
<option id="gnu.c.compiler.option.misc.other.204394496" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections" valueType="string"/>
<option id="gnu.c.compiler.option.include.paths.1207481236" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/CMSISv2p10_LPC13Uxx/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/lpc13uxx/CMSISv2p10_LPC13Uxx/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/lpc13uxx/LPC13Uxx_DriverLib/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/tinyusb}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
@ -69,12 +70,8 @@
<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
<listOptionValue builtIn="false" value="--gc-sections"/>
</option>
<option id="gnu.c.link.option.paths.1465143173" name="Library search path (-L)" superClass="gnu.c.link.option.paths" valueType="libPaths">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/CMSISv2p10_LPC13Uxx/Debug}&quot;"/>
</option>
<option id="gnu.c.link.option.libs.447978281" name="Libraries (-l)" superClass="gnu.c.link.option.libs" valueType="libs">
<listOptionValue builtIn="false" value="CMSISv2p10_LPC13Uxx"/>
</option>
<option id="gnu.c.link.option.paths.1465143173" name="Library search path (-L)" superClass="gnu.c.link.option.paths" valueType="libPaths"/>
<option id="gnu.c.link.option.libs.447978281" name="Libraries (-l)" superClass="gnu.c.link.option.libs" valueType="libs"/>
<option id="com.crt.advproject.link.gcc.hdrlib.1111642583" name="Use C library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.codered.nohost" valueType="enumerated"/>
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1234316494" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
@ -84,7 +81,7 @@
</toolChain>
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<sourceEntries>
<entry excluding="bsp/lpc43xx|bsp/lpc11uxx" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="bsp/boards/embedded_artists/oem_base_board|bsp/lpc43xx|bsp/lpc11uxx" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
@ -739,7 +736,7 @@
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="bsp/lpc43xx|bsp/lpc13uxx" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="bsp/boards/embedded_artists/oem_base_board|bsp/lpc43xx|bsp/lpc13uxx" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

272
demos/device/keyboard/descriptors.c
View File

@ -37,130 +37,121 @@
#include "descriptors.h"
#ifdef TUSB_CFG_DEVICE_HID_KEYBOARD
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const uint8_t HID_KeyboardReportDescriptor[] = {
HID_UsagePage ( HID_USAGE_PAGE_GENERIC ),
HID_Usage ( HID_USAGE_GENERIC_KEYBOARD ),
HID_Collection ( HID_Application ),
HID_UsagePage (HID_USAGE_PAGE_KEYBOARD),
HID_UsageMin (224 ),
HID_UsageMax (231 ),
HID_LogicalMin ( 0 ),
HID_LogicalMax ( 1 ),
#if TUSB_CFG_DEVICE_HID_KEYBOARD
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
const uint8_t keyboard_report_descriptor[] = {
HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ),
HID_USAGE ( HID_USAGE_DESKTOP_KEYBOARD ),
HID_COLLECTION ( HID_COLLECTION_APPLICATION ),
HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD ),
HID_USAGE_MIN ( 224 ),
HID_USAGE_MAX ( 231 ),
HID_LOGICAL_MIN ( 0 ),
HID_LOGICAL_MAX ( 1 ),
HID_ReportCount ( 8 ), /* 8 bits */
HID_ReportSize ( 1 ),
HID_Input ( HID_Data | HID_Variable | HID_Absolute ), /* maskable modifier key */
HID_REPORT_COUNT ( 8 ), /* 8 bits */
HID_REPORT_SIZE ( 1 ),
HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ), /* maskable modifier key */
HID_ReportCount ( 1 ),
HID_ReportSize (8 ),
HID_Input (HID_Constant ), /* reserved */
HID_REPORT_COUNT ( 1 ),
HID_REPORT_SIZE ( 8 ),
HID_INPUT ( HID_CONSTANT ), /* reserved */
HID_UsagePage ( HID_USAGE_PAGE_LED ),
HID_UsageMin (1 ),
HID_UsageMax (5 ),
HID_ReportCount (5 ),
HID_ReportSize (1 ),
HID_Output ( HID_Data | HID_Variable | HID_Absolute ), /* 5-bit Led report */
HID_USAGE_PAGE ( HID_USAGE_PAGE_LED ),
HID_USAGE_MIN ( 1 ),
HID_USAGE_MAX ( 5 ),
HID_REPORT_COUNT ( 5 ),
HID_REPORT_SIZE ( 1 ),
HID_OUTPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ), /* 5-bit Led report */
HID_ReportCount ( 1 ),
HID_ReportSize (3 ), /* led padding */
HID_Output (HID_Constant ),
HID_REPORT_COUNT ( 1 ),
HID_REPORT_SIZE ( 3 ), /* led padding */
HID_OUTPUT ( HID_CONSTANT ),
HID_UsagePage (HID_USAGE_PAGE_KEYBOARD),
HID_UsageMin (0 ),
HID_UsageMax (101 ),
HID_LogicalMin (0 ),
HID_LogicalMax (101 ),
HID_USAGE_PAGE (HID_USAGE_PAGE_KEYBOARD),
HID_USAGE_MIN ( 0 ),
HID_USAGE_MAX ( 101 ),
HID_LOGICAL_MIN ( 0 ),
HID_LOGICAL_MAX ( 101 ),
HID_ReportCount (6 ),
HID_ReportSize (8 ),
HID_Input (HID_Data | HID_Array | HID_Absolute ), /* keycodes array 6 items */
HID_EndCollection,
HID_REPORT_COUNT ( 6 ),
HID_REPORT_SIZE ( 8 ),
HID_INPUT ( HID_DATA | HID_ARRAY | HID_ABSOLUTE ), /* keycodes array 6 items */
HID_COLLECTION_END
};
#endif
#ifdef TUSB_CFG_DEVICE_HID_MOUSE
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const uint8_t HID_MouseReportDescriptor[] = {
HID_UsagePage ( HID_USAGE_PAGE_GENERIC ),
HID_Usage ( HID_USAGE_GENERIC_MOUSE ),
HID_Collection ( HID_Application ),
HID_Usage (HID_USAGE_GENERIC_POINTER),
#if TUSB_CFG_DEVICE_HID_MOUSE
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
const uint8_t mouse_report_descriptor[] = {
HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ),
HID_USAGE ( HID_USAGE_DESKTOP_MOUSE ),
HID_COLLECTION ( HID_COLLECTION_APPLICATION ),
HID_USAGE (HID_USAGE_DESKTOP_POINTER),
HID_Collection ( HID_Physical ),
HID_UsagePage ( HID_USAGE_PAGE_BUTTON ),
HID_UsageMin ( 1 ),
HID_UsageMax ( 3 ),
HID_LogicalMin ( 0 ),
HID_LogicalMax ( 1 ),
HID_COLLECTION ( HID_COLLECTION_PHYSICAL ),
HID_USAGE_PAGE ( HID_USAGE_PAGE_BUTTON ),
HID_USAGE_MIN ( 1 ),
HID_USAGE_MAX ( 3 ),
HID_LOGICAL_MIN ( 0 ),
HID_LOGICAL_MAX ( 1 ),
HID_ReportCount ( 3 ), /* Left, Right and Middle mouse*/
HID_ReportSize ( 1 ),
HID_Input ( HID_Data | HID_Variable | HID_Absolute ),
HID_REPORT_COUNT ( 3 ), /* Left, Right and Middle mouse*/
HID_REPORT_SIZE ( 1 ),
HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),
HID_ReportCount ( 1 ),
HID_ReportSize ( 5 ),
HID_Input (HID_Constant ), /* reserved */
HID_REPORT_COUNT ( 1 ),
HID_REPORT_SIZE ( 5 ),
HID_INPUT ( HID_CONSTANT ), /* reserved */
HID_UsagePage ( HID_USAGE_PAGE_GENERIC ),
HID_Usage ( HID_USAGE_GENERIC_X ),
HID_Usage ( HID_USAGE_GENERIC_Y ),
HID_LogicalMin ( 0x81 ), /* -127 */
HID_LogicalMax ( 0x7f ), /* 127 */
HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ),
HID_USAGE ( HID_USAGE_DESKTOP_X ),
HID_USAGE ( HID_USAGE_DESKTOP_Y ),
HID_LOGICAL_MIN ( 0x81 ), /* -127 */
HID_LOGICAL_MAX ( 0x7f ), /* 127 */
HID_ReportCount ( 2 ), /* X, Y position */
HID_ReportSize ( 8 ),
HID_Input ( HID_Data | HID_Variable | HID_Relative ), /* relative values */
HID_REPORT_COUNT ( 2 ), /* X, Y position */
HID_REPORT_SIZE ( 8 ),
HID_INPUT ( HID_DATA | HID_VARIABLE | HID_RELATIVE ), /* relative values */
HID_COLLECTION_END,
HID_EndCollection,
HID_EndCollection,
HID_COLLECTION_END
};
#endif
/* USB Standard Device Descriptor */
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const USB_DEVICE_DESCRIPTOR USB_DeviceDescriptor =
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
tusb_descriptor_device_t const desc_device =
{
.bLength = sizeof(USB_DEVICE_DESCRIPTOR),
.bDescriptorType = USB_DEVICE_DESCRIPTOR_TYPE,
.bcdUSB = 0x0200,
.bLength = sizeof(tusb_descriptor_device_t),
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = 0x0200,
.bDeviceClass = 0x00,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
#if IAD_DESC_REQUIRED
/* Multiple Interfaces Using Interface Association Descriptor (IAD) */
.bDeviceClass = USB_DEVICE_CLASS_IAD,
.bDeviceSubClass = USB_DEVICE_SUBCLASS_IAD,
.bDeviceProtocol = USB_DEVICE_PROTOCOL_IAD,
#elif defined TUSB_CFG_DEVICE_CDC
.bDeviceClass = CDC_COMMUNICATION_INTERFACE_CLASS,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
#else
.bDeviceClass = 0x00,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
#endif
.bMaxPacketSize0 = USB_MAX_PACKET0,
.bMaxPacketSize0 = USB_MAX_PACKET0,
.idVendor = CFG_USB_VENDORID,
.idProduct = USB_PRODUCT_ID,
.bcdDevice = 0x0100,
.idVendor = CFG_USB_VENDORID,
.idProduct = USB_PRODUCT_ID,
.bcdDevice = 0x0100,
.iManufacturer = 0x01,
.iProduct = 0x02,
.iSerialNumber = 0x03,
.iManufacturer = 0x01,
.iProduct = 0x02,
.iSerialNumber = 0x03,
.bNumConfigurations = 0x01
.bNumConfigurations = 0x01 // TODO configuration number
};
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const USB_FS_CONFIGURATION_DESCRIPTOR USB_FsConfigDescriptor =
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
const app_configuration_desc_t desc_configuration =
{
.Config =
.configuration =
{
.bLength = sizeof(tusb_descriptor_configuration_t),
.bDescriptorType = TUSB_DESC_CONFIGURATION,
.wTotalLength = sizeof(USB_FS_CONFIGURATION_DESCRIPTOR) - 1, // exclude termination
.wTotalLength = sizeof(app_configuration_desc_t) - 1, // exclude termination
.bNumInterfaces = TOTAL_INTEFACES,
.bConfigurationValue = 1,
@ -276,47 +267,45 @@ TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const USB_FS_CONFIGURATION_DESCRIPTOR USB_F
},
#endif
#ifdef TUSB_CFG_DEVICE_HID_KEYBOARD
///// USB HID Keyboard interface
.HID_KeyboardInterface =
//------------- HID Keyboard -------------//
#if TUSB_CFG_DEVICE_HID_KEYBOARD
.keyboard_interface =
{
.bLength = sizeof(tusb_descriptor_interface_t),
.bDescriptorType = TUSB_DESC_INTERFACE,
.bInterfaceNumber = INTERFACE_INDEX_HID_KEYBOARD,
.bInterfaceNumber = 1,
.bAlternateSetting = 0x00,
.bNumEndpoints = 1,
.bInterfaceClass = TUSB_CLASS_HID,
.bInterfaceSubClass = TUSB_HID_SUBCLASS_BOOT,
.bInterfaceProtocol = TUSB_HID_PROTOCOL_KEYBOARD,
.bInterfaceSubClass = HID_SUBCLASS_BOOT,
.bInterfaceProtocol = HID_PROTOCOL_KEYBOARD,
.iInterface = 0x00
},
.HID_KeyboardHID =
.keyboard_hid =
{
.bLength = sizeof(HID_DESCRIPTOR),
.bDescriptorType = HID_HID_DESCRIPTOR_TYPE,
.bLength = sizeof(tusb_hid_descriptor_hid_t),
.bDescriptorType = HID_DESC_HID,
.bcdHID = 0x0111,
.bCountryCode = HID_Local_NotSupported,
.bNumDescriptors = 1,
.DescriptorList[0] =
{
.bDescriptorType = HID_REPORT_DESCRIPTOR_TYPE,
.wDescriptorLength = sizeof(HID_KeyboardReportDescriptor)
},
.bReportType = HID_DESC_REPORT,
.wReportLength = sizeof(keyboard_report_descriptor)
},
.HID_KeyboardEndpoint =
.keyboard_endpoint =
{
.bLength = sizeof(tusb_descriptor_endpoint_t),
.bDescriptorType = TUSB_DESC_ENDPOINT,
.bEndpointAddress = HID_KEYBOARD_EP_IN,
.bmAttributes = USB_ENDPOINT_TYPE_INTERRUPT,
.wMaxPacketSize = 0x08,
.bEndpointAddress = 0x81,
.bmAttributes = { .xfer = TUSB_XFER_INTERRUPT },
.wMaxPacketSize = { .size = 0x08 },
.bInterval = 0x0A
},
#endif
#ifdef TUSB_CFG_DEVICE_HID_MOUSE
//------------- HID Mouse -------------//
#if TUSB_CFG_DEVICE_HID_MOUSE
.HID_MouseInterface =
{
.bLength = sizeof(tusb_descriptor_interface_t),
@ -330,32 +319,65 @@ TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const USB_FS_CONFIGURATION_DESCRIPTOR USB_F
.iInterface = 0x00
},
.HID_MouseHID =
.mouse_hid =
{
.bLength = sizeof(HID_DESCRIPTOR),
.bDescriptorType = HID_HID_DESCRIPTOR_TYPE,
.bLength = sizeof(tusb_hid_descriptor_hid_t),
.bDescriptorType = HID_DESC_HID,
.bcdHID = 0x0111,
.bCountryCode = HID_Local_NotSupported,
.bNumDescriptors = 1,
.DescriptorList[0] =
{
.bDescriptorType = HID_REPORT_DESCRIPTOR_TYPE,
.wDescriptorLength = sizeof(HID_MouseReportDescriptor)
},
.bReportType = HID_DESC_REPORT,
.wReportLength = sizeof(mouse_report_descriptor)
},
.HID_MouseEndpoint =
.mouse_endpoint =
{
.bLength = sizeof(tusb_descriptor_endpoint_t),
.bDescriptorType = TUSB_DESC_ENDPOINT,
.bEndpointAddress = HID_MOUSE_EP_IN,
.bmAttributes = USB_ENDPOINT_TYPE_INTERRUPT,
.bEndpointAddress = 0x82,
.bmAttributes = { .xfer = TUSB_XFER_INTERRUPT },
.wMaxPacketSize = 0x08,
.bInterval = 0x0A
},
#endif
.ConfigDescTermination = 0,
//------------- Mass Storage -------------//
#if TUSB_CFG_DEVICE_MSC
.msc_interface =
{
.bLength = sizeof(tusb_descriptor_interface_t),
.bDescriptorType = TUSB_DESC_INTERFACE,
.bInterfaceNumber = 3,
.bAlternateSetting = 0x00,
.bNumEndpoints = 2,
.bInterfaceClass = TUSB_CLASS_MSC,
.bInterfaceSubClass = MSC_SUBCLASS_SCSI,
.bInterfaceProtocol = MSC_PROTOCOL_BOT,
.iInterface = 0x00
},
.msc_endpoint_in =
{
.bLength = sizeof(tusb_descriptor_endpoint_t),
.bDescriptorType = TUSB_DESC_ENDPOINT,
.bEndpointAddress = 0x83,
.bmAttributes = { .xfer = TUSB_XFER_BULK },
.wMaxPacketSize = 512,
.bInterval = 1
},
.msc_endpoint_out =
{
.bLength = sizeof(tusb_descriptor_endpoint_t),
.bDescriptorType = TUSB_DESC_ENDPOINT,
.bEndpointAddress = 0x03,
.bmAttributes = { .xfer = TUSB_XFER_BULK },
.wMaxPacketSize = 512,
.bInterval = 1
},
#endif
.null_termination = 0,
};
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) const USB_STR_DESCRIPTOR USB_StringDescriptor =

34
demos/device/keyboard/descriptors.h
View File

@ -115,13 +115,13 @@ typedef ATTR_PREPACKED struct ATTR_PACKED _USB_STR_DESCRIPTOR
///////////////////////////////////////////////////////////////////////
typedef struct
{
tusb_descriptor_configuration_t Config;
tusb_descriptor_configuration_t configuration;
#if IAD_DESC_REQUIRED
tusb_descriptor_interface_association_t CDC_IAD;
#endif
#ifdef TUSB_CFG_DEVICE_CDC
#if TUSB_CFG_DEVICE_CDC
//CDC - Serial
//CDC Control Interface
tusb_descriptor_interface_t CDC_CCI_Interface;
@ -136,28 +136,28 @@ typedef struct
tusb_descriptor_endpoint_t CDC_DataInEndpoint;
#endif
#ifdef TUSB_CFG_DEVICE_HID_KEYBOARD
//Keyboard HID Interface
tusb_descriptor_interface_t HID_KeyboardInterface;
HID_DESCRIPTOR HID_KeyboardHID;
tusb_descriptor_endpoint_t HID_KeyboardEndpoint;
//------------- HID Keyboard -------------//
#if TUSB_CFG_DEVICE_HID_KEYBOARD
tusb_descriptor_interface_t keyboard_interface;
tusb_hid_descriptor_hid_t keyboard_hid;
tusb_descriptor_endpoint_t keyboard_endpoint;
#endif
#ifdef TUSB_CFG_DEVICE_HID_MOUSE
//Mouse HID Interface
tusb_descriptor_interface_t HID_MouseInterface;
HID_DESCRIPTOR HID_MouseHID;
tusb_descriptor_endpoint_t HID_MouseEndpoint;
//------------- HID Mouse -------------//
#if TUSB_CFG_DEVICE_HID_MOUSE
tusb_descriptor_interface_t mouse_interface;
tusb_hid_descriptor_hid_t mouse_hid;
tusb_descriptor_endpoint_t mouse_endpoint;
#endif
unsigned char ConfigDescTermination;
} USB_FS_CONFIGURATION_DESCRIPTOR;
uint8_t null_termination;
} app_configuration_desc_t;
extern const USB_DEVICE_DESCRIPTOR USB_DeviceDescriptor;
extern const USB_FS_CONFIGURATION_DESCRIPTOR USB_FsConfigDescriptor;
extern const tusb_descriptor_device_t desc_device;
extern const app_configuration_desc_t desc_configuration;
extern const USB_STR_DESCRIPTOR USB_StringDescriptor;
extern const uint8_t HID_KeyboardReportDescriptor[];
extern const uint8_t keyboard_report_descriptor[];
extern const uint8_t HID_MouseReportDescriptor[];
#endif

51
demos/device/keyboard/tusb_config.h
View File

@ -56,22 +56,49 @@
extern "C" {
#endif
#define TUSB_CFG_CONFIGURATION_MAX 1
//--------------------------------------------------------------------+
// CONTROLLER CONFIGURATION
//--------------------------------------------------------------------+
#define TUSB_CFG_CONTROLLER0_MODE (TUSB_MODE_DEVICE)
#define TUSB_CFG_CONTROLLER1_MODE (TUSB_MODE_NONE)
/// Enable Device Support
#define TUSB_CFG_DEVICE
//--------------------------------------------------------------------+
// HOST CONFIGURATION
//--------------------------------------------------------------------+
#define TUSB_CFG_HOST_DEVICE_MAX 2
#define TUSB_CFG_CONFIGURATION_MAX 1
/// Enable CDC Support
//------------- USBD -------------//
#define TUSB_CFG_HOST_ENUM_BUFFER_SIZE 256
//------------- CLASS -------------//
#define TUSB_CFG_HOST_HUB 0
#define TUSB_CFG_HOST_HID_KEYBOARD 1
#define TUSB_CFG_HOST_HID_MOUSE 1
#define TUSB_CFG_HOST_HID_GENERIC 0
#define TUSB_CFG_HOST_MSC 0
//--------------------------------------------------------------------+
// DEVICE CONFIGURATION
//--------------------------------------------------------------------+
//------------- CORE/CONTROLLER -------------//
//------------- CLASS -------------//
#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
#define TUSB_CFG_DEVICE_HID_MOUSE 0
#define TUSB_CFG_DEVICE_MSC 0
//#define TUSB_CFG_DEVICE_CDC
/// Enable HID Keyboard support
#define TUSB_CFG_DEVICE_HID_KEYBOARD
//--------------------------------------------------------------------+
// COMMON CONFIGURATION
//--------------------------------------------------------------------+
/// Enable HID Mouse support
//#define TUSB_CFG_DEVICE_HID_MOUSE
#define TUSB_CFG_DEBUG 3
#define TUSB_CFG_DEBUG 3
#define TUSB_CFG_OS TUSB_OS_NONE
#define TUSB_CFG_OS TUSB_OS_NONE // defined using eclipse build
//#define TUSB_CFG_OS_TASK_PRIO
#define TUSB_CFG_OS_TICKS_PER_SECOND 1000
#ifdef __CODE_RED // make use of code red's support for ram region macros
#if (MCU == MCU_LPC11UXX) || (MCU == MCU_LPC13UXX)
@ -81,6 +108,10 @@
#endif
#define TUSB_CFG_ATTR_USBRAM __attribute__ ((section(TUSB_RAM_SECTION)))
#elif defined __CC_ARM // Compiled with Keil armcc
#define TUSB_CFG_ATTR_USBRAM
#else
#error compiler not specified
#endif

17
demos/host/host_freertos/.cproject
View File

@ -1332,8 +1332,8 @@
<storageModule moduleId="com.crt.config">
<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_0="" property_3="NXP" property_4="LPC4330" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4330" match_id="0x0" name="LPC4330" stub="crt_emu_lpc18_43_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4330&lt;/name&gt;&#13;
&lt;Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" stub="crt_emu_lpc18_43_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4357&lt;/name&gt;&#13;
&lt;family&gt;LPC43xx&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
@ -1341,11 +1341,17 @@
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc128" location="0x10000000" size="0x20000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc72" location="0x10080000" size="0x12000"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/&gt;&#13;
&lt;prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/&gt;&#13;
&lt;prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
@ -1356,6 +1362,7 @@
&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/&gt;&#13;
&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/&gt;&#13;
@ -1396,8 +1403,6 @@
&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/&gt;&#13;
&lt;peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;

4
demos/host/src/tusb_config.h
View File

@ -87,8 +87,8 @@
//------------- CLASS -------------//
//#define TUSB_CFG_DEVICE_CDC
#define TUSB_CFG_DEVICE_HID_KEYBOARD
//#define TUSB_CFG_DEVICE_HID_MOUSE
//#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
//#define TUSB_CFG_DEVICE_HID_MOUSE 1
//--------------------------------------------------------------------+
// COMMON CONFIGURATION

48
tests/test/support/descriptor_test.c
View File

@ -39,29 +39,6 @@
#include "tusb_option.h"
#include "descriptor_test.h"
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
tusb_descriptor_device_t const desc_device =
{
.bLength = sizeof(tusb_descriptor_device_t),
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = 0x0200,
.bDeviceClass = 0x00,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
.bMaxPacketSize0 = 64,
.idVendor = 0x1FC9,
.idProduct = 0x4000,
.bcdDevice = 0x0100,
.iManufacturer = 0x01,
.iProduct = 0x02,
.iSerialNumber = 0x03,
.bNumConfigurations = 0x02
} ;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
const uint8_t keyboard_report_descriptor[] = {
HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ),
@ -140,6 +117,31 @@ const uint8_t mouse_report_descriptor[] = {
HID_COLLECTION_END
};
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
tusb_descriptor_device_t const desc_device =
{
.bLength = sizeof(tusb_descriptor_device_t),
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = 0x0200,
.bDeviceClass = 0x00,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
.bMaxPacketSize0 = 64,
.idVendor = 0x1FC9,
.idProduct = 0x4000,
.bcdDevice = 0x0100,
.iManufacturer = 0x01,
.iProduct = 0x02,
.iSerialNumber = 0x03,
.bNumConfigurations = 0x02
} ;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4)
const app_configuration_desc_t desc_configuration =
{

64
tinyusb/class/hid.h
View File

@ -52,16 +52,16 @@
extern "C" {
#endif
enum {
HID_SUBCLASS_NONE = 0,
HID_SUBCLASS_BOOT = 1
};
enum {
HID_PROTOCOL_NONE = 0,
HID_PROTOCOL_KEYBOARD = 1,
HID_PROTOCOL_MOUSE = 2
};
//enum {
// HID_SUBCLASS_NONE = 0,
// HID_SUBCLASS_BOOT = 1
//};
//
//enum {
// HID_PROTOCOL_NONE = 0,
// HID_PROTOCOL_KEYBOARD = 1,
// HID_PROTOCOL_MOUSE = 2
//};
enum {
HID_DESC_HID = 0x21,
@ -382,28 +382,28 @@ enum {
HID_USAGE_PAGE_DESKTOP = 0x01,
HID_USAGE_PAGE_SIMULATE = 0x02,
HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03,
HID_USAGE_PAGE_SPORT = 0x04,
HID_USAGE_PAGE_GAME = 0x05,
HID_USAGE_PAGE_GENERIC_DEVICE = 0x06,
HID_USAGE_PAGE_KEYBOARD = 0x07,
HID_USAGE_PAGE_LED = 0x08,
HID_USAGE_PAGE_BUTTON = 0x09,
HID_USAGE_PAGE_ORDINAL = 0x0a,
HID_USAGE_PAGE_TELEPHONY = 0x0b,
HID_USAGE_PAGE_CONSUMER = 0x0c,
HID_USAGE_PAGE_DIGITIZER = 0x0d,
HID_USAGE_PAGE_PID = 0x0f,
HID_USAGE_PAGE_UNICODE = 0x10,
HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14,
HID_USAGE_PAGE_MEDICAL = 0x40,
HID_USAGE_PAGE_MONITOR = 0x80, //0x80 - 0x83
HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87
HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c,
HID_USAGE_PAGE_SCALE = 0x8d,
HID_USAGE_PAGE_MSR = 0x8e,
HID_USAGE_PAGE_CAMERA = 0x90,
HID_USAGE_PAGE_ARCADE = 0x91,
HID_USAGE_PAGE_VENDOR = 0xFFFF // 0xFF00 - 0xFFFF
// HID_USAGE_PAGE_SPORT = 0x04,
// HID_USAGE_PAGE_GAME = 0x05,
// HID_USAGE_PAGE_GENERIC_DEVICE = 0x06,
// HID_USAGE_PAGE_KEYBOARD = 0x07,
// HID_USAGE_PAGE_LED = 0x08,
// HID_USAGE_PAGE_BUTTON = 0x09,
// HID_USAGE_PAGE_ORDINAL = 0x0a,
// HID_USAGE_PAGE_TELEPHONY = 0x0b,
// HID_USAGE_PAGE_CONSUMER = 0x0c,
// HID_USAGE_PAGE_DIGITIZER = 0x0d,
// HID_USAGE_PAGE_PID = 0x0f,
// HID_USAGE_PAGE_UNICODE = 0x10,
// HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14,
// HID_USAGE_PAGE_MEDICAL = 0x40,
// HID_USAGE_PAGE_MONITOR = 0x80, //0x80 - 0x83
// HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87
// HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c,
// HID_USAGE_PAGE_SCALE = 0x8d,
// HID_USAGE_PAGE_MSR = 0x8e,
// HID_USAGE_PAGE_CAMERA = 0x90,
// HID_USAGE_PAGE_ARCADE = 0x91,
// HID_USAGE_PAGE_VENDOR = 0xFFFF // 0xFF00 - 0xFFFF
};
/// HID Usage Table - Table 6: Generic Desktop Page

1
tinyusb/class/hid_device.h
View File

@ -52,6 +52,7 @@
#ifndef _TUSB_HID_DEVICE_H_
#define _TUSB_HID_DEVICE_H_
#include "common/common.h"
#include "hid.h"
#ifdef __cplusplus

66
tinyusb/device/usbd.c Normal file
View File

@ -0,0 +1,66 @@
/**************************************************************************/
/*!
@file usbd.c
@author hathach (tinyusb.org)
@section LICENSE
Software License Agreement (BSD License)
Copyright (c) 2013, hathach (tinyusb.org)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This file is part of the tinyusb stack.
*/
/**************************************************************************/
#include "tusb_option.h"
#if MODE_DEVICE_SUPPORTED
#define _TINY_USB_SOURCE_FILE_
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
#include "tusb.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// IMPLEMENTATION
//--------------------------------------------------------------------+
tusb_error_t usbd_init (void)
{
return TUSB_ERROR_NONE;
}
#endif

86
tinyusb/device/usbd.h Normal file
View File

@ -0,0 +1,86 @@
/**************************************************************************/
/*!
@file usbd.h
@author hathach (tinyusb.org)
@section LICENSE
Software License Agreement (BSD License)
Copyright (c) 2013, hathach (tinyusb.org)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This file is part of the tinyusb stack.
*/
/**************************************************************************/
/** \ingroup TBD
* \defgroup TBD
* \brief TBD
*
* @{
*/
#ifndef _TUSB_USBD_H_
#define _TUSB_USBD_H_
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
#include "osal/osal.h" // TODO refractor move to common.h ?
#include "dcd.h"
#ifdef __cplusplus
extern "C" {
#endif
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// APPLICATION API
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// CLASS-USBD & INTERNAL API
//--------------------------------------------------------------------+
#ifdef _TINY_USB_SOURCE_FILE_
tusb_error_t usbd_init(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* _TUSB_USBD_H_ */
/** @} */

14
tinyusb/host/usbh.c
View File

@ -48,14 +48,6 @@
#include "tusb.h"
#include "usbh_hcd.h"
//TODO temporarily
#if TUSB_CFG_OS == TUSB_OS_NONE && !defined(_TEST_)
void tusb_tick_tock(void)
{
osal_tick_tock();
}
#endif
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
@ -300,7 +292,7 @@ tusb_error_t enumeration_body_subtask(void)
#ifndef _TEST_
// TODO hack delay 20 ms for slow device (use retry on the 1st xfer instead later)
osal_task_delay(20);
osal_task_delay(50);
#endif
//------------- Get first 8 bytes of device descriptor to get Control Endpoint Size -------------//
@ -484,7 +476,7 @@ tusb_error_t enumeration_body_subtask(void)
#endif
//--------------------------------------------------------------------+
// INTERNAL HELPER
@ -512,3 +504,5 @@ static inline uint8_t get_configure_number_for_device(tusb_descriptor_device_t*
return config_num;
}
#endif

10
tinyusb/host/usbh.h
View File

@ -101,16 +101,8 @@ uint8_t tusbh_device_attached_cb (tusb_descriptor_device_t const *p_desc_de
void tusbh_device_mount_succeed_cb (uint8_t dev_addr) ATTR_WEAK;
void tusbh_device_mount_failed_cb(tusb_error_t error, tusb_descriptor_device_t const *p_desc_device) ATTR_WEAK; // TODO refractor remove desc_device
#if TUSB_CFG_OS == TUSB_OS_NONE // TODO move later
//static inline void tusb_tick_tock(void) ATTR_ALWAYS_INLINE;
//static inline void tusb_tick_tock(void)
//{
// osal_tick_tock();
//}
#endif
//--------------------------------------------------------------------+
// CLASS-USBD & INTERNAL API
// CLASS-USBH & INTERNAL API
//--------------------------------------------------------------------+
#ifdef _TINY_USB_SOURCE_FILE_

6
tinyusb/tusb.c
View File

@ -47,8 +47,8 @@ tusb_error_t tusb_init(void)
ASSERT_STATUS( usbh_init() ); // host stack init
#endif
#ifdef TUSB_CFG_DEVICE
ASSERT_STATUS( dcd_init(0) ); // device stack init
#if MODE_DEVICE_SUPPORTED
ASSERT_STATUS ( usbd_init() ); // device stack init
#endif
return TUSB_ERROR_NONE;
@ -61,7 +61,7 @@ void tusb_isr(uint8_t controller_id)
hcd_isr(controller_id);
#endif
#ifdef TUSB_CFG_DEVICE
#if MODE_DEVICE_SUPPORTED
dcd_isr(controller_id);
#endif

23
tinyusb/tusb.h
View File

@ -48,10 +48,14 @@
extern "C" {
#endif
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
#include "common/common.h"
#include "hal/hal.h"
#include "osal/osal.h"
//------------- HOST -------------//
#if MODE_HOST_SUPPORTED
#include "host/usbh.h"
@ -66,27 +70,38 @@
#endif
//------------- DEVICE -------------//
#if MODE_DEVICE_SUPPORTED
#include "device/dcd.h"
#include "device/usbd.h"
#if DEVICE_CLASS_HID
#include "class/hid_device.h"
#endif
#ifdef TUSB_CFG_DEVICE_CDC
#if TUSB_CFG_DEVICE_CDC
#include "class/cdc.h"
#endif
#endif
//--------------------------------------------------------------------+
// APPLICATION API
//--------------------------------------------------------------------+
tusb_error_t tusb_init(void);
// TODO merge with tick_tock
#if TUSB_CFG_OS == TUSB_OS_NONE
void tusb_task_runner(void);
#endif
#if TUSB_CFG_OS == TUSB_OS_NONE && !defined(_TEST_)
static inline void tusb_tick_tock(void) ATTR_ALWAYS_INLINE;
static inline void tusb_tick_tock(void)
{
osal_tick_tock();
}
#endif
#ifdef __cplusplus
}
#endif

4
tinyusb/tusb_option.h
View File

@ -156,7 +156,7 @@
//--------------------------------------------------------------------+
// DEVICE OPTIONS
//--------------------------------------------------------------------+
//#define TUSB_CFG_DEVICE
//#if MODE_DEVICE_SUPPORTED
#define DEVICE_CLASS_HID ( (defined TUSB_CFG_DEVICE_HID_KEYBOARD) || (defined TUSB_CFG_DEVICE_HID_MOUSE) )
@ -183,7 +183,7 @@
#define CDC_NOTIFICATION_EP_MAXPACKETSIZE 8
#define CDC_DATA_EP_MAXPACKET_SIZE 16
//#endif
#ifdef __cplusplus
}