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Merge pull request #454 from me-no-dev/esp32-s2-fifos
ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
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commit
8dda0a0dd1
@ -54,6 +54,9 @@
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// FIFO size in bytes
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#define EP_FIFO_SIZE 1024
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// Max number of IN EP FIFOs
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#define EP_FIFO_NUM 5
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typedef struct {
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uint8_t *buffer;
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uint16_t total_len;
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@ -71,6 +74,15 @@ static uint32_t _setup_packet[2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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static xfer_ctl_t xfer_status[EP_MAX][2];
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// Keep count of how many FIFOs are in use
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static uint8_t _allocated_fifos = 1; //FIFO0 is always in use
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// Will either return an unused FIFO number, or 0 if all are used.
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static uint8_t get_free_fifo(){
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if (_allocated_fifos < EP_FIFO_NUM) return _allocated_fifos++;
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return 0;
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}
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// Setup the control endpoint 0.
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static void bus_reset(void)
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{
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@ -271,8 +283,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
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// - Offset: GRXFSIZ + 16 + Size*(epnum-1)
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// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
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uint8_t fifo_num = get_free_fifo();
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TU_ASSERT(fifo_num != 0);
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in_ep[epnum].diepctl &= ~(USB_D_TXFNUM1_M | USB_D_EPTYPE1_M | USB_DI_SETD0PID1 | USB_D_MPS1_M);
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in_ep[epnum].diepctl |= USB_D_USBACTEP1_M |
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epnum << USB_D_TXFNUM1_S |
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fifo_num << USB_D_TXFNUM1_S |
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desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
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(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
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desc_edpt->wMaxPacketSize.size << 0;
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@ -282,8 +298,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
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// Both TXFD and TXSA are in unit of 32-bit words.
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// IN FIFO 0 was configured during enumeration, hence the "+ 16".
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uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16;
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uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
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uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
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uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_FIFO_NUM-1);
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uint32_t const fifo_offset = allocated_size + fifo_size*(fifo_num-1);
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// DIEPTXF starts at FIFO #1.
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USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset;
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@ -361,7 +377,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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}
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// Flush the FIFO, and wait until we have confirmed it cleared.
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USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S);
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uint8_t const fifo_num = ((in_ep[epnum].diepctl >> USB_D_TXFNUM1_S) & USB_D_TXFNUM1_V);
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USB0.grstctl |= (fifo_num << USB_TXFNUM_S);
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USB0.grstctl |= USB_TXFFLSH_M;
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while ((USB0.grstctl & USB_TXFFLSH_M) != 0) ;
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} else {
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@ -660,6 +677,8 @@ static void _dcd_int_handler(void* arg)
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// start of reset
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ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
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USB0.gintsts = USB_USBRST_M;
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// FIFOs will be reassigned when the endpoints are reopen
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_allocated_fifos = 1;
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bus_reset();
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}
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