mirror of
https://github.com/hathach/tinyusb.git
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used pin generated by rasc
This commit is contained in:
hathach
parent
69dd473a4c
commit
8f2b1bc7b9
@ -1,45 +1,13 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#ifndef _BOARD_CFG_H
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#define _BOARD_CFG_H
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/* generated configuration header file - do not edit */
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#ifndef BOARD_CFG_H_
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#define BOARD_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern "C" {
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#endif
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#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
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#define BOARD_HAS_USB_HIGHSPEED
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#endif
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void bsp_init(void * p_args);
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// for SystemInit()
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void bsp_init(void * p_args);
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#ifdef __cplusplus
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}
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_CFG_H_ */
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@ -31,19 +31,9 @@
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extern "C" {
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#endif
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#define LED1 BSP_IO_PORT_01_PIN_12
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#define LED_STATE_ON 1
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#define SW1 BSP_IO_PORT_04_PIN_15
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#define LED_STATE_ON 1
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#define BUTTON_STATE_ACTIVE 0
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static const ioport_pin_cfg_t board_pin_cfg[] = {
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{ .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT },
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{ .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
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// USB FS
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{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
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};
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#ifdef __cplusplus
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}
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#endif
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@ -1,68 +1,62 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (2)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#define BSP_CFG_PFS_PROTECT ((1))
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifdef __cplusplus
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}
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */
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@ -2,10 +2,10 @@
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA6M1AD3CFP
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (524288)
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#define BSP_RAM_SIZE_BYTES (262144)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (100)
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (524288)
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#define BSP_RAM_SIZE_BYTES (262144)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (100)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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@ -2,83 +2,83 @@
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern "C" {
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#endif
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA6M1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_MCU_GROUP_RA6M1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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/*
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ID Code
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Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
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WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
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*/
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#if defined(BSP_ID_CODE_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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/*
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ID Code
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Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
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WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
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*/
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#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_MCU_FAMILY_CFG_H_ */
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||||
17
hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
17
hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
@ -0,0 +1,17 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_PIN_CFG_H_
|
||||
#define BSP_PIN_CFG_H_
|
||||
#include "r_ioport.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#define LED1 (BSP_IO_PORT_01_PIN_12)
|
||||
#define SW1 (BSP_IO_PORT_04_PIN_15)
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
11
hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c
Normal file
11
hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* generated common source file - do not edit */
|
||||
#include "common_data.h"
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport =
|
||||
{
|
||||
.p_api = &g_ioport_on_ioport,
|
||||
.p_ctrl = &g_ioport_ctrl,
|
||||
.p_cfg = &g_bsp_pin_cfg,
|
||||
};
|
||||
void g_common_init(void) {
|
||||
}
|
||||
20
hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h
Normal file
20
hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* generated common header file - do not edit */
|
||||
#ifndef COMMON_DATA_H_
|
||||
#define COMMON_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "bsp_pin_cfg.h"
|
||||
FSP_HEADER
|
||||
#define IOPORT_CFG_NAME g_bsp_pin_cfg
|
||||
#define IOPORT_CFG_OPEN R_IOPORT_Open
|
||||
#define IOPORT_CFG_CTRL g_ioport_ctrl
|
||||
|
||||
/* IOPORT Instance */
|
||||
extern const ioport_instance_t g_ioport;
|
||||
|
||||
/* IOPORT control structure. */
|
||||
extern ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
void g_common_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* COMMON_DATA_H_ */
|
||||
115
hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c
Normal file
115
hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c
Normal file
@ -0,0 +1,115 @@
|
||||
/* generated pin source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
|
||||
},
|
||||
};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
|
||||
void R_BSP_PinCfgSecurityInit(void);
|
||||
|
||||
/* Initialize SAR registers for secure pins. */
|
||||
void R_BSP_PinCfgSecurityInit(void)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#else
|
||||
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#endif
|
||||
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
|
||||
|
||||
|
||||
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
|
||||
{
|
||||
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
|
||||
uint32_t port = port_pin >> 8U;
|
||||
uint32_t pin = port_pin & 0xFFU;
|
||||
pmsar[port] &= (uint16_t) ~(1U << pin);
|
||||
}
|
||||
|
||||
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
|
||||
#else
|
||||
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
@ -1,7 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="3">
|
||||
<raConfiguration version="9">
|
||||
<generalSettings>
|
||||
<option key="#pinconfiguration#" value="R7FA6M1AD3CFP.pincfg"/>
|
||||
<option key="#Board#" value="board.ra6m1ek"/>
|
||||
<option key="CPU" value="RA6M1"/>
|
||||
<option key="Core" value="CM4"/>
|
||||
@ -9,9 +8,10 @@
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m4"/>
|
||||
<option key="#DeviceCommand#" value="R7FA6M1AD"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA6M1AD3CFP.pincfg"/>
|
||||
<option key="#FSPVersion#" value="5.6.0"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m1_ek##"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra6m1.R7FA6M1AD3CFP">
|
||||
@ -87,8 +87,8 @@
|
||||
<property id="config.bsp.common.id_fixed" value=""/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x400"/>
|
||||
<property id="config.bsp.common.heap" value="0"/>
|
||||
<property id="config.bsp.common.main" value="0x1000"/>
|
||||
<property id="config.bsp.common.heap" value="0x1000"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
@ -175,125 +175,96 @@
|
||||
<originalPack>Renesas.RA_mcu_ra6m1.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raMessagingConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<pincfg active="true" name="RA6M1-EK.pincfg" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
|
||||
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
|
||||
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
|
||||
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
|
||||
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
|
||||
<configSetting altId="system0.vss.vss" configurationId="system0.vss"/>
|
||||
<configSetting altId="system0.vcc.vcc" configurationId="system0.vcc"/>
|
||||
<configSetting altId="vcl0.vcl0" configurationId="vcl0"/>
|
||||
<configSetting altId="vssusb.vssusb" configurationId="vssusb"/>
|
||||
<configSetting altId="cgc0.xcout.xcout" configurationId="cgc0.xcout"/>
|
||||
<configSetting altId="vccusb.vccusb" configurationId="vccusb"/>
|
||||
<configSetting altId="vrefl.vrefl" configurationId="vrefl"/>
|
||||
<configSetting altId="system0.vcl.vcl" configurationId="system0.vcl"/>
|
||||
<configSetting altId="vrefh.vrefh" configurationId="vrefh"/>
|
||||
<configSetting altId="res.system0.res" configurationId="res"/>
|
||||
<configSetting altId="analog0.vrefl0.vrefl0" configurationId="analog0.vrefl0"/>
|
||||
<configSetting altId="system0.vbatt.vbatt" configurationId="system0.vbatt"/>
|
||||
<configSetting altId="usbdm.usbfs0.usbdm" configurationId="usbdm"/>
|
||||
<configSetting altId="vrefl0.vrefl0" configurationId="vrefl0"/>
|
||||
<configSetting altId="vrefh0.vrefh0" configurationId="vrefh0"/>
|
||||
<configSetting altId="usbdp.usbfs0.usbdp" configurationId="usbdp"/>
|
||||
<configSetting altId="analog0.vrefh0.vrefh0" configurationId="analog0.vrefh0"/>
|
||||
<configSetting altId="analog0.vrefh.vrefh" configurationId="analog0.vrefh"/>
|
||||
<configSetting altId="analog0.vrefl.vrefl" configurationId="analog0.vrefl"/>
|
||||
<configSetting altId="xcout.cgc0.xcout" configurationId="xcout"/>
|
||||
<configSetting altId="cgc0.xcin.xcin" configurationId="cgc0.xcin"/>
|
||||
<configSetting altId="usbfs0.dm.usbdm" configurationId="usbfs0.dm"/>
|
||||
<configSetting altId="usbfs0.vcc.vccusb" configurationId="usbfs0.vcc"/>
|
||||
<configSetting altId="usbfs0.vss.vssusb" configurationId="usbfs0.vss"/>
|
||||
<configSetting altId="usbfs0.dp.usbdp" configurationId="usbfs0.dp"/>
|
||||
<configSetting altId="analog0.avcc0.avcc0" configurationId="analog0.avcc0"/>
|
||||
<configSetting altId="analog0.avss0.avss0" configurationId="analog0.avss0"/>
|
||||
<configSetting altId="vss.vss" configurationId="vss"/>
|
||||
<configSetting altId="vcc.vcc" configurationId="vcc"/>
|
||||
<configSetting altId="vbatt.system0.vbatt" configurationId="vbatt"/>
|
||||
<configSetting altId="system0.res.res" configurationId="system0.res"/>
|
||||
<configSetting altId="vcl.vcl" configurationId="vcl"/>
|
||||
<configSetting altId="xcin.cgc0.xcin" configurationId="xcin"/>
|
||||
<configSetting altId="system0.vcl0.vcl0" configurationId="system0.vcl0"/>
|
||||
<configSetting altId="avcc0.avcc0" configurationId="avcc0"/>
|
||||
<configSetting altId="avss0.avss0" configurationId="avss0"/>
|
||||
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
|
||||
<configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
|
||||
<symbolicName propertyId="p112.symbolic_name" value="LED1"/>
|
||||
<symbolicName propertyId="p415.symbolic_name" value="SW1"/>
|
||||
<pincfg active="true" name="RA6M1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="adc1.an00.p004" configurationId="adc1.an00"/>
|
||||
<configSetting altId="adc1.mode.custom" configurationId="adc1.mode"/>
|
||||
<configSetting altId="sci8.rxd.p104" configurationId="sci8.rxd"/>
|
||||
<configSetting altId="p105.sci8.txd" configurationId="p105"/>
|
||||
<configSetting altId="p104.sci8.rxd" configurationId="p104"/>
|
||||
<configSetting altId="sci8.txd.p105" configurationId="sci8.txd"/>
|
||||
<configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
|
||||
<configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
|
||||
<configSetting altId="ctsu0.ts02.p207" configurationId="ctsu0.ts02"/>
|
||||
<configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/>
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p004.asel" configurationId="p004"/>
|
||||
<configSetting altId="sci8.mode.asynchronous.free" configurationId="sci8.mode"/>
|
||||
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
|
||||
<configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/>
|
||||
<configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/>
|
||||
<configSetting altId="p102.spi0.rspck" configurationId="p102"/>
|
||||
<configSetting altId="p101.spi0.mosi" configurationId="p101"/>
|
||||
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
|
||||
<configSetting altId="p100.spi0.miso" configurationId="p100"/>
|
||||
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
|
||||
<configSetting altId="p101.spi0.mosi" configurationId="p101"/>
|
||||
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
|
||||
<configSetting altId="p102.spi0.rspck" configurationId="p102"/>
|
||||
<configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
|
||||
<configSetting altId="p103.spi0.ssl0" configurationId="p103"/>
|
||||
<configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
|
||||
<configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/>
|
||||
<configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/>
|
||||
<configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
|
||||
<configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
|
||||
<configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
|
||||
<configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/>
|
||||
<configSetting altId="ctsu0.tscap.p205" configurationId="ctsu0.tscap"/>
|
||||
<configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
|
||||
<configSetting altId="ctsu0.ts02.p207" configurationId="ctsu0.ts02"/>
|
||||
<configSetting altId="p205.ctsu0.tscap" configurationId="p205"/>
|
||||
<configSetting altId="p207.ctsu0.ts02" configurationId="p207"/>
|
||||
<configSetting altId="p112.gpio_mode.gpio_mode_out.low" configurationId="p112.gpio_mode"/>
|
||||
<configSetting altId="p112.output.low" configurationId="p112"/>
|
||||
<configSetting altId="p104.sci8.rxd" configurationId="p104"/>
|
||||
<configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
|
||||
<configSetting altId="p105.sci8.txd" configurationId="p105"/>
|
||||
<configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
|
||||
<configSetting altId="p106.output.low" configurationId="p106"/>
|
||||
<configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
|
||||
<configSetting altId="p107.output.low" configurationId="p107"/>
|
||||
<configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
|
||||
<configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
|
||||
<configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/>
|
||||
<configSetting altId="p201.input" configurationId="p201"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R7FA6M1AD3CFP.pincfg" symbol="">
|
||||
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
|
||||
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
|
||||
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
|
||||
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
|
||||
<configSetting altId="p112.output.low" configurationId="p112"/>
|
||||
<configSetting altId="p112.gpio_mode.gpio_mode_out.low" configurationId="p112.gpio_mode"/>
|
||||
<configSetting altId="p201.input" configurationId="p201"/>
|
||||
<configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/>
|
||||
<configSetting altId="p205.ctsu0.tscap" configurationId="p205"/>
|
||||
<configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
|
||||
<configSetting altId="p207.ctsu0.ts02" configurationId="p207"/>
|
||||
<configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
|
||||
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="p415.input" configurationId="p415"/>
|
||||
<configSetting altId="p415.gpio_mode.gpio_mode_in" configurationId="p415.gpio_mode"/>
|
||||
<configSetting altId="p415.gpio_pupd.gpio_pupd_ip_up" configurationId="p415.gpio_pupd"/>
|
||||
<configSetting altId="sci8.mode.asynchronous.free" configurationId="sci8.mode"/>
|
||||
<configSetting altId="sci8.rxd.p104" configurationId="sci8.rxd"/>
|
||||
<configSetting altId="sci8.txd.p105" configurationId="sci8.txd"/>
|
||||
<configSetting altId="spi0.miso.p100" configurationId="spi0.miso"/>
|
||||
<configSetting altId="spi0.mode.enabled.a" configurationId="spi0.mode"/>
|
||||
<configSetting altId="spi0.mosi.p101" configurationId="spi0.mosi"/>
|
||||
<configSetting altId="spi0.rspck.p102" configurationId="spi0.rspck"/>
|
||||
<configSetting altId="spi0.ssl0.p103" configurationId="spi0.ssl0"/>
|
||||
<configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R7FA6M1AD3CFP.pincfg" selected="false" symbol="">
|
||||
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
|
||||
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
|
||||
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
|
||||
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
|
||||
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
|
||||
@ -31,35 +31,9 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 BSP_IO_PORT_00_PIN_08
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 BSP_IO_PORT_00_PIN_05
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
static const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{ .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
|
||||
{ .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
|
||||
|
||||
// USB FS
|
||||
{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
|
||||
{ .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
|
||||
{ .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
|
||||
|
||||
// USB HS
|
||||
{ .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
|
||||
{ .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
|
||||
{ .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
|
||||
|
||||
// ETM Trace
|
||||
#ifdef TRACE_ETM
|
||||
{ .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@ -2,62 +2,61 @@
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
#include "board_cfg.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
#include "board_cfg.h"
|
||||
#define RA_NOT_DEFINED 0
|
||||
#ifndef BSP_CFG_RTOS
|
||||
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
#define BSP_CFG_RTOS (2)
|
||||
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
#define BSP_CFG_RTOS (1)
|
||||
#else
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef BSP_CFG_RTC_USED
|
||||
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
|
||||
#define BSP_CFG_HEAP_BYTES (0x1000)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
|
||||
#define RA_NOT_DEFINED 0
|
||||
#ifndef BSP_CFG_RTOS
|
||||
#if (RA_NOT_DEFINED) != (2)
|
||||
#define BSP_CFG_RTOS (2)
|
||||
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
#define BSP_CFG_RTOS (1)
|
||||
#else
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef BSP_CFG_RTC_USED
|
||||
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
|
||||
#define BSP_CFG_HEAP_BYTES (0x1000)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_CFG_H_ */
|
||||
|
||||
@ -2,10 +2,10 @@
|
||||
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_R7FA6M5BH3CFC
|
||||
#define BSP_MCU_FEATURE_SET ('B')
|
||||
#define BSP_ROM_SIZE_BYTES (2097152)
|
||||
#define BSP_RAM_SIZE_BYTES (524288)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (176)
|
||||
#define BSP_MCU_FEATURE_SET ('B')
|
||||
#define BSP_ROM_SIZE_BYTES (2097152)
|
||||
#define BSP_RAM_SIZE_BYTES (524288)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (176)
|
||||
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
|
||||
|
||||
99
hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
99
hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
@ -0,0 +1,99 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_PIN_CFG_H_
|
||||
#define BSP_PIN_CFG_H_
|
||||
#include "r_ioport.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#define MIKROBUS_AN_ARDUINO_A0 (BSP_IO_PORT_00_PIN_00)
|
||||
#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01)
|
||||
#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_02)
|
||||
#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_03)
|
||||
#define SW2 (BSP_IO_PORT_00_PIN_04)
|
||||
#define SW1 (BSP_IO_PORT_00_PIN_05)
|
||||
#define LED1 (BSP_IO_PORT_00_PIN_06)
|
||||
#define LED2 (BSP_IO_PORT_00_PIN_07)
|
||||
#define LED3 (BSP_IO_PORT_00_PIN_08)
|
||||
#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
|
||||
#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
|
||||
#define OSPI_CLK (BSP_IO_PORT_01_PIN_00)
|
||||
#define OSPI_SIO7 (BSP_IO_PORT_01_PIN_01)
|
||||
#define OSPI_SIO1 (BSP_IO_PORT_01_PIN_02)
|
||||
#define OSPI_SIO6 (BSP_IO_PORT_01_PIN_03)
|
||||
#define OSPI_DQS (BSP_IO_PORT_01_PIN_04)
|
||||
#define OSPI_SIO5 (BSP_IO_PORT_01_PIN_05)
|
||||
#define OSPI_SIO0 (BSP_IO_PORT_01_PIN_06)
|
||||
#define OSPI_SIO3 (BSP_IO_PORT_01_PIN_07)
|
||||
#define MIKROBUS_PWM_ARDUINO_D3_PWM (BSP_IO_PORT_01_PIN_11)
|
||||
#define ARDUINO_D4 (BSP_IO_PORT_01_PIN_12)
|
||||
#define ARDUINO_D5 (BSP_IO_PORT_01_PIN_13)
|
||||
#define ARDUINO_D6 (BSP_IO_PORT_01_PIN_14)
|
||||
#define ARDUINO_D9 (BSP_IO_PORT_01_PIN_15)
|
||||
#define MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02)
|
||||
#define MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03)
|
||||
#define MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK (BSP_IO_PORT_02_PIN_04)
|
||||
#define MIKROBUS_SS_ARDUINO_SS (BSP_IO_PORT_02_PIN_05)
|
||||
#define PMOD1_SS (BSP_IO_PORT_02_PIN_06)
|
||||
#define ARDUINO_D8 (BSP_IO_PORT_02_PIN_07)
|
||||
#define PMOD1_SS2 (BSP_IO_PORT_03_PIN_01)
|
||||
#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02)
|
||||
#define MIKROBUS_RESET_ARDUINO_RESET (BSP_IO_PORT_03_PIN_03)
|
||||
#define QSPI_CLK (BSP_IO_PORT_03_PIN_05)
|
||||
#define QSPI_CS (BSP_IO_PORT_03_PIN_06)
|
||||
#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07)
|
||||
#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08)
|
||||
#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09)
|
||||
#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10)
|
||||
#define PMOD1_RST (BSP_IO_PORT_03_PIN_11)
|
||||
#define PMOD2_INT (BSP_IO_PORT_04_PIN_00)
|
||||
#define ETH_MDC (BSP_IO_PORT_04_PIN_01)
|
||||
#define ETH_MDIO (BSP_IO_PORT_04_PIN_02)
|
||||
#define ETH_RST (BSP_IO_PORT_04_PIN_03)
|
||||
#define PMOD2_RST (BSP_IO_PORT_04_PIN_04)
|
||||
#define ETH_TXEN (BSP_IO_PORT_04_PIN_05)
|
||||
#define ETH_TXD1 (BSP_IO_PORT_04_PIN_06)
|
||||
#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
|
||||
#define PMOD2_SS2 (BSP_IO_PORT_04_PIN_08)
|
||||
#define MIKROBUS_INT_ARDUINO_INT0 (BSP_IO_PORT_04_PIN_09)
|
||||
#define PMOD2_MISO (BSP_IO_PORT_04_PIN_10)
|
||||
#define PMOD2_MOSI (BSP_IO_PORT_04_PIN_11)
|
||||
#define PMOD2_SCK (BSP_IO_PORT_04_PIN_12)
|
||||
#define PMOS2_SS (BSP_IO_PORT_04_PIN_13)
|
||||
#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_04_PIN_14)
|
||||
#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_04_PIN_15)
|
||||
#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
|
||||
#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
|
||||
#define GROVE2_SCL (BSP_IO_PORT_05_PIN_05)
|
||||
#define GROVE2_SDA (BSP_IO_PORT_05_PIN_06)
|
||||
#define MIKROBUS_SDA_ARDUINO_SDA (BSP_IO_PORT_05_PIN_11)
|
||||
#define MIKROBUS_SCL_ARDUINO_SCL (BSP_IO_PORT_05_PIN_12)
|
||||
#define OSPI_SIO4 (BSP_IO_PORT_06_PIN_00)
|
||||
#define OSPI_SIO2 (BSP_IO_PORT_06_PIN_01)
|
||||
#define OSPI_CS1 (BSP_IO_PORT_06_PIN_02)
|
||||
#define ARDUINO_D7 (BSP_IO_PORT_06_PIN_08)
|
||||
#define CAN_TXD (BSP_IO_PORT_06_PIN_09)
|
||||
#define CAN_RDX (BSP_IO_PORT_06_PIN_10)
|
||||
#define CAN_STBY (BSP_IO_PORT_06_PIN_11)
|
||||
#define MIKROBUS_TX_ARDUINO_TX (BSP_IO_PORT_06_PIN_13)
|
||||
#define MIKROBUS_RX_ARDUINO_RX (BSP_IO_PORT_06_PIN_14)
|
||||
#define OSPI_RST (BSP_IO_PORT_06_PIN_15)
|
||||
#define ETH_TXD0 (BSP_IO_PORT_07_PIN_00)
|
||||
#define ETH_50REF (BSP_IO_PORT_07_PIN_01)
|
||||
#define ETH_RXD0 (BSP_IO_PORT_07_PIN_02)
|
||||
#define ETH_RXD1 (BSP_IO_PORT_07_PIN_03)
|
||||
#define ETH_RXERR (BSP_IO_PORT_07_PIN_04)
|
||||
#define ETH_CRSDV (BSP_IO_PORT_07_PIN_05)
|
||||
#define ETH_INT (BSP_IO_PORT_07_PIN_06)
|
||||
#define USBHS_OVERCURA (BSP_IO_PORT_07_PIN_07)
|
||||
#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_08)
|
||||
#define PMOD1_INT (BSP_IO_PORT_09_PIN_05)
|
||||
#define USBHS_VBUS_EN (BSP_IO_PORT_11_PIN_00)
|
||||
#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M5 EK */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
11
hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c
Normal file
11
hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* generated common source file - do not edit */
|
||||
#include "common_data.h"
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport =
|
||||
{
|
||||
.p_api = &g_ioport_on_ioport,
|
||||
.p_ctrl = &g_ioport_ctrl,
|
||||
.p_cfg = &g_bsp_pin_cfg,
|
||||
};
|
||||
void g_common_init(void) {
|
||||
}
|
||||
20
hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h
Normal file
20
hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* generated common header file - do not edit */
|
||||
#ifndef COMMON_DATA_H_
|
||||
#define COMMON_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "bsp_pin_cfg.h"
|
||||
FSP_HEADER
|
||||
#define IOPORT_CFG_NAME g_bsp_pin_cfg
|
||||
#define IOPORT_CFG_OPEN R_IOPORT_Open
|
||||
#define IOPORT_CFG_CTRL g_ioport_ctrl
|
||||
|
||||
/* IOPORT Instance */
|
||||
extern const ioport_instance_t g_ioport;
|
||||
|
||||
/* IOPORT control structure. */
|
||||
extern ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
void g_common_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* COMMON_DATA_H_ */
|
||||
411
hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c
Normal file
411
hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c
Normal file
@ -0,0 +1,411 @@
|
||||
/* generated pin source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_13,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_13,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_13,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_09_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_11_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_11_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
|
||||
},
|
||||
};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
|
||||
void R_BSP_PinCfgSecurityInit(void);
|
||||
|
||||
/* Initialize SAR registers for secure pins. */
|
||||
void R_BSP_PinCfgSecurityInit(void)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#else
|
||||
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#endif
|
||||
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
|
||||
|
||||
|
||||
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
|
||||
{
|
||||
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
|
||||
uint32_t port = port_pin >> 8U;
|
||||
uint32_t pin = port_pin & 0xFFU;
|
||||
pmsar[port] &= (uint16_t) ~(1U << pin);
|
||||
}
|
||||
|
||||
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
|
||||
#else
|
||||
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
@ -1,7 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="3">
|
||||
<raConfiguration version="9">
|
||||
<generalSettings>
|
||||
<option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/>
|
||||
<option key="#Board#" value="board.ra6m5ek"/>
|
||||
<option key="CPU" value="RA6M5"/>
|
||||
<option key="Core" value="CM33"/>
|
||||
@ -9,9 +8,10 @@
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
|
||||
<option key="#DeviceCommand#" value="R7FA6M5BH"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/>
|
||||
<option key="#FSPVersion#" value="5.6.0"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra6m5_ek##"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra6m5.R7FA6M5BH3CFC">
|
||||
@ -63,12 +63,12 @@
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
|
||||
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
|
||||
<property id="config.bsp.fsp.BPS.BPS0" value="0U"/>
|
||||
<property id="config.bsp.fsp.BPS.BPS1" value="0U"/>
|
||||
<property id="config.bsp.fsp.BPS.BPS2" value="0U"/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS0" value="0U"/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS1" value="0U"/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS2" value="0U"/>
|
||||
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
|
||||
<property id="config.bsp.fsp.BPS.BPS1" value=""/>
|
||||
<property id="config.bsp.fsp.BPS.BPS2" value=""/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
|
||||
<property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
|
||||
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||
@ -93,8 +93,8 @@
|
||||
<property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x400"/>
|
||||
<property id="config.bsp.common.heap" value="0"/>
|
||||
<property id="config.bsp.common.main" value="0x1000"/>
|
||||
<property id="config.bsp.common.heap" value="0x1000"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
@ -198,15 +198,23 @@
|
||||
<originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raMessagingConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<symbolicName propertyId="p000.symbolic_name" value="MIKROBUS_AN_ARDUINO_A0"/>
|
||||
@ -427,10 +435,20 @@
|
||||
<configSetting altId="p207.output.low" configurationId="p207"/>
|
||||
<configSetting altId="p207.gpio_speed.gpio_speed_high" configurationId="p207.gpio_drivecapacity"/>
|
||||
<configSetting altId="p207.gpio_mode.gpio_mode_out.low" configurationId="p207.gpio_mode"/>
|
||||
<configSetting altId="p208.trace0.tdata3" configurationId="p208"/>
|
||||
<configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/>
|
||||
<configSetting altId="p209.trace0.tdata2" configurationId="p209"/>
|
||||
<configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
|
||||
<configSetting altId="p210.trace0.tdata1" configurationId="p210"/>
|
||||
<configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
|
||||
<configSetting altId="p211.trace0.tdata0" configurationId="p211"/>
|
||||
<configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
|
||||
<configSetting altId="p212.cgc0.extal" configurationId="p212"/>
|
||||
<configSetting altId="p212.gpio_mode.gpio_mode_peripheral" configurationId="p212.gpio_mode"/>
|
||||
<configSetting altId="p213.cgc0.xtal" configurationId="p213"/>
|
||||
<configSetting altId="p213.gpio_mode.gpio_mode_peripheral" configurationId="p213.gpio_mode"/>
|
||||
<configSetting altId="p214.trace0.tclk" configurationId="p214"/>
|
||||
<configSetting altId="p214.gpio_mode.gpio_mode_peripheral" configurationId="p214.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p301.spi0.ssl2" configurationId="p301"/>
|
||||
@ -540,25 +558,20 @@
|
||||
<configSetting altId="p601.gpio_speed.gpio_speed_highspeedhigh" configurationId="p601.gpio_drivecapacity"/>
|
||||
<configSetting altId="p601.gpio_mode.gpio_mode_peripheral" configurationId="p601.gpio_mode"/>
|
||||
<configSetting altId="p602.ospi0.omcs1" configurationId="p602"/>
|
||||
<configSetting altId="p602.gpio_speed.gpio_speed_highspeedhigh" configurationId="p602.gpio_drivecapacity"/>
|
||||
<configSetting altId="p602.gpio_mode.gpio_mode_peripheral" configurationId="p602.gpio_mode"/>
|
||||
<configSetting altId="p608.output.low" configurationId="p608"/>
|
||||
<configSetting altId="p608.gpio_speed.gpio_speed_high" configurationId="p608.gpio_drivecapacity"/>
|
||||
<configSetting altId="p608.gpio_mode.gpio_mode_out.low" configurationId="p608.gpio_mode"/>
|
||||
<configSetting altId="p609.can1.ctx" configurationId="p609"/>
|
||||
<configSetting altId="p609.gpio_speed.gpio_speed_highspeedhigh" configurationId="p609.gpio_drivecapacity"/>
|
||||
<configSetting altId="p609.gpio_mode.gpio_mode_peripheral" configurationId="p609.gpio_mode"/>
|
||||
<configSetting altId="p610.can1.crx" configurationId="p610"/>
|
||||
<configSetting altId="p610.gpio_speed.gpio_speed_highspeedhigh" configurationId="p610.gpio_drivecapacity"/>
|
||||
<configSetting altId="p610.gpio_mode.gpio_mode_peripheral" configurationId="p610.gpio_mode"/>
|
||||
<configSetting altId="p611.output.low" configurationId="p611"/>
|
||||
<configSetting altId="p611.gpio_speed.gpio_speed_high" configurationId="p611.gpio_drivecapacity"/>
|
||||
<configSetting altId="p611.gpio_mode.gpio_mode_out.low" configurationId="p611.gpio_mode"/>
|
||||
<configSetting altId="p613.sci7.txd" configurationId="p613"/>
|
||||
<configSetting altId="p613.gpio_speed.gpio_speed_highspeedhigh" configurationId="p613.gpio_drivecapacity"/>
|
||||
<configSetting altId="p613.gpio_mode.gpio_mode_peripheral" configurationId="p613.gpio_mode"/>
|
||||
<configSetting altId="p614.sci7.rxd" configurationId="p614"/>
|
||||
<configSetting altId="p614.gpio_speed.gpio_speed_highspeedhigh" configurationId="p614.gpio_drivecapacity"/>
|
||||
<configSetting altId="p614.gpio_mode.gpio_mode_peripheral" configurationId="p614.gpio_mode"/>
|
||||
<configSetting altId="p615.output.high" configurationId="p615"/>
|
||||
<configSetting altId="p615.gpio_speed.gpio_speed_medium" configurationId="p615.gpio_drivecapacity"/>
|
||||
@ -629,6 +642,12 @@
|
||||
<configSetting altId="spi1.rspck.p412" configurationId="spi1.rspck"/>
|
||||
<configSetting altId="spi1.ssl0.p413" configurationId="spi1.ssl0"/>
|
||||
<configSetting altId="spi1.ssl3.p708" configurationId="spi1.ssl3"/>
|
||||
<configSetting altId="trace0.mode.trace4bit" configurationId="trace0.mode"/>
|
||||
<configSetting altId="trace0.tclk.p214" configurationId="trace0.tclk"/>
|
||||
<configSetting altId="trace0.tdata0.p211" configurationId="trace0.tdata0"/>
|
||||
<configSetting altId="trace0.tdata1.p210" configurationId="trace0.tdata1"/>
|
||||
<configSetting altId="trace0.tdata2.p209" configurationId="trace0.tdata2"/>
|
||||
<configSetting altId="trace0.tdata3.p208" configurationId="trace0.tdata3"/>
|
||||
<configSetting altId="usbfs0.mode.custom" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.ovrcura.p501" configurationId="usbfs0.ovrcura"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
@ -638,14 +657,14 @@
|
||||
<configSetting altId="usbhs0.vbus.pb01" configurationId="usbhs0.vbus"/>
|
||||
<configSetting altId="usbhs0.vbusen.pb00" configurationId="usbhs0.vbusen"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R7FA6M5BH3CFC.pincfg" symbol="">
|
||||
<pincfg active="false" name="R7FA6M5BH3CFC.pincfg" selected="false" symbol="">
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
|
||||
@ -31,20 +31,8 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 BSP_IO_PORT_01_PIN_11 // D13
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 BSP_IO_PORT_01_PIN_10 // D12
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
static const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
|
||||
{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
|
||||
// USB FS D+, D-, VBus
|
||||
{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
};
|
||||
#define LED_STATE_ON 1
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
17
hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
17
hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
@ -0,0 +1,17 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_PIN_CFG_H_
|
||||
#define BSP_PIN_CFG_H_
|
||||
#include "r_ioport.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#define SW1 (BSP_IO_PORT_01_PIN_10) /* active low */
|
||||
#define LED1 (BSP_IO_PORT_01_PIN_11) /* active high */
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CNE.pincfg */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
11
hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c
Normal file
11
hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* generated common source file - do not edit */
|
||||
#include "common_data.h"
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport =
|
||||
{
|
||||
.p_api = &g_ioport_on_ioport,
|
||||
.p_ctrl = &g_ioport_ctrl,
|
||||
.p_cfg = &g_bsp_pin_cfg,
|
||||
};
|
||||
void g_common_init(void) {
|
||||
}
|
||||
20
hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h
Normal file
20
hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* generated common header file - do not edit */
|
||||
#ifndef COMMON_DATA_H_
|
||||
#define COMMON_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "bsp_pin_cfg.h"
|
||||
FSP_HEADER
|
||||
#define IOPORT_CFG_NAME g_bsp_pin_cfg
|
||||
#define IOPORT_CFG_OPEN R_IOPORT_Open
|
||||
#define IOPORT_CFG_CTRL g_ioport_ctrl
|
||||
|
||||
/* IOPORT Instance */
|
||||
extern const ioport_instance_t g_ioport;
|
||||
|
||||
/* IOPORT control structure. */
|
||||
extern ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
void g_common_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* COMMON_DATA_H_ */
|
||||
75
hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c
Normal file
75
hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c
Normal file
@ -0,0 +1,75 @@
|
||||
/* generated pin source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_09_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_09_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
|
||||
void R_BSP_PinCfgSecurityInit(void);
|
||||
|
||||
/* Initialize SAR registers for secure pins. */
|
||||
void R_BSP_PinCfgSecurityInit(void)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#else
|
||||
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#endif
|
||||
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
|
||||
|
||||
|
||||
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
|
||||
{
|
||||
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
|
||||
uint32_t port = port_pin >> 8U;
|
||||
uint32_t pin = port_pin & 0xFFU;
|
||||
pmsar[port] &= (uint16_t) ~(1U << pin);
|
||||
}
|
||||
|
||||
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
|
||||
#else
|
||||
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
@ -186,20 +186,33 @@
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<symbolicName propertyId="p110.symbolic_name" value="SW1"/>
|
||||
<symbolicName propertyId="p111.symbolic_name" value="LED1"/>
|
||||
<comment propertyId="p110.comment" value="active low"/>
|
||||
<comment propertyId="p111.comment" value="active high"/>
|
||||
<pincfg active="true" name="R7FA4M1AB3CNE.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
|
||||
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
|
||||
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
|
||||
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
|
||||
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
|
||||
<configSetting altId="p110.input" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_in" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p110.gpio_pupd.gpio_pupd_ip_up" configurationId="p110.gpio_pupd"/>
|
||||
<configSetting altId="p111.output.low" configurationId="p111"/>
|
||||
<configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="p914.usbfs0.usbdp" configurationId="p914"/>
|
||||
<configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
|
||||
<configSetting altId="p915.usbfs0.usbdm" configurationId="p915"/>
|
||||
<configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
|
||||
<configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.usbdm.p915" configurationId="usbfs0.usbdm"/>
|
||||
<configSetting altId="usbfs0.usbdp.p914" configurationId="usbfs0.usbdp"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
|
||||
@ -30,13 +30,12 @@
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#pragma GCC diagnostic ignored "-Wundef"
|
||||
|
||||
// extra push due to https://github.com/renesas/fsp/pull/278
|
||||
#pragma GCC diagnostic push
|
||||
#endif
|
||||
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
//#include "bsp_api.h"
|
||||
//#include "r_ioport.h"
|
||||
#include "common_data.h"
|
||||
|
||||
#include "r_ioport_api.h"
|
||||
#include "renesas.h"
|
||||
|
||||
@ -50,11 +49,11 @@
|
||||
/* Key code for writing PRCR register. */
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
|
||||
static const ioport_cfg_t family_pin_cfg = {
|
||||
.number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = board_pin_cfg,
|
||||
};
|
||||
static ioport_instance_ctrl_t port_ctrl;
|
||||
// static const ioport_cfg_t family_pin_cfg = {
|
||||
// .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
|
||||
// .p_pin_cfg_data = board_pin_cfg,
|
||||
// };
|
||||
// static ioport_instance_ctrl_t port_ctrl;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Vector Data
|
||||
@ -103,7 +102,7 @@ void board_init(void) {
|
||||
__enable_irq();
|
||||
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
|
||||
R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME);
|
||||
|
||||
#ifdef TRACE_ETM
|
||||
// TRCKCR is protected by PRCR bit0 register
|
||||
@ -138,12 +137,12 @@ void board_init_after_tusb(void) {
|
||||
}
|
||||
|
||||
void board_led_write(bool state) {
|
||||
R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
|
||||
R_IOPORT_PinWrite(&IOPORT_CFG_CTRL, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void) {
|
||||
bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE;
|
||||
R_IOPORT_PinRead(&port_ctrl, SW1, &lvl);
|
||||
R_IOPORT_PinRead(&IOPORT_CFG_CTRL, SW1, &lvl);
|
||||
return lvl == BUTTON_STATE_ACTIVE;
|
||||
}
|
||||
|
||||
|
||||
@ -36,6 +36,8 @@ function(add_board_target BOARD_TARGET)
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_security.c
|
||||
${FSP_RA}/src/r_ioport/r_ioport.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/common_data.c
|
||||
)
|
||||
|
||||
target_compile_options(${BOARD_TARGET} PUBLIC
|
||||
@ -60,14 +62,12 @@ function(add_board_target BOARD_TARGET)
|
||||
|
||||
if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script/fsp.ld)
|
||||
#set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld)
|
||||
endif ()
|
||||
|
||||
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
# linker file
|
||||
"LINKER:--script=${LD_FILE_GNU}"
|
||||
#-L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc
|
||||
-L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script
|
||||
-Wl,--defsym=end=__bss_end__
|
||||
-nostartfiles
|
||||
|
||||
@ -6,6 +6,10 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
|
||||
#define BOARD_HAS_USB_HIGHSPEED
|
||||
#endif
|
||||
|
||||
/* ISR prototypes */
|
||||
void usbfs_interrupt_handler(void);
|
||||
void usbfs_resume_handler(void);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user