mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
- minor update to ep_set_response_and_toggle/xfer_data_packet
- merge USBHS_ISO_ACT_FLAG, USBHS_TRANSFER_FLAG handler since they are similar - improve uart output - add note for link speed in bus reset
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@ -28,7 +28,7 @@
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#include <ch32v30x.h>
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#define UART_RINGBUFFER_SIZE_TX 64
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#define UART_RINGBUFFER_SIZE_TX 128
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#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
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static char tx_buf[UART_RINGBUFFER_SIZE_TX];
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@ -72,7 +72,7 @@ void board_init(void) {
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SysTick_Config(SystemCoreClock / 1000);
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#endif
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usart_printf_init(115200);
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usart_printf_init(CFG_BOARD_UART_BAUDRATE);
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#if CFG_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED
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// Use Highspeed USB
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@ -150,10 +150,11 @@ int board_uart_read(uint8_t* buf, int len) {
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int board_uart_write(void const* buf, int len) {
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int txsize = len;
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const char* bufc = (const char*) buf;
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while (txsize--) {
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uart_write(*(uint8_t const*) buf);
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buf++;
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uart_write(*bufc++);
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}
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uart_sync();
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return len;
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}
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@ -74,7 +74,10 @@
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// USB SPEED TYPE
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#define USBHS_SPEED_TYPE_OFFSET 0x08
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#define USBSPEED_MASK (0x03)
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#define USBHS_SPEED_TYPE_MASK 0x03
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#define USBHS_SPEED_TYPE_FULL 0
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#define USBHS_SPEED_TYPE_HIGH 1
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#define USBHS_SPEED_TYPE_LOW 2
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// USB_MIS_ST
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#define USBHS_MIS_ST_OFFSET 0x09
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@ -64,9 +64,8 @@ static xfer_ctl_t xfer_status[EP_MAX][2];
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/* Endpoint Buffer */
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TU_ATTR_ALIGNED(4) static uint8_t ep0_buffer[CFG_TUD_ENDPOINT0_SIZE];
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static void ep_set_response_and_toggle(uint8_t ep_addr, ep_response_list_t response_type) {
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uint8_t const ep_num = tu_edpt_number(ep_addr);
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if (ep_addr & TUSB_DIR_IN_MASK) {
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static void ep_set_response_and_toggle(uint8_t ep_num, tusb_dir_t ep_dir, ep_response_list_t response_type) {
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if (ep_dir == TUSB_DIR_IN) {
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uint8_t response = (response_type == EP_RESPONSE_ACK) ? USBHS_EP_T_RES_ACK : USBHS_EP_T_RES_NAK;
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if (ep_num == 0) {
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if (response_type == EP_RESPONSE_ACK) {
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@ -97,11 +96,8 @@ static void ep_set_response_and_toggle(uint8_t ep_addr, ep_response_list_t respo
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}
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}
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static void xfer_data_packet(uint8_t ep_addr, xfer_ctl_t* xfer) {
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uint8_t const ep_num = tu_edpt_number(ep_addr);
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tusb_dir_t const dir = tu_edpt_dir(ep_addr);
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if (dir == TUSB_DIR_IN) {
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static void xfer_data_packet(uint8_t ep_num, tusb_dir_t ep_dir, xfer_ctl_t* xfer) {
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if (ep_dir == TUSB_DIR_IN) {
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uint16_t remaining = xfer->total_len - xfer->queued_len;
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uint16_t next_tx_size = TU_MIN(remaining, xfer->max_size);
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@ -133,7 +129,7 @@ static void xfer_data_packet(uint8_t ep_addr, xfer_ctl_t* xfer) {
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EP_RX_MAX_LEN(ep_num) = max_possible_rx_size;
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}
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}
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ep_set_response_and_toggle(ep_addr, USBHS_EP_R_RES_ACK);
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ep_set_response_and_toggle(ep_num, ep_dir, USBHS_EP_R_RES_ACK);
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}
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void dcd_init(uint8_t rhport) {
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@ -154,7 +150,7 @@ void dcd_init(uint8_t rhport) {
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#endif
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USBHSD->INT_EN = 0;
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USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN | USBHS_ISO_ACT_EN;
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USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_BUS_RST_EN | USBHS_SUSPEND_EN | USBHS_ISO_ACT_EN;
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USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
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USBHSD->ENDP_TYPE = 0x00;
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@ -328,7 +324,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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xfer->queued_len = 0;
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xfer->is_last_packet = false;
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xfer_data_packet(ep_addr, xfer);
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xfer_data_packet(ep_num, dir, xfer);
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return true;
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}
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@ -339,77 +335,67 @@ void dcd_int_handler(uint8_t rhport) {
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uint8_t int_flag = USBHSD->INT_FG;
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uint8_t int_status = USBHSD->INT_ST;
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if (int_flag & USBHS_ISO_ACT_FLAG) {
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uint8_t ep_num = int_status & MASK_UIS_ENDP;
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uint8_t rx_token = int_status & MASK_UIS_TOKEN;
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uint8_t ep_addr = (rx_token == USBHS_TOKEN_PID_IN) ? (TUSB_DIR_IN_MASK | ep_num) : ep_num;
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xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, tu_edpt_dir(ep_addr));
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if (int_flag & (USBHS_ISO_ACT_FLAG | USBHS_TRANSFER_FLAG)) {
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uint8_t const rx_token = int_status & MASK_UIS_TOKEN;
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uint8_t const ep_num = int_status & MASK_UIS_ENDP;
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tusb_dir_t const ep_dir = (rx_token == USBHS_TOKEN_PID_IN) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
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xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, ep_dir);
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if (rx_token == USBHS_TOKEN_PID_OUT) {
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uint16_t rx_len = USBHSD->RX_LEN;
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if (ep_num == 0) {
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memcpy(&xfer->buffer[xfer->queued_len], ep0_buffer, rx_len);
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}
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xfer->queued_len += rx_len;
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if (rx_len < xfer->max_size) {
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xfer->is_last_packet = true;
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}
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} else if (rx_token == USBHS_TOKEN_PID_IN) {
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if (xfer->is_last_packet == true) {
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if (xfer->is_iso && xfer->is_last_packet) {
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/* Disable EP to avoid ISO_ACT interrupt generation */
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USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_T_EN << ep_num);
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}else {
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// Do nothing, no need to update xfer->is_last_packet, it is already updated in xfer_data_packet
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}
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}
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if (xfer->is_last_packet == true) {
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ep_set_response_and_toggle(ep_addr, EP_RESPONSE_NAK);
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ep_set_response_and_toggle(ep_num, ep_dir, EP_RESPONSE_NAK);
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dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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} else {
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/* prepare next part of packet to xref */
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xfer_data_packet(ep_addr, xfer);
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xfer_data_packet(ep_num, ep_dir, xfer);
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}
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USBHSD->INT_FG = USBHS_ISO_ACT_FLAG; /* Clear flag */
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} else if (int_flag & USBHS_TRANSFER_FLAG) {
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uint8_t ep_num = int_status & MASK_UIS_ENDP;
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uint8_t rx_token = int_status & MASK_UIS_TOKEN;
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uint8_t ep_addr = (rx_token == USBHS_TOKEN_PID_IN) ? (TUSB_DIR_IN_MASK | ep_num) : ep_num;
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xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, tu_edpt_dir(ep_addr));
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if (xfer->is_iso == false) {
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if (rx_token == USBHS_TOKEN_PID_OUT) {
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uint16_t rx_len = USBHSD->RX_LEN;
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if (ep_num == 0) {
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memcpy(&xfer->buffer[xfer->queued_len], ep0_buffer, rx_len);
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}
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xfer->queued_len += rx_len;
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if (rx_len < xfer->max_size) {
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xfer->is_last_packet = true;
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}
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} else if (rx_token == USBHS_TOKEN_PID_IN) {
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// Do nothing, no need to update xfer->is_last_packet, it is already updated in xfer_data_packet
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// Common processing below
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}
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if (xfer->is_last_packet == true) {
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ep_set_response_and_toggle(ep_addr, EP_RESPONSE_NAK);
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dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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} else {
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/* prepare next part of packet to xref */
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xfer_data_packet(ep_addr, xfer);
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}
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}
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USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
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USBHSD->INT_FG = (int_flag & (USBHS_ISO_ACT_FLAG | USBHS_TRANSFER_FLAG)); /* Clear flag */
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} else if (int_flag & USBHS_SETUP_FLAG) {
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ep_set_response_and_toggle(0x80, EP_RESPONSE_NAK);
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ep_set_response_and_toggle(0x00, EP_RESPONSE_NAK);
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ep_set_response_and_toggle(0, TUSB_DIR_IN, EP_RESPONSE_NAK);
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ep_set_response_and_toggle(0, TUSB_DIR_OUT, EP_RESPONSE_NAK);
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dcd_event_setup_received(0, ep0_buffer, true);
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USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
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} else if (int_flag & USBHS_DETECT_FLAG) {
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} else if (int_flag & USBHS_BUS_RST_FLAG) {
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// TODO CH32 does not detect actual speed at this time (should be known at end of reset)
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// This interrupt probably triggered at start of bus reset
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// tusb_speed_t actual_speed;
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// switch(USBHSD->SPEED_TYPE & USBHS_SPEED_TYPE_MASK){
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// case USBHS_SPEED_TYPE_HIGH:
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// actual_speed = TUSB_SPEED_HIGH;
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// break;
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// case USBHS_SPEED_TYPE_FULL:
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// actual_speed = TUSB_SPEED_FULL;
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// break;
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// case USBHS_SPEED_TYPE_LOW:
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// actual_speed = TUSB_SPEED_LOW;
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// break;
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// default:
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// TU_ASSERT(0,);
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// break;
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// }
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// dcd_event_bus_reset(0, actual_speed, true);
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dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
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@ -417,7 +403,7 @@ void dcd_int_handler(uint8_t rhport) {
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EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
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EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
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USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
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USBHSD->INT_FG = USBHS_BUS_RST_FLAG; /* Clear flag */
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} else if (int_flag & USBHS_SUSPEND_FLAG) {
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dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SUSPEND};
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dcd_event_handler(&event, true);
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