From 6280e4e7cbad956aab1a2a519d93620c3990eedc Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 14 Sep 2019 18:01:52 -0400 Subject: [PATCH 01/71] msp430f5529: Add empty msp_exp430f5529lp BSP and DCD. --- examples/make.mk | 13 +- examples/rules.mk | 16 +- hw/bsp/msp_exp430f5529lp/board.mk | 21 + hw/bsp/msp_exp430f5529lp/in430.h | 345 ++ hw/bsp/msp_exp430f5529lp/iomacros.h | 87 + hw/bsp/msp_exp430f5529lp/msp430.h | 1920 +++++++ hw/bsp/msp_exp430f5529lp/msp430f5529.h | 4789 +++++++++++++++++ hw/bsp/msp_exp430f5529lp/msp430f5529.ld | 457 ++ .../msp_exp430f5529lp/msp430f5529_symbols.ld | 867 +++ hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c | 75 + src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 116 + 11 files changed, 8697 insertions(+), 9 deletions(-) create mode 100644 hw/bsp/msp_exp430f5529lp/board.mk create mode 100644 hw/bsp/msp_exp430f5529lp/in430.h create mode 100644 hw/bsp/msp_exp430f5529lp/iomacros.h create mode 100644 hw/bsp/msp_exp430f5529lp/msp430.h create mode 100644 hw/bsp/msp_exp430f5529lp/msp430f5529.h create mode 100644 hw/bsp/msp_exp430f5529lp/msp430f5529.ld create mode 100644 hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld create mode 100644 hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c create mode 100644 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c diff --git a/examples/make.mk b/examples/make.mk index b0aa5659e..f2428f5e3 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -2,8 +2,12 @@ # Common make definition for all examples # -# Compiler -CROSS_COMPILE = arm-none-eabi- +# Compiler +ifeq ($(BOARD), msp_exp430f5529lp) + CROSS_COMPILE = msp430-elf- +else + CROSS_COMPILE = arm-none-eabi- +endif CC = $(CROSS_COMPILE)gcc CXX = $(CROSS_COMPILE)g++ OBJCOPY = $(CROSS_COMPILE)objcopy @@ -67,10 +71,13 @@ CFLAGS += \ -Wno-deprecated-declarations \ -Wnested-externs \ -Wunreachable-code \ - -Wno-error=lto-type-mismatch \ -ffunction-sections \ -fdata-sections +ifneq ($(BOARD), msp_exp430f5529lp) + CFLAGS += -Wno-error=lto-type-mismatch +endif + # This causes lots of warning with nrf5x build due to nrfx code # CFLAGS += -Wcast-align diff --git a/examples/rules.mk b/examples/rules.mk index 478a5907a..f57b506ca 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -23,10 +23,14 @@ INC += $(TOP)/src # CFLAGS += $(addprefix -I,$(INC)) -LDFLAGS += $(CFLAGS) -fshort-enums -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nosys.specs -specs=nano.specs +ifeq ($(BOARD), msp_exp430f5529lp) + LDFLAGS += $(CFLAGS) -fshort-enums -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections +else + LDFLAGS += $(CFLAGS) -fshort-enums -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nosys.specs -specs=nano.specs +endif ASFLAGS += $(CFLAGS) -# Assembly files can be name with upper case .S, convert it to .s +# Assembly files can be name with upper case .S, convert it to .s SRC_S := $(SRC_S:.S=.s) # Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966 @@ -59,8 +63,8 @@ $(BUILD)/$(BOARD)-firmware.elf: $(OBJ) $(BUILD)/$(BOARD)-firmware.bin: $(BUILD)/$(BOARD)-firmware.elf @echo CREATE $@ @$(OBJCOPY) -O binary $^ $@ - -$(BUILD)/$(BOARD)-firmware.hex: $(BUILD)/$(BOARD)-firmware.elf + +$(BUILD)/$(BOARD)-firmware.hex: $(BUILD)/$(BOARD)-firmware.elf @echo CREATE $@ @$(OBJCOPY) -O ihex $^ $@ @@ -103,11 +107,11 @@ size: $(BUILD)/$(BOARD)-firmware.elf clean: rm -rf $(BUILD) - + # Flash binary using Jlink ifeq ($(OS),Windows_NT) JLINKEXE = JLink.exe -else +else JLINKEXE = JLinkExe endif diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk new file mode 100644 index 000000000..27e94e6ca --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -0,0 +1,21 @@ +CFLAGS += \ + -D__MSP430F5529__ \ + -nostdlib -nostartfiles \ + -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx + +# All source paths should be relative to the top level. +LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld +LDFLAGS += -L$(TOP)/hw/bsp/$(BOARD) + +INC += $(TOP)/hw/bsp/$(BOARD) + +# For TinyUSB port source +VENDOR = ti +CHIP_FAMILY = msp430x5xx + +# Path to STM32 Cube Programmer CLI, should be added into system path +MSPDEBUG = mspdebug + +# flash target using on-board stlink +flash: $(BUILD)/$(BOARD)-firmware.elf + $(MSPDEBUG) tilib "prog $<" diff --git a/hw/bsp/msp_exp430f5529lp/in430.h b/hw/bsp/msp_exp430f5529lp/in430.h new file mode 100644 index 000000000..9df9194c6 --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/in430.h @@ -0,0 +1,345 @@ +/******************************************************************************* + * in430.h - + * + * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +/* 1.207 */ + +#ifndef __IN430_H__ +#define __IN430_H__ + +/* Definitions for projects using the GNU C/C++ compiler */ +#if !defined(__ASSEMBLER__) + +/* Definitions of things which are intrinsics with IAR and CCS, but which don't + appear to be intrinsics with the GCC compiler */ + +/* The data type used to hold interrupt state */ +typedef unsigned int __istate_t; + +#define _no_operation() __asm__ __volatile__ ("nop") + +#define _get_interrupt_state() \ +({ \ + unsigned int __x; \ + __asm__ __volatile__( \ + "mov SR, %0" \ + : "=r" ((unsigned int) __x) \ + :); \ + __x; \ +}) + +#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__) +#define _set_interrupt_state(x) \ +({ \ + __asm__ __volatile__ ("nop { mov %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + );\ +}) + +#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop") + +#define _bis_SR_register(x) \ + __asm__ __volatile__ ("nop { bis.w %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + ) +#else + +#define _set_interrupt_state(x) \ +({ \ + __asm__ __volatile__ ("mov %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + );\ +}) + +#define _enable_interrupts() __asm__ __volatile__ ("eint") + +#define _bis_SR_register(x) \ + __asm__ __volatile__ ("bis.w %0, SR" \ + : : "ri"((unsigned int) x) \ + ) + +#endif + +#define _disable_interrupts() __asm__ __volatile__ ("dint { nop") + +#define _bic_SR_register(x) \ + __asm__ __volatile__ ("bic.w %0, SR { nop" \ + : : "ri"((unsigned int) x) \ + ) + +#define _get_SR_register() \ +({ \ + unsigned int __x; \ + __asm__ __volatile__( \ + "mov SR, %0" \ + : "=r" ((unsigned int) __x) \ + :); \ + __x; \ +}) + +#define _swap_bytes(x) \ +({ \ + unsigned int __dst = x; \ + __asm__ __volatile__( \ + "swpb %0" \ + : "+r" ((unsigned int) __dst) \ + :); \ + __dst; \ +}) + +/* Alternative names for GCC built-ins */ +#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x) +#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x) + +/* Additional intrinsics provided for IAR/CCS compatibility */ +#define _bcd_add_short(x,y) \ +({ \ + unsigned short __z = ((unsigned short) y); \ + __asm__ __volatile__( \ + "clrc \n\t" \ + "dadd.w %1, %0" \ + : "+r" ((unsigned short) __z) \ + : "ri" ((unsigned short) x) \ + ); \ + __z; \ +}) + +#define __bcd_add_short(x,y) _bcd_add_short(x,y) + +#define _bcd_add_long(x,y) \ +({ \ + unsigned long __z = ((unsigned long) y); \ + __asm__ __volatile__( \ + "clrc \n\t" \ + "dadd.w %L1, %L0 \n\t" \ + "dadd.w %H1, %H0" \ + : "+r" ((unsigned long) __z) \ + : "ri" ((unsigned long) x) \ + ); \ + __z; \ + }) + +#define __bcd_add_long(x,y) _bcd_add_long(x,y) + +#define _get_SP_register() \ +({ \ + unsigned int __x; \ + __asm__ __volatile__( \ + "mov SP, %0" \ + : "=r" ((unsigned int) __x) \ + :); \ + __x; \ +}) + +#define __get_SP_register() _get_SP_register() + +#define _set_SP_register(x) \ +({ \ + __asm__ __volatile__ ("mov %0, SP" \ + : : "ri"((unsigned int) x) \ + );\ +}) + +#define __set_SP_register(x) _set_SP_register(x) + +#define _data16_write_addr(addr,src) \ +({ \ + unsigned long __src = src; \ + __asm__ __volatile__ ( \ + "movx.a %1, 0(%0)" \ + : : "r"((unsigned int) addr), "m"((unsigned long) __src) \ + ); \ +}) + +#define __data16_write_addr(addr,src) _data16_write_addr(addr,src) + +#define _data16_read_addr(addr) \ +({ \ + unsigned long __dst; \ + __asm__ __volatile__ ( \ + "movx.a @%1, %0" \ + : "=m"((unsigned long) __dst) \ + : "r"((unsigned int) addr) \ + ); \ + __dst; \ +}) + +#define __data16_read_addr(addr) _data16_read_addr(addr) + +#define _data20_write_char(addr,src) \ +({ \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %1, %0 \n\t" \ + "mov.b %2, 0(%0)" \ + : "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr), "ri"((char) src) \ + ); \ +}) + +#define __data20_write_char(addr,src) _data20_write_char(addr,src) + +#define _data20_read_char(addr) \ +({ \ + char __dst; \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %2, %1 \n\t" \ + "mov.b 0(%1), %0" \ + : "=r"((char) __dst), "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr) \ + ); \ + __dst ; \ +}) + +#define __data20_read_char(addr) _data20_read_char(addr) + +#define _data20_write_short(addr,src) \ +({ \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %1, %0 \n\t" \ + "mov.w %2, 0(%0)" \ + : "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr), "ri"((short) src) \ + ); \ +}) + +#define __data20_write_short(addr,src) _data20_write_short(addr,src) + +#define _data20_read_short(addr) \ +({ \ + short __dst; \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %2, %1 \n\t" \ + "mov.w 0(%1), %0" \ + : "=r"((short) __dst), "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr) \ + ); \ + __dst ; \ +}) + +#define __data20_read_short(addr) _data20_read_short(addr) + +#define _data20_write_long(addr,src) \ +({ \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %1, %0 \n\t" \ + "mov.w %L2, 0(%0) \n\t" \ + "mov.w %H2, 2(%0)" \ + : "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr), "ri"((long) src) \ + ); \ +}) + +#define __data20_write_long(addr,src) _data20_write_long(addr,src) + +#define _data20_read_long(addr) \ +({ \ + long __dst; \ + unsigned int __tmp; \ + unsigned long __addr = addr; \ + __asm__ __volatile__ ( \ + "movx.a %2, %1 \n\t" \ + "mov.w 0(%1), %L0 \n\t" \ + "mov.w 2(%1), %H0" \ + : "=r"((long) __dst), "=&r"((unsigned int) __tmp) \ + : "m"((unsigned long) __addr) \ + ); \ + __dst ; \ +}) + +#define __data20_read_long(addr) _data20_read_long(addr) + +#define _low_power_mode_0() _bis_SR_register(0x18) +#define _low_power_mode_1() _bis_SR_register(0x58) +#define _low_power_mode_2() _bis_SR_register(0x98) +#define _low_power_mode_3() _bis_SR_register(0xD8) +#define _low_power_mode_4() _bis_SR_register(0xF8) +#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0) + +#define __low_power_mode_0() _low_power_mode_0() +#define __low_power_mode_1() _low_power_mode_1() +#define __low_power_mode_2() _low_power_mode_2() +#define __low_power_mode_3() _low_power_mode_3() +#define __low_power_mode_4() _low_power_mode_4() +#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit() + +#define _even_in_range(x,y) (x) +#define __even_in_range(x,y) _even_in_range(x,y) + +/* Define some alternative names for the intrinsics, which have been used + in the various versions of IAR and GCC */ +#define __no_operation() _no_operation() + +#define __get_interrupt_state() _get_interrupt_state() +#define __set_interrupt_state(x) _set_interrupt_state(x) +#define __enable_interrupt() _enable_interrupts() +#define __disable_interrupt() _disable_interrupts() + +#define __bic_SR_register(x) _bic_SR_register(x) +#define __bis_SR_register(x) _bis_SR_register(x) +#define __get_SR_register() _get_SR_register() + +#define __swap_bytes(x) _swap_bytes(x) + +#define __nop() _no_operation() + +#define __eint() _enable_interrupts() +#define __dint() _disable_interrupts() + +#define _NOP() _no_operation() +#define _EINT() _enable_interrupts() +#define _DINT() _disable_interrupts() + +#define _BIC_SR(x) _bic_SR_register(x) +#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x) +#define _BIS_SR(x) _bis_SR_register(x) +#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x) +#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x) + +#define _SWAP_BYTES(x) _swap_bytes(x) + +#define __no_init __attribute__((noinit)) + +#endif /* !defined _GNU_ASSEMBLER_ */ + +#endif /* __IN430_H__ */ diff --git a/hw/bsp/msp_exp430f5529lp/iomacros.h b/hw/bsp/msp_exp430f5529lp/iomacros.h new file mode 100644 index 000000000..5ddda4873 --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/iomacros.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * iomacros.h - + * + * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +/* 1.207 */ + +#if !defined(_IOMACROS_H_) +#define _IOMACROS_H_ + + +#if defined(__ASSEMBLER__) + +/* Definitions for assembly compilation using the GNU assembler */ +#define sfrb(x,x_) x=x_ +#define sfrw(x,x_) x=x_ +#define sfra(x,x_) x=x_ +#define sfrl(x,x_) x=x_ + +#define const_sfrb(x,x_) x=x_ +#define const_sfrw(x,x_) x=x_ +#define const_sfra(x,x_) x=x_ +#define const_sfrl(x,x_) x=x_ + +#define sfr_b(x) +#define sfr_w(x) +#define sfr_a(x) +#define sfr_l(x) + +#else + +#define sfr_b(x) extern volatile unsigned char x +#define sfr_w(x) extern volatile unsigned int x +#define sfr_a(x) extern volatile unsigned long int x +#define sfr_l(x) extern volatile unsigned long int x + +#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_) +#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_) +#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_) +#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_) + +#define sfrb(x,x_) sfrb_(x,x_) +#define sfrw(x,x_) sfrw_(x,x_) +#define sfra(x,x_) sfra_(x,x_) +#define sfrl(x,x_) sfrl_(x,x_) + +#define const_sfrb(x,x_) const sfrb_(x,x_) +#define const_sfrw(x,x_) const sfrw_(x,x_) +#define const_sfra(x,x_) const sfra_(x,x_) +#define const_sfrl(x,x_) const sfrl_(x,x_) + +#define __interrupt __attribute__((__interrupt__)) +#define __interrupt_vec(vec) __attribute__((interrupt(vec))) + +#endif /* defined(__ASSEMBLER__) */ + +#endif /* _IOMACROS_H_ */ diff --git a/hw/bsp/msp_exp430f5529lp/msp430.h b/hw/bsp/msp_exp430f5529lp/msp430.h new file mode 100644 index 000000000..a162addc0 --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/msp430.h @@ -0,0 +1,1920 @@ +/******************************************************************* +* * +* This file is a generic include file controlled by * +* compiler/assembler IDE generated defines * +* * +*******************************************************************/ + +#ifndef __msp430 +#define __msp430 + + +#if defined (__MSP430C111__) +#include "msp430c111.h" + +#elif defined (__MSP430C1111__) +#include "msp430c1111.h" + +#elif defined (__MSP430C112__) +#include "msp430c112.h" + +#elif defined (__MSP430C1121__) +#include "msp430c1121.h" + +#elif defined (__MSP430C1331__) +#include "msp430c1331.h" + +#elif defined (__MSP430C1351__) +#include "msp430c1351.h" + +#elif defined (__MSP430C311S__) +#include "msp430c311s.h" + +#elif defined (__MSP430C312__) +#include "msp430c312.h" + +#elif defined (__MSP430C313__) +#include "msp430c313.h" + +#elif defined (__MSP430C314__) +#include "msp430c314.h" + +#elif defined (__MSP430C315__) +#include "msp430c315.h" + +#elif defined (__MSP430C323__) +#include "msp430c323.h" + +#elif defined (__MSP430C325__) +#include "msp430c325.h" + +#elif defined (__MSP430C336__) +#include "msp430c336.h" + +#elif defined (__MSP430C337__) +#include "msp430c337.h" + +#elif defined (__MSP430C412__) +#include "msp430c412.h" + +#elif defined (__MSP430C413__) +#include "msp430c413.h" + +#elif defined (__MSP430CG4616__) +#include "msp430cg4616.h" + +#elif defined (__MSP430CG4617__) +#include "msp430cg4617.h" + +#elif defined (__MSP430CG4618__) +#include "msp430cg4618.h" + +#elif defined (__MSP430CG4619__) +#include "msp430cg4619.h" + +#elif defined (__MSP430E112__) +#include "msp430e112.h" + +#elif defined (__MSP430E313__) +#include "msp430e313.h" + +#elif defined (__MSP430E315__) +#include "msp430e315.h" + +#elif defined (__MSP430E325__) +#include "msp430e325.h" + +#elif defined (__MSP430E337__) +#include "msp430e337.h" + +#elif defined (__MSP430F110__) +#include "msp430f110.h" + +#elif defined (__MSP430F1101__) +#include "msp430f1101.h" + +#elif defined (__MSP430F1101A__) +#include "msp430f1101a.h" + +#elif defined (__MSP430F1111__) +#include "msp430f1111.h" + +#elif defined (__MSP430F1111A__) +#include "msp430f1111a.h" + +#elif defined (__MSP430F112__) +#include "msp430f112.h" + +#elif defined (__MSP430F1121__) +#include "msp430f1121.h" + +#elif defined (__MSP430F1121A__) +#include "msp430f1121a.h" + +#elif defined (__MSP430F1122__) +#include "msp430f1122.h" + +#elif defined (__MSP430F1132__) +#include "msp430f1132.h" + +#elif defined (__MSP430F122__) +#include "msp430f122.h" + +#elif defined (__MSP430F1222__) +#include "msp430f1222.h" + +#elif defined (__MSP430F123__) +#include "msp430f123.h" + +#elif defined (__MSP430F1232__) +#include "msp430f1232.h" + +#elif defined (__MSP430F133__) +#include "msp430f133.h" + +#elif defined (__MSP430F135__) +#include "msp430f135.h" + +#elif defined (__MSP430F147__) +#include "msp430f147.h" + +#elif defined (__MSP430F148__) +#include "msp430f148.h" + +#elif defined (__MSP430F149__) +#include "msp430f149.h" + +#elif defined (__MSP430F1471__) +#include "msp430f1471.h" + +#elif defined (__MSP430F1481__) +#include "msp430f1481.h" + +#elif defined (__MSP430F1491__) +#include "msp430f1491.h" + +#elif defined (__MSP430F155__) +#include "msp430f155.h" + +#elif defined (__MSP430F156__) +#include "msp430f156.h" + +#elif defined (__MSP430F157__) +#include "msp430f157.h" + +#elif defined (__MSP430F167__) +#include "msp430f167.h" + +#elif defined (__MSP430F168__) +#include "msp430f168.h" + +#elif defined (__MSP430F169__) +#include "msp430f169.h" + +#elif defined (__MSP430F1610__) +#include "msp430f1610.h" + +#elif defined (__MSP430F1611__) +#include "msp430f1611.h" + +#elif defined (__MSP430F1612__) +#include "msp430f1612.h" + +#elif defined (__MSP430F2001__) +#include "msp430f2001.h" + +#elif defined (__MSP430F2011__) +#include "msp430f2011.h" + +#elif defined (__MSP430F2002__) +#include "msp430f2002.h" + +#elif defined (__MSP430F2012__) +#include "msp430f2012.h" + +#elif defined (__MSP430F2003__) +#include "msp430f2003.h" + +#elif defined (__MSP430F2013__) +#include "msp430f2013.h" + +#elif defined (__MSP430F2101__) +#include "msp430f2101.h" + +#elif defined (__MSP430F2111__) +#include "msp430f2111.h" + +#elif defined (__MSP430F2121__) +#include "msp430f2121.h" + +#elif defined (__MSP430F2131__) +#include "msp430f2131.h" + +#elif defined (__MSP430F2112__) +#include "msp430f2112.h" + +#elif defined (__MSP430F2122__) +#include "msp430f2122.h" + +#elif defined (__MSP430F2132__) +#include "msp430f2132.h" + +#elif defined (__MSP430F2232__) +#include "msp430f2232.h" + +#elif defined (__MSP430F2252__) +#include "msp430f2252.h" + +#elif defined (__MSP430F2272__) +#include "msp430f2272.h" + +#elif defined (__MSP430F2234__) +#include "msp430f2234.h" + +#elif defined (__MSP430F2254__) +#include "msp430f2254.h" + +#elif defined (__MSP430F2274__) +#include "msp430f2274.h" + +#elif defined (__MSP430F2330__) +#include "msp430f2330.h" + +#elif defined (__MSP430F2350__) +#include "msp430f2350.h" + +#elif defined (__MSP430F2370__) +#include "msp430f2370.h" + +#elif defined (__MSP430F233__) +#include "msp430f233.h" + +#elif defined (__MSP430F235__) +#include "msp430f235.h" + +#elif defined (__MSP430F247__) +#include "msp430f247.h" + +#elif defined (__MSP430F248__) +#include "msp430f248.h" + +#elif defined (__MSP430F249__) +#include "msp430f249.h" + +#elif defined (__MSP430F2410__) +#include "msp430f2410.h" + +#elif defined (__MSP430F2471__) +#include "msp430f2471.h" + +#elif defined (__MSP430F2481__) +#include "msp430f2481.h" + +#elif defined (__MSP430F2491__) +#include "msp430f2491.h" + +#elif defined (__MSP430F2416__) +#include "msp430f2416.h" + +#elif defined (__MSP430F2417__) +#include "msp430f2417.h" + +#elif defined (__MSP430F2418__) +#include "msp430f2418.h" + +#elif defined (__MSP430F2419__) +#include "msp430f2419.h" + +#elif defined (__MSP430F2616__) +#include "msp430f2616.h" + +#elif defined (__MSP430F2617__) +#include "msp430f2617.h" + +#elif defined (__MSP430F2618__) +#include "msp430f2618.h" + +#elif defined (__MSP430F2619__) +#include "msp430f2619.h" + +#elif defined (__MSP430F412__) +#include "msp430f412.h" + +#elif defined (__MSP430F413__) +#include "msp430f413.h" + +#elif defined (__MSP430F415__) +#include "msp430f415.h" + +#elif defined (__MSP430F417__) +#include "msp430f417.h" + +#elif defined (__MSP430F4132__) +#include "msp430f4132.h" + +#elif defined (__MSP430F4152__) +#include "msp430f4152.h" + +#elif defined (__MSP430F423__) +#include "msp430f423.h" + +#elif defined (__MSP430F425__) +#include "msp430f425.h" + +#elif defined (__MSP430F427__) +#include "msp430f427.h" + +#elif defined (__MSP430F423A__) +#include "msp430f423a.h" + +#elif defined (__MSP430F425A__) +#include "msp430f425a.h" + +#elif defined (__MSP430F427A__) +#include "msp430f427a.h" + +#elif defined (__MSP430F435__) +#include "msp430f435.h" + +#elif defined (__MSP430F436__) +#include "msp430f436.h" + +#elif defined (__MSP430F437__) +#include "msp430f437.h" + +#elif defined (__MSP430F4351__) +#include "msp430f4351.h" + +#elif defined (__MSP430F4361__) +#include "msp430f4361.h" + +#elif defined (__MSP430F4371__) +#include "msp430f4371.h" + +#elif defined (__MSP430F4481__) +#include "msp430f4481.h" + +#elif defined (__MSP430F4491__) +#include "msp430f4491.h" + +#elif defined (__MSP430F447__) +#include "msp430f447.h" + +#elif defined (__MSP430F448__) +#include "msp430f448.h" + +#elif defined (__MSP430F449__) +#include "msp430f449.h" + +#elif defined (__MSP430FE423__) +#include "msp430fe423.h" + +#elif defined (__MSP430FE425__) +#include "msp430fe425.h" + +#elif defined (__MSP430FE427__) +#include "msp430fe427.h" + +#elif defined (__MSP430FE423A__) +#include "msp430fe423a.h" + +#elif defined (__MSP430FE425A__) +#include "msp430fe425a.h" + +#elif defined (__MSP430FE427A__) +#include "msp430fe427a.h" + +#elif defined (__MSP430FE4232__) +#include "msp430fe4232.h" + +#elif defined (__MSP430FE4242__) +#include "msp430fe4242.h" + +#elif defined (__MSP430FE4252__) +#include "msp430fe4252.h" + +#elif defined (__MSP430FE4272__) +#include "msp430fe4272.h" + +#elif defined (__MSP430F4783__) +#include "msp430f4783.h" + +#elif defined (__MSP430F4793__) +#include "msp430f4793.h" + +#elif defined (__MSP430F4784__) +#include "msp430f4784.h" + +#elif defined (__MSP430F4794__) +#include "msp430f4794.h" + +#elif defined (__MSP430F47126__) +#include "msp430f47126.h" + +#elif defined (__MSP430F47127__) +#include "msp430f47127.h" + +#elif defined (__MSP430F47163__) +#include "msp430f47163.h" + +#elif defined (__MSP430F47173__) +#include "msp430f47173.h" + +#elif defined (__MSP430F47183__) +#include "msp430f47183.h" + +#elif defined (__MSP430F47193__) +#include "msp430f47193.h" + +#elif defined (__MSP430F47166__) +#include "msp430f47166.h" + +#elif defined (__MSP430F47176__) +#include "msp430f47176.h" + +#elif defined (__MSP430F47186__) +#include "msp430f47186.h" + +#elif defined (__MSP430F47196__) +#include "msp430f47196.h" + +#elif defined (__MSP430F47167__) +#include "msp430f47167.h" + +#elif defined (__MSP430F47177__) +#include "msp430f47177.h" + +#elif defined (__MSP430F47187__) +#include "msp430f47187.h" + +#elif defined (__MSP430F47197__) +#include "msp430f47197.h" + +#elif defined (__MSP430F4250__) +#include "msp430f4250.h" + +#elif defined (__MSP430F4260__) +#include "msp430f4260.h" + +#elif defined (__MSP430F4270__) +#include "msp430f4270.h" + +#elif defined (__MSP430FG4250__) +#include "msp430fg4250.h" + +#elif defined (__MSP430FG4260__) +#include "msp430fg4260.h" + +#elif defined (__MSP430FG4270__) +#include "msp430fg4270.h" + +#elif defined (__MSP430FW423__) +#include "msp430fw423.h" + +#elif defined (__MSP430FW425__) +#include "msp430fw425.h" + +#elif defined (__MSP430FW427__) +#include "msp430fw427.h" + +#elif defined (__MSP430FW428__) +#include "msp430fw428.h" + +#elif defined (__MSP430FW429__) +#include "msp430fw429.h" + +#elif defined (__MSP430FG437__) +#include "msp430fg437.h" + +#elif defined (__MSP430FG438__) +#include "msp430fg438.h" + +#elif defined (__MSP430FG439__) +#include "msp430fg439.h" + +#elif defined (__MSP430F438__) +#include "msp430f438.h" + +#elif defined (__MSP430F439__) +#include "msp430f439.h" + +#elif defined (__MSP430F477__) +#include "msp430f477.h" + +#elif defined (__MSP430F478__) +#include "msp430f478.h" + +#elif defined (__MSP430F479__) +#include "msp430f479.h" + +#elif defined (__MSP430FG477__) +#include "msp430fg477.h" + +#elif defined (__MSP430FG478__) +#include "msp430fg478.h" + +#elif defined (__MSP430FG479__) +#include "msp430fg479.h" + +#elif defined (__MSP430F46161__) +#include "msp430f46161.h" + +#elif defined (__MSP430F46171__) +#include "msp430f46171.h" + +#elif defined (__MSP430F46181__) +#include "msp430f46181.h" + +#elif defined (__MSP430F46191__) +#include "msp430f46191.h" + +#elif defined (__MSP430F4616__) +#include "msp430f4616.h" + +#elif defined (__MSP430F4617__) +#include "msp430f4617.h" + +#elif defined (__MSP430F4618__) +#include "msp430f4618.h" + +#elif defined (__MSP430F4619__) +#include "msp430f4619.h" + +#elif defined (__MSP430FG4616__) +#include "msp430fg4616.h" + +#elif defined (__MSP430FG4617__) +#include "msp430fg4617.h" + +#elif defined (__MSP430FG4618__) +#include "msp430fg4618.h" + +#elif defined (__MSP430FG4619__) +#include "msp430fg4619.h" + +#elif defined (__MSP430F5418__) +#include "msp430f5418.h" + +#elif defined (__MSP430F5419__) +#include "msp430f5419.h" + +#elif defined (__MSP430F5435__) +#include "msp430f5435.h" + +#elif defined (__MSP430F5436__) +#include "msp430f5436.h" + +#elif defined (__MSP430F5437__) +#include "msp430f5437.h" + +#elif defined (__MSP430F5438__) +#include "msp430f5438.h" + +#elif defined (__MSP430F5418A__) +#include "msp430f5418a.h" + +#elif defined (__MSP430F5419A__) +#include "msp430f5419a.h" + +#elif defined (__MSP430F5435A__) +#include "msp430f5435a.h" + +#elif defined (__MSP430F5436A__) +#include "msp430f5436a.h" + +#elif defined (__MSP430F5437A__) +#include "msp430f5437a.h" + +#elif defined (__MSP430F5438A__) +#include "msp430f5438a.h" + +#elif defined (__MSP430F5212__) +#include "msp430f5212.h" + +#elif defined (__MSP430F5213__) +#include "msp430f5213.h" + +#elif defined (__MSP430F5214__) +#include "msp430f5214.h" + +#elif defined (__MSP430F5217__) +#include "msp430f5217.h" + +#elif defined (__MSP430F5218__) +#include "msp430f5218.h" + +#elif defined (__MSP430F5219__) +#include "msp430f5219.h" + +#elif defined (__MSP430F5222__) +#include "msp430f5222.h" + +#elif defined (__MSP430F5223__) +#include "msp430f5223.h" + +#elif defined (__MSP430F5224__) +#include "msp430f5224.h" + +#elif defined (__MSP430F5227__) +#include "msp430f5227.h" + +#elif defined (__MSP430F5228__) +#include "msp430f5228.h" + +#elif defined (__MSP430F5229__) +#include "msp430f5229.h" + +#elif defined (__MSP430F5232__) +#include "msp430f5232.h" + +#elif defined (__MSP430F5234__) +#include "msp430f5234.h" + +#elif defined (__MSP430F5237__) +#include "msp430f5237.h" + +#elif defined (__MSP430F5239__) +#include "msp430f5239.h" + +#elif defined (__MSP430F5242__) +#include "msp430f5242.h" + +#elif defined (__MSP430F5244__) +#include "msp430f5244.h" + +#elif defined (__MSP430F5247__) +#include "msp430f5247.h" + +#elif defined (__MSP430F5249__) +#include "msp430f5249.h" + +#elif defined (__MSP430F5304__) +#include "msp430f5304.h" + +#elif defined (__MSP430F5308__) +#include "msp430f5308.h" + +#elif defined (__MSP430F5309__) +#include "msp430f5309.h" + +#elif defined (__MSP430F5310__) +#include "msp430f5310.h" + +#elif defined (__MSP430F5340__) +#include "msp430f5340.h" + +#elif defined (__MSP430F5341__) +#include "msp430f5341.h" + +#elif defined (__MSP430F5342__) +#include "msp430f5342.h" + +#elif defined (__MSP430F5324__) +#include "msp430f5324.h" + +#elif defined (__MSP430F5325__) +#include "msp430f5325.h" + +#elif defined (__MSP430F5326__) +#include "msp430f5326.h" + +#elif defined (__MSP430F5327__) +#include "msp430f5327.h" + +#elif defined (__MSP430F5328__) +#include "msp430f5328.h" + +#elif defined (__MSP430F5329__) +#include "msp430f5329.h" + +#elif defined (__MSP430F5500__) +#include "msp430f5500.h" + +#elif defined (__MSP430F5501__) +#include "msp430f5501.h" + +#elif defined (__MSP430F5502__) +#include "msp430f5502.h" + +#elif defined (__MSP430F5503__) +#include "msp430f5503.h" + +#elif defined (__MSP430F5504__) +#include "msp430f5504.h" + +#elif defined (__MSP430F5505__) +#include "msp430f5505.h" + +#elif defined (__MSP430F5506__) +#include "msp430f5506.h" + +#elif defined (__MSP430F5507__) +#include "msp430f5507.h" + +#elif defined (__MSP430F5508__) +#include "msp430f5508.h" + +#elif defined (__MSP430F5509__) +#include "msp430f5509.h" + +#elif defined (__MSP430F5510__) +#include "msp430f5510.h" + +#elif defined (__MSP430F5513__) +#include "msp430f5513.h" + +#elif defined (__MSP430F5514__) +#include "msp430f5514.h" + +#elif defined (__MSP430F5515__) +#include "msp430f5515.h" + +#elif defined (__MSP430F5517__) +#include "msp430f5517.h" + +#elif defined (__MSP430F5519__) +#include "msp430f5519.h" + +#elif defined (__MSP430F5521__) +#include "msp430f5521.h" + +#elif defined (__MSP430F5522__) +#include "msp430f5522.h" + +#elif defined (__MSP430F5524__) +#include "msp430f5524.h" + +#elif defined (__MSP430F5525__) +#include "msp430f5525.h" + +#elif defined (__MSP430F5526__) +#include "msp430f5526.h" + +#elif defined (__MSP430F5527__) +#include "msp430f5527.h" + +#elif defined (__MSP430F5528__) +#include "msp430f5528.h" + +#elif defined (__MSP430F5529__) +#include "msp430f5529.h" + +#elif defined (__MSP430P112__) +#include "msp430p112.h" + +#elif defined (__MSP430P313__) +#include "msp430p313.h" + +#elif defined (__MSP430P315__) +#include "msp430p315.h" + +#elif defined (__MSP430P315S__) +#include "msp430p315s.h" + +#elif defined (__MSP430P325__) +#include "msp430p325.h" + +#elif defined (__MSP430P337__) +#include "msp430p337.h" + +#elif defined (__CC430F5133__) +#include "cc430f5133.h" + +#elif defined (__CC430F5135__) +#include "cc430f5135.h" + +#elif defined (__CC430F5137__) +#include "cc430f5137.h" + +#elif defined (__CC430F6125__) +#include "cc430f6125.h" + +#elif defined (__CC430F6126__) +#include "cc430f6126.h" + +#elif defined (__CC430F6127__) +#include "cc430f6127.h" + +#elif defined (__CC430F6135__) +#include "cc430f6135.h" + +#elif defined (__CC430F6137__) +#include "cc430f6137.h" + +#elif defined (__CC430F5123__) +#include "cc430f5123.h" + +#elif defined (__CC430F5125__) +#include "cc430f5125.h" + +#elif defined (__CC430F5143__) +#include "cc430f5143.h" + +#elif defined (__CC430F5145__) +#include "cc430f5145.h" + +#elif defined (__CC430F5147__) +#include "cc430f5147.h" + +#elif defined (__CC430F6143__) +#include "cc430f6143.h" + +#elif defined (__CC430F6145__) +#include "cc430f6145.h" + +#elif defined (__CC430F6147__) +#include "cc430f6147.h" + +#elif defined (__MSP430F5333__) +#include "msp430f5333.h" + +#elif defined (__MSP430F5335__) +#include "msp430f5335.h" + +#elif defined (__MSP430F5336__) +#include "msp430f5336.h" + +#elif defined (__MSP430F5338__) +#include "msp430f5338.h" + +#elif defined (__MSP430F5630__) +#include "msp430f5630.h" + +#elif defined (__MSP430F5631__) +#include "msp430f5631.h" + +#elif defined (__MSP430F5632__) +#include "msp430f5632.h" + +#elif defined (__MSP430F5633__) +#include "msp430f5633.h" + +#elif defined (__MSP430F5634__) +#include "msp430f5634.h" + +#elif defined (__MSP430F5635__) +#include "msp430f5635.h" + +#elif defined (__MSP430F5636__) +#include "msp430f5636.h" + +#elif defined (__MSP430F5637__) +#include "msp430f5637.h" + +#elif defined (__MSP430F5638__) +#include "msp430f5638.h" + +#elif defined (__MSP430F6433__) +#include "msp430f6433.h" + +#elif defined (__MSP430F6435__) +#include "msp430f6435.h" + +#elif defined (__MSP430F6436__) +#include "msp430f6436.h" + +#elif defined (__MSP430F6438__) +#include "msp430f6438.h" + +#elif defined (__MSP430F6630__) +#include "msp430f6630.h" + +#elif defined (__MSP430F6631__) +#include "msp430f6631.h" + +#elif defined (__MSP430F6632__) +#include "msp430f6632.h" + +#elif defined (__MSP430F6633__) +#include "msp430f6633.h" + +#elif defined (__MSP430F6634__) +#include "msp430f6634.h" + +#elif defined (__MSP430F6635__) +#include "msp430f6635.h" + +#elif defined (__MSP430F6636__) +#include "msp430f6636.h" + +#elif defined (__MSP430F6637__) +#include "msp430f6637.h" + +#elif defined (__MSP430F6638__) +#include "msp430f6638.h" + +#elif defined (__MSP430F5358__) +#include "msp430f5358.h" + +#elif defined (__MSP430F5359__) +#include "msp430f5359.h" + +#elif defined (__MSP430F5658__) +#include "msp430f5658.h" + +#elif defined (__MSP430F5659__) +#include "msp430f5659.h" + +#elif defined (__MSP430F6458__) +#include "msp430f6458.h" + +#elif defined (__MSP430F6459__) +#include "msp430f6459.h" + +#elif defined (__MSP430F6658__) +#include "msp430f6658.h" + +#elif defined (__MSP430F6659__) +#include "msp430f6659.h" + +#elif defined (__MSP430FG6425__) +#include "msp430fg6425.h" + +#elif defined (__MSP430FG6426__) +#include "msp430fg6426.h" + +#elif defined (__MSP430FG6625__) +#include "msp430fg6625.h" + +#elif defined (__MSP430FG6626__) +#include "msp430fg6626.h" + +#elif defined (__MSP430L092__) +#include "msp430l092.h" + +#elif defined (__MSP430C091__) +#include "msp430c091.h" + +#elif defined (__MSP430C092__) +#include "msp430c092.h" + +#elif defined (__MSP430F5131__) +#include "msp430f5131.h" + +#elif defined (__MSP430F5151__) +#include "msp430f5151.h" + +#elif defined (__MSP430F5171__) +#include "msp430f5171.h" + +#elif defined (__MSP430F5132__) +#include "msp430f5132.h" + +#elif defined (__MSP430F5152__) +#include "msp430f5152.h" + +#elif defined (__MSP430F5172__) +#include "msp430f5172.h" + +#elif defined (__MSP430F6720__) +#include "msp430f6720.h" + +#elif defined (__MSP430F6721__) +#include "msp430f6721.h" + +#elif defined (__MSP430F6723__) +#include "msp430f6723.h" + +#elif defined (__MSP430F6724__) +#include "msp430f6724.h" + +#elif defined (__MSP430F6725__) +#include "msp430f6725.h" + +#elif defined (__MSP430F6726__) +#include "msp430f6726.h" + +#elif defined (__MSP430F6730__) +#include "msp430f6730.h" + +#elif defined (__MSP430F6731__) +#include "msp430f6731.h" + +#elif defined (__MSP430F6733__) +#include "msp430f6733.h" + +#elif defined (__MSP430F6734__) +#include "msp430f6734.h" + +#elif defined (__MSP430F6735__) +#include "msp430f6735.h" + +#elif defined (__MSP430F6736__) +#include "msp430f6736.h" + +#elif defined (__MSP430F67621__) +#include "msp430f67621.h" + +#elif defined (__MSP430F67641__) +#include "msp430f67641.h" + +#elif defined (__MSP430F6720A__) +#include "msp430f6720a.h" + +#elif defined (__MSP430F6721A__) +#include "msp430f6721a.h" + +#elif defined (__MSP430F6723A__) +#include "msp430f6723a.h" + +#elif defined (__MSP430F6724A__) +#include "msp430f6724a.h" + +#elif defined (__MSP430F6725A__) +#include "msp430f6725a.h" + +#elif defined (__MSP430F6726A__) +#include "msp430f6726a.h" + +#elif defined (__MSP430F6730A__) +#include "msp430f6730a.h" + +#elif defined (__MSP430F6731A__) +#include "msp430f6731a.h" + +#elif defined (__MSP430F6733A__) +#include "msp430f6733a.h" + +#elif defined (__MSP430F6734A__) +#include "msp430f6734a.h" + +#elif defined (__MSP430F6735A__) +#include "msp430f6735a.h" + +#elif defined (__MSP430F6736A__) +#include "msp430f6736a.h" + +#elif defined (__MSP430F67621A__) +#include "msp430f67621a.h" + +#elif defined (__MSP430F67641A__) +#include "msp430f67641a.h" + +#elif defined (__MSP430F67451__) +#include "msp430f67451.h" + +#elif defined (__MSP430F67651__) +#include "msp430f67651.h" + +#elif defined (__MSP430F67751__) +#include "msp430f67751.h" + +#elif defined (__MSP430F67461__) +#include "msp430f67461.h" + +#elif defined (__MSP430F67661__) +#include "msp430f67661.h" + +#elif defined (__MSP430F67761__) +#include "msp430f67761.h" + +#elif defined (__MSP430F67471__) +#include "msp430f67471.h" + +#elif defined (__MSP430F67671__) +#include "msp430f67671.h" + +#elif defined (__MSP430F67771__) +#include "msp430f67771.h" + +#elif defined (__MSP430F67481__) +#include "msp430f67481.h" + +#elif defined (__MSP430F67681__) +#include "msp430f67681.h" + +#elif defined (__MSP430F67781__) +#include "msp430f67781.h" + +#elif defined (__MSP430F67491__) +#include "msp430f67491.h" + +#elif defined (__MSP430F67691__) +#include "msp430f67691.h" + +#elif defined (__MSP430F67791__) +#include "msp430f67791.h" + +#elif defined (__MSP430F6745__) +#include "msp430f6745.h" + +#elif defined (__MSP430F6765__) +#include "msp430f6765.h" + +#elif defined (__MSP430F6775__) +#include "msp430f6775.h" + +#elif defined (__MSP430F6746__) +#include "msp430f6746.h" + +#elif defined (__MSP430F6766__) +#include "msp430f6766.h" + +#elif defined (__MSP430F6776__) +#include "msp430f6776.h" + +#elif defined (__MSP430F6747__) +#include "msp430f6747.h" + +#elif defined (__MSP430F6767__) +#include "msp430f6767.h" + +#elif defined (__MSP430F6777__) +#include "msp430f6777.h" + +#elif defined (__MSP430F6748__) +#include "msp430f6748.h" + +#elif defined (__MSP430F6768__) +#include "msp430f6768.h" + +#elif defined (__MSP430F6778__) +#include "msp430f6778.h" + +#elif defined (__MSP430F6749__) +#include "msp430f6749.h" + +#elif defined (__MSP430F6769__) +#include "msp430f6769.h" + +#elif defined (__MSP430F6779__) +#include "msp430f6779.h" + +#elif defined (__MSP430F67451A__) +#include "msp430f67451a.h" + +#elif defined (__MSP430F67651A__) +#include "msp430f67651a.h" + +#elif defined (__MSP430F67751A__) +#include "msp430f67751a.h" + +#elif defined (__MSP430F67461A__) +#include "msp430f67461a.h" + +#elif defined (__MSP430F67661A__) +#include "msp430f67661a.h" + +#elif defined (__MSP430F67761A__) +#include "msp430f67761a.h" + +#elif defined (__MSP430F67471A__) +#include "msp430f67471a.h" + +#elif defined (__MSP430F67671A__) +#include "msp430f67671a.h" + +#elif defined (__MSP430F67771A__) +#include "msp430f67771a.h" + +#elif defined (__MSP430F67481A__) +#include "msp430f67481a.h" + +#elif defined (__MSP430F67681A__) +#include "msp430f67681a.h" + +#elif defined (__MSP430F67781A__) +#include "msp430f67781a.h" + +#elif defined (__MSP430F67491A__) +#include "msp430f67491a.h" + +#elif defined (__MSP430F67691A__) +#include "msp430f67691a.h" + +#elif defined (__MSP430F67791A__) +#include "msp430f67791a.h" + +#elif defined (__MSP430F6745A__) +#include "msp430f6745a.h" + +#elif defined (__MSP430F6765A__) +#include "msp430f6765a.h" + +#elif defined (__MSP430F6775A__) +#include "msp430f6775a.h" + +#elif defined (__MSP430F6746A__) +#include "msp430f6746a.h" + +#elif defined (__MSP430F6766A__) +#include "msp430f6766a.h" + +#elif defined (__MSP430F6776A__) +#include "msp430f6776a.h" + +#elif defined (__MSP430F6747A__) +#include "msp430f6747a.h" + +#elif defined (__MSP430F6767A__) +#include "msp430f6767a.h" + +#elif defined (__MSP430F6777A__) +#include "msp430f6777a.h" + +#elif defined (__MSP430F6748A__) +#include "msp430f6748a.h" + +#elif defined (__MSP430F6768A__) +#include "msp430f6768a.h" + +#elif defined (__MSP430F6778A__) +#include "msp430f6778a.h" + +#elif defined (__MSP430F6749A__) +#include "msp430f6749a.h" + +#elif defined (__MSP430F6769A__) +#include "msp430f6769a.h" + +#elif defined (__MSP430F6779A__) +#include "msp430f6779a.h" + +#elif defined (__MSP430FR5720__) +#include "msp430fr5720.h" + +#elif defined (__MSP430FR5721__) +#include "msp430fr5721.h" + +#elif defined (__MSP430FR5722__) +#include "msp430fr5722.h" + +#elif defined (__MSP430FR5723__) +#include "msp430fr5723.h" + +#elif defined (__MSP430FR5724__) +#include "msp430fr5724.h" + +#elif defined (__MSP430FR5725__) +#include "msp430fr5725.h" + +#elif defined (__MSP430FR5726__) +#include "msp430fr5726.h" + +#elif defined (__MSP430FR5727__) +#include "msp430fr5727.h" + +#elif defined (__MSP430FR5728__) +#include "msp430fr5728.h" + +#elif defined (__MSP430FR5729__) +#include "msp430fr5729.h" + +#elif defined (__MSP430FR5730__) +#include "msp430fr5730.h" + +#elif defined (__MSP430FR5731__) +#include "msp430fr5731.h" + +#elif defined (__MSP430FR5732__) +#include "msp430fr5732.h" + +#elif defined (__MSP430FR5733__) +#include "msp430fr5733.h" + +#elif defined (__MSP430FR5734__) +#include "msp430fr5734.h" + +#elif defined (__MSP430FR5735__) +#include "msp430fr5735.h" + +#elif defined (__MSP430FR5736__) +#include "msp430fr5736.h" + +#elif defined (__MSP430FR5737__) +#include "msp430fr5737.h" + +#elif defined (__MSP430FR5738__) +#include "msp430fr5738.h" + +#elif defined (__MSP430FR5739__) +#include "msp430fr5739.h" + +#elif defined (__MSP430G2211__) +#include "msp430g2211.h" + +#elif defined (__MSP430G2201__) +#include "msp430g2201.h" + +#elif defined (__MSP430G2111__) +#include "msp430g2111.h" + +#elif defined (__MSP430G2101__) +#include "msp430g2101.h" + +#elif defined (__MSP430G2001__) +#include "msp430g2001.h" + +#elif defined (__MSP430G2231__) +#include "msp430g2231.h" + +#elif defined (__MSP430G2221__) +#include "msp430g2221.h" + +#elif defined (__MSP430G2131__) +#include "msp430g2131.h" + +#elif defined (__MSP430G2121__) +#include "msp430g2121.h" + +#elif defined (__MSP430AFE221__) +#include "msp430afe221.h" + +#elif defined (__MSP430AFE231__) +#include "msp430afe231.h" + +#elif defined (__MSP430AFE251__) +#include "msp430afe251.h" + +#elif defined (__MSP430AFE222__) +#include "msp430afe222.h" + +#elif defined (__MSP430AFE232__) +#include "msp430afe232.h" + +#elif defined (__MSP430AFE252__) +#include "msp430afe252.h" + +#elif defined (__MSP430AFE223__) +#include "msp430afe223.h" + +#elif defined (__MSP430AFE233__) +#include "msp430afe233.h" + +#elif defined (__MSP430AFE253__) +#include "msp430afe253.h" + +#elif defined (__MSP430G2102__) +#include "msp430g2102.h" + +#elif defined (__MSP430G2202__) +#include "msp430g2202.h" + +#elif defined (__MSP430G2302__) +#include "msp430g2302.h" + +#elif defined (__MSP430G2402__) +#include "msp430g2402.h" + +#elif defined (__MSP430G2132__) +#include "msp430g2132.h" + +#elif defined (__MSP430G2232__) +#include "msp430g2232.h" + +#elif defined (__MSP430G2332__) +#include "msp430g2332.h" + +#elif defined (__MSP430G2432__) +#include "msp430g2432.h" + +#elif defined (__MSP430G2112__) +#include "msp430g2112.h" + +#elif defined (__MSP430G2212__) +#include "msp430g2212.h" + +#elif defined (__MSP430G2312__) +#include "msp430g2312.h" + +#elif defined (__MSP430G2412__) +#include "msp430g2412.h" + +#elif defined (__MSP430G2152__) +#include "msp430g2152.h" + +#elif defined (__MSP430G2252__) +#include "msp430g2252.h" + +#elif defined (__MSP430G2352__) +#include "msp430g2352.h" + +#elif defined (__MSP430G2452__) +#include "msp430g2452.h" + +#elif defined (__MSP430G2113__) +#include "msp430g2113.h" + +#elif defined (__MSP430G2213__) +#include "msp430g2213.h" + +#elif defined (__MSP430G2313__) +#include "msp430g2313.h" + +#elif defined (__MSP430G2413__) +#include "msp430g2413.h" + +#elif defined (__MSP430G2513__) +#include "msp430g2513.h" + +#elif defined (__MSP430G2153__) +#include "msp430g2153.h" + +#elif defined (__MSP430G2253__) +#include "msp430g2253.h" + +#elif defined (__MSP430G2353__) +#include "msp430g2353.h" + +#elif defined (__MSP430G2453__) +#include "msp430g2453.h" + +#elif defined (__MSP430G2553__) +#include "msp430g2553.h" + +#elif defined (__MSP430G2203__) +#include "msp430g2203.h" + +#elif defined (__MSP430G2303__) +#include "msp430g2303.h" + +#elif defined (__MSP430G2403__) +#include "msp430g2403.h" + +#elif defined (__MSP430G2233__) +#include "msp430g2233.h" + +#elif defined (__MSP430G2333__) +#include "msp430g2333.h" + +#elif defined (__MSP430G2433__) +#include "msp430g2433.h" + +#elif defined (__MSP430G2533__) +#include "msp430g2533.h" + +#elif defined (__MSP430TCH5E__) +#include "msp430tch5e.h" + +#elif defined (__MSP430G2444__) +#include "msp430g2444.h" + +#elif defined (__MSP430G2544__) +#include "msp430g2544.h" + +#elif defined (__MSP430G2744__) +#include "msp430g2744.h" + +#elif defined (__MSP430G2755__) +#include "msp430g2755.h" + +#elif defined (__MSP430G2855__) +#include "msp430g2855.h" + +#elif defined (__MSP430G2955__) +#include "msp430g2955.h" + +#elif defined (__MSP430G2230__) +#include "msp430g2230.h" + +#elif defined (__MSP430G2210__) +#include "msp430g2210.h" + +#elif defined (__MSP430BT5190__) +#include "msp430bt5190.h" + +#elif defined (__MSP430FR5857__) +#include "msp430fr5857.h" + +#elif defined (__MSP430FR5858__) +#include "msp430fr5858.h" + +#elif defined (__MSP430FR5859__) +#include "msp430fr5859.h" + +#elif defined (__MSP430FR5847__) +#include "msp430fr5847.h" + +#elif defined (__MSP430FR58471__) +#include "msp430fr58471.h" + +#elif defined (__MSP430FR5848__) +#include "msp430fr5848.h" + +#elif defined (__MSP430FR5849__) +#include "msp430fr5849.h" + +#elif defined (__MSP430FR5867__) +#include "msp430fr5867.h" + +#elif defined (__MSP430FR58671__) +#include "msp430fr58671.h" + +#elif defined (__MSP430FR5868__) +#include "msp430fr5868.h" + +#elif defined (__MSP430FR5869__) +#include "msp430fr5869.h" + +#elif defined (__MSP430FR5957__) +#include "msp430fr5957.h" + +#elif defined (__MSP430FR5958__) +#include "msp430fr5958.h" + +#elif defined (__MSP430FR5959__) +#include "msp430fr5959.h" + +#elif defined (__MSP430FR5947__) +#include "msp430fr5947.h" + +#elif defined (__MSP430FR59471__) +#include "msp430fr59471.h" + +#elif defined (__MSP430FR5948__) +#include "msp430fr5948.h" + +#elif defined (__MSP430FR5949__) +#include "msp430fr5949.h" + +#elif defined (__MSP430FR5967__) +#include "msp430fr5967.h" + +#elif defined (__MSP430FR5968__) +#include "msp430fr5968.h" + +#elif defined (__MSP430FR5969__) +#include "msp430fr5969.h" + +#elif defined (__MSP430FR59691__) +#include "msp430fr59691.h" + +#elif defined (__MSP430FR5962__) +#include "msp430fr5962.h" + +#elif defined (__MSP430FR5964__) +#include "msp430fr5964.h" + +#elif defined (__MSP430FR5992__) +#include "msp430fr5992.h" + +#elif defined (__MSP430FR5994__) +#include "msp430fr5994.h" + +#elif defined (__MSP430FR59941__) +#include "msp430fr59941.h" + +#elif defined (__MSP430i2020__) +#include "msp430i2020.h" + +#elif defined (__MSP430i2021__) +#include "msp430i2021.h" + +#elif defined (__MSP430i2030__) +#include "msp430i2030.h" + +#elif defined (__MSP430i2031__) +#include "msp430i2031.h" + +#elif defined (__MSP430i2040__) +#include "msp430i2040.h" + +#elif defined (__MSP430i2041__) +#include "msp430i2041.h" + +#elif defined (__RF430FRL152H__) +#include "rf430frl152h.h" + +#elif defined (__RF430FRL153H__) +#include "rf430frl153h.h" + +#elif defined (__RF430FRL154H__) +#include "rf430frl154h.h" + +#elif defined (__RF430FRL152H_ROM__) +#include "rf430frl152h_rom.h" + +#elif defined (__RF430FRL153H_ROM__) +#include "rf430frl153h_rom.h" + +#elif defined (__RF430FRL154H_ROM__) +#include "rf430frl154h_rom.h" + +#elif defined (__RF430F5175__) +#include "rf430f5175.h" + +#elif defined (__RF430F5155__) +#include "rf430f5155.h" + +#elif defined (__RF430F5144__) +#include "rf430f5144.h" + +#elif defined (__MSP430FR69271__) +#include "msp430fr69271.h" + +#elif defined (__MSP430FR68791__) +#include "msp430fr68791.h" + +#elif defined (__MSP430FR69791__) +#include "msp430fr69791.h" + +#elif defined (__MSP430FR6927__) +#include "msp430fr6927.h" + +#elif defined (__MSP430FR6928__) +#include "msp430fr6928.h" + +#elif defined (__MSP430FR6877__) +#include "msp430fr6877.h" + +#elif defined (__MSP430FR6977__) +#include "msp430fr6977.h" + +#elif defined (__MSP430FR6879__) +#include "msp430fr6879.h" + +#elif defined (__MSP430FR6979__) +#include "msp430fr6979.h" + +#elif defined (__MSP430FR58891__) +#include "msp430fr58891.h" + +#elif defined (__MSP430FR68891__) +#include "msp430fr68891.h" + +#elif defined (__MSP430FR59891__) +#include "msp430fr59891.h" + +#elif defined (__MSP430FR69891__) +#include "msp430fr69891.h" + +#elif defined (__MSP430FR5887__) +#include "msp430fr5887.h" + +#elif defined (__MSP430FR5888__) +#include "msp430fr5888.h" + +#elif defined (__MSP430FR5889__) +#include "msp430fr5889.h" + +#elif defined (__MSP430FR6887__) +#include "msp430fr6887.h" + +#elif defined (__MSP430FR6888__) +#include "msp430fr6888.h" + +#elif defined (__MSP430FR6889__) +#include "msp430fr6889.h" + +#elif defined (__MSP430FR5986__) +#include "msp430fr5986.h" + +#elif defined (__MSP430FR5987__) +#include "msp430fr5987.h" + +#elif defined (__MSP430FR5988__) +#include "msp430fr5988.h" + +#elif defined (__MSP430FR5989__) +#include "msp430fr5989.h" + +#elif defined (__MSP430FR6987__) +#include "msp430fr6987.h" + +#elif defined (__MSP430FR6988__) +#include "msp430fr6988.h" + +#elif defined (__MSP430FR6989__) +#include "msp430fr6989.h" + +#elif defined (__MSP430FR5922__) +#include "msp430fr5922.h" + +#elif defined (__MSP430FR5870__) +#include "msp430fr5870.h" + +#elif defined (__MSP430FR5970__) +#include "msp430fr5970.h" + +#elif defined (__MSP430FR5872__) +#include "msp430fr5872.h" + +#elif defined (__MSP430FR5972__) +#include "msp430fr5972.h" + +#elif defined (__MSP430FR6820__) +#include "msp430fr6820.h" + +#elif defined (__MSP430FR6920__) +#include "msp430fr6920.h" + +#elif defined (__MSP430FR6822__) +#include "msp430fr6822.h" + +#elif defined (__MSP430FR6922__) +#include "msp430fr6922.h" + +#elif defined (__MSP430FR6870__) +#include "msp430fr6870.h" + +#elif defined (__MSP430FR6970__) +#include "msp430fr6970.h" + +#elif defined (__MSP430FR6872__) +#include "msp430fr6872.h" + +#elif defined (__MSP430FR6972__) +#include "msp430fr6972.h" + +#elif defined (__MSP430FR59221__) +#include "msp430fr59221.h" + +#elif defined (__MSP430FR58721__) +#include "msp430fr58721.h" + +#elif defined (__MSP430FR59721__) +#include "msp430fr59721.h" + +#elif defined (__MSP430FR68221__) +#include "msp430fr68221.h" + +#elif defined (__MSP430FR69221__) +#include "msp430fr69221.h" + +#elif defined (__MSP430FR68721__) +#include "msp430fr68721.h" + +#elif defined (__MSP430FR69721__) +#include "msp430fr69721.h" + +#elif defined (__MSP430SL5438A__) +#include "msp430sl5438a.h" + +#elif defined (__MSP430FR4131__) +#include "msp430fr4131.h" + +#elif defined (__MSP430FR4132__) +#include "msp430fr4132.h" + +#elif defined (__MSP430FR4133__) +#include "msp430fr4133.h" + +#elif defined (__MSP430FR2032__) +#include "msp430fr2032.h" + +#elif defined (__MSP430FR2033__) +#include "msp430fr2033.h" + +#elif defined (__MSP430FR2000__) +#include "msp430fr2000.h" + +#elif defined (__MSP430FR2100__) +#include "msp430fr2100.h" + +#elif defined (__MSP430FR2110__) +#include "msp430fr2110.h" + +#elif defined (__MSP430FR2111__) +#include "msp430fr2111.h" + +#elif defined (__MSP430FR2310__) +#include "msp430fr2310.h" + +#elif defined (__MSP430FR2311__) +#include "msp430fr2311.h" + +#elif defined (__MSP430FR2422__) +#include "msp430fr2422.h" + +#elif defined (__MSP430FR2433__) +#include "msp430fr2433.h" + +#elif defined (__MSP430FR2512__) +#include "msp430fr2512.h" + +#elif defined (__MSP430FR2522__) +#include "msp430fr2522.h" + +#elif defined (__MSP430FR2532__) +#include "msp430fr2532.h" + +#elif defined (__MSP430FR2533__) +#include "msp430fr2533.h" + +#elif defined (__MSP430FR2632__) +#include "msp430fr2632.h" + +#elif defined (__MSP430FR2633__) +#include "msp430fr2633.h" + +#elif defined (__MSP430F5252__) +#include "msp430f5252.h" + +#elif defined (__MSP430F5253__) +#include "msp430f5253.h" + +#elif defined (__MSP430F5254__) +#include "msp430f5254.h" + +#elif defined (__MSP430F5255__) +#include "msp430f5255.h" + +#elif defined (__MSP430F5256__) +#include "msp430f5256.h" + +#elif defined (__MSP430F5257__) +#include "msp430f5257.h" + +#elif defined (__MSP430F5258__) +#include "msp430f5258.h" + +#elif defined (__MSP430F5259__) +#include "msp430f5259.h" + +#elif defined (__MSP430FR6035__) +#include "msp430fr6035.h" + +#elif defined (__MSP430FR6037__) +#include "msp430fr6037.h" + +#elif defined (__MSP430FR60371__) +#include "msp430fr60371.h" + +#elif defined (__MSP430FR6045__) +#include "msp430fr6045.h" + +#elif defined (__MSP430FR6047__) +#include "msp430fr6047.h" + +#elif defined (__MSP430FR60471__) +#include "msp430fr60471.h" + +#elif defined (__MSP430FR5041__) +#include "msp430fr5041.h" + +#elif defined (__MSP430FR5043__) +#include "msp430fr5043.h" + +#elif defined (__MSP430FR50431__) +#include "msp430fr50431.h" + +#elif defined (__MSP430FR6041__) +#include "msp430fr6041.h" + +#elif defined (__MSP430FR6043__) +#include "msp430fr6043.h" + +#elif defined (__MSP430FR60431__) +#include "msp430fr60431.h" + +#elif defined (__MSP430FR2153__) +#include "msp430fr2153.h" + +#elif defined (__MSP430FR2155__) +#include "msp430fr2155.h" + +#elif defined (__MSP430FR2353__) +#include "msp430fr2353.h" + +#elif defined (__MSP430FR2355__) +#include "msp430fr2355.h" + +#elif defined (__MSP430FR2475__) +#include "msp430fr2475.h" + +#elif defined (__MSP430FR2476__) +#include "msp430fr2476.h" + +#elif defined (__MSP430FR2675__) +#include "msp430fr2675.h" + +#elif defined (__MSP430FR2676__) +#include "msp430fr2676.h" + +#elif defined (__MSP430XGENERIC__) +#include "msp430xgeneric.h" + +#elif defined (__MSP430F5XX_6XXGENERIC__) +#include "msp430f5xx_6xxgeneric.h" + +#elif defined (__MSP430FR5XX_6XXGENERIC__) +#include "msp430fr5xx_6xxgeneric.h" + +#elif defined (__MSP430FR2XX_4XXGENERIC__) +#include "msp430fr2xx_4xxgeneric.h" + +#elif defined (__MSP430FR57XXGENERIC__) +#include "msp430fr57xxgeneric.h" + +#elif defined (__MSP430I2XXGENERIC__) +#include "msp430i2xxgeneric.h" + +/******************************************************************** + * msp430 generic + ********************************************************************/ +#elif defined (__MSP430GENERIC__) +#error "msp430 generic device does not have a default include file" + +#elif defined (__MSP430XGENERIC__) +#error "msp430X generic device does not have a default include file" + + +/******************************************************************** + * + ********************************************************************/ +#else +#error "Failed to match a default include file" +#endif + +#endif /* #ifndef __msp430 */ + diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529.h b/hw/bsp/msp_exp430f5529lp/msp430f5529.h new file mode 100644 index 000000000..e7e5d31fa --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/msp430f5529.h @@ -0,0 +1,4789 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430F5529 devices. +* +* Texas Instruments, Version 1.4 +* +* Rev. 1.0, Setup +* Rev. 1.1, Fixed Error in DMA Trigger Definitons +* Rev. 1.2, fixed SYSUNIV_BUSIFG definition +* fixed wrong bit definition in PM5CTL0 (LOCKLPM5) +* Rev. 1.3, Changed access type of DMAxSZ registers to word only +* Rev. 1.4 Changed access type of TimerA/B registers to word only +* +********************************************************************/ + +#ifndef __MSP430F5529 +#define __MSP430F5529 + +#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ +#define __MSP430F5XX_6XX_FAMILY__ + +#define __MSP430_HEADER_VERSION__ 1207 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#define __MSP430_TI_HEADERS__ + +#include + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* ADC12 PLUS +************************************************************/ +#define __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_ADC12_PLUS__ 0x0700 +#define ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__ + +sfr_w(ADC12CTL0); /* ADC12+ Control 0 */ +sfr_b(ADC12CTL0_L); /* ADC12+ Control 0 */ +sfr_b(ADC12CTL0_H); /* ADC12+ Control 0 */ +sfr_w(ADC12CTL1); /* ADC12+ Control 1 */ +sfr_b(ADC12CTL1_L); /* ADC12+ Control 1 */ +sfr_b(ADC12CTL1_H); /* ADC12+ Control 1 */ +sfr_w(ADC12CTL2); /* ADC12+ Control 2 */ +sfr_b(ADC12CTL2_L); /* ADC12+ Control 2 */ +sfr_b(ADC12CTL2_H); /* ADC12+ Control 2 */ +sfr_w(ADC12IFG); /* ADC12+ Interrupt Flag */ +sfr_b(ADC12IFG_L); /* ADC12+ Interrupt Flag */ +sfr_b(ADC12IFG_H); /* ADC12+ Interrupt Flag */ +sfr_w(ADC12IE); /* ADC12+ Interrupt Enable */ +sfr_b(ADC12IE_L); /* ADC12+ Interrupt Enable */ +sfr_b(ADC12IE_H); /* ADC12+ Interrupt Enable */ +sfr_w(ADC12IV); /* ADC12+ Interrupt Vector Word */ +sfr_b(ADC12IV_L); /* ADC12+ Interrupt Vector Word */ +sfr_b(ADC12IV_H); /* ADC12+ Interrupt Vector Word */ + +sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ +sfr_b(ADC12MEM0_L); /* ADC12 Conversion Memory 0 */ +sfr_b(ADC12MEM0_H); /* ADC12 Conversion Memory 0 */ +sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ +sfr_b(ADC12MEM1_L); /* ADC12 Conversion Memory 1 */ +sfr_b(ADC12MEM1_H); /* ADC12 Conversion Memory 1 */ +sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ +sfr_b(ADC12MEM2_L); /* ADC12 Conversion Memory 2 */ +sfr_b(ADC12MEM2_H); /* ADC12 Conversion Memory 2 */ +sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ +sfr_b(ADC12MEM3_L); /* ADC12 Conversion Memory 3 */ +sfr_b(ADC12MEM3_H); /* ADC12 Conversion Memory 3 */ +sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ +sfr_b(ADC12MEM4_L); /* ADC12 Conversion Memory 4 */ +sfr_b(ADC12MEM4_H); /* ADC12 Conversion Memory 4 */ +sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ +sfr_b(ADC12MEM5_L); /* ADC12 Conversion Memory 5 */ +sfr_b(ADC12MEM5_H); /* ADC12 Conversion Memory 5 */ +sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ +sfr_b(ADC12MEM6_L); /* ADC12 Conversion Memory 6 */ +sfr_b(ADC12MEM6_H); /* ADC12 Conversion Memory 6 */ +sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ +sfr_b(ADC12MEM7_L); /* ADC12 Conversion Memory 7 */ +sfr_b(ADC12MEM7_H); /* ADC12 Conversion Memory 7 */ +sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ +sfr_b(ADC12MEM8_L); /* ADC12 Conversion Memory 8 */ +sfr_b(ADC12MEM8_H); /* ADC12 Conversion Memory 8 */ +sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ +sfr_b(ADC12MEM9_L); /* ADC12 Conversion Memory 9 */ +sfr_b(ADC12MEM9_H); /* ADC12 Conversion Memory 9 */ +sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ +sfr_b(ADC12MEM10_L); /* ADC12 Conversion Memory 10 */ +sfr_b(ADC12MEM10_H); /* ADC12 Conversion Memory 10 */ +sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ +sfr_b(ADC12MEM11_L); /* ADC12 Conversion Memory 11 */ +sfr_b(ADC12MEM11_H); /* ADC12 Conversion Memory 11 */ +sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ +sfr_b(ADC12MEM12_L); /* ADC12 Conversion Memory 12 */ +sfr_b(ADC12MEM12_H); /* ADC12 Conversion Memory 12 */ +sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ +sfr_b(ADC12MEM13_L); /* ADC12 Conversion Memory 13 */ +sfr_b(ADC12MEM13_H); /* ADC12 Conversion Memory 13 */ +sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ +sfr_b(ADC12MEM14_L); /* ADC12 Conversion Memory 14 */ +sfr_b(ADC12MEM14_H); /* ADC12 Conversion Memory 14 */ +sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ +sfr_b(ADC12MEM15_L); /* ADC12 Conversion Memory 15 */ +sfr_b(ADC12MEM15_H); /* ADC12 Conversion Memory 15 */ +#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ +#ifndef __STDC__ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((volatile int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ +#endif + +sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ +sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ +sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ +sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ +sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ +sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ +sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ +sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ +sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ +sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ +sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ +sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ +sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ +sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ +sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ +sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ +#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ +#ifndef __STDC__ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((volatile char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ +#endif + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x0010) /* ADC12 On/enable */ +#define ADC12REFON (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON_L (0x0010) /* ADC12 On/enable */ +#define ADC12REFON_L (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */ + +#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ + +#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */ +#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF_L (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */ + +#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ + +#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ + +#define ADC12SREF_0 (0x0000) /* ADC12 Select Reference 0 */ +#define ADC12SREF_1 (0x0010) /* ADC12 Select Reference 1 */ +#define ADC12SREF_2 (0x0020) /* ADC12 Select Reference 2 */ +#define ADC12SREF_3 (0x0030) /* ADC12 Select Reference 3 */ +#define ADC12SREF_4 (0x0040) /* ADC12 Select Reference 4 */ +#define ADC12SREF_5 (0x0050) /* ADC12 Select Reference 5 */ +#define ADC12SREF_6 (0x0060) /* ADC12 Select Reference 6 */ +#define ADC12SREF_7 (0x0070) /* ADC12 Select Reference 7 */ + +#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ + +#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ + +#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ + +#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +/************************************************************ +* Comparator B +************************************************************/ +#define __MSP430_HAS_COMPB__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_COMPB__ 0x08C0 +#define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ + +sfr_w(CBCTL0); /* Comparator B Control Register 0 */ +sfr_b(CBCTL0_L); /* Comparator B Control Register 0 */ +sfr_b(CBCTL0_H); /* Comparator B Control Register 0 */ +sfr_w(CBCTL1); /* Comparator B Control Register 1 */ +sfr_b(CBCTL1_L); /* Comparator B Control Register 1 */ +sfr_b(CBCTL1_H); /* Comparator B Control Register 1 */ +sfr_w(CBCTL2); /* Comparator B Control Register 2 */ +sfr_b(CBCTL2_L); /* Comparator B Control Register 2 */ +sfr_b(CBCTL2_H); /* Comparator B Control Register 2 */ +sfr_w(CBCTL3); /* Comparator B Control Register 3 */ +sfr_b(CBCTL3_L); /* Comparator B Control Register 3 */ +sfr_b(CBCTL3_H); /* Comparator B Control Register 3 */ +sfr_w(CBINT); /* Comparator B Interrupt Register */ +sfr_b(CBINT_L); /* Comparator B Interrupt Register */ +sfr_b(CBINT_H); /* Comparator B Interrupt Register */ +sfr_w(CBIV); /* Comparator B Interrupt Vector Word */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */ +#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ + +/* CBCTL0 Control Bits */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */ + +#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */ +#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */ +#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */ +#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */ +#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */ +#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */ +#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */ +#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */ +#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */ +#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */ +#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */ +#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */ +#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */ +#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */ +#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */ +#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */ + +#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */ +#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */ +#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */ +#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */ +#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */ +#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */ +#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */ +#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */ +#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */ +#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */ +#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */ +#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */ +#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */ +#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */ +#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */ +#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */ + +/* CBCTL1 Control Bits */ +#define CBOUT (0x0001) /* Comp. B Output */ +#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */ +#define CBF (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT (0x0010) /* Comp. B Input Short */ +#define CBEX (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */ +#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */ +#define CBON (0x0400) /* Comp. B enable */ +#define CBMRVL (0x0800) /* Comp. B CBMRV Level */ +#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBOUT_L (0x0001) /* Comp. B Output */ +#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */ +#define CBF_L (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT_L (0x0010) /* Comp. B Input Short */ +#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */ +#define CBON_H (0x0004) /* Comp. B enable */ +#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */ +#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */ +#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */ +#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */ +#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */ + +#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */ +#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */ +#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/ +#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */ + +/* CBCTL2 Control Bits */ +#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL (0x0020) /* Comp. B Reference select */ +#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */ +#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */ + +/* CBCTL2 Control Bits */ +#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL_L (0x0020) /* Comp. B Reference select */ +#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */ + +/* CBCTL2 Control Bits */ +#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */ + +#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ +#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ +#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ +#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ +#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ +#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ +#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ +#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ +#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ +#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ +#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ +#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ +#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ +#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ +#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ +#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ +#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ +#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ +#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ +#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ +#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ +#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ +#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ +#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ +#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ +#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ +#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ +#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ +#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ +#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ +#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ +#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ + +#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */ +#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */ +#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */ +#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */ + +#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ +#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ +#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ +#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ +#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ +#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ +#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ +#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ +#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ +#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ +#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ +#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ +#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ +#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ +#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ +#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ +#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ +#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ +#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ +#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ +#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ +#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ +#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ +#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ +#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ +#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ +#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ +#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ +#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ +#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ +#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ +#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ + +#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */ +#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */ +#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */ +#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */ + +#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ +#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */ + +#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ + +#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */ + +/* CBINT Control Bits */ +#define CBIFG (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE (0x0100) /* Comp. B Interrupt Enable */ +#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */ +#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBIV Definitions */ +#define CBIV_NONE (0x0000) /* No Interrupt pending */ +#define CBIV_CBIFG (0x0002) /* CBIFG */ +#define CBIV_CBIIFG (0x0004) /* CBIIFG */ + +/************************************************************* +* CRC Module +*************************************************************/ +#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_CRC__ 0x0150 +#define CRC_BASE __MSP430_BASEADDRESS_CRC__ + +sfr_w(CRCDI); /* CRC Data In Register */ +sfr_b(CRCDI_L); /* CRC Data In Register */ +sfr_b(CRCDI_H); /* CRC Data In Register */ +sfr_w(CRCDIRB); /* CRC data in reverse byte Register */ +sfr_b(CRCDIRB_L); /* CRC data in reverse byte Register */ +sfr_b(CRCDIRB_H); /* CRC data in reverse byte Register */ +sfr_w(CRCINIRES); /* CRC Initialisation Register and Result Register */ +sfr_b(CRCINIRES_L); /* CRC Initialisation Register and Result Register */ +sfr_b(CRCINIRES_H); /* CRC Initialisation Register and Result Register */ +sfr_w(CRCRESR); /* CRC reverse result Register */ +sfr_b(CRCRESR_L); /* CRC reverse result Register */ +sfr_b(CRCRESR_H); /* CRC reverse result Register */ + +/************************************************************ +* DMA_X +************************************************************/ +#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500 +#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ + +sfr_w(DMACTL0); /* DMA Module Control 0 */ +sfr_w(DMACTL1); /* DMA Module Control 1 */ +sfr_w(DMACTL2); /* DMA Module Control 2 */ +sfr_w(DMACTL3); /* DMA Module Control 3 */ +sfr_w(DMACTL4); /* DMA Module Control 4 */ +sfr_w(DMAIV); /* DMA Interrupt Vector Word */ + +sfr_w(DMA0CTL); /* DMA Channel 0 Control */ +sfr_l(DMA0SA); /* DMA Channel 0 Source Address */ +sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */ +sfr_w(DMA0SAH); /* DMA Channel 0 Source Address */ +sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0DAH); /* DMA Channel 0 Destination Address */ +sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ + +sfr_w(DMA1CTL); /* DMA Channel 1 Control */ +sfr_l(DMA1SA); /* DMA Channel 1 Source Address */ +sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */ +sfr_w(DMA1SAH); /* DMA Channel 1 Source Address */ +sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1DAH); /* DMA Channel 1 Destination Address */ +sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ + +sfr_w(DMA2CTL); /* DMA Channel 2 Control */ +sfr_l(DMA2SA); /* DMA Channel 2 Source Address */ +sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */ +sfr_w(DMA2SAH); /* DMA Channel 2 Source Address */ +sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2DAH); /* DMA Channel 2 Destination Address */ +sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ +#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ +#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ +#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ +#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ +#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ +#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ +#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ +#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ +#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ +#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ +#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ +#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ +#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ +#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ +#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: USB ready */ +#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ +#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ +#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ +#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ +#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ +#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ +#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ +#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ +#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ +#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ +#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ +#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ +#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ +#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ +#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ +#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ +#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ +#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ +#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ +#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ +#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ +#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ +#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ +#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ +#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ +#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ +#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ +#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ +#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ +#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ +#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ +#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ +#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ +#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ +#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ +#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ +#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ +#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ +#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ +#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ +#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ +#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: USB ready */ +#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ +#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA0TSEL__DMA_REQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA0TSEL__TA2CCR2 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ +#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ +#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ +#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ +#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ +#define DMA0TSEL__RES14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ +#define DMA0TSEL__RES15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ +#define DMA0TSEL__USCIA0RX (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ +#define DMA0TSEL__USCIA0TX (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ +#define DMA0TSEL__USCIB0RX (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ +#define DMA0TSEL__USCIB0TX (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ +#define DMA0TSEL__USCIA1RX (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ +#define DMA0TSEL__USCIA1TX (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ +#define DMA0TSEL__USCIB1RX (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ +#define DMA0TSEL__USCIB1TX (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ +#define DMA0TSEL__ADC12IFG (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ +#define DMA0TSEL__RES25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ +#define DMA0TSEL__RES26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ +#define DMA0TSEL__USB_FNRXD (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ +#define DMA0TSEL__USB_READY (0x001C) /* DMA channel 0 transfer select 28: USB ready */ +#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ +#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL__DMA_REQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA1TSEL__TA2CCR2 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ +#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ +#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ +#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ +#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ +#define DMA1TSEL__RES14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ +#define DMA1TSEL__RES15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ +#define DMA1TSEL__USCIA0RX (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ +#define DMA1TSEL__USCIA0TX (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ +#define DMA1TSEL__USCIB0RX (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ +#define DMA1TSEL__USCIB0TX (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ +#define DMA1TSEL__USCIA1RX (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ +#define DMA1TSEL__USCIA1TX (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ +#define DMA1TSEL__USCIB1RX (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ +#define DMA1TSEL__USCIB1TX (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ +#define DMA1TSEL__ADC12IFG (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ +#define DMA1TSEL__RES25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ +#define DMA1TSEL__RES26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ +#define DMA1TSEL__USB_FNRXD (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ +#define DMA1TSEL__USB_READY (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ +#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ +#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL__DMA_REQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA2TSEL__TA2CCR2 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ +#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ +#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ +#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ +#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ +#define DMA2TSEL__RES14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ +#define DMA2TSEL__RES15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ +#define DMA2TSEL__USCIA0RX (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ +#define DMA2TSEL__USCIA0TX (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ +#define DMA2TSEL__USCIB0RX (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ +#define DMA2TSEL__USCIB0TX (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ +#define DMA2TSEL__USCIA1RX (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ +#define DMA2TSEL__USCIA1TX (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ +#define DMA2TSEL__USCIB1RX (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ +#define DMA2TSEL__USCIB1TX (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ +#define DMA2TSEL__ADC12IFG (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ +#define DMA2TSEL__RES25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ +#define DMA2TSEL__RES26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ +#define DMA2TSEL__USB_FNRXD (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ +#define DMA2TSEL__USB_READY (0x001C) /* DMA channel 2 transfer select 28: USB ready */ +#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ +#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_FLASH__ 0x0140 +#define FLASH_BASE __MSP430_BASEADDRESS_FLASH__ + +sfr_w(FCTL1); /* FLASH Control 1 */ +sfr_b(FCTL1_L); /* FLASH Control 1 */ +sfr_b(FCTL1_H); /* FLASH Control 1 */ +//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */ +sfr_w(FCTL3); /* FLASH Control 3 */ +sfr_b(FCTL3_L); /* FLASH Control 3 */ +sfr_b(FCTL3_H); /* FLASH Control 3 */ +sfr_w(FCTL4); /* FLASH Control 4 */ +sfr_b(FCTL4_L); /* FLASH Control 4 */ +sfr_b(FCTL4_H); /* FLASH Control 4 */ + +#define FRPW (0x9600) /* Flash password returned by read */ +#define FWPW (0xA500) /* Flash password for write */ +#define FXPW (0x3300) /* for use with XOR instruction */ +#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */ +#define FWKEY (0xA500) /* (legacy definition) Flash key for write */ +#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT (0x0020) /* Smart Write enable */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT_L (0x0020) /* Smart Write enable */ +#define WRT_L (0x0040) /* Enable bit for Flash write */ +#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL3 Control Bits */ +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL3 Control Bits */ +#define BUSY_L (0x0001) /* Flash busy: 1 */ +#define KEYV_L (0x0002) /* Flash Key violation flag */ +#define ACCVIFG_L (0x0004) /* Flash Access violation flag */ +#define WAIT_L (0x0008) /* Wait flag for segment write */ +#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX_L (0x0020) /* Flash Emergency Exit */ +#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL4 Control Bits */ +#define VPE (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0 (0x0010) /* Marginal read 0 mode. */ +#define MGR1 (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/* FCTL4 Control Bits */ +#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0_L (0x0010) /* Marginal read 0 mode. */ +#define MGR1_L (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_MPY32__ 0x04C0 +#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__ + +sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ +sfr_b(MPY_L); /* Multiply Unsigned/Operand 1 */ +sfr_b(MPY_H); /* Multiply Unsigned/Operand 1 */ +sfr_w(MPYS); /* Multiply Signed/Operand 1 */ +sfr_b(MPYS_L); /* Multiply Signed/Operand 1 */ +sfr_b(MPYS_H); /* Multiply Signed/Operand 1 */ +sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_b(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_b(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */ +sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_b(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_b(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */ +sfr_w(OP2); /* Operand 2 */ +sfr_b(OP2_L); /* Operand 2 */ +sfr_b(OP2_H); /* Operand 2 */ +sfr_w(RESLO); /* Result Low Word */ +sfr_b(RESLO_L); /* Result Low Word */ +sfr_b(RESLO_H); /* Result Low Word */ +sfr_w(RESHI); /* Result High Word */ +sfr_b(RESHI_L); /* Result High Word */ +sfr_b(RESHI_H); /* Result High Word */ +sfr_w(SUMEXT); /* Sum Extend */ +sfr_b(SUMEXT_L); /* Sum Extend */ +sfr_b(SUMEXT_H); /* Sum Extend */ + +sfr_w(MPY32L); /* 32-bit operand 1 - multiply - low word */ +sfr_b(MPY32L_L); /* 32-bit operand 1 - multiply - low word */ +sfr_b(MPY32L_H); /* 32-bit operand 1 - multiply - low word */ +sfr_w(MPY32H); /* 32-bit operand 1 - multiply - high word */ +sfr_b(MPY32H_L); /* 32-bit operand 1 - multiply - high word */ +sfr_b(MPY32H_H); /* 32-bit operand 1 - multiply - high word */ +sfr_w(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */ +sfr_b(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */ +sfr_b(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */ +sfr_w(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */ +sfr_b(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */ +sfr_b(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */ +sfr_w(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */ +sfr_b(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */ +sfr_b(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */ +sfr_w(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */ +sfr_b(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */ +sfr_b(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */ +sfr_w(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */ +sfr_b(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */ +sfr_b(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */ +sfr_w(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */ +sfr_b(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */ +sfr_b(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */ +sfr_w(OP2L); /* 32-bit operand 2 - low word */ +sfr_b(OP2L_L); /* 32-bit operand 2 - low word */ +sfr_b(OP2L_H); /* 32-bit operand 2 - low word */ +sfr_w(OP2H); /* 32-bit operand 2 - high word */ +sfr_b(OP2H_L); /* 32-bit operand 2 - high word */ +sfr_b(OP2H_H); /* 32-bit operand 2 - high word */ +sfr_w(RES0); /* 32x32-bit result 0 - least significant word */ +sfr_b(RES0_L); /* 32x32-bit result 0 - least significant word */ +sfr_b(RES0_H); /* 32x32-bit result 0 - least significant word */ +sfr_w(RES1); /* 32x32-bit result 1 */ +sfr_b(RES1_L); /* 32x32-bit result 1 */ +sfr_b(RES1_H); /* 32x32-bit result 1 */ +sfr_w(RES2); /* 32x32-bit result 2 */ +sfr_b(RES2_L); /* 32x32-bit result 2 */ +sfr_b(RES2_H); /* 32x32-bit result 2 */ +sfr_w(RES3); /* 32x32-bit result 3 - most significant word */ +sfr_b(RES3_L); /* 32x32-bit result 3 - most significant word */ +sfr_b(RES3_H); /* 32x32-bit result 3 - most significant word */ +sfr_w(MPY32CTL0); /* MPY32 Control Register 0 */ +sfr_b(MPY32CTL0_L); /* MPY32 Control Register 0 */ +sfr_b(MPY32CTL0_H); /* MPY32 Control Register 0 */ + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC (0x0004) /* Fractional mode */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ +#define MPYDLY32 (0x0200) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC_L (0x0004) /* Fractional mode */ +#define MPYSAT_L (0x0008) /* Saturation mode */ +#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ +#define MPYDLY32_H (0x0002) /* Delayed write mode */ + +#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200 +#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__ +#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200 +#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__ +#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200 +#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__ +#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PASEL__ /* Define for DriverLib */ + +sfr_w(PAIN); /* Port A Input */ +sfr_b(PAIN_L); /* Port A Input */ +sfr_b(PAIN_H); /* Port A Input */ +sfr_w(PAOUT); /* Port A Output */ +sfr_b(PAOUT_L); /* Port A Output */ +sfr_b(PAOUT_H); /* Port A Output */ +sfr_w(PADIR); /* Port A Direction */ +sfr_b(PADIR_L); /* Port A Direction */ +sfr_b(PADIR_H); /* Port A Direction */ +sfr_w(PAREN); /* Port A Resistor Enable */ +sfr_b(PAREN_L); /* Port A Resistor Enable */ +sfr_b(PAREN_H); /* Port A Resistor Enable */ +sfr_w(PADS); /* Port A Drive Strenght */ +sfr_b(PADS_L); /* Port A Drive Strenght */ +sfr_b(PADS_H); /* Port A Drive Strenght */ +sfr_w(PASEL); /* Port A Selection */ +sfr_b(PASEL_L); /* Port A Selection */ +sfr_b(PASEL_H); /* Port A Selection */ +sfr_w(PAIES); /* Port A Interrupt Edge Select */ +sfr_b(PAIES_L); /* Port A Interrupt Edge Select */ +sfr_b(PAIES_H); /* Port A Interrupt Edge Select */ +sfr_w(PAIE); /* Port A Interrupt Enable */ +sfr_b(PAIE_L); /* Port A Interrupt Enable */ +sfr_b(PAIE_H); /* Port A Interrupt Enable */ +sfr_w(PAIFG); /* Port A Interrupt Flag */ +sfr_b(PAIFG_L); /* Port A Interrupt Flag */ +sfr_b(PAIFG_H); /* Port A Interrupt Flag */ + + +sfr_w(P1IV); /* Port 1 Interrupt Vector Word */ +sfr_w(P2IV); /* Port 2 Interrupt Vector Word */ +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1DS (PADS_L) /* Port 1 Drive Strenght */ +#define P1SEL (PASEL_L) /* Port 1 Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2DS (PADS_H) /* Port 2 Drive Strenght */ +#define P2SEL (PASEL_H) /* Port 2 Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ + + +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220 +#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__ +#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220 +#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__ +#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220 +#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__ +#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PBSEL__ /* Define for DriverLib */ + +sfr_w(PBIN); /* Port B Input */ +sfr_b(PBIN_L); /* Port B Input */ +sfr_b(PBIN_H); /* Port B Input */ +sfr_w(PBOUT); /* Port B Output */ +sfr_b(PBOUT_L); /* Port B Output */ +sfr_b(PBOUT_H); /* Port B Output */ +sfr_w(PBDIR); /* Port B Direction */ +sfr_b(PBDIR_L); /* Port B Direction */ +sfr_b(PBDIR_H); /* Port B Direction */ +sfr_w(PBREN); /* Port B Resistor Enable */ +sfr_b(PBREN_L); /* Port B Resistor Enable */ +sfr_b(PBREN_H); /* Port B Resistor Enable */ +sfr_w(PBDS); /* Port B Drive Strenght */ +sfr_b(PBDS_L); /* Port B Drive Strenght */ +sfr_b(PBDS_H); /* Port B Drive Strenght */ +sfr_w(PBSEL); /* Port B Selection */ +sfr_b(PBSEL_L); /* Port B Selection */ +sfr_b(PBSEL_H); /* Port B Selection */ + + +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ +#define P3SEL (PBSEL_L) /* Port 3 Selection */ + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ +#define P4SEL (PBSEL_H) /* Port 4 Selection */ + + +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240 +#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__ +#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240 +#define P6_BASE __MSP430_BASEADDRESS_PORT6_R__ +#define __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240 +#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__ +#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P6SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PCSEL__ /* Define for DriverLib */ + +sfr_w(PCIN); /* Port C Input */ +sfr_b(PCIN_L); /* Port C Input */ +sfr_b(PCIN_H); /* Port C Input */ +sfr_w(PCOUT); /* Port C Output */ +sfr_b(PCOUT_L); /* Port C Output */ +sfr_b(PCOUT_H); /* Port C Output */ +sfr_w(PCDIR); /* Port C Direction */ +sfr_b(PCDIR_L); /* Port C Direction */ +sfr_b(PCDIR_H); /* Port C Direction */ +sfr_w(PCREN); /* Port C Resistor Enable */ +sfr_b(PCREN_L); /* Port C Resistor Enable */ +sfr_b(PCREN_H); /* Port C Resistor Enable */ +sfr_w(PCDS); /* Port C Drive Strenght */ +sfr_b(PCDS_L); /* Port C Drive Strenght */ +sfr_b(PCDS_H); /* Port C Drive Strenght */ +sfr_w(PCSEL); /* Port C Selection */ +sfr_b(PCSEL_L); /* Port C Selection */ +sfr_b(PCSEL_H); /* Port C Selection */ + + +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ +#define P5SEL (PCSEL_L) /* Port 5 Selection */ + +#define P6IN (PCIN_H) /* Port 6 Input */ +#define P6OUT (PCOUT_H) /* Port 6 Output */ +#define P6DIR (PCDIR_H) /* Port 6 Direction */ +#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ +#define P6DS (PCDS_H) /* Port 6 Drive Strenght */ +#define P6SEL (PCSEL_H) /* Port 6 Selection */ + + +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260 +#define P7_BASE __MSP430_BASEADDRESS_PORT7_R__ +#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260 +#define P8_BASE __MSP430_BASEADDRESS_PORT8_R__ +#define __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260 +#define PD_BASE __MSP430_BASEADDRESS_PORTD_R__ +#define __MSP430_HAS_P7SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P8SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_PDSEL__ /* Define for DriverLib */ + +sfr_w(PDIN); /* Port D Input */ +sfr_b(PDIN_L); /* Port D Input */ +sfr_b(PDIN_H); /* Port D Input */ +sfr_w(PDOUT); /* Port D Output */ +sfr_b(PDOUT_L); /* Port D Output */ +sfr_b(PDOUT_H); /* Port D Output */ +sfr_w(PDDIR); /* Port D Direction */ +sfr_b(PDDIR_L); /* Port D Direction */ +sfr_b(PDDIR_H); /* Port D Direction */ +sfr_w(PDREN); /* Port D Resistor Enable */ +sfr_b(PDREN_L); /* Port D Resistor Enable */ +sfr_b(PDREN_H); /* Port D Resistor Enable */ +sfr_w(PDDS); /* Port D Drive Strenght */ +sfr_b(PDDS_L); /* Port D Drive Strenght */ +sfr_b(PDDS_H); /* Port D Drive Strenght */ +sfr_w(PDSEL); /* Port D Selection */ +sfr_b(PDSEL_L); /* Port D Selection */ +sfr_b(PDSEL_H); /* Port D Selection */ + + +#define P7IN (PDIN_L) /* Port 7 Input */ +#define P7OUT (PDOUT_L) /* Port 7 Output */ +#define P7DIR (PDDIR_L) /* Port 7 Direction */ +#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ +#define P7DS (PDDS_L) /* Port 7 Drive Strenght */ +#define P7SEL (PDSEL_L) /* Port 7 Selection */ + +#define P8IN (PDIN_H) /* Port 8 Input */ +#define P8OUT (PDOUT_H) /* Port 8 Output */ +#define P8DIR (PDDIR_H) /* Port 8 Direction */ +#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ +#define P8DS (PDDS_H) /* Port 8 Drive Strenght */ +#define P8SEL (PDSEL_H) /* Port 8 Selection */ + + +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320 +#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ + +sfr_w(PJIN); /* Port J Input */ +sfr_b(PJIN_L); /* Port J Input */ +sfr_b(PJIN_H); /* Port J Input */ +sfr_w(PJOUT); /* Port J Output */ +sfr_b(PJOUT_L); /* Port J Output */ +sfr_b(PJOUT_H); /* Port J Output */ +sfr_w(PJDIR); /* Port J Direction */ +sfr_b(PJDIR_L); /* Port J Direction */ +sfr_b(PJDIR_H); /* Port J Direction */ +sfr_w(PJREN); /* Port J Resistor Enable */ +sfr_b(PJREN_L); /* Port J Resistor Enable */ +sfr_b(PJREN_H); /* Port J Resistor Enable */ +sfr_w(PJDS); /* Port J Drive Strenght */ +sfr_b(PJDS_L); /* Port J Drive Strenght */ +sfr_b(PJDS_H); /* Port J Drive Strenght */ + +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +#define __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0 +#define PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__ + +sfr_w(PMAPKEYID); /* Port Mapping Key register */ +sfr_b(PMAPKEYID_L); /* Port Mapping Key register */ +sfr_b(PMAPKEYID_H); /* Port Mapping Key register */ +sfr_w(PMAPCTL); /* Port Mapping control register */ +sfr_b(PMAPCTL_L); /* Port Mapping control register */ +sfr_b(PMAPCTL_H); /* Port Mapping control register */ + +#define PMAPKEY (0x2D52) /* Port Mapping Key */ +#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ +#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */ + +/************************************************************ +* PORT 4 MAPPING CONTROLLER +************************************************************/ +#define __MSP430_HAS_PORT4_MAPPING__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PORT4_MAPPING__ 0x01E0 +#define P4MAP_BASE __MSP430_BASEADDRESS_PORT4_MAPPING__ + +sfr_w(P4MAP01); /* Port P4.0/1 mapping register */ +sfr_b(P4MAP01_L); /* Port P4.0/1 mapping register */ +sfr_b(P4MAP01_H); /* Port P4.0/1 mapping register */ +sfr_w(P4MAP23); /* Port P4.2/3 mapping register */ +sfr_b(P4MAP23_L); /* Port P4.2/3 mapping register */ +sfr_b(P4MAP23_H); /* Port P4.2/3 mapping register */ +sfr_w(P4MAP45); /* Port P4.4/5 mapping register */ +sfr_b(P4MAP45_L); /* Port P4.4/5 mapping register */ +sfr_b(P4MAP45_H); /* Port P4.4/5 mapping register */ +sfr_w(P4MAP67); /* Port P4.6/7 mapping register */ +sfr_b(P4MAP67_L); /* Port P4.6/7 mapping register */ +sfr_b(P4MAP67_H); /* Port P4.6/7 mapping register */ + +#define P4MAP0 P4MAP01_L /* Port P4.0 mapping register */ +#define P4MAP1 P4MAP01_H /* Port P4.1 mapping register */ +#define P4MAP2 P4MAP23_L /* Port P4.2 mapping register */ +#define P4MAP3 P4MAP23_H /* Port P4.3 mapping register */ +#define P4MAP4 P4MAP45_L /* Port P4.4 mapping register */ +#define P4MAP5 P4MAP45_H /* Port P4.5 mapping register */ +#define P4MAP6 P4MAP67_L /* Port P4.6 mapping register */ +#define P4MAP7 P4MAP67_H /* Port P4.7 mapping register */ + +#define PM_NONE 0 +#define PM_CBOUT0 1 +#define PM_TB0CLK 1 +#define PM_ADC12CLK 2 +#define PM_DMAE0 2 +#define PM_SVMOUT 3 +#define PM_TB0OUTH 3 +#define PM_TB0CCR0A 4 +#define PM_TB0CCR1A 5 +#define PM_TB0CCR2A 6 +#define PM_TB0CCR3A 7 +#define PM_TB0CCR4A 8 +#define PM_TB0CCR5A 9 +#define PM_TB0CCR6A 10 +#define PM_UCA1RXD 11 +#define PM_UCA1SOMI 11 +#define PM_UCA1TXD 12 +#define PM_UCA1SIMO 12 +#define PM_UCA1CLK 13 +#define PM_UCB1STE 13 +#define PM_UCB1SOMI 14 +#define PM_UCB1SCL 14 +#define PM_UCB1SIMO 15 +#define PM_UCB1SDA 15 +#define PM_UCB1CLK 16 +#define PM_UCA1STE 16 +#define PM_CBOUT1 17 +#define PM_MCLK 18 +#define PM_ANALOG 31 + +/************************************************************ +* PMM - Power Management System +************************************************************/ +#define __MSP430_HAS_PMM__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_PMM__ 0x0120 +#define PMM_BASE __MSP430_BASEADDRESS_PMM__ + +sfr_w(PMMCTL0); /* PMM Control 0 */ +sfr_b(PMMCTL0_L); /* PMM Control 0 */ +sfr_b(PMMCTL0_H); /* PMM Control 0 */ +sfr_w(PMMCTL1); /* PMM Control 1 */ +sfr_b(PMMCTL1_L); /* PMM Control 1 */ +sfr_b(PMMCTL1_H); /* PMM Control 1 */ +sfr_w(SVSMHCTL); /* SVS and SVM high side control register */ +sfr_b(SVSMHCTL_L); /* SVS and SVM high side control register */ +sfr_b(SVSMHCTL_H); /* SVS and SVM high side control register */ +sfr_w(SVSMLCTL); /* SVS and SVM low side control register */ +sfr_b(SVSMLCTL_L); /* SVS and SVM low side control register */ +sfr_b(SVSMLCTL_H); /* SVS and SVM low side control register */ +sfr_w(SVSMIO); /* SVSIN and SVSOUT control register */ +sfr_b(SVSMIO_L); /* SVSIN and SVSOUT control register */ +sfr_b(SVSMIO_H); /* SVSIN and SVSOUT control register */ +sfr_w(PMMIFG); /* PMM Interrupt Flag */ +sfr_b(PMMIFG_L); /* PMM Interrupt Flag */ +sfr_b(PMMIFG_H); /* PMM Interrupt Flag */ +sfr_w(PMMRIE); /* PMM and RESET Interrupt Enable */ +sfr_b(PMMRIE_L); /* PMM and RESET Interrupt Enable */ +sfr_b(PMMRIE_H); /* PMM and RESET Interrupt Enable */ +sfr_w(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */ +sfr_b(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */ +sfr_b(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */ + +#define PMMPW (0xA500) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR (0x0004) /* PMM Software BOR */ +#define PMMSWPOR (0x0008) /* PMM Software POR */ +#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */ + +#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */ +#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */ +#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */ +#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD (0x0001) /* PMM Reference Mode */ +#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD_L (0x0001) /* PMM Reference Mode */ +#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD (0x0010) /* SVS high side mode */ +#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */ +#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE (0x0400) /* SVS high side enable */ +#define SVSHFP (0x0800) /* SVS high side full performace mode */ +#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */ +#define SVMHE (0x4000) /* SVM high side enable */ +#define SVMHFP (0x8000) /* SVM high side full performace mode */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD_L (0x0010) /* SVS high side mode */ +#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */ + +/* SVSMHCTL Control Bits */ +#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE_H (0x0004) /* SVS high side enable */ +#define SVSHFP_H (0x0008) /* SVS high side full performace mode */ +#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */ +#define SVMHE_H (0x0040) /* SVM high side enable */ +#define SVMHFP_H (0x0080) /* SVM high side full performace mode */ + +#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */ +#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */ +#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */ +#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */ +#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */ +#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */ +#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */ +#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */ + +#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */ +#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */ +#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */ +#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD (0x0010) /* SVS low side mode */ +#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */ +#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE (0x0400) /* SVS low side enable */ +#define SVSLFP (0x0800) /* SVS low side full performace mode */ +#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */ +#define SVMLE (0x4000) /* SVM low side enable */ +#define SVMLFP (0x8000) /* SVM low side full performace mode */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD_L (0x0010) /* SVS low side mode */ +#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */ + +/* SVSMLCTL Control Bits */ +#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE_H (0x0004) /* SVS low side enable */ +#define SVSLFP_H (0x0008) /* SVS low side full performace mode */ +#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */ +#define SVMLE_H (0x0040) /* SVM low side enable */ +#define SVMLFP_H (0x0080) /* SVM low side full performace mode */ + +#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */ +#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */ +#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */ +#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */ +#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */ +#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */ +#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */ +#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */ + +#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */ +#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */ +#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */ +#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */ + +/* SVSMIO Control Bits */ +#define SVMLOE (0x0008) /* SVM low side output enable */ +#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */ +#define SVMHOE (0x0800) /* SVM high side output enable */ +#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */ + +/* SVSMIO Control Bits */ +#define SVMLOE_L (0x0008) /* SVM low side output enable */ +#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */ + +/* SVSMIO Control Bits */ +#define SVMHOE_H (0x0008) /* SVM high side output enable */ +#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ +#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x1000) /* SVS low side interrupt flag */ +#define SVSLIFG (0x2000) /* SVS high side interrupt flag */ +#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */ +#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */ +#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ + +#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ +#define SVSLPE (0x0100) /* SVS low side POR enable */ +#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE (0x1000) /* SVS high side POR enable */ +#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSLPE_H (0x0001) /* SVS low side POR enable */ +#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE_H (0x0010) /* SVS high side POR enable */ +#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/************************************************************* +* RAM Control Module +*************************************************************/ +#define __MSP430_HAS_RC__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_RC__ 0x0158 +#define RAM_BASE __MSP430_BASEADDRESS_RC__ + +sfr_w(RCCTL0); /* Ram Controller Control Register */ +sfr_b(RCCTL0_L); /* Ram Controller Control Register */ +sfr_b(RCCTL0_H); /* Ram Controller Control Register */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */ +#define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */ +#define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ + +#define RCKEY (0x5A00) + +/************************************************************ +* Shared Reference +************************************************************/ +#define __MSP430_HAS_REF__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_REF__ 0x01B0 +#define REF_BASE __MSP430_BASEADDRESS_REF__ + +sfr_w(REFCTL0); /* REF Shared Reference control register 0 */ +sfr_b(REFCTL0_L); /* REF Shared Reference control register 0 */ +sfr_b(REFCTL0_H); /* REF Shared Reference control register 0 */ + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +#define REFOUT (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR (0x0080) /* REF Master Control */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR_L (0x0080) /* REF Master Control */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004) /* Reserved */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +/************************************************************ +* Real Time Clock +************************************************************/ +#define __MSP430_HAS_RTC__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_RTC__ 0x04A0 +#define RTC_A_BASE __MSP430_BASEADDRESS_RTC__ + +sfr_w(RTCCTL01); /* Real Timer Control 0/1 */ +sfr_b(RTCCTL01_L); /* Real Timer Control 0/1 */ +sfr_b(RTCCTL01_H); /* Real Timer Control 0/1 */ +sfr_w(RTCCTL23); /* Real Timer Control 2/3 */ +sfr_b(RTCCTL23_L); /* Real Timer Control 2/3 */ +sfr_b(RTCCTL23_H); /* Real Timer Control 2/3 */ +sfr_w(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */ +sfr_b(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */ +sfr_b(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */ +sfr_w(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */ +sfr_b(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */ +sfr_b(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */ +sfr_w(RTCPS); /* Real Timer Prescale Timer Control */ +sfr_b(RTCPS_L); /* Real Timer Prescale Timer Control */ +sfr_b(RTCPS_H); /* Real Timer Prescale Timer Control */ +sfr_w(RTCIV); /* Real Time Clock Interrupt Vector */ +sfr_w(RTCTIM0); /* Real Time Clock Time 0 */ +sfr_b(RTCTIM0_L); /* Real Time Clock Time 0 */ +sfr_b(RTCTIM0_H); /* Real Time Clock Time 0 */ +sfr_w(RTCTIM1); /* Real Time Clock Time 1 */ +sfr_b(RTCTIM1_L); /* Real Time Clock Time 1 */ +sfr_b(RTCTIM1_H); /* Real Time Clock Time 1 */ +sfr_w(RTCDATE); /* Real Time Clock Date */ +sfr_b(RTCDATE_L); /* Real Time Clock Date */ +sfr_b(RTCDATE_H); /* Real Time Clock Date */ +sfr_w(RTCYEAR); /* Real Time Clock Year */ +sfr_b(RTCYEAR_L); /* Real Time Clock Year */ +sfr_b(RTCYEAR_H); /* Real Time Clock Year */ +sfr_w(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */ +sfr_b(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */ +sfr_b(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */ +sfr_w(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */ +sfr_b(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */ +sfr_b(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */ + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x1000) /* RTC Ready */ +#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define Reserved (0x0080) +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +//#define Reserved (0x0008) + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */ +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */ +#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */ +#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */ +#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */ +#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */ +#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */ +#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */ +#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */ +#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */ +#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */ +#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */ +#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */ +#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */ +#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */ +#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */ + +#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */ +#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */ +#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */ +#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_SFR__ 0x0100 +#define SFR_BASE __MSP430_BASEADDRESS_SFR__ + +sfr_w(SFRIE1); /* Interrupt Enable 1 */ +sfr_b(SFRIE1_L); /* Interrupt Enable 1 */ +sfr_b(SFRIE1_H); /* Interrupt Enable 1 */ + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* WDT Interrupt Enable */ +#define OFIE (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010) /* NMI Interrupt Enable */ +#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */ +#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ +#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */ +#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +sfr_w(SFRIFG1); /* Interrupt Flag 1 */ +sfr_b(SFRIFG1_L); /* Interrupt Flag 1 */ +sfr_b(SFRIFG1_H); /* Interrupt Flag 1 */ +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001) /* WDT Interrupt Flag */ +#define OFIFG (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +sfr_w(SFRRPCR); /* RESET Pin Control Register */ +sfr_b(SFRRPCR_L); /* RESET Pin Control Register */ +sfr_b(SFRRPCR_H); /* RESET Pin Control Register */ +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001) /* NMI select */ +#define SYSNMIIES_L (0x0002) /* NMI edge select */ +#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ + +/************************************************************ +* SYS - System Module +************************************************************/ +#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_SYS__ 0x0180 +#define SYS_BASE __MSP430_BASEADDRESS_SYS__ + +sfr_w(SYSCTL); /* System control */ +sfr_b(SYSCTL_L); /* System control */ +sfr_b(SYSCTL_H); /* System control */ +sfr_w(SYSBSLC); /* Boot strap configuration area */ +sfr_b(SYSBSLC_L); /* Boot strap configuration area */ +sfr_b(SYSBSLC_H); /* Boot strap configuration area */ +sfr_w(SYSJMBC); /* JTAG mailbox control */ +sfr_b(SYSJMBC_L); /* JTAG mailbox control */ +sfr_b(SYSJMBC_H); /* JTAG mailbox control */ +sfr_w(SYSJMBI0); /* JTAG mailbox input 0 */ +sfr_b(SYSJMBI0_L); /* JTAG mailbox input 0 */ +sfr_b(SYSJMBI0_H); /* JTAG mailbox input 0 */ +sfr_w(SYSJMBI1); /* JTAG mailbox input 1 */ +sfr_b(SYSJMBI1_L); /* JTAG mailbox input 1 */ +sfr_b(SYSJMBI1_H); /* JTAG mailbox input 1 */ +sfr_w(SYSJMBO0); /* JTAG mailbox output 0 */ +sfr_b(SYSJMBO0_L); /* JTAG mailbox output 0 */ +sfr_b(SYSJMBO0_H); /* JTAG mailbox output 0 */ +sfr_w(SYSJMBO1); /* JTAG mailbox output 1 */ +sfr_b(SYSJMBO1_L); /* JTAG mailbox output 1 */ +sfr_b(SYSJMBO1_H); /* JTAG mailbox output 1 */ + +sfr_w(SYSBERRIV); /* Bus Error vector generator */ +sfr_b(SYSBERRIV_L); /* Bus Error vector generator */ +sfr_b(SYSBERRIV_H); /* Bus Error vector generator */ +sfr_w(SYSUNIV); /* User NMI vector generator */ +sfr_b(SYSUNIV_L); /* User NMI vector generator */ +sfr_b(SYSUNIV_H); /* User NMI vector generator */ +sfr_w(SYSSNIV); /* System NMI vector generator */ +sfr_b(SYSSNIV_L); /* System NMI vector generator */ +sfr_b(SYSSNIV_H); /* System NMI vector generator */ +sfr_w(SYSRSTIV); /* Reset vector generator */ +sfr_b(SYSRSTIV_L); /* Reset vector generator */ +sfr_b(SYSRSTIV_H); /* Reset vector generator */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + +/* SYSUNIV Definitions */ +#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */ +#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */ +#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */ +#define SYSUNIV_BUSIFG (0x0008) /* SYSUNIV : Bus Error */ +#define SYSUNIV_SYSBUSIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIFG (legacy) */ + +/* SYSSNIV Definitions */ +#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */ +#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */ +#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */ +#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */ +#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */ +#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */ +#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */ +#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */ +#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */ + +/* SYSRSTIV Definitions */ +#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */ +#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */ +#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */ +#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */ +#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */ +#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */ +#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */ +#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */ +#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */ +#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */ +#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */ +#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */ +#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */ +//#define RESERVED (0x001C) /* SYSRSTIV : Reserved */ +#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */ +#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */ + +/************************************************************ +* Timer0_A5 +************************************************************/ +#define __MSP430_HAS_T0A5__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_T0A5__ 0x0340 +#define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__ + +sfr_w(TA0CTL); /* Timer0_A5 Control */ +sfr_w(TA0CCTL0); /* Timer0_A5 Capture/Compare Control 0 */ +sfr_w(TA0CCTL1); /* Timer0_A5 Capture/Compare Control 1 */ +sfr_w(TA0CCTL2); /* Timer0_A5 Capture/Compare Control 2 */ +sfr_w(TA0CCTL3); /* Timer0_A5 Capture/Compare Control 3 */ +sfr_w(TA0CCTL4); /* Timer0_A5 Capture/Compare Control 4 */ +sfr_w(TA0R); /* Timer0_A5 */ +sfr_w(TA0CCR0); /* Timer0_A5 Capture/Compare 0 */ +sfr_w(TA0CCR1); /* Timer0_A5 Capture/Compare 1 */ +sfr_w(TA0CCR2); /* Timer0_A5 Capture/Compare 2 */ +sfr_w(TA0CCR3); /* Timer0_A5 Capture/Compare 3 */ +sfr_w(TA0CCR4); /* Timer0_A5 Capture/Compare 4 */ +sfr_w(TA0IV); /* Timer0_A5 Interrupt Vector Word */ +sfr_w(TA0EX0); /* Timer0_A5 Expansion Register 0 */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (0x0020) /* Legacy define */ +#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */ + +/* T0A5IV Definitions */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TACCR3 (0x0006) /* TA0CCR3_CCIFG */ +#define TA0IV_TACCR4 (0x0008) /* TA0CCR4_CCIFG */ +#define TA0IV_5 (0x000A) /* Reserved */ +#define TA0IV_6 (0x000C) /* Reserved */ +#define TA0IV_TAIFG (0x000E) /* TA0IFG */ + +/* Legacy Defines */ +#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TA0CCR3 (0x0006) /* TA0CCR3_CCIFG */ +#define TA0IV_TA0CCR4 (0x0008) /* TA0CCR4_CCIFG */ +#define TA0IV_TA0IFG (0x000E) /* TA0IFG */ + +/************************************************************ +* Timer1_A3 +************************************************************/ +#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_T1A3__ 0x0380 +#define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__ + +sfr_w(TA1CTL); /* Timer1_A3 Control */ +sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */ +sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */ +sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */ +sfr_w(TA1R); /* Timer1_A3 */ +sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */ +sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */ +sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */ +sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */ +sfr_w(TA1EX0); /* Timer1_A3 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA1IV Definitions */ +#define TA1IV_NONE (0x0000) /* No Interrupt pending */ +#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_3 (0x0006) /* Reserved */ +#define TA1IV_4 (0x0008) /* Reserved */ +#define TA1IV_5 (0x000A) /* Reserved */ +#define TA1IV_6 (0x000C) /* Reserved */ +#define TA1IV_TAIFG (0x000E) /* TA1IFG */ + +/* Legacy Defines */ +#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_TA1IFG (0x000E) /* TA1IFG */ + +/************************************************************ +* Timer2_A3 +************************************************************/ +#define __MSP430_HAS_T2A3__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_T2A3__ 0x0400 +#define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A3__ + +sfr_w(TA2CTL); /* Timer2_A3 Control */ +sfr_w(TA2CCTL0); /* Timer2_A3 Capture/Compare Control 0 */ +sfr_w(TA2CCTL1); /* Timer2_A3 Capture/Compare Control 1 */ +sfr_w(TA2CCTL2); /* Timer2_A3 Capture/Compare Control 2 */ +sfr_w(TA2R); /* Timer2_A3 */ +sfr_w(TA2CCR0); /* Timer2_A3 Capture/Compare 0 */ +sfr_w(TA2CCR1); /* Timer2_A3 Capture/Compare 1 */ +sfr_w(TA2CCR2); /* Timer2_A3 Capture/Compare 2 */ +sfr_w(TA2IV); /* Timer2_A3 Interrupt Vector Word */ +sfr_w(TA2EX0); /* Timer2_A3 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA2IV Definitions */ +#define TA2IV_NONE (0x0000) /* No Interrupt pending */ +#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */ +#define TA2IV_TACCR2 (0x0004) /* TA2CCR2_CCIFG */ +#define TA2IV_3 (0x0006) /* Reserved */ +#define TA2IV_4 (0x0008) /* Reserved */ +#define TA2IV_5 (0x000A) /* Reserved */ +#define TA2IV_6 (0x000C) /* Reserved */ +#define TA2IV_TAIFG (0x000E) /* TA2IFG */ + +/* Legacy Defines */ +#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */ +#define TA2IV_TA2CCR2 (0x0004) /* TA2CCR2_CCIFG */ +#define TA2IV_TA2IFG (0x000E) /* TA2IFG */ + +/************************************************************ +* Timer0_B7 +************************************************************/ +#define __MSP430_HAS_T0B7__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_T0B7__ 0x03C0 +#define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__ + +sfr_w(TB0CTL); /* Timer0_B7 Control */ +sfr_w(TB0CCTL0); /* Timer0_B7 Capture/Compare Control 0 */ +sfr_w(TB0CCTL1); /* Timer0_B7 Capture/Compare Control 1 */ +sfr_w(TB0CCTL2); /* Timer0_B7 Capture/Compare Control 2 */ +sfr_w(TB0CCTL3); /* Timer0_B7 Capture/Compare Control 3 */ +sfr_w(TB0CCTL4); /* Timer0_B7 Capture/Compare Control 4 */ +sfr_w(TB0CCTL5); /* Timer0_B7 Capture/Compare Control 5 */ +sfr_w(TB0CCTL6); /* Timer0_B7 Capture/Compare Control 6 */ +sfr_w(TB0R); /* Timer0_B7 */ +sfr_w(TB0CCR0); /* Timer0_B7 Capture/Compare 0 */ +sfr_w(TB0CCR1); /* Timer0_B7 Capture/Compare 1 */ +sfr_w(TB0CCR2); /* Timer0_B7 Capture/Compare 2 */ +sfr_w(TB0CCR3); /* Timer0_B7 Capture/Compare 3 */ +sfr_w(TB0CCR4); /* Timer0_B7 Capture/Compare 4 */ +sfr_w(TB0CCR5); /* Timer0_B7 Capture/Compare 5 */ +sfr_w(TB0CCR6); /* Timer0_B7 Capture/Compare 6 */ +sfr_w(TB0EX0); /* Timer0_B7 Expansion Register 0 */ +sfr_w(TB0IV); /* Timer0_B7 Interrupt Vector Word */ + +/* Legacy Type Definitions for TimerB */ +#define TBCTL TB0CTL /* Timer0_B7 Control */ +#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */ +#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */ +#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */ +#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */ +#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */ +#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */ +#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */ +#define TBR TB0R /* Timer0_B7 */ +#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */ +#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */ +#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */ +#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */ +#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */ +#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */ +#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */ +#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */ +#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */ +#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */ +#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */ + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer0_B7 counter clear */ +#define TBIE (0x0002) /* Timer0_B7 interrupt enable */ +#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */ + +#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ +#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ +#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ +#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ +#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ +#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ +#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ +#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ + +/* TB0IV Definitions */ +#define TB0IV_NONE (0x0000) /* No Interrupt pending */ +#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */ +#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */ +#define TB0IV_TBIFG (0x000E) /* TB0IFG */ + +/* Legacy Defines */ +#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */ +#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */ +#define TB0IV_TB0IFG (0x000E) /* TB0IFG */ + + +/************************************************************ +* USB +************************************************************/ +#define __MSP430_HAS_USB__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USB__ 0x0900 +#define USB_BASE __MSP430_BASEADDRESS_USB__ + +/* ========================================================================= */ +/* USB Configuration Registers */ +/* ========================================================================= */ +sfr_w(USBKEYID); /* USB Controller key register */ +sfr_b(USBKEYID_L); /* USB Controller key register */ +sfr_b(USBKEYID_H); /* USB Controller key register */ +sfr_w(USBCNF); /* USB Module configuration register */ +sfr_b(USBCNF_L); /* USB Module configuration register */ +sfr_b(USBCNF_H); /* USB Module configuration register */ +sfr_w(USBPHYCTL); /* USB PHY control register */ +sfr_b(USBPHYCTL_L); /* USB PHY control register */ +sfr_b(USBPHYCTL_H); /* USB PHY control register */ +sfr_w(USBPWRCTL); /* USB Power control register */ +sfr_b(USBPWRCTL_L); /* USB Power control register */ +sfr_b(USBPWRCTL_H); /* USB Power control register */ +sfr_w(USBPLLCTL); /* USB PLL control register */ +sfr_b(USBPLLCTL_L); /* USB PLL control register */ +sfr_b(USBPLLCTL_H); /* USB PLL control register */ +sfr_w(USBPLLDIVB); /* USB PLL Clock Divider Buffer control register */ +sfr_b(USBPLLDIVB_L); /* USB PLL Clock Divider Buffer control register */ +sfr_b(USBPLLDIVB_H); /* USB PLL Clock Divider Buffer control register */ +sfr_w(USBPLLIR); /* USB PLL Interrupt control register */ +sfr_b(USBPLLIR_L); /* USB PLL Interrupt control register */ +sfr_b(USBPLLIR_H); /* USB PLL Interrupt control register */ + +#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */ +#define USBKEY (0x9628) /* USB Control Register key */ + +/* USBCNF Control Bits */ +#define USB_EN (0x0001) /* USB - Module enable */ +#define PUR_EN (0x0002) /* USB - PUR pin enable */ +#define PUR_IN (0x0004) /* USB - PUR pin input value */ +#define BLKRDY (0x0008) /* USB - Block ready signal for DMA */ +#define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBCNF Control Bits */ +#define USB_EN_L (0x0001) /* USB - Module enable */ +#define PUR_EN_L (0x0002) /* USB - PUR pin enable */ +#define PUR_IN_L (0x0004) /* USB - PUR pin input value */ +#define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */ +#define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0 (0x0004) /* USB - PU0/DP Input Data */ +#define PUIN1 (0x0008) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010) /* USB - */ +#define PUOPE (0x0020) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040) /* USB - */ +#define PUSEL (0x0080) /* USB - USB Port Function Select */ +#define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */ +#define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010) /* USB - */ +#define PUOPE_L (0x0020) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040) /* USB - */ +#define PUSEL_L (0x0080) /* USB - USB Port Function Select */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +#define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */ +#define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN (0x0010) /* USB - VBUS on/off events enable */ +#define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */ +#define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080) /* USB - */ +#define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */ +#define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */ +#define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */ +#define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */ +#define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPWRCTL Control Bits */ +//#define RESERVED (0x0080) /* USB - */ +#define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */ +#define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */ +#define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */ +#define UPLLEN (0x0100) /* USB - PLL enable */ +#define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UPLLEN_H (0x0001) /* USB - PLL enable */ +#define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */ +#define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */ +#define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */ +#define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */ + +#define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */ +#define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */ +#define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLDIVB Control Bits */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */ +#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */ +#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */ +#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */ +#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */ +#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */ +#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */ +#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */ +#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */ +#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */ +#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */ +#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */ +#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */ +#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */ +#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */ +#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */ +#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */ +#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */ +#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */ +#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */ +#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */ +#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */ +#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */ +#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */ +#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */ +#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */ +#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */ +#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */ +#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */ +#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */ +#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */ +#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */ +#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */ +#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */ +#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */ +#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */ +#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */ +#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */ +#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */ +#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */ +#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */ +#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */ +#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLIR Control Bits */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* ========================================================================= */ +/* USB Control Registers */ +/* ========================================================================= */ +sfr_b(USBIEPCNF_0); /* USB Input endpoint_0: Configuration */ +sfr_b(USBIEPCNT_0); /* USB Input endpoint_0: Byte Count */ +sfr_b(USBOEPCNF_0); /* USB Output endpoint_0: Configuration */ +sfr_b(USBOEPCNT_0); /* USB Output endpoint_0: byte count */ +sfr_b(USBIEPIE); /* USB Input endpoint interrupt enable flags */ +sfr_b(USBOEPIE); /* USB Output endpoint interrupt enable flags */ +sfr_b(USBIEPIFG); /* USB Input endpoint interrupt flags */ +sfr_b(USBOEPIFG); /* USB Output endpoint interrupt flags */ +sfr_w(USBVECINT); /* USB Vector interrupt register */ +sfr_b(USBVECINT_L); /* USB Vector interrupt register */ +sfr_b(USBVECINT_H); /* USB Vector interrupt register */ +sfr_w(USBMAINT); /* USB maintenance register */ +sfr_b(USBMAINT_L); /* USB maintenance register */ +sfr_b(USBMAINT_H); /* USB maintenance register */ +sfr_w(USBTSREG); /* USB Time Stamp register */ +sfr_b(USBTSREG_L); /* USB Time Stamp register */ +sfr_b(USBTSREG_H); /* USB Time Stamp register */ +sfr_w(USBFN); /* USB Frame number */ +sfr_b(USBFN_L); /* USB Frame number */ +sfr_b(USBFN_H); /* USB Frame number */ +sfr_b(USBCTL); /* USB control register */ +sfr_b(USBIE); /* USB interrupt enable register */ +sfr_b(USBIFG); /* USB interrupt flag register */ +sfr_b(USBFUNADR); /* USB Function address register */ + +#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */ + +/* USBIEPCNF_0 Control Bits */ +/* USBOEPCNF_0 Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0001) /* USB - */ +#define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */ +#define STALL (0x0008) /* USB - Stall Condition */ +//#define RESERVED (0x0010) /* USB - */ +#define TOGGLE (0x0020) /* USB - Toggle Bit */ +//#define RESERVED (0x0040) /* USB - */ +#define UBME (0x0080) /* USB - UBM In-Endpoint Enable */ + +/* USBIEPBCNT_0 Control Bits */ +/* USBOEPBCNT_0 Control Bits */ +#define CNT0 (0x0001) /* USB - Byte Count Bit 0 */ +#define CNT1 (0x0001) /* USB - Byte Count Bit 1 */ +#define CNT2 (0x0004) /* USB - Byte Count Bit 2 */ +#define CNT3 (0x0008) /* USB - Byte Count Bit 3 */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +#define NAK (0x0080) /* USB - No Acknowledge Status Bit */ + +/* USBMAINT Control Bits */ +#define UTIFG (0x0001) /* USB - Timer Interrupt Flag */ +#define UTIE (0x0002) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */ +#define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000) /* USB - */ +#define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */ +#define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */ +#define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */ + +/* USBMAINT Control Bits */ +#define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */ +#define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ + +/* USBMAINT Control Bits */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */ +#define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000) /* USB - */ +#define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */ +#define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */ +#define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */ + +#define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */ +#define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */ +#define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */ +#define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */ + +#define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */ +#define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */ +#define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */ +#define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */ +#define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */ +#define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */ +#define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */ +#define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */ + +/* USBCTL Control Bits */ +#define DIR (0x0001) /* USB - Data Response Bit */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +#define FRSTE (0x0010) /* USB - Function Reset Connection Enable */ +#define RWUP (0x0020) /* USB - Device Remote Wakeup Request */ +#define FEN (0x0040) /* USB - Function Enable Bit */ +//#define RESERVED (0x0080) /* USB - */ + +/* USBIE Control Bits */ +#define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */ +//#define RESERVED (0x0002) /* USB - */ +#define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +#define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */ +#define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */ +#define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */ + +/* USBIFG Control Bits */ +#define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */ +//#define RESERVED (0x0002) /* USB - */ +#define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +#define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */ +#define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */ +#define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */ + +//values of USBVECINT when USB-interrupt occured +#define USBVECINT_NONE 0x00 +#define USBVECINT_PWR_DROP 0x02 +#define USBVECINT_PLL_LOCK 0x04 +#define USBVECINT_PLL_SIGNAL 0x06 +#define USBVECINT_PLL_RANGE 0x08 +#define USBVECINT_PWR_VBUSOn 0x0A +#define USBVECINT_PWR_VBUSOff 0x0C +#define USBVECINT_USB_TIMESTAMP 0x10 +#define USBVECINT_INPUT_ENDPOINT0 0x12 +#define USBVECINT_OUTPUT_ENDPOINT0 0x14 +#define USBVECINT_RSTR 0x16 +#define USBVECINT_SUSR 0x18 +#define USBVECINT_RESR 0x1A +#define USBVECINT_SETUP_PACKET_RECEIVED 0x20 +#define USBVECINT_STPOW_PACKET_RECEIVED 0x22 +#define USBVECINT_INPUT_ENDPOINT1 0x24 +#define USBVECINT_INPUT_ENDPOINT2 0x26 +#define USBVECINT_INPUT_ENDPOINT3 0x28 +#define USBVECINT_INPUT_ENDPOINT4 0x2A +#define USBVECINT_INPUT_ENDPOINT5 0x2C +#define USBVECINT_INPUT_ENDPOINT6 0x2E +#define USBVECINT_INPUT_ENDPOINT7 0x30 +#define USBVECINT_OUTPUT_ENDPOINT1 0x32 +#define USBVECINT_OUTPUT_ENDPOINT2 0x34 +#define USBVECINT_OUTPUT_ENDPOINT3 0x36 +#define USBVECINT_OUTPUT_ENDPOINT4 0x38 +#define USBVECINT_OUTPUT_ENDPOINT5 0x3A +#define USBVECINT_OUTPUT_ENDPOINT6 0x3C +#define USBVECINT_OUTPUT_ENDPOINT7 0x3E + + +/* ========================================================================= */ +/* USB Operation Registers */ +/* ========================================================================= */ + +sfr_b(USBIEPSIZXY_7); /* Input Endpoint_7: X/Y-buffer size */ +sfr_b(USBIEPBCTY_7); /* Input Endpoint_7: Y-byte count */ +sfr_b(USBIEPBBAY_7); /* Input Endpoint_7: Y-buffer base addr. */ +//sfrb Spare (0x23FC) /* Not used */ +//sfrb Spare (0x23FB) /* Not used */ +sfr_b(USBIEPBCTX_7); /* Input Endpoint_7: X-byte count */ +sfr_b(USBIEPBBAX_7); /* Input Endpoint_7: X-buffer base addr. */ +sfr_b(USBIEPCNF_7); /* Input Endpoint_7: Configuration */ +sfr_b(USBIEPSIZXY_6); /* Input Endpoint_6: X/Y-buffer size */ +sfr_b(USBIEPBCTY_6); /* Input Endpoint_6: Y-byte count */ +sfr_b(USBIEPBBAY_6); /* Input Endpoint_6: Y-buffer base addr. */ +//sfrb Spare (0x23F4) /* Not used */ +//sfrb Spare (0x23F3) /* Not used */ +sfr_b(USBIEPBCTX_6); /* Input Endpoint_6: X-byte count */ +sfr_b(USBIEPBBAX_6); /* Input Endpoint_6: X-buffer base addr. */ +sfr_b(USBIEPCNF_6); /* Input Endpoint_6: Configuration */ +sfr_b(USBIEPSIZXY_5); /* Input Endpoint_5: X/Y-buffer size */ +sfr_b(USBIEPBCTY_5); /* Input Endpoint_5: Y-byte count */ +sfr_b(USBIEPBBAY_5); /* Input Endpoint_5: Y-buffer base addr. */ +//sfrb Spare (0x23EC) /* Not used */ +//sfrb Spare (0x23EB) /* Not used */ +sfr_b(USBIEPBCTX_5); /* Input Endpoint_5: X-byte count */ +sfr_b(USBIEPBBAX_5); /* Input Endpoint_5: X-buffer base addr. */ +sfr_b(USBIEPCNF_5); /* Input Endpoint_5: Configuration */ +sfr_b(USBIEPSIZXY_4); /* Input Endpoint_4: X/Y-buffer size */ +sfr_b(USBIEPBCTY_4); /* Input Endpoint_4: Y-byte count */ +sfr_b(USBIEPBBAY_4); /* Input Endpoint_4: Y-buffer base addr. */ +//sfrb Spare (0x23E4) /* Not used */ +//sfrb Spare (0x23E3) /* Not used */ +sfr_b(USBIEPBCTX_4); /* Input Endpoint_4: X-byte count */ +sfr_b(USBIEPBBAX_4); /* Input Endpoint_4: X-buffer base addr. */ +sfr_b(USBIEPCNF_4); /* Input Endpoint_4: Configuration */ +sfr_b(USBIEPSIZXY_3); /* Input Endpoint_3: X/Y-buffer size */ +sfr_b(USBIEPBCTY_3); /* Input Endpoint_3: Y-byte count */ +sfr_b(USBIEPBBAY_3); /* Input Endpoint_3: Y-buffer base addr. */ +//sfrb Spare (0x23DC) /* Not used */ +//sfrb Spare (0x23DB) /* Not used */ +sfr_b(USBIEPBCTX_3); /* Input Endpoint_3: X-byte count */ +sfr_b(USBIEPBBAX_3); /* Input Endpoint_3: X-buffer base addr. */ +sfr_b(USBIEPCNF_3); /* Input Endpoint_3: Configuration */ +sfr_b(USBIEPSIZXY_2); /* Input Endpoint_2: X/Y-buffer size */ +sfr_b(USBIEPBCTY_2); /* Input Endpoint_2: Y-byte count */ +sfr_b(USBIEPBBAY_2); /* Input Endpoint_2: Y-buffer base addr. */ +//sfrb Spare (0x23D4) /* Not used */ +//sfrb Spare (0x23D3) /* Not used */ +sfr_b(USBIEPBCTX_2); /* Input Endpoint_2: X-byte count */ +sfr_b(USBIEPBBAX_2); /* Input Endpoint_2: X-buffer base addr. */ +sfr_b(USBIEPCNF_2); /* Input Endpoint_2: Configuration */ +sfr_b(USBIEPSIZXY_1); /* Input Endpoint_1: X/Y-buffer size */ +sfr_b(USBIEPBCTY_1); /* Input Endpoint_1: Y-byte count */ +sfr_b(USBIEPBBAY_1); /* Input Endpoint_1: Y-buffer base addr. */ +//sfrb Spare (0x23CC) /* Not used */ +//sfrb Spare (0x23CB) /* Not used */ +sfr_b(USBIEPBCTX_1); /* Input Endpoint_1: X-byte count */ +sfr_b(USBIEPBBAX_1); /* Input Endpoint_1: X-buffer base addr. */ +sfr_b(USBIEPCNF_1); /* Input Endpoint_1: Configuration */ +//sfrb (0x23C7) /* */ +//sfrb RESERVED (0x1C00) /* */ +//sfrb (0x23C0) /* */ +sfr_b(USBOEPSIZXY_7); /* Output Endpoint_7: X/Y-buffer size */ +sfr_b(USBOEPBCTY_7); /* Output Endpoint_7: Y-byte count */ +sfr_b(USBOEPBBAY_7); /* Output Endpoint_7: Y-buffer base addr. */ +//sfrb Spare (0x23BC) /* Not used */ +//sfrb Spare (0x23BB) /* Not used */ +sfr_b(USBOEPBCTX_7); /* Output Endpoint_7: X-byte count */ +sfr_b(USBOEPBBAX_7); /* Output Endpoint_7: X-buffer base addr. */ +sfr_b(USBOEPCNF_7); /* Output Endpoint_7: Configuration */ +sfr_b(USBOEPSIZXY_6); /* Output Endpoint_6: X/Y-buffer size */ +sfr_b(USBOEPBCTY_6); /* Output Endpoint_6: Y-byte count */ +sfr_b(USBOEPBBAY_6); /* Output Endpoint_6: Y-buffer base addr. */ +//sfrb Spare (0x23B4) /* Not used */ +//sfrb Spare (0x23B3) /* Not used */ +sfr_b(USBOEPBCTX_6); /* Output Endpoint_6: X-byte count */ +sfr_b(USBOEPBBAX_6); /* Output Endpoint_6: X-buffer base addr. */ +sfr_b(USBOEPCNF_6); /* Output Endpoint_6: Configuration */ +sfr_b(USBOEPSIZXY_5); /* Output Endpoint_5: X/Y-buffer size */ +sfr_b(USBOEPBCTY_5); /* Output Endpoint_5: Y-byte count */ +sfr_b(USBOEPBBAY_5); /* Output Endpoint_5: Y-buffer base addr. */ +//sfrb Spare (0x23AC) /* Not used */ +//sfrb Spare (0x23AB) /* Not used */ +sfr_b(USBOEPBCTX_5); /* Output Endpoint_5: X-byte count */ +sfr_b(USBOEPBBAX_5); /* Output Endpoint_5: X-buffer base addr. */ +sfr_b(USBOEPCNF_5); /* Output Endpoint_5: Configuration */ +sfr_b(USBOEPSIZXY_4); /* Output Endpoint_4: X/Y-buffer size */ +sfr_b(USBOEPBCTY_4); /* Output Endpoint_4: Y-byte count */ +sfr_b(USBOEPBBAY_4); /* Output Endpoint_4: Y-buffer base addr. */ +//sfrb Spare (0x23A4) /* Not used */ +//sfrb Spare (0x23A3) /* Not used */ +sfr_b(USBOEPBCTX_4); /* Output Endpoint_4: X-byte count */ +sfr_b(USBOEPBBAX_4); /* Output Endpoint_4: X-buffer base addr. */ +sfr_b(USBOEPCNF_4); /* Output Endpoint_4: Configuration */ +sfr_b(USBOEPSIZXY_3); /* Output Endpoint_3: X/Y-buffer size */ +sfr_b(USBOEPBCTY_3); /* Output Endpoint_3: Y-byte count */ +sfr_b(USBOEPBBAY_3); /* Output Endpoint_3: Y-buffer base addr. */ +//sfrb Spare (0x239C) /* Not used */ +//sfrb Spare (0x239B) /* Not used */ +sfr_b(USBOEPBCTX_3); /* Output Endpoint_3: X-byte count */ +sfr_b(USBOEPBBAX_3); /* Output Endpoint_3: X-buffer base addr. */ +sfr_b(USBOEPCNF_3); /* Output Endpoint_3: Configuration */ +sfr_b(USBOEPSIZXY_2); /* Output Endpoint_2: X/Y-buffer size */ +sfr_b(USBOEPBCTY_2); /* Output Endpoint_2: Y-byte count */ +sfr_b(USBOEPBBAY_2); /* Output Endpoint_2: Y-buffer base addr. */ +//sfrb Spare (0x2394) /* Not used */ +//sfrb Spare (0x2393) /* Not used */ +sfr_b(USBOEPBCTX_2); /* Output Endpoint_2: X-byte count */ +sfr_b(USBOEPBBAX_2); /* Output Endpoint_2: X-buffer base addr. */ +sfr_b(USBOEPCNF_2); /* Output Endpoint_2: Configuration */ +sfr_b(USBOEPSIZXY_1); /* Output Endpoint_1: X/Y-buffer size */ +sfr_b(USBOEPBCTY_1); /* Output Endpoint_1: Y-byte count */ +sfr_b(USBOEPBBAY_1); /* Output Endpoint_1: Y-buffer base addr. */ +//sfrb Spare (0x238C) /* Not used */ +//sfrb Spare (0x238B) /* Not used */ +sfr_b(USBOEPBCTX_1); /* Output Endpoint_1: X-byte count */ +sfr_b(USBOEPBBAX_1); /* Output Endpoint_1: X-buffer base addr. */ +sfr_b(USBOEPCNF_1); /* Output Endpoint_1: Configuration */ +sfr_b(USBSUBLK); /* Setup Packet Block */ +sfr_b(USBIEP0BUF); /* Input endpoint_0 buffer */ +sfr_b(USBOEP0BUF); /* Output endpoint_0 buffer */ +sfr_b(USBTOPBUFF); /* Top of buffer space */ +// (1904 Bytes) /* Buffer space */ +sfr_b(USBSTABUFF); /* Start of buffer space */ + +/* USBIEPCNF_n Control Bits */ +/* USBOEPCNF_n Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0001) /* USB - */ +#define DBUF (0x0010) /* USB - Double Buffer Enable */ +//#define RESERVED (0x0040) /* USB - */ + +/* USBIEPBCNT_n Control Bits */ +/* USBOEPBCNT_n Control Bits */ +#define CNT4 (0x0010) /* USB - Byte Count Bit 3 */ +#define CNT5 (0x0020) /* USB - Byte Count Bit 3 */ +#define CNT6 (0x0040) /* USB - Byte Count Bit 3 */ +/************************************************************ +* UNIFIED CLOCK SYSTEM +************************************************************/ +#define __MSP430_HAS_UCS__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_UCS__ 0x0160 +#define UCS_BASE __MSP430_BASEADDRESS_UCS__ + +sfr_w(UCSCTL0); /* UCS Control Register 0 */ +sfr_b(UCSCTL0_L); /* UCS Control Register 0 */ +sfr_b(UCSCTL0_H); /* UCS Control Register 0 */ +sfr_w(UCSCTL1); /* UCS Control Register 1 */ +sfr_b(UCSCTL1_L); /* UCS Control Register 1 */ +sfr_b(UCSCTL1_H); /* UCS Control Register 1 */ +sfr_w(UCSCTL2); /* UCS Control Register 2 */ +sfr_b(UCSCTL2_L); /* UCS Control Register 2 */ +sfr_b(UCSCTL2_H); /* UCS Control Register 2 */ +sfr_w(UCSCTL3); /* UCS Control Register 3 */ +sfr_b(UCSCTL3_L); /* UCS Control Register 3 */ +sfr_b(UCSCTL3_H); /* UCS Control Register 3 */ +sfr_w(UCSCTL4); /* UCS Control Register 4 */ +sfr_b(UCSCTL4_L); /* UCS Control Register 4 */ +sfr_b(UCSCTL4_H); /* UCS Control Register 4 */ +sfr_w(UCSCTL5); /* UCS Control Register 5 */ +sfr_b(UCSCTL5_L); /* UCS Control Register 5 */ +sfr_b(UCSCTL5_H); /* UCS Control Register 5 */ +sfr_w(UCSCTL6); /* UCS Control Register 6 */ +sfr_b(UCSCTL6_L); /* UCS Control Register 6 */ +sfr_b(UCSCTL6_H); /* UCS Control Register 6 */ +sfr_w(UCSCTL7); /* UCS Control Register 7 */ +sfr_b(UCSCTL7_L); /* UCS Control Register 7 */ +sfr_b(UCSCTL7_H); /* UCS Control Register 7 */ +sfr_w(UCSCTL8); /* UCS Control Register 8 */ +sfr_b(UCSCTL8_L); /* UCS Control Register 8 */ +sfr_b(UCSCTL8_H); /* UCS Control Register 8 */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000) /* RESERVED */ +#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000) /* RESERVED */ +#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */ + +#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ +#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */ +#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */ +#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */ +#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +//#define RESERVED (0x0004) /* RESERVED */ +#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +//#define RESERVED (0x0004) /* RESERVED */ +#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/************************************************************ +* USCI A0 +************************************************************/ +#define __MSP430_HAS_USCI_A0__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0 +#define USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__ + +sfr_w(UCA0CTLW0); /* USCI A0 Control Word Register 0 */ +sfr_b(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */ +sfr_b(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */ +#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ +#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ +sfr_w(UCA0BRW); /* USCI A0 Baud Word Rate 0 */ +sfr_b(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */ +sfr_b(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */ +#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ +#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ +sfr_b(UCA0MCTL); /* USCI A0 Modulation Control */ +sfr_b(UCA0STAT); /* USCI A0 Status Register */ +sfr_b(UCA0RXBUF); /* USCI A0 Receive Buffer */ +sfr_b(UCA0TXBUF); /* USCI A0 Transmit Buffer */ +sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */ +sfr_w(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */ +sfr_b(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */ +sfr_b(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */ +#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ +#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ +sfr_w(UCA0ICTL); /* USCI A0 Interrupt Enable Register */ +sfr_b(UCA0ICTL_L); /* USCI A0 Interrupt Enable Register */ +sfr_b(UCA0ICTL_H); /* USCI A0 Interrupt Enable Register */ +#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */ +#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */ +sfr_w(UCA0IV); /* USCI A0 Interrupt Vector Register */ + + +/************************************************************ +* USCI B0 +************************************************************/ +#define __MSP430_HAS_USCI_B0__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0 +#define USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__ + + +sfr_w(UCB0CTLW0); /* USCI B0 Control Word Register 0 */ +sfr_b(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */ +sfr_b(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */ +#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ +#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ +sfr_w(UCB0BRW); /* USCI B0 Baud Word Rate 0 */ +sfr_b(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */ +sfr_b(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */ +#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ +#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ +sfr_b(UCB0STAT); /* USCI B0 Status Register */ +sfr_b(UCB0RXBUF); /* USCI B0 Receive Buffer */ +sfr_b(UCB0TXBUF); /* USCI B0 Transmit Buffer */ +sfr_w(UCB0I2COA); /* USCI B0 I2C Own Address */ +sfr_b(UCB0I2COA_L); /* USCI B0 I2C Own Address */ +sfr_b(UCB0I2COA_H); /* USCI B0 I2C Own Address */ +sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */ +sfr_b(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */ +sfr_b(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */ +sfr_w(UCB0ICTL); /* USCI B0 Interrupt Enable Register */ +sfr_b(UCB0ICTL_L); /* USCI B0 Interrupt Enable Register */ +sfr_b(UCB0ICTL_H); /* USCI B0 Interrupt Enable Register */ +#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */ +#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */ +sfr_w(UCB0IV); /* USCI B0 Interrupt Vector Register */ + +// UCAxCTL0 UART-Mode Control Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTL0 SPI-Mode Control Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// UCBxCTL0 I2C-Mode Control Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UCAxCTL1 UART-Mode Control Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// UCxxCTL1 SPI-Mode Control Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// UCBxCTL1 I2C-Mode Control Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ + +/* UCAxMCTL Control Bits */ +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +/* UCAxSTAT Control Bits */ +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +/* UCBxSTAT Control Bits */ +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ + +/* UCAxIRTCTL Control Bits */ +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRRCTL Control Bits */ +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOA9_H (0x0002) /* I2C Own Address 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address 8 */ + +/* UCAxIE Control Bits */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x0004) /* START Condition interrupt enable */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* USCI Interrupt Vector Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */ +#define USCI_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */ +#define USCI_I2C_UCALIFG (0x0002) /* Interrupt Vector: I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* Interrupt Vector: I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* Interrupt Vector: I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* Interrupt Vector: I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG (0x000A) /* Interrupt Vector: I2C Mode: UCRXIFG */ +#define USCI_I2C_UCTXIFG (0x000C) /* Interrupt Vector: I2C Mode: UCTXIFG */ + +/************************************************************ +* USCI A1 +************************************************************/ +#define __MSP430_HAS_USCI_A1__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USCI_A1__ 0x0600 +#define USCI_A1_BASE __MSP430_BASEADDRESS_USCI_A1__ + +sfr_w(UCA1CTLW0); /* USCI A1 Control Word Register 0 */ +sfr_b(UCA1CTLW0_L); /* USCI A1 Control Word Register 0 */ +sfr_b(UCA1CTLW0_H); /* USCI A1 Control Word Register 0 */ +#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */ +#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */ +sfr_w(UCA1BRW); /* USCI A1 Baud Word Rate 0 */ +sfr_b(UCA1BRW_L); /* USCI A1 Baud Word Rate 0 */ +sfr_b(UCA1BRW_H); /* USCI A1 Baud Word Rate 0 */ +#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */ +#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */ +sfr_b(UCA1MCTL); /* USCI A1 Modulation Control */ +sfr_b(UCA1STAT); /* USCI A1 Status Register */ +sfr_b(UCA1RXBUF); /* USCI A1 Receive Buffer */ +sfr_b(UCA1TXBUF); /* USCI A1 Transmit Buffer */ +sfr_b(UCA1ABCTL); /* USCI A1 LIN Control */ +sfr_w(UCA1IRCTL); /* USCI A1 IrDA Transmit Control */ +sfr_b(UCA1IRCTL_L); /* USCI A1 IrDA Transmit Control */ +sfr_b(UCA1IRCTL_H); /* USCI A1 IrDA Transmit Control */ +#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */ +#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */ +sfr_w(UCA1ICTL); /* USCI A1 Interrupt Enable Register */ +sfr_b(UCA1ICTL_L); /* USCI A1 Interrupt Enable Register */ +sfr_b(UCA1ICTL_H); /* USCI A1 Interrupt Enable Register */ +#define UCA1IE UCA1ICTL_L /* USCI A1 Interrupt Enable Register */ +#define UCA1IFG UCA1ICTL_H /* USCI A1 Interrupt Flags Register */ +sfr_w(UCA1IV); /* USCI A1 Interrupt Vector Register */ + + +/************************************************************ +* USCI B1 +************************************************************/ +#define __MSP430_HAS_USCI_B1__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_USCI_B1__ 0x0620 +#define USCI_B1_BASE __MSP430_BASEADDRESS_USCI_B1__ + + +sfr_w(UCB1CTLW0); /* USCI B1 Control Word Register 0 */ +sfr_b(UCB1CTLW0_L); /* USCI B1 Control Word Register 0 */ +sfr_b(UCB1CTLW0_H); /* USCI B1 Control Word Register 0 */ +#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */ +#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */ +sfr_w(UCB1BRW); /* USCI B1 Baud Word Rate 0 */ +sfr_b(UCB1BRW_L); /* USCI B1 Baud Word Rate 0 */ +sfr_b(UCB1BRW_H); /* USCI B1 Baud Word Rate 0 */ +#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */ +#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */ +sfr_b(UCB1STAT); /* USCI B1 Status Register */ +sfr_b(UCB1RXBUF); /* USCI B1 Receive Buffer */ +sfr_b(UCB1TXBUF); /* USCI B1 Transmit Buffer */ +sfr_w(UCB1I2COA); /* USCI B1 I2C Own Address */ +sfr_b(UCB1I2COA_L); /* USCI B1 I2C Own Address */ +sfr_b(UCB1I2COA_H); /* USCI B1 I2C Own Address */ +sfr_w(UCB1I2CSA); /* USCI B1 I2C Slave Address */ +sfr_b(UCB1I2CSA_L); /* USCI B1 I2C Slave Address */ +sfr_b(UCB1I2CSA_H); /* USCI B1 I2C Slave Address */ +sfr_w(UCB1ICTL); /* USCI B1 Interrupt Enable Register */ +sfr_b(UCB1ICTL_L); /* USCI B1 Interrupt Enable Register */ +sfr_b(UCB1ICTL_H); /* USCI B1 Interrupt Enable Register */ +#define UCB1IE UCB1ICTL_L /* USCI B1 Interrupt Enable Register */ +#define UCB1IFG UCB1ICTL_H /* USCI B1 Interrupt Flags Register */ +sfr_w(UCB1IV); /* USCI B1 Interrupt Vector Register */ + +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_WDT_A__ 0x0150 +#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ + +sfr_w(WDTCTL); /* Watchdog Timer Control */ +sfr_b(WDTCTL_L); /* Watchdog Timer Control */ +sfr_b(WDTCTL_H); /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ + +#define WDTPW (0x5A00) + +#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + + +/************************************************************ +* TLV Descriptors +************************************************************/ +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ +#define TLV_BASE __MSP430_BASEADDRESS_TLV__ + +#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ +#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) // Tag End of Table + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + + +#define RTC_VECTOR (42) /* 0xFFD2 RTC */ +#define PORT2_VECTOR (43) /* 0xFFD4 Port 2 */ +#define TIMER2_A1_VECTOR (44) /* 0xFFD6 Timer2_A5 CC1-4, TA */ +#define TIMER2_A0_VECTOR (45) /* 0xFFD8 Timer2_A5 CC0 */ +#define USCI_B1_VECTOR (46) /* 0xFFDA USCI B1 Receive/Transmit */ +#define USCI_A1_VECTOR (47) /* 0xFFDC USCI A1 Receive/Transmit */ +#define PORT1_VECTOR (48) /* 0xFFDE Port 1 */ +#define TIMER1_A1_VECTOR (49) /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ +#define TIMER1_A0_VECTOR (50) /* 0xFFE2 Timer1_A3 CC0 */ +#define DMA_VECTOR (51) /* 0xFFE4 DMA */ +#define USB_UBM_VECTOR (52) /* 0xFFE6 USB Timer / cable event / USB reset */ +#define TIMER0_A1_VECTOR (53) /* 0xFFE8 Timer0_A5 CC1-4, TA */ +#define TIMER0_A0_VECTOR (54) /* 0xFFEA Timer0_A5 CC0 */ +#define ADC12_VECTOR (55) /* 0xFFEC ADC */ +#define USCI_B0_VECTOR (56) /* 0xFFEE USCI B0 Receive/Transmit */ +#define USCI_A0_VECTOR (57) /* 0xFFF0 USCI A0 Receive/Transmit */ +#define WDT_VECTOR (58) /* 0xFFF2 Watchdog Timer */ +#define TIMER0_B1_VECTOR (59) /* 0xFFF4 Timer0_B7 CC1-6, TB */ +#define TIMER0_B0_VECTOR (60) /* 0xFFF6 Timer0_B7 CC0 */ +#define COMP_B_VECTOR (61) /* 0xFFF8 Comparator B */ +#define UNMI_VECTOR (62) /* 0xFFFA User Non-maskable */ +#define SYSNMI_VECTOR (63) /* 0xFFFC System Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __MSP430F5529 */ + diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529.ld b/hw/bsp/msp_exp430f5529lp/msp430f5529.ld new file mode 100644 index 000000000..6fe18de01 --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/msp430f5529.ld @@ -0,0 +1,457 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F5529 devices. */ +/* Version: 1.207 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + BSL : ORIGIN = 0x1000, LENGTH = 0x0800 + RAM : ORIGIN = 0x2400, LENGTH = 0x2000 /* END=0x43FF, size 8192 */ + USBRAM : ORIGIN = 0x1C00, LENGTH = 0x0800 + INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 as 4 128-byte segments */ + INFOA : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x19FF, size 128 */ + INFOB : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x197F, size 128 */ + INFOC : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x18FF, size 128 */ + INFOD : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x187F, size 128 */ + ROM (rx) : ORIGIN = 0x4400, LENGTH = 0xBB80 /* END=0xFF7F, size 48000 */ + HIROM (rx) : ORIGIN = 0x00010000, LENGTH = 0x000143FF + VECT1 : ORIGIN = 0xFF80, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFF82, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFF84, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFF86, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFF88, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFF8A, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFF8C, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFF8E, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFF90, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFF92, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFF94, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFF96, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFF98, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFF9A, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFF9C, LENGTH = 0x0002 + VECT16 : ORIGIN = 0xFF9E, LENGTH = 0x0002 + VECT17 : ORIGIN = 0xFFA0, LENGTH = 0x0002 + VECT18 : ORIGIN = 0xFFA2, LENGTH = 0x0002 + VECT19 : ORIGIN = 0xFFA4, LENGTH = 0x0002 + VECT20 : ORIGIN = 0xFFA6, LENGTH = 0x0002 + VECT21 : ORIGIN = 0xFFA8, LENGTH = 0x0002 + VECT22 : ORIGIN = 0xFFAA, LENGTH = 0x0002 + VECT23 : ORIGIN = 0xFFAC, LENGTH = 0x0002 + VECT24 : ORIGIN = 0xFFAE, LENGTH = 0x0002 + VECT25 : ORIGIN = 0xFFB0, LENGTH = 0x0002 + VECT26 : ORIGIN = 0xFFB2, LENGTH = 0x0002 + VECT27 : ORIGIN = 0xFFB4, LENGTH = 0x0002 + VECT28 : ORIGIN = 0xFFB6, LENGTH = 0x0002 + VECT29 : ORIGIN = 0xFFB8, LENGTH = 0x0002 + VECT30 : ORIGIN = 0xFFBA, LENGTH = 0x0002 + VECT31 : ORIGIN = 0xFFBC, LENGTH = 0x0002 + VECT32 : ORIGIN = 0xFFBE, LENGTH = 0x0002 + VECT33 : ORIGIN = 0xFFC0, LENGTH = 0x0002 + VECT34 : ORIGIN = 0xFFC2, LENGTH = 0x0002 + VECT35 : ORIGIN = 0xFFC4, LENGTH = 0x0002 + VECT36 : ORIGIN = 0xFFC6, LENGTH = 0x0002 + VECT37 : ORIGIN = 0xFFC8, LENGTH = 0x0002 + VECT38 : ORIGIN = 0xFFCA, LENGTH = 0x0002 + VECT39 : ORIGIN = 0xFFCC, LENGTH = 0x0002 + VECT40 : ORIGIN = 0xFFCE, LENGTH = 0x0002 + VECT41 : ORIGIN = 0xFFD0, LENGTH = 0x0002 + VECT42 : ORIGIN = 0xFFD2, LENGTH = 0x0002 + VECT43 : ORIGIN = 0xFFD4, LENGTH = 0x0002 + VECT44 : ORIGIN = 0xFFD6, LENGTH = 0x0002 + VECT45 : ORIGIN = 0xFFD8, LENGTH = 0x0002 + VECT46 : ORIGIN = 0xFFDA, LENGTH = 0x0002 + VECT47 : ORIGIN = 0xFFDC, LENGTH = 0x0002 + VECT48 : ORIGIN = 0xFFDE, LENGTH = 0x0002 + VECT49 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT50 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT51 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT52 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT53 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT54 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT55 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT56 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT57 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT58 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT59 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT60 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT61 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT62 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT63 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15 + __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16 + __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17 + __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18 + __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19 + __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) } > VECT20 + __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) } > VECT21 + __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) } > VECT22 + __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) } > VECT23 + __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) } > VECT24 + __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) } > VECT25 + __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) } > VECT26 + __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) } > VECT27 + __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) } > VECT28 + __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) } > VECT29 + __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) } > VECT30 + __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) } > VECT31 + __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) } > VECT32 + __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) } > VECT33 + __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) } > VECT34 + __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) } > VECT35 + __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) } > VECT36 + __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) } > VECT37 + __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) } > VECT38 + __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) } > VECT39 + __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) } > VECT40 + __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) } > VECT41 + __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) KEEP (*(__interrupt_vector_rtc)) } > VECT42 + __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) KEEP (*(__interrupt_vector_port2)) } > VECT43 + __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) KEEP (*(__interrupt_vector_timer2_a1)) } > VECT44 + __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) KEEP (*(__interrupt_vector_timer2_a0)) } > VECT45 + __interrupt_vector_46 : { KEEP (*(__interrupt_vector_46)) KEEP (*(__interrupt_vector_usci_b1)) } > VECT46 + __interrupt_vector_47 : { KEEP (*(__interrupt_vector_47)) KEEP (*(__interrupt_vector_usci_a1)) } > VECT47 + __interrupt_vector_48 : { KEEP (*(__interrupt_vector_48)) KEEP (*(__interrupt_vector_port1)) } > VECT48 + __interrupt_vector_49 : { KEEP (*(__interrupt_vector_49)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT49 + __interrupt_vector_50 : { KEEP (*(__interrupt_vector_50)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT50 + __interrupt_vector_51 : { KEEP (*(__interrupt_vector_51)) KEEP (*(__interrupt_vector_dma)) } > VECT51 + __interrupt_vector_52 : { KEEP (*(__interrupt_vector_52)) KEEP (*(__interrupt_vector_usb_ubm)) } > VECT52 + __interrupt_vector_53 : { KEEP (*(__interrupt_vector_53)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT53 + __interrupt_vector_54 : { KEEP (*(__interrupt_vector_54)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT54 + __interrupt_vector_55 : { KEEP (*(__interrupt_vector_55)) KEEP (*(__interrupt_vector_adc12)) } > VECT55 + __interrupt_vector_56 : { KEEP (*(__interrupt_vector_56)) KEEP (*(__interrupt_vector_usci_b0)) } > VECT56 + __interrupt_vector_57 : { KEEP (*(__interrupt_vector_57)) KEEP (*(__interrupt_vector_usci_a0)) } > VECT57 + __interrupt_vector_58 : { KEEP (*(__interrupt_vector_58)) KEEP (*(__interrupt_vector_wdt)) } > VECT58 + __interrupt_vector_59 : { KEEP (*(__interrupt_vector_59)) KEEP (*(__interrupt_vector_timer0_b1)) } > VECT59 + __interrupt_vector_60 : { KEEP (*(__interrupt_vector_60)) KEEP (*(__interrupt_vector_timer0_b0)) } > VECT60 + __interrupt_vector_61 : { KEEP (*(__interrupt_vector_61)) KEEP (*(__interrupt_vector_comp_b)) } > VECT61 + __interrupt_vector_62 : { KEEP (*(__interrupt_vector_62)) KEEP (*(__interrupt_vector_unmi)) } > VECT62 + __interrupt_vector_63 : { KEEP (*(__interrupt_vector_63)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT63 + __reset_vector : + { + KEEP (*(__interrupt_vector_64)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .lower.rodata : + { + . = ALIGN(2); + *(.lower.rodata.* .lower.rodata) + } > ROM + + .rodata : + { + . = ALIGN(2); + *(.plt) + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + } > ROM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from from the + crtend.o file until after the sorted ctors. The .ctor section + from the crtend file contains the end of ctors marker and it + must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .upper.rodata : + { + *(.upper.rodata.* .upper.rodata) + } > HIROM + + .data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + *(.lower.data.* .lower.data) + + . = ALIGN(2); + *(.either.data.* .either.data) + + . = ALIGN(2); + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + . = ALIGN(2); + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT> ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.lower.bss.* .lower.bss) + . = ALIGN(2); + *(.either.bss.* .either.bss) + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + /* This is just for crt0.S and interrupt handlers. */ + .lowtext : + { + PROVIDE (_start = .); + . = ALIGN(2); + KEEP (*(SORT(.crt_*))) + KEEP (*(.lowtext)) + } > ROM + + .lower.text : + { + . = ALIGN(2); + *(.lower.text.* .lower.text) + } > ROM + + .text : + { + . = ALIGN(2); + *(.text .stub .text.* .gnu.linkonce.t.* .text:*) + + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .upper.text : + { + . = ALIGN(2); + *(.upper.text.* .upper.text) + } > HIROM + + .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* Make sure that upper data sections are not used. */ + .upper : + { + *(.upper.bss.* .upper.bss) + *(.upper.data.* .upper.data) + ASSERT (SIZEOF(.upper) == 0, "This MCU does not support placing read/write data into high memory"); + } > HIROM + + /* The rest are all not normally part of the runtime image. */ + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE msp430f5529_symbols.ld + diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld b/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld new file mode 100644 index 000000000..91448ad4f --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld @@ -0,0 +1,867 @@ +/* ============================================================================ */ +/* Copyright (c) 2019, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430F5529 devices. */ +/* Version: 1.207 */ + +/************************************************************ +* STANDARD BITS +************************************************************/ +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ +/************************************************************ +* ADC12 PLUS +************************************************************/ +PROVIDE(ADC12CTL0 = 0x0700); +PROVIDE(ADC12CTL0_L = 0x0700); +PROVIDE(ADC12CTL0_H = 0x0701); +PROVIDE(ADC12CTL1 = 0x0702); +PROVIDE(ADC12CTL1_L = 0x0702); +PROVIDE(ADC12CTL1_H = 0x0703); +PROVIDE(ADC12CTL2 = 0x0704); +PROVIDE(ADC12CTL2_L = 0x0704); +PROVIDE(ADC12CTL2_H = 0x0705); +PROVIDE(ADC12IFG = 0x070A); +PROVIDE(ADC12IFG_L = 0x070A); +PROVIDE(ADC12IFG_H = 0x070B); +PROVIDE(ADC12IE = 0x070C); +PROVIDE(ADC12IE_L = 0x070C); +PROVIDE(ADC12IE_H = 0x070D); +PROVIDE(ADC12IV = 0x070E); +PROVIDE(ADC12IV_L = 0x070E); +PROVIDE(ADC12IV_H = 0x070F); +PROVIDE(ADC12MEM0 = 0x0720); +PROVIDE(ADC12MEM0_L = 0x0720); +PROVIDE(ADC12MEM0_H = 0x0721); +PROVIDE(ADC12MEM1 = 0x0722); +PROVIDE(ADC12MEM1_L = 0x0722); +PROVIDE(ADC12MEM1_H = 0x0723); +PROVIDE(ADC12MEM2 = 0x0724); +PROVIDE(ADC12MEM2_L = 0x0724); +PROVIDE(ADC12MEM2_H = 0x0725); +PROVIDE(ADC12MEM3 = 0x0726); +PROVIDE(ADC12MEM3_L = 0x0726); +PROVIDE(ADC12MEM3_H = 0x0727); +PROVIDE(ADC12MEM4 = 0x0728); +PROVIDE(ADC12MEM4_L = 0x0728); +PROVIDE(ADC12MEM4_H = 0x0729); +PROVIDE(ADC12MEM5 = 0x072A); +PROVIDE(ADC12MEM5_L = 0x072A); +PROVIDE(ADC12MEM5_H = 0x072B); +PROVIDE(ADC12MEM6 = 0x072C); +PROVIDE(ADC12MEM6_L = 0x072C); +PROVIDE(ADC12MEM6_H = 0x072D); +PROVIDE(ADC12MEM7 = 0x072E); +PROVIDE(ADC12MEM7_L = 0x072E); +PROVIDE(ADC12MEM7_H = 0x072F); +PROVIDE(ADC12MEM8 = 0x0730); +PROVIDE(ADC12MEM8_L = 0x0730); +PROVIDE(ADC12MEM8_H = 0x0731); +PROVIDE(ADC12MEM9 = 0x0732); +PROVIDE(ADC12MEM9_L = 0x0732); +PROVIDE(ADC12MEM9_H = 0x0733); +PROVIDE(ADC12MEM10 = 0x0734); +PROVIDE(ADC12MEM10_L = 0x0734); +PROVIDE(ADC12MEM10_H = 0x0735); +PROVIDE(ADC12MEM11 = 0x0736); +PROVIDE(ADC12MEM11_L = 0x0736); +PROVIDE(ADC12MEM11_H = 0x0737); +PROVIDE(ADC12MEM12 = 0x0738); +PROVIDE(ADC12MEM12_L = 0x0738); +PROVIDE(ADC12MEM12_H = 0x0739); +PROVIDE(ADC12MEM13 = 0x073A); +PROVIDE(ADC12MEM13_L = 0x073A); +PROVIDE(ADC12MEM13_H = 0x073B); +PROVIDE(ADC12MEM14 = 0x073C); +PROVIDE(ADC12MEM14_L = 0x073C); +PROVIDE(ADC12MEM14_H = 0x073D); +PROVIDE(ADC12MEM15 = 0x073E); +PROVIDE(ADC12MEM15_L = 0x073E); +PROVIDE(ADC12MEM15_H = 0x073F); +PROVIDE(ADC12MCTL0 = 0x0710); +PROVIDE(ADC12MCTL1 = 0x0711); +PROVIDE(ADC12MCTL2 = 0x0712); +PROVIDE(ADC12MCTL3 = 0x0713); +PROVIDE(ADC12MCTL4 = 0x0714); +PROVIDE(ADC12MCTL5 = 0x0715); +PROVIDE(ADC12MCTL6 = 0x0716); +PROVIDE(ADC12MCTL7 = 0x0717); +PROVIDE(ADC12MCTL8 = 0x0718); +PROVIDE(ADC12MCTL9 = 0x0719); +PROVIDE(ADC12MCTL10 = 0x071A); +PROVIDE(ADC12MCTL11 = 0x071B); +PROVIDE(ADC12MCTL12 = 0x071C); +PROVIDE(ADC12MCTL13 = 0x071D); +PROVIDE(ADC12MCTL14 = 0x071E); +PROVIDE(ADC12MCTL15 = 0x071F); +/************************************************************ +* Comparator B +************************************************************/ +PROVIDE(CBCTL0 = 0x08C0); +PROVIDE(CBCTL0_L = 0x08C0); +PROVIDE(CBCTL0_H = 0x08C1); +PROVIDE(CBCTL1 = 0x08C2); +PROVIDE(CBCTL1_L = 0x08C2); +PROVIDE(CBCTL1_H = 0x08C3); +PROVIDE(CBCTL2 = 0x08C4); +PROVIDE(CBCTL2_L = 0x08C4); +PROVIDE(CBCTL2_H = 0x08C5); +PROVIDE(CBCTL3 = 0x08C6); +PROVIDE(CBCTL3_L = 0x08C6); +PROVIDE(CBCTL3_H = 0x08C7); +PROVIDE(CBINT = 0x08CC); +PROVIDE(CBINT_L = 0x08CC); +PROVIDE(CBINT_H = 0x08CD); +PROVIDE(CBIV = 0x08CE); +/************************************************************* +* CRC Module +*************************************************************/ +PROVIDE(CRCDI = 0x0150); +PROVIDE(CRCDI_L = 0x0150); +PROVIDE(CRCDI_H = 0x0151); +PROVIDE(CRCDIRB = 0x0152); +PROVIDE(CRCDIRB_L = 0x0152); +PROVIDE(CRCDIRB_H = 0x0153); +PROVIDE(CRCINIRES = 0x0154); +PROVIDE(CRCINIRES_L = 0x0154); +PROVIDE(CRCINIRES_H = 0x0155); +PROVIDE(CRCRESR = 0x0156); +PROVIDE(CRCRESR_L = 0x0156); +PROVIDE(CRCRESR_H = 0x0157); +/************************************************************ +* DMA_X +************************************************************/ +PROVIDE(DMACTL0 = 0x0500); +PROVIDE(DMACTL1 = 0x0502); +PROVIDE(DMACTL2 = 0x0504); +PROVIDE(DMACTL3 = 0x0506); +PROVIDE(DMACTL4 = 0x0508); +PROVIDE(DMAIV = 0x050E); +PROVIDE(DMA0CTL = 0x0510); +PROVIDE(DMA0SA = 0x0512); +PROVIDE(DMA0SAL = 0x0512); +PROVIDE(DMA0DA = 0x0516); +PROVIDE(DMA0DAL = 0x0516); +PROVIDE(DMA0SZ = 0x051A); +PROVIDE(DMA1CTL = 0x0520); +PROVIDE(DMA1SA = 0x0522); +PROVIDE(DMA1SAL = 0x0522); +PROVIDE(DMA1DA = 0x0526); +PROVIDE(DMA1DAL = 0x0526); +PROVIDE(DMA1SZ = 0x052A); +PROVIDE(DMA2CTL = 0x0530); +PROVIDE(DMA2SA = 0x0532); +PROVIDE(DMA2SAL = 0x0532); +PROVIDE(DMA2DA = 0x0536); +PROVIDE(DMA2DAL = 0x0536); +PROVIDE(DMA2SZ = 0x053A); +/************************************************************* +* Flash Memory +*************************************************************/ +PROVIDE(FCTL1 = 0x0140); +PROVIDE(FCTL1_L = 0x0140); +PROVIDE(FCTL1_H = 0x0141); +PROVIDE(FCTL3 = 0x0144); +PROVIDE(FCTL3_L = 0x0144); +PROVIDE(FCTL3_H = 0x0145); +PROVIDE(FCTL4 = 0x0146); +PROVIDE(FCTL4_L = 0x0146); +PROVIDE(FCTL4_H = 0x0147); +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +PROVIDE(MPY = 0x04C0); +PROVIDE(MPY_L = 0x04C0); +PROVIDE(MPY_H = 0x04C1); +PROVIDE(MPYS = 0x04C2); +PROVIDE(MPYS_L = 0x04C2); +PROVIDE(MPYS_H = 0x04C3); +PROVIDE(MAC = 0x04C4); +PROVIDE(MAC_L = 0x04C4); +PROVIDE(MAC_H = 0x04C5); +PROVIDE(MACS = 0x04C6); +PROVIDE(MACS_L = 0x04C6); +PROVIDE(MACS_H = 0x04C7); +PROVIDE(OP2 = 0x04C8); +PROVIDE(OP2_L = 0x04C8); +PROVIDE(OP2_H = 0x04C9); +PROVIDE(RESLO = 0x04CA); +PROVIDE(RESLO_L = 0x04CA); +PROVIDE(RESLO_H = 0x04CB); +PROVIDE(RESHI = 0x04CC); +PROVIDE(RESHI_L = 0x04CC); +PROVIDE(RESHI_H = 0x04CD); +PROVIDE(SUMEXT = 0x04CE); +PROVIDE(SUMEXT_L = 0x04CE); +PROVIDE(SUMEXT_H = 0x04CF); +PROVIDE(MPY32L = 0x04D0); +PROVIDE(MPY32L_L = 0x04D0); +PROVIDE(MPY32L_H = 0x04D1); +PROVIDE(MPY32H = 0x04D2); +PROVIDE(MPY32H_L = 0x04D2); +PROVIDE(MPY32H_H = 0x04D3); +PROVIDE(MPYS32L = 0x04D4); +PROVIDE(MPYS32L_L = 0x04D4); +PROVIDE(MPYS32L_H = 0x04D5); +PROVIDE(MPYS32H = 0x04D6); +PROVIDE(MPYS32H_L = 0x04D6); +PROVIDE(MPYS32H_H = 0x04D7); +PROVIDE(MAC32L = 0x04D8); +PROVIDE(MAC32L_L = 0x04D8); +PROVIDE(MAC32L_H = 0x04D9); +PROVIDE(MAC32H = 0x04DA); +PROVIDE(MAC32H_L = 0x04DA); +PROVIDE(MAC32H_H = 0x04DB); +PROVIDE(MACS32L = 0x04DC); +PROVIDE(MACS32L_L = 0x04DC); +PROVIDE(MACS32L_H = 0x04DD); +PROVIDE(MACS32H = 0x04DE); +PROVIDE(MACS32H_L = 0x04DE); +PROVIDE(MACS32H_H = 0x04DF); +PROVIDE(OP2L = 0x04E0); +PROVIDE(OP2L_L = 0x04E0); +PROVIDE(OP2L_H = 0x04E1); +PROVIDE(OP2H = 0x04E2); +PROVIDE(OP2H_L = 0x04E2); +PROVIDE(OP2H_H = 0x04E3); +PROVIDE(RES0 = 0x04E4); +PROVIDE(RES0_L = 0x04E4); +PROVIDE(RES0_H = 0x04E5); +PROVIDE(RES1 = 0x04E6); +PROVIDE(RES1_L = 0x04E6); +PROVIDE(RES1_H = 0x04E7); +PROVIDE(RES2 = 0x04E8); +PROVIDE(RES2_L = 0x04E8); +PROVIDE(RES2_H = 0x04E9); +PROVIDE(RES3 = 0x04EA); +PROVIDE(RES3_L = 0x04EA); +PROVIDE(RES3_H = 0x04EB); +PROVIDE(MPY32CTL0 = 0x04EC); +PROVIDE(MPY32CTL0_L = 0x04EC); +PROVIDE(MPY32CTL0_H = 0x04ED); +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PAIN = 0x0200); +PROVIDE(PAIN_L = 0x0200); +PROVIDE(PAIN_H = 0x0201); +PROVIDE(PAOUT = 0x0202); +PROVIDE(PAOUT_L = 0x0202); +PROVIDE(PAOUT_H = 0x0203); +PROVIDE(PADIR = 0x0204); +PROVIDE(PADIR_L = 0x0204); +PROVIDE(PADIR_H = 0x0205); +PROVIDE(PAREN = 0x0206); +PROVIDE(PAREN_L = 0x0206); +PROVIDE(PAREN_H = 0x0207); +PROVIDE(PADS = 0x0208); +PROVIDE(PADS_L = 0x0208); +PROVIDE(PADS_H = 0x0209); +PROVIDE(PASEL = 0x020A); +PROVIDE(PASEL_L = 0x020A); +PROVIDE(PASEL_H = 0x020B); +PROVIDE(PAIES = 0x0218); +PROVIDE(PAIES_L = 0x0218); +PROVIDE(PAIES_H = 0x0219); +PROVIDE(PAIE = 0x021A); +PROVIDE(PAIE_L = 0x021A); +PROVIDE(PAIE_H = 0x021B); +PROVIDE(PAIFG = 0x021C); +PROVIDE(PAIFG_L = 0x021C); +PROVIDE(PAIFG_H = 0x021D); +PROVIDE(P1IV = 0x020E); +PROVIDE(P2IV = 0x021E); +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PBIN = 0x0220); +PROVIDE(PBIN_L = 0x0220); +PROVIDE(PBIN_H = 0x0221); +PROVIDE(PBOUT = 0x0222); +PROVIDE(PBOUT_L = 0x0222); +PROVIDE(PBOUT_H = 0x0223); +PROVIDE(PBDIR = 0x0224); +PROVIDE(PBDIR_L = 0x0224); +PROVIDE(PBDIR_H = 0x0225); +PROVIDE(PBREN = 0x0226); +PROVIDE(PBREN_L = 0x0226); +PROVIDE(PBREN_H = 0x0227); +PROVIDE(PBDS = 0x0228); +PROVIDE(PBDS_L = 0x0228); +PROVIDE(PBDS_H = 0x0229); +PROVIDE(PBSEL = 0x022A); +PROVIDE(PBSEL_L = 0x022A); +PROVIDE(PBSEL_H = 0x022B); +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PCIN = 0x0240); +PROVIDE(PCIN_L = 0x0240); +PROVIDE(PCIN_H = 0x0241); +PROVIDE(PCOUT = 0x0242); +PROVIDE(PCOUT_L = 0x0242); +PROVIDE(PCOUT_H = 0x0243); +PROVIDE(PCDIR = 0x0244); +PROVIDE(PCDIR_L = 0x0244); +PROVIDE(PCDIR_H = 0x0245); +PROVIDE(PCREN = 0x0246); +PROVIDE(PCREN_L = 0x0246); +PROVIDE(PCREN_H = 0x0247); +PROVIDE(PCDS = 0x0248); +PROVIDE(PCDS_L = 0x0248); +PROVIDE(PCDS_H = 0x0249); +PROVIDE(PCSEL = 0x024A); +PROVIDE(PCSEL_L = 0x024A); +PROVIDE(PCSEL_H = 0x024B); +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PDIN = 0x0260); +PROVIDE(PDIN_L = 0x0260); +PROVIDE(PDIN_H = 0x0261); +PROVIDE(PDOUT = 0x0262); +PROVIDE(PDOUT_L = 0x0262); +PROVIDE(PDOUT_H = 0x0263); +PROVIDE(PDDIR = 0x0264); +PROVIDE(PDDIR_L = 0x0264); +PROVIDE(PDDIR_H = 0x0265); +PROVIDE(PDREN = 0x0266); +PROVIDE(PDREN_L = 0x0266); +PROVIDE(PDREN_H = 0x0267); +PROVIDE(PDDS = 0x0268); +PROVIDE(PDDS_L = 0x0268); +PROVIDE(PDDS_H = 0x0269); +PROVIDE(PDSEL = 0x026A); +PROVIDE(PDSEL_L = 0x026A); +PROVIDE(PDSEL_H = 0x026B); +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +PROVIDE(PJIN = 0x0320); +PROVIDE(PJIN_L = 0x0320); +PROVIDE(PJIN_H = 0x0321); +PROVIDE(PJOUT = 0x0322); +PROVIDE(PJOUT_L = 0x0322); +PROVIDE(PJOUT_H = 0x0323); +PROVIDE(PJDIR = 0x0324); +PROVIDE(PJDIR_L = 0x0324); +PROVIDE(PJDIR_H = 0x0325); +PROVIDE(PJREN = 0x0326); +PROVIDE(PJREN_L = 0x0326); +PROVIDE(PJREN_H = 0x0327); +PROVIDE(PJDS = 0x0328); +PROVIDE(PJDS_L = 0x0328); +PROVIDE(PJDS_H = 0x0329); +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +PROVIDE(PMAPKEYID = 0x01C0); +PROVIDE(PMAPKEYID_L = 0x01C0); +PROVIDE(PMAPKEYID_H = 0x01C1); +PROVIDE(PMAPCTL = 0x01C2); +PROVIDE(PMAPCTL_L = 0x01C2); +PROVIDE(PMAPCTL_H = 0x01C3); +/************************************************************ +* PORT 4 MAPPING CONTROLLER +************************************************************/ +PROVIDE(P4MAP01 = 0x01E0); +PROVIDE(P4MAP01_L = 0x01E0); +PROVIDE(P4MAP01_H = 0x01E1); +PROVIDE(P4MAP23 = 0x01E2); +PROVIDE(P4MAP23_L = 0x01E2); +PROVIDE(P4MAP23_H = 0x01E3); +PROVIDE(P4MAP45 = 0x01E4); +PROVIDE(P4MAP45_L = 0x01E4); +PROVIDE(P4MAP45_H = 0x01E5); +PROVIDE(P4MAP67 = 0x01E6); +PROVIDE(P4MAP67_L = 0x01E6); +PROVIDE(P4MAP67_H = 0x01E7); +/************************************************************ +* PMM - Power Management System +************************************************************/ +PROVIDE(PMMCTL0 = 0x0120); +PROVIDE(PMMCTL0_L = 0x0120); +PROVIDE(PMMCTL0_H = 0x0121); +PROVIDE(PMMCTL1 = 0x0122); +PROVIDE(PMMCTL1_L = 0x0122); +PROVIDE(PMMCTL1_H = 0x0123); +PROVIDE(SVSMHCTL = 0x0124); +PROVIDE(SVSMHCTL_L = 0x0124); +PROVIDE(SVSMHCTL_H = 0x0125); +PROVIDE(SVSMLCTL = 0x0126); +PROVIDE(SVSMLCTL_L = 0x0126); +PROVIDE(SVSMLCTL_H = 0x0127); +PROVIDE(SVSMIO = 0x0128); +PROVIDE(SVSMIO_L = 0x0128); +PROVIDE(SVSMIO_H = 0x0129); +PROVIDE(PMMIFG = 0x012C); +PROVIDE(PMMIFG_L = 0x012C); +PROVIDE(PMMIFG_H = 0x012D); +PROVIDE(PMMRIE = 0x012E); +PROVIDE(PMMRIE_L = 0x012E); +PROVIDE(PMMRIE_H = 0x012F); +PROVIDE(PM5CTL0 = 0x0130); +PROVIDE(PM5CTL0_L = 0x0130); +PROVIDE(PM5CTL0_H = 0x0131); +/************************************************************* +* RAM Control Module +*************************************************************/ +PROVIDE(RCCTL0 = 0x0158); +PROVIDE(RCCTL0_L = 0x0158); +PROVIDE(RCCTL0_H = 0x0159); +/************************************************************ +* Shared Reference +************************************************************/ +PROVIDE(REFCTL0 = 0x01B0); +PROVIDE(REFCTL0_L = 0x01B0); +PROVIDE(REFCTL0_H = 0x01B1); +/************************************************************ +* Real Time Clock +************************************************************/ +PROVIDE(RTCCTL01 = 0x04A0); +PROVIDE(RTCCTL01_L = 0x04A0); +PROVIDE(RTCCTL01_H = 0x04A1); +PROVIDE(RTCCTL23 = 0x04A2); +PROVIDE(RTCCTL23_L = 0x04A2); +PROVIDE(RTCCTL23_H = 0x04A3); +PROVIDE(RTCPS0CTL = 0x04A8); +PROVIDE(RTCPS0CTL_L = 0x04A8); +PROVIDE(RTCPS0CTL_H = 0x04A9); +PROVIDE(RTCPS1CTL = 0x04AA); +PROVIDE(RTCPS1CTL_L = 0x04AA); +PROVIDE(RTCPS1CTL_H = 0x04AB); +PROVIDE(RTCPS = 0x04AC); +PROVIDE(RTCPS_L = 0x04AC); +PROVIDE(RTCPS_H = 0x04AD); +PROVIDE(RTCIV = 0x04AE); +PROVIDE(RTCTIM0 = 0x04B0); +PROVIDE(RTCTIM0_L = 0x04B0); +PROVIDE(RTCTIM0_H = 0x04B1); +PROVIDE(RTCTIM1 = 0x04B2); +PROVIDE(RTCTIM1_L = 0x04B2); +PROVIDE(RTCTIM1_H = 0x04B3); +PROVIDE(RTCDATE = 0x04B4); +PROVIDE(RTCDATE_L = 0x04B4); +PROVIDE(RTCDATE_H = 0x04B5); +PROVIDE(RTCYEAR = 0x04B6); +PROVIDE(RTCYEAR_L = 0x04B6); +PROVIDE(RTCYEAR_H = 0x04B7); +PROVIDE(RTCAMINHR = 0x04B8); +PROVIDE(RTCAMINHR_L = 0x04B8); +PROVIDE(RTCAMINHR_H = 0x04B9); +PROVIDE(RTCADOWDAY = 0x04BA); +PROVIDE(RTCADOWDAY_L = 0x04BA); +PROVIDE(RTCADOWDAY_H = 0x04BB); +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +PROVIDE(SFRIE1 = 0x0100); +PROVIDE(SFRIE1_L = 0x0100); +PROVIDE(SFRIE1_H = 0x0101); +PROVIDE(SFRIFG1 = 0x0102); +PROVIDE(SFRIFG1_L = 0x0102); +PROVIDE(SFRIFG1_H = 0x0103); +PROVIDE(SFRRPCR = 0x0104); +PROVIDE(SFRRPCR_L = 0x0104); +PROVIDE(SFRRPCR_H = 0x0105); +/************************************************************ +* SYS - System Module +************************************************************/ +PROVIDE(SYSCTL = 0x0180); +PROVIDE(SYSCTL_L = 0x0180); +PROVIDE(SYSCTL_H = 0x0181); +PROVIDE(SYSBSLC = 0x0182); +PROVIDE(SYSBSLC_L = 0x0182); +PROVIDE(SYSBSLC_H = 0x0183); +PROVIDE(SYSJMBC = 0x0186); +PROVIDE(SYSJMBC_L = 0x0186); +PROVIDE(SYSJMBC_H = 0x0187); +PROVIDE(SYSJMBI0 = 0x0188); +PROVIDE(SYSJMBI0_L = 0x0188); +PROVIDE(SYSJMBI0_H = 0x0189); +PROVIDE(SYSJMBI1 = 0x018A); +PROVIDE(SYSJMBI1_L = 0x018A); +PROVIDE(SYSJMBI1_H = 0x018B); +PROVIDE(SYSJMBO0 = 0x018C); +PROVIDE(SYSJMBO0_L = 0x018C); +PROVIDE(SYSJMBO0_H = 0x018D); +PROVIDE(SYSJMBO1 = 0x018E); +PROVIDE(SYSJMBO1_L = 0x018E); +PROVIDE(SYSJMBO1_H = 0x018F); +PROVIDE(SYSBERRIV = 0x0198); +PROVIDE(SYSBERRIV_L = 0x0198); +PROVIDE(SYSBERRIV_H = 0x0199); +PROVIDE(SYSUNIV = 0x019A); +PROVIDE(SYSUNIV_L = 0x019A); +PROVIDE(SYSUNIV_H = 0x019B); +PROVIDE(SYSSNIV = 0x019C); +PROVIDE(SYSSNIV_L = 0x019C); +PROVIDE(SYSSNIV_H = 0x019D); +PROVIDE(SYSRSTIV = 0x019E); +PROVIDE(SYSRSTIV_L = 0x019E); +PROVIDE(SYSRSTIV_H = 0x019F); +/************************************************************ +* Timer0_A5 +************************************************************/ +PROVIDE(TA0CTL = 0x0340); +PROVIDE(TA0CCTL0 = 0x0342); +PROVIDE(TA0CCTL1 = 0x0344); +PROVIDE(TA0CCTL2 = 0x0346); +PROVIDE(TA0CCTL3 = 0x0348); +PROVIDE(TA0CCTL4 = 0x034A); +PROVIDE(TA0R = 0x0350); +PROVIDE(TA0CCR0 = 0x0352); +PROVIDE(TA0CCR1 = 0x0354); +PROVIDE(TA0CCR2 = 0x0356); +PROVIDE(TA0CCR3 = 0x0358); +PROVIDE(TA0CCR4 = 0x035A); +PROVIDE(TA0IV = 0x036E); +PROVIDE(TA0EX0 = 0x0360); +/************************************************************ +* Timer1_A3 +************************************************************/ +PROVIDE(TA1CTL = 0x0380); +PROVIDE(TA1CCTL0 = 0x0382); +PROVIDE(TA1CCTL1 = 0x0384); +PROVIDE(TA1CCTL2 = 0x0386); +PROVIDE(TA1R = 0x0390); +PROVIDE(TA1CCR0 = 0x0392); +PROVIDE(TA1CCR1 = 0x0394); +PROVIDE(TA1CCR2 = 0x0396); +PROVIDE(TA1IV = 0x03AE); +PROVIDE(TA1EX0 = 0x03A0); +/************************************************************ +* Timer2_A3 +************************************************************/ +PROVIDE(TA2CTL = 0x0400); +PROVIDE(TA2CCTL0 = 0x0402); +PROVIDE(TA2CCTL1 = 0x0404); +PROVIDE(TA2CCTL2 = 0x0406); +PROVIDE(TA2R = 0x0410); +PROVIDE(TA2CCR0 = 0x0412); +PROVIDE(TA2CCR1 = 0x0414); +PROVIDE(TA2CCR2 = 0x0416); +PROVIDE(TA2IV = 0x042E); +PROVIDE(TA2EX0 = 0x0420); +/************************************************************ +* Timer0_B7 +************************************************************/ +PROVIDE(TB0CTL = 0x03C0); +PROVIDE(TB0CCTL0 = 0x03C2); +PROVIDE(TB0CCTL1 = 0x03C4); +PROVIDE(TB0CCTL2 = 0x03C6); +PROVIDE(TB0CCTL3 = 0x03C8); +PROVIDE(TB0CCTL4 = 0x03CA); +PROVIDE(TB0CCTL5 = 0x03CC); +PROVIDE(TB0CCTL6 = 0x03CE); +PROVIDE(TB0R = 0x03D0); +PROVIDE(TB0CCR0 = 0x03D2); +PROVIDE(TB0CCR1 = 0x03D4); +PROVIDE(TB0CCR2 = 0x03D6); +PROVIDE(TB0CCR3 = 0x03D8); +PROVIDE(TB0CCR4 = 0x03DA); +PROVIDE(TB0CCR5 = 0x03DC); +PROVIDE(TB0CCR6 = 0x03DE); +PROVIDE(TB0EX0 = 0x03E0); +PROVIDE(TB0IV = 0x03EE); +/************************************************************ +* USB +************************************************************/ +PROVIDE(USBKEYID = 0x0900); +PROVIDE(USBKEYID_L = 0x0900); +PROVIDE(USBKEYID_H = 0x0901); +PROVIDE(USBCNF = 0x0902); +PROVIDE(USBCNF_L = 0x0902); +PROVIDE(USBCNF_H = 0x0903); +PROVIDE(USBPHYCTL = 0x0904); +PROVIDE(USBPHYCTL_L = 0x0904); +PROVIDE(USBPHYCTL_H = 0x0905); +PROVIDE(USBPWRCTL = 0x0908); +PROVIDE(USBPWRCTL_L = 0x0908); +PROVIDE(USBPWRCTL_H = 0x0909); +PROVIDE(USBPLLCTL = 0x0910); +PROVIDE(USBPLLCTL_L = 0x0910); +PROVIDE(USBPLLCTL_H = 0x0911); +PROVIDE(USBPLLDIVB = 0x0912); +PROVIDE(USBPLLDIVB_L = 0x0912); +PROVIDE(USBPLLDIVB_H = 0x0913); +PROVIDE(USBPLLIR = 0x0914); +PROVIDE(USBPLLIR_L = 0x0914); +PROVIDE(USBPLLIR_H = 0x0915); +PROVIDE(USBIEPCNF_0 = 0x0920); +PROVIDE(USBIEPCNT_0 = 0x0921); +PROVIDE(USBOEPCNF_0 = 0x0922); +PROVIDE(USBOEPCNT_0 = 0x0923); +PROVIDE(USBIEPIE = 0x092E); +PROVIDE(USBOEPIE = 0x092F); +PROVIDE(USBIEPIFG = 0x0930); +PROVIDE(USBOEPIFG = 0x0931); +PROVIDE(USBVECINT = 0x0932); +PROVIDE(USBVECINT_L = 0x0932); +PROVIDE(USBVECINT_H = 0x0933); +PROVIDE(USBMAINT = 0x0936); +PROVIDE(USBMAINT_L = 0x0936); +PROVIDE(USBMAINT_H = 0x0937); +PROVIDE(USBTSREG = 0x0938); +PROVIDE(USBTSREG_L = 0x0938); +PROVIDE(USBTSREG_H = 0x0939); +PROVIDE(USBFN = 0x093A); +PROVIDE(USBFN_L = 0x093A); +PROVIDE(USBFN_H = 0x093B); +PROVIDE(USBCTL = 0x093C); +PROVIDE(USBIE = 0x093D); +PROVIDE(USBIFG = 0x093E); +PROVIDE(USBFUNADR = 0x093F); +PROVIDE(USBIEPSIZXY_7 = 0x23FF); +PROVIDE(USBIEPBCTY_7 = 0x23FE); +PROVIDE(USBIEPBBAY_7 = 0x23FD); +PROVIDE(USBIEPBCTX_7 = 0x23FA); +PROVIDE(USBIEPBBAX_7 = 0x23F9); +PROVIDE(USBIEPCNF_7 = 0x23F8); +PROVIDE(USBIEPSIZXY_6 = 0x23F7); +PROVIDE(USBIEPBCTY_6 = 0x23F6); +PROVIDE(USBIEPBBAY_6 = 0x23F5); +PROVIDE(USBIEPBCTX_6 = 0x23F2); +PROVIDE(USBIEPBBAX_6 = 0x23F1); +PROVIDE(USBIEPCNF_6 = 0x23F0); +PROVIDE(USBIEPSIZXY_5 = 0x23EF); +PROVIDE(USBIEPBCTY_5 = 0x23EE); +PROVIDE(USBIEPBBAY_5 = 0x23ED); +PROVIDE(USBIEPBCTX_5 = 0x23EA); +PROVIDE(USBIEPBBAX_5 = 0x23E9); +PROVIDE(USBIEPCNF_5 = 0x23E8); +PROVIDE(USBIEPSIZXY_4 = 0x23E7); +PROVIDE(USBIEPBCTY_4 = 0x23E6); +PROVIDE(USBIEPBBAY_4 = 0x23E5); +PROVIDE(USBIEPBCTX_4 = 0x23E2); +PROVIDE(USBIEPBBAX_4 = 0x23E1); +PROVIDE(USBIEPCNF_4 = 0x23E0); +PROVIDE(USBIEPSIZXY_3 = 0x23DF); +PROVIDE(USBIEPBCTY_3 = 0x23DE); +PROVIDE(USBIEPBBAY_3 = 0x23DD); +PROVIDE(USBIEPBCTX_3 = 0x23DA); +PROVIDE(USBIEPBBAX_3 = 0x23D9); +PROVIDE(USBIEPCNF_3 = 0x23D8); +PROVIDE(USBIEPSIZXY_2 = 0x23D7); +PROVIDE(USBIEPBCTY_2 = 0x23D6); +PROVIDE(USBIEPBBAY_2 = 0x23D5); +PROVIDE(USBIEPBCTX_2 = 0x23D2); +PROVIDE(USBIEPBBAX_2 = 0x23D1); +PROVIDE(USBIEPCNF_2 = 0x23D0); +PROVIDE(USBIEPSIZXY_1 = 0x23CF); +PROVIDE(USBIEPBCTY_1 = 0x23CE); +PROVIDE(USBIEPBBAY_1 = 0x23CD); +PROVIDE(USBIEPBCTX_1 = 0x23CA); +PROVIDE(USBIEPBBAX_1 = 0x23C9); +PROVIDE(USBIEPCNF_1 = 0x23C8); +PROVIDE(USBOEPSIZXY_7 = 0x23BF); +PROVIDE(USBOEPBCTY_7 = 0x23BE); +PROVIDE(USBOEPBBAY_7 = 0x23BD); +PROVIDE(USBOEPBCTX_7 = 0x23BA); +PROVIDE(USBOEPBBAX_7 = 0x23B9); +PROVIDE(USBOEPCNF_7 = 0x23B8); +PROVIDE(USBOEPSIZXY_6 = 0x23B7); +PROVIDE(USBOEPBCTY_6 = 0x23B6); +PROVIDE(USBOEPBBAY_6 = 0x23B5); +PROVIDE(USBOEPBCTX_6 = 0x23B2); +PROVIDE(USBOEPBBAX_6 = 0x23B1); +PROVIDE(USBOEPCNF_6 = 0x23B0); +PROVIDE(USBOEPSIZXY_5 = 0x23AF); +PROVIDE(USBOEPBCTY_5 = 0x23AE); +PROVIDE(USBOEPBBAY_5 = 0x23AD); +PROVIDE(USBOEPBCTX_5 = 0x23AA); +PROVIDE(USBOEPBBAX_5 = 0x23A9); +PROVIDE(USBOEPCNF_5 = 0x23A8); +PROVIDE(USBOEPSIZXY_4 = 0x23A7); +PROVIDE(USBOEPBCTY_4 = 0x23A6); +PROVIDE(USBOEPBBAY_4 = 0x23A5); +PROVIDE(USBOEPBCTX_4 = 0x23A2); +PROVIDE(USBOEPBBAX_4 = 0x23A1); +PROVIDE(USBOEPCNF_4 = 0x23A0); +PROVIDE(USBOEPSIZXY_3 = 0x239F); +PROVIDE(USBOEPBCTY_3 = 0x239E); +PROVIDE(USBOEPBBAY_3 = 0x239D); +PROVIDE(USBOEPBCTX_3 = 0x239A); +PROVIDE(USBOEPBBAX_3 = 0x2399); +PROVIDE(USBOEPCNF_3 = 0x2398); +PROVIDE(USBOEPSIZXY_2 = 0x2397); +PROVIDE(USBOEPBCTY_2 = 0x2396); +PROVIDE(USBOEPBBAY_2 = 0x2395); +PROVIDE(USBOEPBCTX_2 = 0x2392); +PROVIDE(USBOEPBBAX_2 = 0x2391); +PROVIDE(USBOEPCNF_2 = 0x2390); +PROVIDE(USBOEPSIZXY_1 = 0x238F); +PROVIDE(USBOEPBCTY_1 = 0x238E); +PROVIDE(USBOEPBBAY_1 = 0x238D); +PROVIDE(USBOEPBCTX_1 = 0x238A); +PROVIDE(USBOEPBBAX_1 = 0x2389); +PROVIDE(USBOEPCNF_1 = 0x2388); +PROVIDE(USBSUBLK = 0x2380); +PROVIDE(USBIEP0BUF = 0x2378); +PROVIDE(USBOEP0BUF = 0x2370); +PROVIDE(USBTOPBUFF = 0x236F); +PROVIDE(USBSTABUFF = 0x1C00); +/************************************************************ +* UNIFIED CLOCK SYSTEM +************************************************************/ +PROVIDE(UCSCTL0 = 0x0160); +PROVIDE(UCSCTL0_L = 0x0160); +PROVIDE(UCSCTL0_H = 0x0161); +PROVIDE(UCSCTL1 = 0x0162); +PROVIDE(UCSCTL1_L = 0x0162); +PROVIDE(UCSCTL1_H = 0x0163); +PROVIDE(UCSCTL2 = 0x0164); +PROVIDE(UCSCTL2_L = 0x0164); +PROVIDE(UCSCTL2_H = 0x0165); +PROVIDE(UCSCTL3 = 0x0166); +PROVIDE(UCSCTL3_L = 0x0166); +PROVIDE(UCSCTL3_H = 0x0167); +PROVIDE(UCSCTL4 = 0x0168); +PROVIDE(UCSCTL4_L = 0x0168); +PROVIDE(UCSCTL4_H = 0x0169); +PROVIDE(UCSCTL5 = 0x016A); +PROVIDE(UCSCTL5_L = 0x016A); +PROVIDE(UCSCTL5_H = 0x016B); +PROVIDE(UCSCTL6 = 0x016C); +PROVIDE(UCSCTL6_L = 0x016C); +PROVIDE(UCSCTL6_H = 0x016D); +PROVIDE(UCSCTL7 = 0x016E); +PROVIDE(UCSCTL7_L = 0x016E); +PROVIDE(UCSCTL7_H = 0x016F); +PROVIDE(UCSCTL8 = 0x0170); +PROVIDE(UCSCTL8_L = 0x0170); +PROVIDE(UCSCTL8_H = 0x0171); +/************************************************************ +* USCI A0 +************************************************************/ +PROVIDE(UCA0CTLW0 = 0x05C0); +PROVIDE(UCA0CTLW0_L = 0x05C0); +PROVIDE(UCA0CTLW0_H = 0x05C1); +PROVIDE(UCA0BRW = 0x05C6); +PROVIDE(UCA0BRW_L = 0x05C6); +PROVIDE(UCA0BRW_H = 0x05C7); +PROVIDE(UCA0MCTL = 0x05C8); +PROVIDE(UCA0STAT = 0x05CA); +PROVIDE(UCA0RXBUF = 0x05CC); +PROVIDE(UCA0TXBUF = 0x05CE); +PROVIDE(UCA0ABCTL = 0x05D0); +PROVIDE(UCA0IRCTL = 0x05D2); +PROVIDE(UCA0IRCTL_L = 0x05D2); +PROVIDE(UCA0IRCTL_H = 0x05D3); +PROVIDE(UCA0ICTL = 0x05DC); +PROVIDE(UCA0ICTL_L = 0x05DC); +PROVIDE(UCA0ICTL_H = 0x05DD); +PROVIDE(UCA0IV = 0x05DE); +/************************************************************ +* USCI B0 +************************************************************/ +PROVIDE(UCB0CTLW0 = 0x05E0); +PROVIDE(UCB0CTLW0_L = 0x05E0); +PROVIDE(UCB0CTLW0_H = 0x05E1); +PROVIDE(UCB0BRW = 0x05E6); +PROVIDE(UCB0BRW_L = 0x05E6); +PROVIDE(UCB0BRW_H = 0x05E7); +PROVIDE(UCB0STAT = 0x05EA); +PROVIDE(UCB0RXBUF = 0x05EC); +PROVIDE(UCB0TXBUF = 0x05EE); +PROVIDE(UCB0I2COA = 0x05F0); +PROVIDE(UCB0I2COA_L = 0x05F0); +PROVIDE(UCB0I2COA_H = 0x05F1); +PROVIDE(UCB0I2CSA = 0x05F2); +PROVIDE(UCB0I2CSA_L = 0x05F2); +PROVIDE(UCB0I2CSA_H = 0x05F3); +PROVIDE(UCB0ICTL = 0x05FC); +PROVIDE(UCB0ICTL_L = 0x05FC); +PROVIDE(UCB0ICTL_H = 0x05FD); +PROVIDE(UCB0IV = 0x05FE); +/************************************************************ +* USCI A1 +************************************************************/ +PROVIDE(UCA1CTLW0 = 0x0600); +PROVIDE(UCA1CTLW0_L = 0x0600); +PROVIDE(UCA1CTLW0_H = 0x0601); +PROVIDE(UCA1BRW = 0x0606); +PROVIDE(UCA1BRW_L = 0x0606); +PROVIDE(UCA1BRW_H = 0x0607); +PROVIDE(UCA1MCTL = 0x0608); +PROVIDE(UCA1STAT = 0x060A); +PROVIDE(UCA1RXBUF = 0x060C); +PROVIDE(UCA1TXBUF = 0x060E); +PROVIDE(UCA1ABCTL = 0x0610); +PROVIDE(UCA1IRCTL = 0x0612); +PROVIDE(UCA1IRCTL_L = 0x0612); +PROVIDE(UCA1IRCTL_H = 0x0613); +PROVIDE(UCA1ICTL = 0x061C); +PROVIDE(UCA1ICTL_L = 0x061C); +PROVIDE(UCA1ICTL_H = 0x061D); +PROVIDE(UCA1IV = 0x061E); +/************************************************************ +* USCI B1 +************************************************************/ +PROVIDE(UCB1CTLW0 = 0x0620); +PROVIDE(UCB1CTLW0_L = 0x0620); +PROVIDE(UCB1CTLW0_H = 0x0621); +PROVIDE(UCB1BRW = 0x0626); +PROVIDE(UCB1BRW_L = 0x0626); +PROVIDE(UCB1BRW_H = 0x0627); +PROVIDE(UCB1STAT = 0x062A); +PROVIDE(UCB1RXBUF = 0x062C); +PROVIDE(UCB1TXBUF = 0x062E); +PROVIDE(UCB1I2COA = 0x0630); +PROVIDE(UCB1I2COA_L = 0x0630); +PROVIDE(UCB1I2COA_H = 0x0631); +PROVIDE(UCB1I2CSA = 0x0632); +PROVIDE(UCB1I2CSA_L = 0x0632); +PROVIDE(UCB1I2CSA_H = 0x0633); +PROVIDE(UCB1ICTL = 0x063C); +PROVIDE(UCB1ICTL_L = 0x063C); +PROVIDE(UCB1ICTL_H = 0x063D); +PROVIDE(UCB1IV = 0x063E); +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +PROVIDE(WDTCTL = 0x015C); +PROVIDE(WDTCTL_L = 0x015C); +PROVIDE(WDTCTL_H = 0x015D); +/************************************************************ +* TLV Descriptors +************************************************************/ +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ +/************************************************************ +* End of Modules +************************************************************/ diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c new file mode 100644 index 000000000..fe904b12b --- /dev/null +++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c @@ -0,0 +1,75 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "../board.h" + +#include "msp430.h" + +#define LED_PORT P1OUT +#define LED_PIN BIT0 +#define LED_STATE_ON 1 + +#define BUTTON_PORT P1IN +#define BUTTON_PIN BIT1 +#define BUTTON_STATE_ACTIVE 1 + + +static void SystemClock_Config(void) +{ + +} + +void board_init(void) +{ + SystemClock_Config(); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + +} + +uint32_t board_button_read(void) +{ + return 0; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c new file mode 100644 index 000000000..4c8c370ce --- /dev/null +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -0,0 +1,116 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 William D. Jones + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MSP430x5xx ) + +#include "device/dcd.h" + +/*------------------------------------------------------------------*/ +/* MACRO TYPEDEF CONSTANT ENUM + *------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------*/ +/* Controller API + *------------------------------------------------------------------*/ +void dcd_init (uint8_t rhport) +{ + (void) rhport; +} + +void dcd_int_enable (uint8_t rhport) +{ + (void) rhport; +} + +void dcd_int_disable (uint8_t rhport) +{ + (void) rhport; +} + +void dcd_set_address (uint8_t rhport, uint8_t dev_addr) +{ + (void) rhport; + (void) dev_addr; +} + +void dcd_set_config (uint8_t rhport, uint8_t config_num) +{ + (void) rhport; + (void) config_num; + // Nothing to do +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; +} + +/*------------------------------------------------------------------*/ +/* DCD Endpoint port + *------------------------------------------------------------------*/ + +bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) +{ + (void) rhport; + (void) desc_edpt; + + return false; +} + +bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + (void) rhport; + (void) ep_addr; + (void) buffer; + (void) total_bytes; + + return false; +} + +void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + (void) ep_addr; +} + +void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + (void) ep_addr; +} + +/*------------------------------------------------------------------*/ + +void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) +{ + +} + +#endif From d464c26ab28d04c9eecbd8b8015d6f544f440352 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 14 Sep 2019 21:06:57 -0400 Subject: [PATCH 02/71] msp430f5529: Remove -nostdlib and -nostartfiles, as the compiler provides them. --- hw/bsp/msp_exp430f5529lp/board.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index 27e94e6ca..5e4b72555 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -1,6 +1,5 @@ CFLAGS += \ -D__MSP430F5529__ \ - -nostdlib -nostartfiles \ -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx # All source paths should be relative to the top level. From 772b0c17bf59df89bfc011b6c97cb63612afa8b8 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 14 Sep 2019 21:16:10 -0400 Subject: [PATCH 03/71] rules.mk: Create an LDINC variable for linker script search path. --- examples/rules.mk | 1 + hw/bsp/msp_exp430f5529lp/board.mk | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/examples/rules.mk b/examples/rules.mk index f57b506ca..a56b3668b 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -28,6 +28,7 @@ ifeq ($(BOARD), msp_exp430f5529lp) else LDFLAGS += $(CFLAGS) -fshort-enums -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nosys.specs -specs=nano.specs endif +LDFLAGS += $(addprefix -L,$(LDINC)) ASFLAGS += $(CFLAGS) # Assembly files can be name with upper case .S, convert it to .s diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index 5e4b72555..741b3e00e 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -4,7 +4,7 @@ CFLAGS += \ # All source paths should be relative to the top level. LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld -LDFLAGS += -L$(TOP)/hw/bsp/$(BOARD) +LDINC += $(TOP)/hw/bsp/$(BOARD) INC += $(TOP)/hw/bsp/$(BOARD) @@ -12,9 +12,9 @@ INC += $(TOP)/hw/bsp/$(BOARD) VENDOR = ti CHIP_FAMILY = msp430x5xx -# Path to STM32 Cube Programmer CLI, should be added into system path +# Path to mspdebug, should be added into system path MSPDEBUG = mspdebug -# flash target using on-board stlink +# flash target using mspdebug. flash: $(BUILD)/$(BOARD)-firmware.elf $(MSPDEBUG) tilib "prog $<" From 49f2507b3824260bcb5df3a8c740dd935ac21149 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Thu, 19 Sep 2019 01:21:29 -0400 Subject: [PATCH 04/71] msp_exp430f5529lp: Implement enough functionality for board_test. --- hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c | 65 +++++++++++++++++++- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c index fe904b12b..5fa69465d 100644 --- a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c +++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c @@ -36,15 +36,66 @@ #define BUTTON_PIN BIT1 #define BUTTON_STATE_ACTIVE 1 - static void SystemClock_Config(void) { + WDTCTL = WDTPW + WDTHOLD; // Disable watchdog. + // Increase VCore to level 2- required for 16 MHz operation on this MCU. + PMMCTL0 = PMMPW + PMMCOREV_2; + + UCSCTL3 = SELREF__XT2CLK; // FLL is fed by XT2. + + // XT1 used for ACLK (default- not used in this demo) + P5SEL |= BIT4; // Required to enable XT1 + // Loop until XT1 fault flag is cleared. + do + { + UCSCTL7 &= ~XT1LFOFFG; + }while(UCSCTL7 & XT1LFOFFG); + + // XT2 is 4 MHz an external oscillator, use PLL to boost to 16 MHz. + P5SEL |= BIT2; // Required to enable XT2. + // Loop until XT2 fault flag is cleared + do + { + UCSCTL7 &= ~XT2OFFG; + }while(UCSCTL7 & XT2OFFG); + + // Kickstart the DCO into the correct frequency range, otherwise a + // fault will occur. + // FIXME: DCORSEL_6 should work according to datasheet params, but generates + // a fault. I am not sure why it faults. + UCSCTL1 = DCORSEL_7; + UCSCTL2 = FLLD_2 + 3; // DCO freq = D * (N + 1) * (FLLREFCLK / n) + // DCOCLKDIV freq = (N + 1) * (FLLREFCLK / n) + // N = 3, D = 2, thus DCO freq = 32 MHz. + + // MCLK configured for 16 MHz using XT2. + // SMCLK configured for 8 MHz using XT2. + UCSCTL4 |= SELM__DCOCLKDIV + SELS__DCOCLKDIV; + UCSCTL5 |= DIVM__16 + DIVS__2; + + // Now wait till everything's stabilized. + do + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); + SFRIFG1 &= ~OFIFG; + }while(SFRIFG1 & OFIFG); + + // Configure Timer A to use SMCLK as a source. Count 1000 ticks at 1 MHz. + TA0CCTL0 |= CCIE; + TA0CCR0 = 999; // 1000 ticks. + TA0CTL |= TASSEL_2 + ID_3 + MC__UP; // Use SMCLK, divide by 8, start timer. } void board_init(void) { SystemClock_Config(); + __bis_SR_register(GIE); // Enable interrupts. + + P1DIR |= LED_PIN; // LED output. + P1REN |= BUTTON_PIN; // Internal resistor enable. + P1OUT |= BUTTON_PIN; // Pullup. } //--------------------------------------------------------------------+ @@ -53,12 +104,19 @@ void board_init(void) void board_led_write(bool state) { - + if(state) + { + LED_PORT |= LED_PIN; + } + else + { + LED_PORT &= ~LED_PIN; + } } uint32_t board_button_read(void) { - return 0; + return (P1IN & BIT1); } #if CFG_TUSB_OS == OPT_OS_NONE @@ -66,6 +124,7 @@ volatile uint32_t system_ticks = 0; void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void) { system_ticks++; + // TAxCCR0 CCIFG resets itself as soon as interrupt is invoked. } uint32_t board_millis(void) From 907bc3df9ba70c9a82ad2f98031879f17e2ad2b5 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Mon, 23 Sep 2019 17:48:18 -0400 Subject: [PATCH 05/71] msp430f5529: Ensure cdc_msc demo compiles. --- hw/bsp/msp_exp430f5529lp/board.mk | 3 ++- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 1 + src/tusb_option.h | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index 741b3e00e..b47e764bd 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -1,6 +1,7 @@ CFLAGS += \ -D__MSP430F5529__ \ - -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx + -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx \ + -DCFG_EXAMPLE_MSC_READONLY # All source paths should be relative to the top level. LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 4c8c370ce..b2df9e3b6 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -29,6 +29,7 @@ #if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MSP430x5xx ) +#include "msp430.h" #include "device/dcd.h" /*------------------------------------------------------------------*/ diff --git a/src/tusb_option.h b/src/tusb_option.h index eccb4245c..5de599951 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -60,6 +60,8 @@ #define OPT_MCU_STM32F7 305 ///< ST STM32F7 #define OPT_MCU_STM32H7 306 ///< ST STM32H7 +#define OPT_MCU_MSP430x5xx 400 ///< TI MSP430x5xx + /** @} */ From a6a79df9fb6864ad2d30dde85fd04c836f28f5d5 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Mon, 23 Sep 2019 18:53:31 -0400 Subject: [PATCH 06/71] msp430f5529: Enable clocks/PLL for msp_exp430f5529lp and enable USB module in dcd_msp430x5xx; device does not enumerate. --- hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c | 33 +++++++++++++++++++- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 5 +++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c index 5fa69465d..29f88ccf5 100644 --- a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c +++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c @@ -36,6 +36,8 @@ #define BUTTON_PIN BIT1 #define BUTTON_STATE_ACTIVE 1 +uint32_t cnt = 0; + static void SystemClock_Config(void) { WDTCTL = WDTPW + WDTHOLD; // Disable watchdog. @@ -86,16 +88,45 @@ static void SystemClock_Config(void) TA0CCTL0 |= CCIE; TA0CCR0 = 999; // 1000 ticks. TA0CTL |= TASSEL_2 + ID_3 + MC__UP; // Use SMCLK, divide by 8, start timer. + + // Initialize USB power and PLL. + USBKEYPID = USBKEY; + + // VUSB enabled automatically. + // Wait two milliseconds to stabilize, per manual recommendation. + uint32_t ms_elapsed = board_millis(); + do + { + while((board_millis() - ms_elapsed) < 2); + }while(!(USBPWRCTL & USBBGVBV)); + + // USB uses XT2 (4 MHz) directly. Enable the PLL. + USBPLLDIVB |= USBPLL_SETCLK_4_0; + USBPLLCTL |= (UPFDEN | UPLLEN); + + // Wait until PLL locks. Check every 2ms, per manual. + ms_elapsed = board_millis(); + do + { + USBPLLIR &= ~USBOOLIFG; + while((board_millis() - ms_elapsed) < 2); + }while(USBPLLIR & USBOOLIFG); + + USBKEYPID = 0; } void board_init(void) { - SystemClock_Config(); __bis_SR_register(GIE); // Enable interrupts. + SystemClock_Config(); P1DIR |= LED_PIN; // LED output. P1REN |= BUTTON_PIN; // Internal resistor enable. P1OUT |= BUTTON_PIN; // Pullup. + + USBKEYPID = USBKEY; + USBPHYCTL |= PUSEL; // Convert USB D+/D- pins to USB functionality. + USBKEYPID = 0; } //--------------------------------------------------------------------+ diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index b2df9e3b6..e9ca76853 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -43,6 +43,11 @@ void dcd_init (uint8_t rhport) { (void) rhport; + + // Enable the module! + USBKEYPID = USBKEY; + USBCNF |= (PUR_EN | USB_EN); + USBKEYPID = 0; } void dcd_int_enable (uint8_t rhport) From 950614a841a69f09ffd8b97205183e1c85b09443 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Mon, 23 Sep 2019 22:58:49 -0400 Subject: [PATCH 07/71] msp430f5529: Implement dcd_int_enable/disable. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 31 +++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index e9ca76853..e01c0243f 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -35,6 +35,11 @@ /*------------------------------------------------------------------*/ /* MACRO TYPEDEF CONSTANT ENUM *------------------------------------------------------------------*/ +// usbpllir_mirror and usbmaintl_mirror can be added later if needed. +static volatile uint16_t usbiepie_mirror = 0; +static volatile uint16_t usboepie_mirror = 0; +static volatile uint16_t usbie_mirror = 0; +static volatile uint16_t usbpwrctl_mirror = 0; /*------------------------------------------------------------------*/ @@ -50,14 +55,40 @@ void dcd_init (uint8_t rhport) USBKEYPID = 0; } +// There is no "USB peripheral interrupt disable" bit on MSP430, so we have +// to save the relevant registers individually. +// WARNING: Unlike the ARM/NVIC routines, these functions are _not_ idempotent +// if you modified the registers saved in between calls so they don't match +// the mirrors; mirrors will be updated to reflect most recent register +// contents. void dcd_int_enable (uint8_t rhport) { (void) rhport; + + __bic_SR_register(GIE); // Unlikely to be called in ISR, but let's be safe. + // Also, this cleanly disables all USB interrupts + // atomically from application's POV. + USBOEPIE = usboepie_mirror; + USBIEPIE = usbiepie_mirror; + USBIE = usbie_mirror; + USBPWRCTL |= usbpwrctl_mirror; + __bis_SR_register(GIE); } void dcd_int_disable (uint8_t rhport) { (void) rhport; + + __bic_SR_register(GIE); + usboepie_mirror = USBOEPIE; + usbiepie_mirror = USBIEPIE; + usbie_mirror = USBIE; + usbpwrctl_mirror = (USBPWRCTL & (VUOVLIE | VBONIE | VBOFFIE)); + USBOEPIE = 0; + USBIEPIE = 0; + USBIE = 0; + USBPWRCTL &= ~(VUOVLIE | VBONIE | VBOFFIE); + __bis_SR_register(GIE); } void dcd_set_address (uint8_t rhport, uint8_t dev_addr) From 742f1f23c56c6c7ed9b65fac4269aa37e6881aa1 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Mon, 23 Sep 2019 23:11:47 -0400 Subject: [PATCH 08/71] examples: Allow user to override EP0 size. --- examples/device/cdc_msc/src/tusb_config.h | 3 ++- examples/device/cdc_msc_hid_freertos/src/tusb_config.h | 4 +++- examples/device/hid_composite/src/tusb_config.h | 4 +++- examples/device/hid_generic_inout/src/tusb_config.h | 4 +++- examples/device/midi_test/src/tusb_config.h | 4 +++- examples/device/msc_dual_lun/src/tusb_config.h | 4 +++- examples/device/webusb_serial/src/tusb_config.h | 4 +++- 7 files changed, 20 insertions(+), 7 deletions(-) diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h index ff7fafd8f..e307870ed 100644 --- a/examples/device/cdc_msc/src/tusb_config.h +++ b/examples/device/cdc_msc/src/tusb_config.h @@ -68,8 +68,9 @@ //-------------------------------------------------------------------- // DEVICE CONFIGURATION //-------------------------------------------------------------------- - +#ifndef CFG_TUD_ENDOINT0_SIZE #define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 1 diff --git a/examples/device/cdc_msc_hid_freertos/src/tusb_config.h b/examples/device/cdc_msc_hid_freertos/src/tusb_config.h index bb31eac06..7869e24cc 100644 --- a/examples/device/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_hid_freertos/src/tusb_config.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -69,7 +69,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- +#ifndef CFG_TUD_ENDOINT0_SIZE #define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 1 diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h index 57fcbd595..13ecfa415 100644 --- a/examples/device/hid_composite/src/tusb_config.h +++ b/examples/device/hid_composite/src/tusb_config.h @@ -69,7 +69,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDOINT0_SIZE +#define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_HID 1 diff --git a/examples/device/hid_generic_inout/src/tusb_config.h b/examples/device/hid_generic_inout/src/tusb_config.h index c55529fcb..c82588c2f 100644 --- a/examples/device/hid_generic_inout/src/tusb_config.h +++ b/examples/device/hid_generic_inout/src/tusb_config.h @@ -69,7 +69,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDOINT0_SIZE +#define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 0 diff --git a/examples/device/midi_test/src/tusb_config.h b/examples/device/midi_test/src/tusb_config.h index d588b4df9..4a84812c5 100644 --- a/examples/device/midi_test/src/tusb_config.h +++ b/examples/device/midi_test/src/tusb_config.h @@ -69,7 +69,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDOINT0_SIZE +#define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 0 diff --git a/examples/device/msc_dual_lun/src/tusb_config.h b/examples/device/msc_dual_lun/src/tusb_config.h index 2e40b9e86..073e2379f 100644 --- a/examples/device/msc_dual_lun/src/tusb_config.h +++ b/examples/device/msc_dual_lun/src/tusb_config.h @@ -69,7 +69,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDOINT0_SIZE +#define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 0 diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h index ffedb997d..b2f09cac0 100644 --- a/examples/device/webusb_serial/src/tusb_config.h +++ b/examples/device/webusb_serial/src/tusb_config.h @@ -69,7 +69,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDOINT0_SIZE +#define CFG_TUD_ENDOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 1 From d2e4af5a7b42ab54510bc8507ca28aed3604d9d1 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 24 Sep 2019 02:41:11 -0400 Subject: [PATCH 09/71] msp430f5529: Change EP0 size to 8, implement interrupt logic up to bus reset detection. --- hw/bsp/msp_exp430f5529lp/board.mk | 3 +- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 81 +++++++++++++++++++-- 2 files changed, 75 insertions(+), 9 deletions(-) diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index b47e764bd..1ae7330c9 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -1,7 +1,8 @@ CFLAGS += \ -D__MSP430F5529__ \ -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx \ - -DCFG_EXAMPLE_MSC_READONLY + -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_TUD_ENDOINT0_SIZE=8 # All source paths should be relative to the top level. LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index e01c0243f..9ff63f839 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -38,8 +38,16 @@ // usbpllir_mirror and usbmaintl_mirror can be added later if needed. static volatile uint16_t usbiepie_mirror = 0; static volatile uint16_t usboepie_mirror = 0; -static volatile uint16_t usbie_mirror = 0; +static volatile uint8_t usbie_mirror = 0; static volatile uint16_t usbpwrctl_mirror = 0; +static bool in_isr = false; + +uint8_t _setup_packet[8]; + +static void bus_reset(void) +{ + +} /*------------------------------------------------------------------*/ @@ -49,9 +57,27 @@ void dcd_init (uint8_t rhport) { (void) rhport; - // Enable the module! USBKEYPID = USBKEY; - USBCNF |= (PUR_EN | USB_EN); + + // Enable the module (required to write config regs)! + USBCNF |= USB_EN; + + // Reset used interrupts + USBOEPIE = 0; + USBIEPIE = 0; + USBIE = 0; + USBOEPIFG = 0; + USBIEPIFG = 0; + USBIFG = 0; + USBPWRCTL &= ~(VUOVLIE | VBONIE | VBOFFIE | VUOVLIFG | VBONIFG | VBOFFIFG); + USBVECINT = 0; + + // Enable reset and wait for it before continuing. + USBIE |= RSTRIE; + + // Enable pullup. + USBCNF |= PUR_EN; + USBKEYPID = 0; } @@ -68,10 +94,18 @@ void dcd_int_enable (uint8_t rhport) __bic_SR_register(GIE); // Unlikely to be called in ISR, but let's be safe. // Also, this cleanly disables all USB interrupts // atomically from application's POV. - USBOEPIE = usboepie_mirror; - USBIEPIE = usbiepie_mirror; - USBIE = usbie_mirror; - USBPWRCTL |= usbpwrctl_mirror; + + // This guard is required because tinyusb can enable interrupts without + // having disabled them first. + if(in_isr) + { + USBOEPIE = usboepie_mirror; + USBIEPIE = usbiepie_mirror; + USBIE = usbie_mirror; + USBPWRCTL |= usbpwrctl_mirror; + } + + in_isr = false; __bis_SR_register(GIE); } @@ -88,6 +122,7 @@ void dcd_int_disable (uint8_t rhport) USBIEPIE = 0; USBIE = 0; USBPWRCTL &= ~(VUOVLIE | VBONIE | VBOFFIE); + in_isr = true; __bis_SR_register(GIE); } @@ -145,9 +180,39 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------*/ -void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) +static void handle_setup_packet(void) { } +void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) +{ + // Setup is special- reading USBVECINT to handle setup packets is done to + // stop NAKs on EP0. + uint8_t setup_status = USBIFG & SETUPIFG; + + if(setup_status) + { + handle_setup_packet(); + } + + uint16_t curr_vector = USBVECINT; + + switch(curr_vector) + { + case USBVECINT_RSTR: + bus_reset(); + dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); + break; + + // Clear the NAK on EP 0 after a SETUP packet is received. + case USBVECINT_SETUP_PACKET_RECEIVED: + break; + + default: + break; + } + +} + #endif From 550e8215f3ee60c13548e623925ca870023b20e4 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 24 Sep 2019 03:43:51 -0400 Subject: [PATCH 10/71] dcd_msp430x5xx: Setup packets are now received successfully (with delay). --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 41 ++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 9ff63f839..4b35cd984 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -35,6 +35,8 @@ /*------------------------------------------------------------------*/ /* MACRO TYPEDEF CONSTANT ENUM *------------------------------------------------------------------*/ +#define USB_BUF_PTR(_x) (uint8_t *) ((uint16_t) _x) + // usbpllir_mirror and usbmaintl_mirror can be added later if needed. static volatile uint16_t usbiepie_mirror = 0; static volatile uint16_t usboepie_mirror = 0; @@ -46,7 +48,19 @@ uint8_t _setup_packet[8]; static void bus_reset(void) { + // Enable the control EP 0. Also enable Indication Enable- a guard flag + // separate from the Interrupt Enable mask. + USBOEPCNF_0 |= (UBME | USBIIE); + USBIEPCNF_0 |= (UBME | USBIIE); + // Enable interrupts for this endpoint. + USBOEPIE |= BIT0; + USBIEPIE |= BIT0; + + // Clear NAK so packets can be received. + // Dedicated buffers in hardware for SETUP and EP0, no setup needed. + USBOEPCNT_0 &= ~NAK; + USBIEPCNT_0 &= ~NAK; } @@ -180,11 +194,28 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------*/ -static void handle_setup_packet(void) +static void receive_packet(void) { } +static void transmit_packet(void) +{ + +} + +static void handle_setup_packet(void) +{ + volatile uint8_t * setup_buf = &USBSUBLK; + + for(int i = 0; i < 8; i++) + { + _setup_packet[i] = setup_buf[i]; + } + + dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true); +} + void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) { // Setup is special- reading USBVECINT to handle setup packets is done to @@ -209,6 +240,14 @@ void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) case USBVECINT_SETUP_PACKET_RECEIVED: break; + case USBVECINT_INPUT_ENDPOINT0: + transmit_packet(); + break; + + case USBVECINT_OUTPUT_ENDPOINT0: + receive_packet(); + break; + default: break; } From 01b4115b0b26a9fb5c706daf320c85556d16f920 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 24 Sep 2019 04:06:34 -0400 Subject: [PATCH 11/71] dcd_msp430x5xx: Fix Setup packet delay by actually enabling corresponding interrupt. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 4b35cd984..fe78218df 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -61,6 +61,9 @@ static void bus_reset(void) // Dedicated buffers in hardware for SETUP and EP0, no setup needed. USBOEPCNT_0 &= ~NAK; USBIEPCNT_0 &= ~NAK; + + // Now safe to respond to SETUP packets. + USBIE |= SETUPIE; } From c4483d244b04a6679d85376e3e686c23b9ee82af Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Fri, 27 Sep 2019 12:41:46 -0400 Subject: [PATCH 12/71] Fix typo of CFG_TUD_ENDOINT0_SIZE. --- examples/device/board_test/src/tusb_config.h | 2 +- examples/device/cdc_msc/src/tusb_config.h | 4 ++-- examples/device/cdc_msc/src/usb_descriptors.c | 2 +- examples/device/cdc_msc_hid_freertos/src/tusb_config.h | 4 ++-- examples/device/cdc_msc_hid_freertos/src/usb_descriptors.c | 2 +- examples/device/hid_composite/src/tusb_config.h | 4 ++-- examples/device/hid_composite/src/usb_descriptors.c | 2 +- examples/device/hid_generic_inout/src/tusb_config.h | 4 ++-- examples/device/hid_generic_inout/src/usb_descriptors.c | 2 +- examples/device/midi_test/src/tusb_config.h | 4 ++-- examples/device/midi_test/src/usb_descriptors.c | 2 +- examples/device/msc_dual_lun/src/tusb_config.h | 4 ++-- examples/device/msc_dual_lun/src/usb_descriptors.c | 2 +- examples/device/webusb_serial/src/tusb_config.h | 4 ++-- examples/device/webusb_serial/src/usb_descriptors.c | 2 +- hw/bsp/msp_exp430f5529lp/board.mk | 2 +- src/device/usbd_control.c | 2 +- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 4 ++-- src/portable/nxp/lpc18_43/dcd_lpc18_43.c | 2 +- 19 files changed, 27 insertions(+), 27 deletions(-) diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 5c3cac83a..2f2a4deeb 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -64,7 +64,7 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#define CFG_TUD_ENDOINT0_SIZE 64 +#define CFG_TUD_ENDPOINT0_SIZE 64 //------------- CLASS -------------// #define CFG_TUD_CDC 0 diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h index e307870ed..4455f665e 100644 --- a/examples/device/cdc_msc/src/tusb_config.h +++ b/examples/device/cdc_msc/src/tusb_config.h @@ -68,8 +68,8 @@ //-------------------------------------------------------------------- // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index ac8214e37..11d07e9ba 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -50,7 +50,7 @@ tusb_desc_device_t const desc_device = .bDeviceSubClass = MISC_SUBCLASS_COMMON, .bDeviceProtocol = MISC_PROTOCOL_IAD, - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/examples/device/cdc_msc_hid_freertos/src/tusb_config.h b/examples/device/cdc_msc_hid_freertos/src/tusb_config.h index 7869e24cc..f84874ab1 100644 --- a/examples/device/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_hid_freertos/src/tusb_config.h @@ -69,8 +69,8 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/cdc_msc_hid_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_hid_freertos/src/usb_descriptors.c index 5d93cc2f6..d60c9a585 100644 --- a/examples/device/cdc_msc_hid_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_hid_freertos/src/usb_descriptors.c @@ -57,7 +57,7 @@ tusb_desc_device_t const desc_device = .bDeviceProtocol = 0x00, #endif - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h index 13ecfa415..8d29f10be 100644 --- a/examples/device/hid_composite/src/tusb_config.h +++ b/examples/device/hid_composite/src/tusb_config.h @@ -69,8 +69,8 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c index 678b7528b..01f2cb59b 100644 --- a/examples/device/hid_composite/src/usb_descriptors.c +++ b/examples/device/hid_composite/src/usb_descriptors.c @@ -47,7 +47,7 @@ tusb_desc_device_t const desc_device = .bDeviceClass = 0x00, .bDeviceSubClass = 0x00, .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/examples/device/hid_generic_inout/src/tusb_config.h b/examples/device/hid_generic_inout/src/tusb_config.h index c82588c2f..a7ce7acf8 100644 --- a/examples/device/hid_generic_inout/src/tusb_config.h +++ b/examples/device/hid_generic_inout/src/tusb_config.h @@ -69,8 +69,8 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c index d0fc6b1bc..07989c5fd 100644 --- a/examples/device/hid_generic_inout/src/usb_descriptors.c +++ b/examples/device/hid_generic_inout/src/usb_descriptors.c @@ -46,7 +46,7 @@ tusb_desc_device_t const desc_device = .bDeviceClass = 0x00, .bDeviceSubClass = 0x00, .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/examples/device/midi_test/src/tusb_config.h b/examples/device/midi_test/src/tusb_config.h index 4a84812c5..fcd6b97c2 100644 --- a/examples/device/midi_test/src/tusb_config.h +++ b/examples/device/midi_test/src/tusb_config.h @@ -69,8 +69,8 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 7cebc6a15..2305c9f68 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -46,7 +46,7 @@ tusb_desc_device_t const desc_device = .bDeviceClass = 0x00, .bDeviceSubClass = 0x00, .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/examples/device/msc_dual_lun/src/tusb_config.h b/examples/device/msc_dual_lun/src/tusb_config.h index 073e2379f..b45e9c4dc 100644 --- a/examples/device/msc_dual_lun/src/tusb_config.h +++ b/examples/device/msc_dual_lun/src/tusb_config.h @@ -69,8 +69,8 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index cab37cf1f..e0a5904a4 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -46,7 +46,7 @@ tusb_desc_device_t const desc_device = .bDeviceClass = 0x00, .bDeviceSubClass = 0x00, .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h index b2f09cac0..8a73e8353 100644 --- a/examples/device/webusb_serial/src/tusb_config.h +++ b/examples/device/webusb_serial/src/tusb_config.h @@ -69,8 +69,8 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- -#ifndef CFG_TUD_ENDOINT0_SIZE -#define CFG_TUD_ENDOINT0_SIZE 64 +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 #endif //------------- CLASS -------------// diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index a1d5cd9b9..740defe4e 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -50,7 +50,7 @@ tusb_desc_device_t const desc_device = .bDeviceClass = TUSB_CLASS_MISC, .bDeviceSubClass = MISC_SUBCLASS_COMMON, .bDeviceProtocol = MISC_PROTOCOL_IAD, - .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, .idVendor = 0xCafe, .idProduct = USB_PID, diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index 1ae7330c9..2e6e77f18 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -2,7 +2,7 @@ CFLAGS += \ -D__MSP430F5529__ \ -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx \ -DCFG_EXAMPLE_MSC_READONLY \ - -DCFG_TUD_ENDOINT0_SIZE=8 + -DCFG_TUD_ENDPOINT0_SIZE=8 # All source paths should be relative to the top level. LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 4ec432185..eed933f68 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -124,7 +124,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result _control_state.total_transferred += xferred_bytes; _control_state.buffer += xferred_bytes; - if ( _control_state.total_len == _control_state.total_transferred || xferred_bytes < CFG_TUD_ENDOINT0_SIZE ) + if ( _control_state.total_len == _control_state.total_transferred || xferred_bytes < CFG_TUD_ENDPOINT0_SIZE ) { // DATA stage is complete bool is_ok = true; diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 2b49f52e9..97809e758 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -172,8 +172,8 @@ void dcd_init(uint8_t rhport) //------------- user manual 11.13 usb device controller initialization -------------// // step 6 : set up control endpoint - set_ep_size(0, CFG_TUD_ENDOINT0_SIZE); - set_ep_size(1, CFG_TUD_ENDOINT0_SIZE); + set_ep_size(0, CFG_TUD_ENDPOINT0_SIZE); + set_ep_size(1, CFG_TUD_ENDPOINT0_SIZE); bus_reset(); diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c index 519e0dcc6..3619a7c2b 100644 --- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c +++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c @@ -115,7 +115,7 @@ static void bus_reset(uint8_t rhport) //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------// p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1; - p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE; + p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE; p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID; p_dcd->qhd[0].int_on_setup = 1; // OUT only From 3ac43076da7acf8e8e83086bf895e0b2c5f8105e Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Fri, 27 Sep 2019 21:20:33 -0400 Subject: [PATCH 13/71] dcd_msp430x5xx: Implement EP0 IN xfers, clean up. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 105 +++++++++++++++++--- 1 file changed, 91 insertions(+), 14 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index fe78218df..c52cf5505 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -35,8 +35,6 @@ /*------------------------------------------------------------------*/ /* MACRO TYPEDEF CONSTANT ENUM *------------------------------------------------------------------*/ -#define USB_BUF_PTR(_x) (uint8_t *) ((uint16_t) _x) - // usbpllir_mirror and usbmaintl_mirror can be added later if needed. static volatile uint16_t usbiepie_mirror = 0; static volatile uint16_t usboepie_mirror = 0; @@ -46,8 +44,26 @@ static bool in_isr = false; uint8_t _setup_packet[8]; +typedef struct { + uint8_t * buffer; + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; +} xfer_ctl_t; + +xfer_ctl_t xfer_status[8][2]; +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] + + static void bus_reset(void) { + // Hardcoded into the USB core. + xfer_status[0][TUSB_DIR_OUT].max_size = 8; + xfer_status[0][TUSB_DIR_IN].max_size = 8; + + USBKEYPID = USBKEY; + // Enable the control EP 0. Also enable Indication Enable- a guard flag // separate from the Interrupt Enable mask. USBOEPCNF_0 |= (UBME | USBIIE); @@ -57,13 +73,17 @@ static void bus_reset(void) USBOEPIE |= BIT0; USBIEPIE |= BIT0; - // Clear NAK so packets can be received. - // Dedicated buffers in hardware for SETUP and EP0, no setup needed. - USBOEPCNT_0 &= ~NAK; - USBIEPCNT_0 &= ~NAK; + // Set NAK until a setup packet is received. + USBOEPCNT_0 |= NAK; + USBIEPCNT_0 |= NAK; + USBCTL |= FEN; // Enable responding to packets. + + // Dedicated buffers in hardware for SETUP and EP0, no setup needed. // Now safe to respond to SETUP packets. USBIE |= SETUPIE; + + USBKEYPID = 0; } @@ -87,6 +107,11 @@ void dcd_init (uint8_t rhport) USBIEPIFG = 0; USBIFG = 0; USBPWRCTL &= ~(VUOVLIE | VBONIE | VBOFFIE | VUOVLIFG | VBONIFG | VBOFFIFG); + usboepie_mirror = 0; + usbiepie_mirror = 0; + usbie_mirror = 0; + usbpwrctl_mirror = 0; + USBVECINT = 0; // Enable reset and wait for it before continuing. @@ -173,14 +198,40 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return false; } +static volatile uint8_t iepcnt = 0xFF; + bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { (void) rhport; - (void) ep_addr; - (void) buffer; - (void) total_bytes; - return false; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + if(epnum == 0) + { + if(dir == TUSB_DIR_OUT) + { + // Interrupt will notify us when data was received. + USBCTL &= ~DIR; + USBOEPCNT_0 &= ~NAK; + } + else + { + // Kickstart the IN packet handler by queuing initial data and calling + // the ISR to transmit the first packet. + // Interrupt only fires on completed xfer. + USBCTL |= DIR; + USBIEPIFG |= BIT0; + } + } + + return true; } void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) @@ -197,14 +248,39 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------*/ -static void receive_packet(void) +static void receive_packet(uint8_t ep_num) { + (void) ep_num; } -static void transmit_packet(void) +static void transmit_packet(uint8_t ep_num) { + xfer_ctl_t * xfer = XFER_CTL_BASE(ep_num, TUSB_DIR_IN); + if(ep_num == 0) + { + if(xfer->total_len == xfer->queued_len) + { + dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); + return; + } + + uint8_t * base = (xfer->buffer + xfer->queued_len); + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining; + + xfer->queued_len += xfer_size; + + volatile uint8_t * ep0in_buf = &USBIEP0BUF; + for(int i = 0; i < xfer_size; i++) + { + ep0in_buf[i] = base[i]; + } + + USBIEPCNT_0 = (USBIEPCNT_0 & 0xF0) + xfer_size; + USBIEPCNT_0 &= ~NAK; + } } static void handle_setup_packet(void) @@ -244,14 +320,15 @@ void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) break; case USBVECINT_INPUT_ENDPOINT0: - transmit_packet(); + transmit_packet(0); break; case USBVECINT_OUTPUT_ENDPOINT0: - receive_packet(); + receive_packet(0); break; default: + while(true); break; } From 030560792d1d2d6a2d4febf1c54f9735cddc7aca Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Fri, 27 Sep 2019 21:59:45 -0400 Subject: [PATCH 14/71] dcd_msp430x5xx: Implement dcd_set_address. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index c52cf5505..66b7ab293 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -50,6 +50,7 @@ typedef struct { uint16_t queued_len; uint16_t max_size; bool short_packet; + bool zlp_sent; } xfer_ctl_t; xfer_ctl_t xfer_status[8][2]; @@ -171,7 +172,11 @@ void dcd_int_disable (uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { (void) rhport; - (void) dev_addr; + + USBFUNADR = dev_addr; + + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } void dcd_set_config (uint8_t rhport, uint8_t config_num) @@ -212,6 +217,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t xfer->total_len = total_bytes; xfer->queued_len = 0; xfer->short_packet = false; + xfer->zlp_sent = false; if(epnum == 0) { @@ -260,7 +266,8 @@ static void transmit_packet(uint8_t ep_num) if(ep_num == 0) { - if(xfer->total_len == xfer->queued_len) + bool zlp = (xfer->total_len == 0); + if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->zlp_sent) { dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); return; @@ -271,6 +278,10 @@ static void transmit_packet(uint8_t ep_num) uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining; xfer->queued_len += xfer_size; + if(xfer->total_len == 0) + { + xfer->zlp_sent = true; + } volatile uint8_t * ep0in_buf = &USBIEP0BUF; for(int i = 0; i < xfer_size; i++) From 63c94ff684372e804011ef9f2b283f2340bb67fd Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 28 Sep 2019 01:51:05 -0400 Subject: [PATCH 15/71] dcd_msp430x5xx: Improve EP0 IN handling (reuse short_packet field). --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 66b7ab293..62aaee3cb 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -50,7 +50,6 @@ typedef struct { uint16_t queued_len; uint16_t max_size; bool short_packet; - bool zlp_sent; } xfer_ctl_t; xfer_ctl_t xfer_status[8][2]; @@ -203,8 +202,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return false; } -static volatile uint8_t iepcnt = 0xFF; - bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { (void) rhport; @@ -217,7 +214,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t xfer->total_len = total_bytes; xfer->queued_len = 0; xfer->short_packet = false; - xfer->zlp_sent = false; if(epnum == 0) { @@ -266,21 +262,27 @@ static void transmit_packet(uint8_t ep_num) if(ep_num == 0) { - bool zlp = (xfer->total_len == 0); - if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->zlp_sent) + // First, determine whether we should even send a packet or finish + // up the xfer. + bool zlp = (xfer->total_len == 0); // By necessity, xfer->total_len will + // equal xfer->queued_len for ZLPs. + // Of course a ZLP is a short packet. + if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->short_packet) { dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); return; } + // Then actually commit to transmit a packet. uint8_t * base = (xfer->buffer + xfer->queued_len); uint16_t remaining = xfer->total_len - xfer->queued_len; uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining; xfer->queued_len += xfer_size; - if(xfer->total_len == 0) + if(xfer_size < xfer->max_size) { - xfer->zlp_sent = true; + // Next "xfer complete interrupt", the transfer will end. + xfer->short_packet = true; } volatile uint8_t * ep0in_buf = &USBIEP0BUF; From 5d9f83391544261117fffa2dec218b80ccd1d01c Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 28 Sep 2019 02:09:03 -0400 Subject: [PATCH 16/71] dcd_msp430x5xx: Implement STALL logic for EP 0. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 34 +++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 62aaee3cb..7a4599c26 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -239,13 +239,43 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; - (void) ep_addr; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if(epnum == 0) + { + if(dir == TUSB_DIR_OUT) + { + USBOEPCNT_0 |= NAK; + USBOEPCNF_0 |= STALL; + } + else + { + USBIEPCNT_0 |= NAK; + USBIEPCNF_0 |= STALL; + } + } } void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; - (void) ep_addr; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if(epnum == 0) + { + if(dir == TUSB_DIR_OUT) + { + USBOEPCNT_0 &= ~NAK; + } + else + { + USBIEPCNT_0 &= ~NAK; + } + } } /*------------------------------------------------------------------*/ From 529efcc0d2b60cceac14ca01a1f6e5fecab4d8aa Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 29 Sep 2019 00:21:40 -0400 Subject: [PATCH 17/71] dcd_msp430x5xx: Implement dcd_edpt_open. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 74 ++++++++++++++++++++- 1 file changed, 71 insertions(+), 3 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 7a4599c26..aac4f01db 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -44,7 +44,9 @@ static bool in_isr = false; uint8_t _setup_packet[8]; -typedef struct { +// Xfer control +typedef struct +{ uint8_t * buffer; uint16_t total_len; uint16_t queued_len; @@ -55,6 +57,21 @@ typedef struct { xfer_ctl_t xfer_status[8][2]; #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +// Accessing endpoint regs +typedef volatile uint8_t * ep_regs_t; + +typedef enum +{ + CNF = 0, + BBAX = 1, + BCTX = 2, + BBAY = 5, + BCTY = 6, + SIZXY = 7 +} ep_regs_index_t; + +#define EP_REGS(epnum, dir) &USBOEPCNF_1 + 64*dir + 8*(epnum - 1) + static void bus_reset(void) { @@ -197,9 +214,60 @@ void dcd_remote_wakeup(uint8_t rhport) bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - (void) desc_edpt; - return false; + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + // Unsupported endpoint numbers/size or type (Iso not supported. Control + // not supported on nonzero endpoints). + if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 7) || \ + (desc_edpt->bmAttributes.xfer == 0) || \ + (desc_edpt->bmAttributes.xfer == 1)) { + return false; + } + + // Buffer allocation scheme: + // For simplicity, only single buffer for now, since tinyusb currently waits + // for an xfer to complete before scheduling another one. This means only + // the X buffer is used. + // + // 1904 bytes are available, the max endpoint size supported on msp430 is + // 64 bytes. This is enough RAM for all 14 endpoints enabled _with_ double + // bufferring (64*14*2 = 1792 bytes). Extra RAM exists for triple and higher + // order bufferring, which must be maintained in software. + // + // For simplicity, each endpoint gets a hardcoded 64 byte chunk (regardless + // of actual wMaxPacketSize) whose start address is the following: + // addr = 128 * (epnum - 1) + 64 * dir. + // + // Double buffering equation: + // x_addr = 256 * (epnum - 1) + 128 * dir + // y_addr = x_addr + 64 + + ep_regs_t ep_regs = EP_REGS(epnum, dir); + uint8_t buf_base = (128 * (epnum - 1) + 64 * dir) >> 3; + + // IN and OUT EP registers have the same structure. + + ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size; + ep_regs[BCTX] |= NAK; + ep_regs[BBAX] = buf_base; + ep_regs[CNF] &= ~TOGGLE; // ISO xfers not supported on MSP430, so no need + // to gate DATA0/1 and frame behavior. + ep_regs[CNF] |= (UBME | USBIIE); + + USBKEYPID = USBKEY; + if(dir == TUSB_DIR_OUT) + { + USBOEPIE |= (1 << epnum); + } + else + { + USBIEPIE |= (1 << epnum); + } + USBKEYPID = 0; + + return true; } bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) From ea0e799df6594fa6644575493547f41994c9be27 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 29 Sep 2019 02:17:59 -0400 Subject: [PATCH 18/71] dcd_msp430x5xx: Fix clear stall logic. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index aac4f01db..edb707963 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -337,11 +337,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { if(dir == TUSB_DIR_OUT) { - USBOEPCNT_0 &= ~NAK; + USBOEPCNT_0 &= ~STALL; } else { - USBIEPCNT_0 &= ~NAK; + USBIEPCNT_0 &= ~STALL; } } } From 2247f132ca00667253630f833459f0129eb75f11 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 29 Sep 2019 02:22:09 -0400 Subject: [PATCH 19/71] Implement dcd_edpt_xfer for nonzero endpoints. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 56 +++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index edb707963..3950a6204 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -226,6 +226,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return false; } + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = desc_edpt->wMaxPacketSize.size; + // Buffer allocation scheme: // For simplicity, only single buffer for now, since tinyusb currently waits // for an xfer to complete before scheduling another one. This means only @@ -243,17 +246,23 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // Double buffering equation: // x_addr = 256 * (epnum - 1) + 128 * dir // y_addr = x_addr + 64 + // Address is right-shifted by 3 to fit into 8 bits. - ep_regs_t ep_regs = EP_REGS(epnum, dir); uint8_t buf_base = (128 * (epnum - 1) + 64 * dir) >> 3; // IN and OUT EP registers have the same structure. + ep_regs_t ep_regs = EP_REGS(epnum, dir); + // FIXME: I was able to get into a situation where OUT EP 3 would stall + // while debugging, despite stall code never being called. It appears + // these registers don't get cleared on reset, being part of RAM. + // Investigate and see if I can duplicate. ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size; ep_regs[BCTX] |= NAK; ep_regs[BBAX] = buf_base; - ep_regs[CNF] &= ~TOGGLE; // ISO xfers not supported on MSP430, so no need - // to gate DATA0/1 and frame behavior. + ep_regs[CNF] &= ~TOGGLE; // ISO xfers not supported on MSP430, + // so no need to gate DATA0/1 and frame + // behavior. ep_regs[CNF] |= (UBME | USBIIE); USBKEYPID = USBKEY; @@ -300,6 +309,21 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t USBIEPIFG |= BIT0; } } + else + { + ep_regs_t ep_regs = EP_REGS(epnum, dir); + + ep_regs[CNF] &= ~TOGGLE; // Bulk and int begin on DATA0. + + if(dir == TUSB_DIR_OUT) + { + ep_regs[BCTX] &= ~NAK; + } + else + { + USBIEPIFG |= (1 << epnum); + } + } return true; } @@ -438,6 +462,32 @@ void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) receive_packet(0); break; + case USBVECINT_INPUT_ENDPOINT1: + case USBVECINT_INPUT_ENDPOINT2: + case USBVECINT_INPUT_ENDPOINT3: + case USBVECINT_INPUT_ENDPOINT4: + case USBVECINT_INPUT_ENDPOINT5: + case USBVECINT_INPUT_ENDPOINT6: + case USBVECINT_INPUT_ENDPOINT7: + { + uint8_t ep = ((curr_vector - USBVECINT_INPUT_ENDPOINT1) >> 1) + 1; + transmit_packet(ep); + } + break; + + case USBVECINT_OUTPUT_ENDPOINT1: + case USBVECINT_OUTPUT_ENDPOINT2: + case USBVECINT_OUTPUT_ENDPOINT3: + case USBVECINT_OUTPUT_ENDPOINT4: + case USBVECINT_OUTPUT_ENDPOINT5: + case USBVECINT_OUTPUT_ENDPOINT6: + case USBVECINT_OUTPUT_ENDPOINT7: + { + uint8_t ep = ((curr_vector - USBVECINT_OUTPUT_ENDPOINT1) >> 1) + 1; + receive_packet(ep); + } + break; + default: while(true); break; From 838b431faca79e0bd9d627a79b6905010769551c Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 29 Sep 2019 02:43:05 -0400 Subject: [PATCH 20/71] dcd_msp430x5xx: Implement transmit_packet for nonzero endpoints. Untested. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 60 +++++++++++++-------- 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 3950a6204..da68074e7 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -382,31 +382,31 @@ static void transmit_packet(uint8_t ep_num) { xfer_ctl_t * xfer = XFER_CTL_BASE(ep_num, TUSB_DIR_IN); + // First, determine whether we should even send a packet or finish + // up the xfer. + bool zlp = (xfer->total_len == 0); // By necessity, xfer->total_len will + // equal xfer->queued_len for ZLPs. + // Of course a ZLP is a short packet. + if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->short_packet) + { + dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); + return; + } + + // Then actually commit to transmit a packet. + uint8_t * base = (xfer->buffer + xfer->queued_len); + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining; + + xfer->queued_len += xfer_size; + if(xfer_size < xfer->max_size) + { + // Next "xfer complete interrupt", the transfer will end. + xfer->short_packet = true; + } + if(ep_num == 0) { - // First, determine whether we should even send a packet or finish - // up the xfer. - bool zlp = (xfer->total_len == 0); // By necessity, xfer->total_len will - // equal xfer->queued_len for ZLPs. - // Of course a ZLP is a short packet. - if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->short_packet) - { - dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); - return; - } - - // Then actually commit to transmit a packet. - uint8_t * base = (xfer->buffer + xfer->queued_len); - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining; - - xfer->queued_len += xfer_size; - if(xfer_size < xfer->max_size) - { - // Next "xfer complete interrupt", the transfer will end. - xfer->short_packet = true; - } - volatile uint8_t * ep0in_buf = &USBIEP0BUF; for(int i = 0; i < xfer_size; i++) { @@ -416,6 +416,20 @@ static void transmit_packet(uint8_t ep_num) USBIEPCNT_0 = (USBIEPCNT_0 & 0xF0) + xfer_size; USBIEPCNT_0 &= ~NAK; } + else + { + ep_regs_t ep_regs = EP_REGS(ep_num, TUSB_DIR_IN); + uint16_t in_buf_base = USBSTABUFF + (ep_regs[BBAX] << 3); + + volatile uint8_t * ep_buf = (volatile uint8_t *) (in_buf_base); + for(int i = 0; i < xfer_size; i++) + { + ep_buf[i] = base[i]; + } + + ep_regs[BCTX] = (ep_regs[BCTX] & 0xF0) + xfer_size; + ep_regs[BCTX] &= ~NAK; + } } static void handle_setup_packet(void) From 549ad1d9b6a0a5b05e3017c2ed0e46ab65137760 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 29 Sep 2019 03:02:59 -0400 Subject: [PATCH 21/71] dcd_msp430x5xx: Fix missing mask when posting IN xfer events. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index da68074e7..e53a4b7cd 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -389,7 +389,7 @@ static void transmit_packet(uint8_t ep_num) // Of course a ZLP is a short packet. if((!zlp && (xfer->total_len == xfer->queued_len)) || xfer->short_packet) { - dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(0, ep_num | TUSB_DIR_IN_MASK, xfer->queued_len, XFER_RESULT_SUCCESS, true); return; } From b623e3023e7aaa8c9541f7d17a0c458667861cd4 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 29 Sep 2019 03:58:30 -0400 Subject: [PATCH 22/71] dcd_msp430x5xx: Implement receive_packet for all endpoints, correct some mistakes in transmit_packet. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 68 +++++++++++++++++++-- 1 file changed, 64 insertions(+), 4 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index e53a4b7cd..5e9fbf0f1 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -374,8 +374,69 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) static void receive_packet(uint8_t ep_num) { - (void) ep_num; + xfer_ctl_t * xfer = XFER_CTL_BASE(ep_num, TUSB_DIR_OUT); + ep_regs_t ep_regs = EP_REGS(ep_num, TUSB_DIR_OUT); + uint8_t xfer_size; + if(ep_num == 0) + { + xfer_size = USBOEPCNT_0 & 0x0F; + } + else + { + xfer_size = ep_regs[BCTX] & 0x3F; + } + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if(remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + uint8_t * base = (xfer->buffer + xfer->queued_len); + + if(ep_num == 0) + { + volatile uint8_t * ep0out_buf = &USBOEP0BUF; + for(uint16_t i = 0; i < to_recv_size; i++) + { + base[i] = ep0out_buf[i]; + } + } + else + { + volatile uint8_t * ep_buf = &USBSTABUFF + (ep_regs[BBAX] << 3); + for(uint16_t i = 0; i < to_recv_size ; i++) + { + base[i] = ep_buf[i]; + } + } + + xfer->queued_len += xfer_size; + + xfer->short_packet = (xfer_size < xfer->max_size); + if((xfer->total_len == xfer->queued_len) || xfer->short_packet) + { + dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } + else + { + // Schedule to receive another packet. + if(ep_num == 0) + { + USBOEPCNT_0 &= ~NAK; + } + else + { + ep_regs[BCTX] &= ~NAK; + } + } } static void transmit_packet(uint8_t ep_num) @@ -408,7 +469,7 @@ static void transmit_packet(uint8_t ep_num) if(ep_num == 0) { volatile uint8_t * ep0in_buf = &USBIEP0BUF; - for(int i = 0; i < xfer_size; i++) + for(uint16_t i = 0; i < xfer_size; i++) { ep0in_buf[i] = base[i]; } @@ -419,9 +480,8 @@ static void transmit_packet(uint8_t ep_num) else { ep_regs_t ep_regs = EP_REGS(ep_num, TUSB_DIR_IN); - uint16_t in_buf_base = USBSTABUFF + (ep_regs[BBAX] << 3); + volatile uint8_t * ep_buf = &USBSTABUFF + (ep_regs[BBAX] << 3); - volatile uint8_t * ep_buf = (volatile uint8_t *) (in_buf_base); for(int i = 0; i < xfer_size; i++) { ep_buf[i] = base[i]; From fad44c03c874ad5b278e41ab842e2fb36134ad2a Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 1 Oct 2019 23:03:39 -0400 Subject: [PATCH 23/71] dcd_msp430x5xx: Fix TOGGLE bit behavior, clear stall when endpoint opened due to reset potentially not resetting everything. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 5e9fbf0f1..121dd03ac 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -260,9 +260,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size; ep_regs[BCTX] |= NAK; ep_regs[BBAX] = buf_base; - ep_regs[CNF] &= ~TOGGLE; // ISO xfers not supported on MSP430, + ep_regs[CNF] &= ~(TOGGLE | STALL); // ISO xfers not supported on MSP430, // so no need to gate DATA0/1 and frame - // behavior. + // behavior. Clear stall bit- see above comment. ep_regs[CNF] |= (UBME | USBIIE); USBKEYPID = USBKEY; @@ -313,8 +313,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { ep_regs_t ep_regs = EP_REGS(epnum, dir); - ep_regs[CNF] &= ~TOGGLE; // Bulk and int begin on DATA0. - if(dir == TUSB_DIR_OUT) { ep_regs[BCTX] &= ~NAK; From 54478aaa2a57e62f946581f492da5792741116f9 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 1 Oct 2019 23:28:41 -0400 Subject: [PATCH 24/71] dcd_msp430x5xx: Add STALL support for nonzero endpoints. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 121dd03ac..5202f156a 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -346,6 +346,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) USBIEPCNF_0 |= STALL; } } + else + { + ep_regs_t ep_regs = EP_REGS(epnum, dir); + ep_regs[CNF] |= STALL; + } } void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) @@ -366,6 +371,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) USBIEPCNT_0 &= ~STALL; } } + else + { + ep_regs_t ep_regs = EP_REGS(epnum, dir); + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + ep_regs[CNF] &= ~(STALL + TOGGLE); + } } /*------------------------------------------------------------------*/ From 19ee5199265d064e23c376c4ab0fdf92b08a5378 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 2 Oct 2019 00:01:58 -0400 Subject: [PATCH 25/71] dcd_msp430x5xx: Correct byte count masks in transmit/receive routines. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 5202f156a..2f67e5d37 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -394,7 +394,7 @@ static void receive_packet(uint8_t ep_num) } else { - xfer_size = ep_regs[BCTX] & 0x3F; + xfer_size = ep_regs[BCTX] & 0x7F; } uint16_t remaining = xfer->total_len - xfer->queued_len; @@ -497,7 +497,7 @@ static void transmit_packet(uint8_t ep_num) ep_buf[i] = base[i]; } - ep_regs[BCTX] = (ep_regs[BCTX] & 0xF0) + xfer_size; + ep_regs[BCTX] = (ep_regs[BCTX] & 0xF0) + (xfer_size & 0x7F); ep_regs[BCTX] &= ~NAK; } } From 3edb5548e98e76cda7479d2d039b0557eda26a1b Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 2 Oct 2019 01:18:56 -0400 Subject: [PATCH 26/71] dcd_msp430x5xx: Ensure DBUF bit is cleared on endpoint open, as it could get spuriously set in debugging sessions. cdc_msc functional. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 2f67e5d37..ac7e27ee7 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -257,12 +257,16 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // while debugging, despite stall code never being called. It appears // these registers don't get cleared on reset, being part of RAM. // Investigate and see if I can duplicate. + // Also, DBUF got set on OUT EP 2 while debugging. Only OUT EPs seem to be + // affected at this time. USB RAM directly precedes main RAM; perhaps I'm + // overwriting registers via buffer overflow w/ my debugging code? ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size; ep_regs[BCTX] |= NAK; ep_regs[BBAX] = buf_base; - ep_regs[CNF] &= ~(TOGGLE | STALL); // ISO xfers not supported on MSP430, - // so no need to gate DATA0/1 and frame - // behavior. Clear stall bit- see above comment. + ep_regs[CNF] &= ~(TOGGLE | STALL | DBUF); // ISO xfers not supported on + // MSP430, so no need to gate DATA0/1 and frame + // behavior. Clear stall and double buffer bit as + // well- see above comment. ep_regs[CNF] |= (UBME | USBIIE); USBKEYPID = USBKEY; From 05914de10992c0bc0f35f6fc3c6bc8064ffcd935 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 2 Oct 2019 22:36:45 -0400 Subject: [PATCH 27/71] dcd_msp430x5xx: Fix typos in dcd_edpt_clear_stall. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index ac7e27ee7..32565c38e 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -368,11 +368,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { if(dir == TUSB_DIR_OUT) { - USBOEPCNT_0 &= ~STALL; + USBOEPCNF_0 &= ~STALL; } else { - USBIEPCNT_0 &= ~STALL; + USBIEPCNF_0 &= ~STALL; } } else From b0b737b42a14982a1f928e408ba7eadc3f474d04 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 2 Oct 2019 23:02:55 -0400 Subject: [PATCH 28/71] usbd_control.c: Decide whether a control transfer has a data stage based on setup packet wLength. --- src/device/usbd_control.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index eed933f68..69ab47b4d 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -94,7 +94,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo _control_state.total_len = tu_min16(len, request->wLength); _control_state.total_transferred = 0; - if ( len ) + if ( _control_state.total_len ) { TU_ASSERT(buffer); From a01b0a73c13ca771e77440d040b0e1e3c5ecbcf7 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Thu, 3 Oct 2019 23:58:24 -0400 Subject: [PATCH 29/71] Remove accidentally-commited debug var. --- src/device/usbd_control.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 070ff504b..e1e9b9f01 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -116,7 +116,6 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo return true; } -volatile int dummy = 0; // callback when a transaction complete on DATA stage of control endpoint bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) @@ -133,13 +132,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result _control_state.total_transferred += xferred_bytes; _control_state.buffer = ((uint8_t*)_control_state.buffer) + xferred_bytes; - if((_control_state.total_transferred >= 144)) - { - dummy = 1; - } - if ( (_control_state.requested_len == _control_state.total_transferred) || xferred_bytes < CFG_TUD_ENDPOINT0_SIZE ) - { // DATA stage is complete bool is_ok = true; From c5ce4619a388a6409d57f4910ff99ae1f6e9a948 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Fri, 4 Oct 2019 05:24:59 -0400 Subject: [PATCH 30/71] travis.yml: Add msp430 support. --- .travis.yml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 6dfc507fc..6c63a51f2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -14,9 +14,13 @@ addons: install: - gem install ceedling - + before_script: + - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/exports/msp430-gcc-8.2.0.52_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.b2 + - tar -xjf /tmp/msp430-gcc.tar.b2 + - export PATH=$PATH:$PWD/msp430-gcc-8.2.0.52_linux64/bin - arm-none-eabi-gcc --version + - msp430-elf-gcc --version script: # Build all examples @@ -25,6 +29,6 @@ script: - cd test - ceedling test:all - cd .. - + after_success: - source tools/build_success.sh From e4a88bc826a389b452fa0795292f39456585ed05 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Fri, 4 Oct 2019 05:36:51 -0400 Subject: [PATCH 31/71] examples: Fix #ifndef guard for CFG_TUD_ENDPOINT0_SIZE. --- examples/device/board_test/src/tusb_config.h | 2 ++ examples/device/usbtmc/src/tusb_config.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 2f2a4deeb..1a52cc348 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -64,7 +64,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- +#ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 +#endif //------------- CLASS -------------// #define CFG_TUD_CDC 0 diff --git a/examples/device/usbtmc/src/tusb_config.h b/examples/device/usbtmc/src/tusb_config.h index 9141e6a5a..124680ca2 100644 --- a/examples/device/usbtmc/src/tusb_config.h +++ b/examples/device/usbtmc/src/tusb_config.h @@ -51,7 +51,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- +#ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 +#endif //------------- CLASS -------------// From 16ff152129ce8881c2b107bce366fc35a817ab2d Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 5 Oct 2019 09:37:48 -0400 Subject: [PATCH 32/71] msp_exp430f5529lp: Set up UART functionality. --- hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c index 29f88ccf5..4eed41a4f 100644 --- a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c +++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c @@ -115,15 +115,29 @@ static void SystemClock_Config(void) USBKEYPID = 0; } +uint32_t wait = 0; + void board_init(void) { __bis_SR_register(GIE); // Enable interrupts. SystemClock_Config(); + // Enable basic I/O. P1DIR |= LED_PIN; // LED output. P1REN |= BUTTON_PIN; // Internal resistor enable. P1OUT |= BUTTON_PIN; // Pullup. + // Enable the backchannel UART (115200) + P4DIR |= BIT5; + P4SEL |= (BIT5 | BIT4); + + UCA1CTL1 |= (UCSSEL__SMCLK | UCSWRST); // Hold in reset, use SMCLK. + UCA1BRW = 4; + UCA1MCTL |= (UCBRF_3 | UCBRS_5 | UCOS16); // Overampling mode, 115200 baud. + // Copied from manual. + UCA1CTL1 &= ~UCSWRST; + + // Set up USB pins. USBKEYPID = USBKEY; USBPHYCTL |= PUSEL; // Convert USB D+/D- pins to USB functionality. USBKEYPID = 0; @@ -150,6 +164,32 @@ uint32_t board_button_read(void) return (P1IN & BIT1); } +int board_uart_read(uint8_t * buf, int len) +{ + for(int i = 0; i < len; i++) + { + // Wait until something to receive (cleared by reading buffer). + while(!(UCA1IFG & UCRXIFG)); + buf[i] = UCA1RXBUF; + } + + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + const char * char_buf = (const char *) buf; + + for(int i = 0; i < len; i++) + { + // Wait until TX buffer is empty (cleared by writing buffer). + while(!(UCA1IFG & UCTXIFG)); + UCA1TXBUF = char_buf[i]; + } + + return 0; +} + #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void) From 97af9e3332435cfd0fbed9487df2b5c08096e973 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sun, 6 Oct 2019 20:44:06 -0400 Subject: [PATCH 33/71] msp_exp430f5529lp: Make board_millis atomic. --- hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c index 4eed41a4f..937c35d92 100644 --- a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c +++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c @@ -200,6 +200,15 @@ void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void) uint32_t board_millis(void) { - return system_ticks; + uint32_t systick_mirror; + + // 32-bit update is not atomic on MSP430. We can read the bottom 16-bits, + // an interrupt occurs, updates _all_ 32 bits, and then we return a + // garbage value. And I've seen it happen! + TA0CCTL0 &= ~CCIE; + systick_mirror = system_ticks; + TA0CCTL0 |= CCIE; + + return systick_mirror; } #endif From c8e899fef03461d0aecfd82370f818483e8c9a3d Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Thu, 10 Oct 2019 04:02:35 -0400 Subject: [PATCH 34/71] dcd_msp430x5xx: Improve SETUP packet and EP0 NAK interactions, per 42.3.1.3 in Reference Manual; fix is incomplete but works. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 32565c38e..7b31ddd0a 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -90,9 +90,9 @@ static void bus_reset(void) USBOEPIE |= BIT0; USBIEPIE |= BIT0; - // Set NAK until a setup packet is received. - USBOEPCNT_0 |= NAK; - USBIEPCNT_0 |= NAK; + // Clear NAK until a setup packet is received. + USBOEPCNT_0 &= ~NAK; + USBIEPCNT_0 &= ~NAK; USBCTL |= FEN; // Enable responding to packets. @@ -515,6 +515,11 @@ static void handle_setup_packet(void) _setup_packet[i] = setup_buf[i]; } + // The NAK bits must be clear to receive a SETUP packet. Clearing SETUPIFG + // by reading USBVECINT does not set NAK, so now that we have a SETUP packet + // force NAKs. + USBIEPCNT_0 |= NAK; + USBOEPCNT_0 |= NAK; dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true); } From d0146be00b4dd41826f29e36bb10e0ecafce5e47 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Thu, 10 Oct 2019 04:19:48 -0400 Subject: [PATCH 35/71] dcd_msp430x5xx: Fix typo in copy-paste in transmit_packet. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 7b31ddd0a..a6efee094 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -501,7 +501,7 @@ static void transmit_packet(uint8_t ep_num) ep_buf[i] = base[i]; } - ep_regs[BCTX] = (ep_regs[BCTX] & 0xF0) + (xfer_size & 0x7F); + ep_regs[BCTX] = (ep_regs[BCTX] & 0x80) + (xfer_size & 0x7F); ep_regs[BCTX] &= ~NAK; } } From de333a6f1879f43fde6e17f4dc866ad2ad77dc6b Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2019 16:21:31 +0700 Subject: [PATCH 36/71] clean up warning, msp430 gcc 8.3 fixed the library lto issue --- examples/make.mk | 4 ---- src/tusb.c | 4 ++-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/examples/make.mk b/examples/make.mk index 4a2af3c22..95b2593bd 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -77,10 +77,6 @@ CFLAGS += \ -ffunction-sections \ -fdata-sections -ifneq ($(BOARD), msp_exp430f5529lp) - CFLAGS += -Wno-error=lto-type-mismatch -endif - # This causes lots of warning with nrf5x build due to nrfx code # CFLAGS += -Wcast-align diff --git a/src/tusb.c b/src/tusb.c index 271b35f1e..e7f5d800d 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -71,7 +71,7 @@ char const* const tusb_strerr[TUSB_ERROR_COUNT] = { ERROR_TABLE(ERROR_STRING) }; static void dump_str_line(uint8_t const* buf, uint16_t count) { // each line is 16 bytes - for(int i=0; i Date: Tue, 29 Oct 2019 16:24:09 +0700 Subject: [PATCH 37/71] correct read()/write() retarget for msp430, fix msp430 button state --- hw/bsp/board.c | 11 +++++++++-- hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c | 8 ++++---- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 16e713de5..af87a7cdb 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -26,6 +26,13 @@ #include "board.h" +#if defined(__MSP430__) + #define sys_write write + #define sys_read read +#else + #define sys_write _write + #define sys_read _read +#endif //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -45,13 +52,13 @@ // newlib read()/write() retarget -TU_ATTR_USED int _write (int fhdl, const void *buf, size_t count) +TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { (void) fhdl; return board_uart_write(buf, count); } -TU_ATTR_USED int _read (int fhdl, char *buf, size_t count) +TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; return board_uart_read((uint8_t*) buf, count); diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c index 937c35d92..bcae4b09e 100644 --- a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c +++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c @@ -34,7 +34,7 @@ #define BUTTON_PORT P1IN #define BUTTON_PIN BIT1 -#define BUTTON_STATE_ACTIVE 1 +#define BUTTON_STATE_ACTIVE 0 uint32_t cnt = 0; @@ -161,7 +161,7 @@ void board_led_write(bool state) uint32_t board_button_read(void) { - return (P1IN & BIT1); + return ((P1IN & BIT1) >> 1) == BUTTON_STATE_ACTIVE; } int board_uart_read(uint8_t * buf, int len) @@ -173,7 +173,7 @@ int board_uart_read(uint8_t * buf, int len) buf[i] = UCA1RXBUF; } - return 0; + return len; } int board_uart_write(void const * buf, int len) @@ -187,7 +187,7 @@ int board_uart_write(void const * buf, int len) UCA1TXBUF = char_buf[i]; } - return 0; + return len; } #if CFG_TUSB_OS == OPT_OS_NONE From f6a65720e563a5edc69fdb5e2c1aa320e206a059 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2019 16:25:32 +0700 Subject: [PATCH 38/71] should fix #184 only response up to EP0 size with get device descriptor if not addressed. --- src/device/usbd.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index f2becab95..5c6fc3748 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -44,6 +44,7 @@ typedef struct { struct TU_ATTR_PACKED { volatile uint8_t connected : 1; + volatile uint8_t addressed : 1; volatile uint8_t configured : 1; volatile uint8_t suspended : 1; @@ -478,6 +479,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // Depending on mcu, status phase could be sent either before or after changing device address // Therefore DCD must include zero-length status response dcd_set_address(rhport, (uint8_t) p_request->wValue); + _usbd_dev.addressed = 1; return true; // skip status break; @@ -752,7 +754,17 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const switch(desc_type) { case TUSB_DESC_DEVICE: - return tud_control_xfer(rhport, p_request, (void*) tud_descriptor_device_cb(), sizeof(tusb_desc_device_t)); + { + uint16_t len = sizeof(tusb_desc_device_t); + + // Only send up to EP0 Packet Size if not addressed + if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed) + { + len = CFG_TUD_ENDPOINT0_SIZE; + } + + return tud_control_xfer(rhport, p_request, (void*) tud_descriptor_device_cb(), len); + } break; case TUSB_DESC_BOS: @@ -820,6 +832,7 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr) case DCD_EVENT_UNPLUGGED: _usbd_dev.connected = 0; + _usbd_dev.addressed = 0; _usbd_dev.configured = 0; _usbd_dev.suspended = 0; osal_queue_send(_usbd_q, event, in_isr); From 6e204ca567c5f9619bc6bf4849d3943116e122f8 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2019 17:36:53 +0700 Subject: [PATCH 39/71] add --allow-fw-update for convenience --- hw/bsp/msp_exp430f5529lp/board.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index 2e6e77f18..a0893a08e 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -4,6 +4,8 @@ CFLAGS += \ -DCFG_EXAMPLE_MSC_READONLY \ -DCFG_TUD_ENDPOINT0_SIZE=8 +#-mmcu=msp430f5529 + # All source paths should be relative to the top level. LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld LDINC += $(TOP)/hw/bsp/$(BOARD) @@ -19,4 +21,4 @@ MSPDEBUG = mspdebug # flash target using mspdebug. flash: $(BUILD)/$(BOARD)-firmware.elf - $(MSPDEBUG) tilib "prog $<" + $(MSPDEBUG) tilib "prog $<" --allow-fw-update From 66faa96f1609a1a6e95004ec7adbcd1568df01e2 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 29 Oct 2019 11:33:19 -0400 Subject: [PATCH 40/71] tusb_option.h: Assign msp430 ID range 500+ to avoid conflict with Sony. --- src/tusb_option.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/tusb_option.h b/src/tusb_option.h index 5ebda9f3b..d8cd3782b 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -72,7 +72,7 @@ #define OPT_MCU_CXD56 400 ///< SONY CXD56 // TI MSP430 -#define OPT_MCU_MSP430x5xx 400 ///< TI MSP430x5xx +#define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx /** @} */ From ffeb61a71070b262e5ffb975abad74c2d57b8fb9 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 29 Oct 2019 11:43:26 -0400 Subject: [PATCH 41/71] msp_exp430f5529lp: Use ti submodule for includes and linker files. --- hw/bsp/msp_exp430f5529lp/board.mk | 6 +- hw/bsp/msp_exp430f5529lp/in430.h | 345 -- hw/bsp/msp_exp430f5529lp/iomacros.h | 87 - hw/bsp/msp_exp430f5529lp/msp430.h | 1920 ------- hw/bsp/msp_exp430f5529lp/msp430f5529.h | 4789 ----------------- hw/bsp/msp_exp430f5529lp/msp430f5529.ld | 457 -- .../msp_exp430f5529lp/msp430f5529_symbols.ld | 867 --- 7 files changed, 3 insertions(+), 8468 deletions(-) delete mode 100644 hw/bsp/msp_exp430f5529lp/in430.h delete mode 100644 hw/bsp/msp_exp430f5529lp/iomacros.h delete mode 100644 hw/bsp/msp_exp430f5529lp/msp430.h delete mode 100644 hw/bsp/msp_exp430f5529lp/msp430f5529.h delete mode 100644 hw/bsp/msp_exp430f5529lp/msp430f5529.ld delete mode 100644 hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index a0893a08e..95192a990 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -7,10 +7,10 @@ CFLAGS += \ #-mmcu=msp430f5529 # All source paths should be relative to the top level. -LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld -LDINC += $(TOP)/hw/bsp/$(BOARD) +LD_FILE = hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld +LDINC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include -INC += $(TOP)/hw/bsp/$(BOARD) +INC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include # For TinyUSB port source VENDOR = ti diff --git a/hw/bsp/msp_exp430f5529lp/in430.h b/hw/bsp/msp_exp430f5529lp/in430.h deleted file mode 100644 index 9df9194c6..000000000 --- a/hw/bsp/msp_exp430f5529lp/in430.h +++ /dev/null @@ -1,345 +0,0 @@ -/******************************************************************************* - * in430.h - - * - * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -/* 1.207 */ - -#ifndef __IN430_H__ -#define __IN430_H__ - -/* Definitions for projects using the GNU C/C++ compiler */ -#if !defined(__ASSEMBLER__) - -/* Definitions of things which are intrinsics with IAR and CCS, but which don't - appear to be intrinsics with the GCC compiler */ - -/* The data type used to hold interrupt state */ -typedef unsigned int __istate_t; - -#define _no_operation() __asm__ __volatile__ ("nop") - -#define _get_interrupt_state() \ -({ \ - unsigned int __x; \ - __asm__ __volatile__( \ - "mov SR, %0" \ - : "=r" ((unsigned int) __x) \ - :); \ - __x; \ -}) - -#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__) -#define _set_interrupt_state(x) \ -({ \ - __asm__ __volatile__ ("nop { mov %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - );\ -}) - -#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop") - -#define _bis_SR_register(x) \ - __asm__ __volatile__ ("nop { bis.w %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - ) -#else - -#define _set_interrupt_state(x) \ -({ \ - __asm__ __volatile__ ("mov %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - );\ -}) - -#define _enable_interrupts() __asm__ __volatile__ ("eint") - -#define _bis_SR_register(x) \ - __asm__ __volatile__ ("bis.w %0, SR" \ - : : "ri"((unsigned int) x) \ - ) - -#endif - -#define _disable_interrupts() __asm__ __volatile__ ("dint { nop") - -#define _bic_SR_register(x) \ - __asm__ __volatile__ ("bic.w %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - ) - -#define _get_SR_register() \ -({ \ - unsigned int __x; \ - __asm__ __volatile__( \ - "mov SR, %0" \ - : "=r" ((unsigned int) __x) \ - :); \ - __x; \ -}) - -#define _swap_bytes(x) \ -({ \ - unsigned int __dst = x; \ - __asm__ __volatile__( \ - "swpb %0" \ - : "+r" ((unsigned int) __dst) \ - :); \ - __dst; \ -}) - -/* Alternative names for GCC built-ins */ -#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x) -#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x) - -/* Additional intrinsics provided for IAR/CCS compatibility */ -#define _bcd_add_short(x,y) \ -({ \ - unsigned short __z = ((unsigned short) y); \ - __asm__ __volatile__( \ - "clrc \n\t" \ - "dadd.w %1, %0" \ - : "+r" ((unsigned short) __z) \ - : "ri" ((unsigned short) x) \ - ); \ - __z; \ -}) - -#define __bcd_add_short(x,y) _bcd_add_short(x,y) - -#define _bcd_add_long(x,y) \ -({ \ - unsigned long __z = ((unsigned long) y); \ - __asm__ __volatile__( \ - "clrc \n\t" \ - "dadd.w %L1, %L0 \n\t" \ - "dadd.w %H1, %H0" \ - : "+r" ((unsigned long) __z) \ - : "ri" ((unsigned long) x) \ - ); \ - __z; \ - }) - -#define __bcd_add_long(x,y) _bcd_add_long(x,y) - -#define _get_SP_register() \ -({ \ - unsigned int __x; \ - __asm__ __volatile__( \ - "mov SP, %0" \ - : "=r" ((unsigned int) __x) \ - :); \ - __x; \ -}) - -#define __get_SP_register() _get_SP_register() - -#define _set_SP_register(x) \ -({ \ - __asm__ __volatile__ ("mov %0, SP" \ - : : "ri"((unsigned int) x) \ - );\ -}) - -#define __set_SP_register(x) _set_SP_register(x) - -#define _data16_write_addr(addr,src) \ -({ \ - unsigned long __src = src; \ - __asm__ __volatile__ ( \ - "movx.a %1, 0(%0)" \ - : : "r"((unsigned int) addr), "m"((unsigned long) __src) \ - ); \ -}) - -#define __data16_write_addr(addr,src) _data16_write_addr(addr,src) - -#define _data16_read_addr(addr) \ -({ \ - unsigned long __dst; \ - __asm__ __volatile__ ( \ - "movx.a @%1, %0" \ - : "=m"((unsigned long) __dst) \ - : "r"((unsigned int) addr) \ - ); \ - __dst; \ -}) - -#define __data16_read_addr(addr) _data16_read_addr(addr) - -#define _data20_write_char(addr,src) \ -({ \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %1, %0 \n\t" \ - "mov.b %2, 0(%0)" \ - : "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr), "ri"((char) src) \ - ); \ -}) - -#define __data20_write_char(addr,src) _data20_write_char(addr,src) - -#define _data20_read_char(addr) \ -({ \ - char __dst; \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %2, %1 \n\t" \ - "mov.b 0(%1), %0" \ - : "=r"((char) __dst), "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr) \ - ); \ - __dst ; \ -}) - -#define __data20_read_char(addr) _data20_read_char(addr) - -#define _data20_write_short(addr,src) \ -({ \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %1, %0 \n\t" \ - "mov.w %2, 0(%0)" \ - : "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr), "ri"((short) src) \ - ); \ -}) - -#define __data20_write_short(addr,src) _data20_write_short(addr,src) - -#define _data20_read_short(addr) \ -({ \ - short __dst; \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %2, %1 \n\t" \ - "mov.w 0(%1), %0" \ - : "=r"((short) __dst), "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr) \ - ); \ - __dst ; \ -}) - -#define __data20_read_short(addr) _data20_read_short(addr) - -#define _data20_write_long(addr,src) \ -({ \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %1, %0 \n\t" \ - "mov.w %L2, 0(%0) \n\t" \ - "mov.w %H2, 2(%0)" \ - : "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr), "ri"((long) src) \ - ); \ -}) - -#define __data20_write_long(addr,src) _data20_write_long(addr,src) - -#define _data20_read_long(addr) \ -({ \ - long __dst; \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %2, %1 \n\t" \ - "mov.w 0(%1), %L0 \n\t" \ - "mov.w 2(%1), %H0" \ - : "=r"((long) __dst), "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr) \ - ); \ - __dst ; \ -}) - -#define __data20_read_long(addr) _data20_read_long(addr) - -#define _low_power_mode_0() _bis_SR_register(0x18) -#define _low_power_mode_1() _bis_SR_register(0x58) -#define _low_power_mode_2() _bis_SR_register(0x98) -#define _low_power_mode_3() _bis_SR_register(0xD8) -#define _low_power_mode_4() _bis_SR_register(0xF8) -#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0) - -#define __low_power_mode_0() _low_power_mode_0() -#define __low_power_mode_1() _low_power_mode_1() -#define __low_power_mode_2() _low_power_mode_2() -#define __low_power_mode_3() _low_power_mode_3() -#define __low_power_mode_4() _low_power_mode_4() -#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit() - -#define _even_in_range(x,y) (x) -#define __even_in_range(x,y) _even_in_range(x,y) - -/* Define some alternative names for the intrinsics, which have been used - in the various versions of IAR and GCC */ -#define __no_operation() _no_operation() - -#define __get_interrupt_state() _get_interrupt_state() -#define __set_interrupt_state(x) _set_interrupt_state(x) -#define __enable_interrupt() _enable_interrupts() -#define __disable_interrupt() _disable_interrupts() - -#define __bic_SR_register(x) _bic_SR_register(x) -#define __bis_SR_register(x) _bis_SR_register(x) -#define __get_SR_register() _get_SR_register() - -#define __swap_bytes(x) _swap_bytes(x) - -#define __nop() _no_operation() - -#define __eint() _enable_interrupts() -#define __dint() _disable_interrupts() - -#define _NOP() _no_operation() -#define _EINT() _enable_interrupts() -#define _DINT() _disable_interrupts() - -#define _BIC_SR(x) _bic_SR_register(x) -#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x) -#define _BIS_SR(x) _bis_SR_register(x) -#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x) -#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x) - -#define _SWAP_BYTES(x) _swap_bytes(x) - -#define __no_init __attribute__((noinit)) - -#endif /* !defined _GNU_ASSEMBLER_ */ - -#endif /* __IN430_H__ */ diff --git a/hw/bsp/msp_exp430f5529lp/iomacros.h b/hw/bsp/msp_exp430f5529lp/iomacros.h deleted file mode 100644 index 5ddda4873..000000000 --- a/hw/bsp/msp_exp430f5529lp/iomacros.h +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* - * iomacros.h - - * - * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -/* 1.207 */ - -#if !defined(_IOMACROS_H_) -#define _IOMACROS_H_ - - -#if defined(__ASSEMBLER__) - -/* Definitions for assembly compilation using the GNU assembler */ -#define sfrb(x,x_) x=x_ -#define sfrw(x,x_) x=x_ -#define sfra(x,x_) x=x_ -#define sfrl(x,x_) x=x_ - -#define const_sfrb(x,x_) x=x_ -#define const_sfrw(x,x_) x=x_ -#define const_sfra(x,x_) x=x_ -#define const_sfrl(x,x_) x=x_ - -#define sfr_b(x) -#define sfr_w(x) -#define sfr_a(x) -#define sfr_l(x) - -#else - -#define sfr_b(x) extern volatile unsigned char x -#define sfr_w(x) extern volatile unsigned int x -#define sfr_a(x) extern volatile unsigned long int x -#define sfr_l(x) extern volatile unsigned long int x - -#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_) -#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_) -#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_) -#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_) - -#define sfrb(x,x_) sfrb_(x,x_) -#define sfrw(x,x_) sfrw_(x,x_) -#define sfra(x,x_) sfra_(x,x_) -#define sfrl(x,x_) sfrl_(x,x_) - -#define const_sfrb(x,x_) const sfrb_(x,x_) -#define const_sfrw(x,x_) const sfrw_(x,x_) -#define const_sfra(x,x_) const sfra_(x,x_) -#define const_sfrl(x,x_) const sfrl_(x,x_) - -#define __interrupt __attribute__((__interrupt__)) -#define __interrupt_vec(vec) __attribute__((interrupt(vec))) - -#endif /* defined(__ASSEMBLER__) */ - -#endif /* _IOMACROS_H_ */ diff --git a/hw/bsp/msp_exp430f5529lp/msp430.h b/hw/bsp/msp_exp430f5529lp/msp430.h deleted file mode 100644 index a162addc0..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430.h +++ /dev/null @@ -1,1920 +0,0 @@ -/******************************************************************* -* * -* This file is a generic include file controlled by * -* compiler/assembler IDE generated defines * -* * -*******************************************************************/ - -#ifndef __msp430 -#define __msp430 - - -#if defined (__MSP430C111__) -#include "msp430c111.h" - -#elif defined (__MSP430C1111__) -#include "msp430c1111.h" - -#elif defined (__MSP430C112__) -#include "msp430c112.h" - -#elif defined (__MSP430C1121__) -#include "msp430c1121.h" - -#elif defined (__MSP430C1331__) -#include "msp430c1331.h" - -#elif defined (__MSP430C1351__) -#include "msp430c1351.h" - -#elif defined (__MSP430C311S__) -#include "msp430c311s.h" - -#elif defined (__MSP430C312__) -#include "msp430c312.h" - -#elif defined (__MSP430C313__) -#include "msp430c313.h" - -#elif defined (__MSP430C314__) -#include "msp430c314.h" - -#elif defined (__MSP430C315__) -#include "msp430c315.h" - -#elif defined (__MSP430C323__) -#include "msp430c323.h" - -#elif defined (__MSP430C325__) -#include "msp430c325.h" - -#elif defined (__MSP430C336__) -#include "msp430c336.h" - -#elif defined (__MSP430C337__) -#include "msp430c337.h" - -#elif defined (__MSP430C412__) -#include "msp430c412.h" - -#elif defined (__MSP430C413__) -#include "msp430c413.h" - -#elif defined (__MSP430CG4616__) -#include "msp430cg4616.h" - -#elif defined (__MSP430CG4617__) -#include "msp430cg4617.h" - -#elif defined (__MSP430CG4618__) -#include "msp430cg4618.h" - -#elif defined (__MSP430CG4619__) -#include "msp430cg4619.h" - -#elif defined (__MSP430E112__) -#include "msp430e112.h" - -#elif defined (__MSP430E313__) -#include "msp430e313.h" - -#elif defined (__MSP430E315__) -#include "msp430e315.h" - -#elif defined (__MSP430E325__) -#include "msp430e325.h" - -#elif defined (__MSP430E337__) -#include "msp430e337.h" - -#elif defined (__MSP430F110__) -#include "msp430f110.h" - -#elif defined (__MSP430F1101__) -#include "msp430f1101.h" - -#elif defined (__MSP430F1101A__) -#include "msp430f1101a.h" - -#elif defined (__MSP430F1111__) -#include "msp430f1111.h" - -#elif defined (__MSP430F1111A__) -#include "msp430f1111a.h" - -#elif defined (__MSP430F112__) -#include "msp430f112.h" - -#elif defined (__MSP430F1121__) -#include "msp430f1121.h" - -#elif defined (__MSP430F1121A__) -#include "msp430f1121a.h" - -#elif defined (__MSP430F1122__) -#include "msp430f1122.h" - -#elif defined (__MSP430F1132__) -#include "msp430f1132.h" - -#elif defined (__MSP430F122__) -#include "msp430f122.h" - -#elif defined (__MSP430F1222__) -#include "msp430f1222.h" - -#elif defined (__MSP430F123__) -#include "msp430f123.h" - -#elif defined (__MSP430F1232__) -#include "msp430f1232.h" - -#elif defined (__MSP430F133__) -#include "msp430f133.h" - -#elif defined (__MSP430F135__) -#include "msp430f135.h" - -#elif defined (__MSP430F147__) -#include "msp430f147.h" - -#elif defined (__MSP430F148__) -#include "msp430f148.h" - -#elif defined (__MSP430F149__) -#include "msp430f149.h" - -#elif defined (__MSP430F1471__) -#include "msp430f1471.h" - -#elif defined (__MSP430F1481__) -#include "msp430f1481.h" - -#elif defined (__MSP430F1491__) -#include "msp430f1491.h" - -#elif defined (__MSP430F155__) -#include "msp430f155.h" - -#elif defined (__MSP430F156__) -#include "msp430f156.h" - -#elif defined (__MSP430F157__) -#include "msp430f157.h" - -#elif defined (__MSP430F167__) -#include "msp430f167.h" - -#elif defined (__MSP430F168__) -#include "msp430f168.h" - -#elif defined (__MSP430F169__) -#include "msp430f169.h" - -#elif defined (__MSP430F1610__) -#include "msp430f1610.h" - -#elif defined (__MSP430F1611__) -#include "msp430f1611.h" - -#elif defined (__MSP430F1612__) -#include "msp430f1612.h" - -#elif defined (__MSP430F2001__) -#include "msp430f2001.h" - -#elif defined (__MSP430F2011__) -#include "msp430f2011.h" - -#elif defined (__MSP430F2002__) -#include "msp430f2002.h" - -#elif defined (__MSP430F2012__) -#include "msp430f2012.h" - -#elif defined (__MSP430F2003__) -#include "msp430f2003.h" - -#elif defined (__MSP430F2013__) -#include "msp430f2013.h" - -#elif defined (__MSP430F2101__) -#include "msp430f2101.h" - -#elif defined (__MSP430F2111__) -#include "msp430f2111.h" - -#elif defined (__MSP430F2121__) -#include "msp430f2121.h" - -#elif defined (__MSP430F2131__) -#include "msp430f2131.h" - -#elif defined (__MSP430F2112__) -#include "msp430f2112.h" - -#elif defined (__MSP430F2122__) -#include "msp430f2122.h" - -#elif defined (__MSP430F2132__) -#include "msp430f2132.h" - -#elif defined (__MSP430F2232__) -#include "msp430f2232.h" - -#elif defined (__MSP430F2252__) -#include "msp430f2252.h" - -#elif defined (__MSP430F2272__) -#include "msp430f2272.h" - -#elif defined (__MSP430F2234__) -#include "msp430f2234.h" - -#elif defined (__MSP430F2254__) -#include "msp430f2254.h" - -#elif defined (__MSP430F2274__) -#include "msp430f2274.h" - -#elif defined (__MSP430F2330__) -#include "msp430f2330.h" - -#elif defined (__MSP430F2350__) -#include "msp430f2350.h" - -#elif defined (__MSP430F2370__) -#include "msp430f2370.h" - -#elif defined (__MSP430F233__) -#include "msp430f233.h" - -#elif defined (__MSP430F235__) -#include "msp430f235.h" - -#elif defined (__MSP430F247__) -#include "msp430f247.h" - -#elif defined (__MSP430F248__) -#include "msp430f248.h" - -#elif defined (__MSP430F249__) -#include "msp430f249.h" - -#elif defined (__MSP430F2410__) -#include "msp430f2410.h" - -#elif defined (__MSP430F2471__) -#include "msp430f2471.h" - -#elif defined (__MSP430F2481__) -#include "msp430f2481.h" - -#elif defined (__MSP430F2491__) -#include "msp430f2491.h" - -#elif defined (__MSP430F2416__) -#include "msp430f2416.h" - -#elif defined (__MSP430F2417__) -#include "msp430f2417.h" - -#elif defined (__MSP430F2418__) -#include "msp430f2418.h" - -#elif defined (__MSP430F2419__) -#include "msp430f2419.h" - -#elif defined (__MSP430F2616__) -#include "msp430f2616.h" - -#elif defined (__MSP430F2617__) -#include "msp430f2617.h" - -#elif defined (__MSP430F2618__) -#include "msp430f2618.h" - -#elif defined (__MSP430F2619__) -#include "msp430f2619.h" - -#elif defined (__MSP430F412__) -#include "msp430f412.h" - -#elif defined (__MSP430F413__) -#include "msp430f413.h" - -#elif defined (__MSP430F415__) -#include "msp430f415.h" - -#elif defined (__MSP430F417__) -#include "msp430f417.h" - -#elif defined (__MSP430F4132__) -#include "msp430f4132.h" - -#elif defined (__MSP430F4152__) -#include "msp430f4152.h" - -#elif defined (__MSP430F423__) -#include "msp430f423.h" - -#elif defined (__MSP430F425__) -#include "msp430f425.h" - -#elif defined (__MSP430F427__) -#include "msp430f427.h" - -#elif defined (__MSP430F423A__) -#include "msp430f423a.h" - -#elif defined (__MSP430F425A__) -#include "msp430f425a.h" - -#elif defined (__MSP430F427A__) -#include "msp430f427a.h" - -#elif defined (__MSP430F435__) -#include "msp430f435.h" - -#elif defined (__MSP430F436__) -#include "msp430f436.h" - -#elif defined (__MSP430F437__) -#include "msp430f437.h" - -#elif defined (__MSP430F4351__) -#include "msp430f4351.h" - -#elif defined (__MSP430F4361__) -#include "msp430f4361.h" - -#elif defined (__MSP430F4371__) -#include "msp430f4371.h" - -#elif defined (__MSP430F4481__) -#include "msp430f4481.h" - -#elif defined (__MSP430F4491__) -#include "msp430f4491.h" - -#elif defined (__MSP430F447__) -#include "msp430f447.h" - -#elif defined (__MSP430F448__) -#include "msp430f448.h" - -#elif defined (__MSP430F449__) -#include "msp430f449.h" - -#elif defined (__MSP430FE423__) -#include "msp430fe423.h" - -#elif defined (__MSP430FE425__) -#include "msp430fe425.h" - -#elif defined (__MSP430FE427__) -#include "msp430fe427.h" - -#elif defined (__MSP430FE423A__) -#include "msp430fe423a.h" - -#elif defined (__MSP430FE425A__) -#include "msp430fe425a.h" - -#elif defined (__MSP430FE427A__) -#include "msp430fe427a.h" - -#elif defined (__MSP430FE4232__) -#include "msp430fe4232.h" - -#elif defined (__MSP430FE4242__) -#include "msp430fe4242.h" - -#elif defined (__MSP430FE4252__) -#include "msp430fe4252.h" - -#elif defined (__MSP430FE4272__) -#include "msp430fe4272.h" - -#elif defined (__MSP430F4783__) -#include "msp430f4783.h" - -#elif defined (__MSP430F4793__) -#include "msp430f4793.h" - -#elif defined (__MSP430F4784__) -#include "msp430f4784.h" - -#elif defined (__MSP430F4794__) -#include "msp430f4794.h" - -#elif defined (__MSP430F47126__) -#include "msp430f47126.h" - -#elif defined (__MSP430F47127__) -#include "msp430f47127.h" - -#elif defined (__MSP430F47163__) -#include "msp430f47163.h" - -#elif defined (__MSP430F47173__) -#include "msp430f47173.h" - -#elif defined (__MSP430F47183__) -#include "msp430f47183.h" - -#elif defined (__MSP430F47193__) -#include "msp430f47193.h" - -#elif defined (__MSP430F47166__) -#include "msp430f47166.h" - -#elif defined (__MSP430F47176__) -#include "msp430f47176.h" - -#elif defined (__MSP430F47186__) -#include "msp430f47186.h" - -#elif defined (__MSP430F47196__) -#include "msp430f47196.h" - -#elif defined (__MSP430F47167__) -#include "msp430f47167.h" - -#elif defined (__MSP430F47177__) -#include "msp430f47177.h" - -#elif defined (__MSP430F47187__) -#include "msp430f47187.h" - -#elif defined (__MSP430F47197__) -#include "msp430f47197.h" - -#elif defined (__MSP430F4250__) -#include "msp430f4250.h" - -#elif defined (__MSP430F4260__) -#include "msp430f4260.h" - -#elif defined (__MSP430F4270__) -#include "msp430f4270.h" - -#elif defined (__MSP430FG4250__) -#include "msp430fg4250.h" - -#elif defined (__MSP430FG4260__) -#include "msp430fg4260.h" - -#elif defined (__MSP430FG4270__) -#include "msp430fg4270.h" - -#elif defined (__MSP430FW423__) -#include "msp430fw423.h" - -#elif defined (__MSP430FW425__) -#include "msp430fw425.h" - -#elif defined (__MSP430FW427__) -#include "msp430fw427.h" - -#elif defined (__MSP430FW428__) -#include "msp430fw428.h" - -#elif defined (__MSP430FW429__) -#include "msp430fw429.h" - -#elif defined (__MSP430FG437__) -#include "msp430fg437.h" - -#elif defined (__MSP430FG438__) -#include "msp430fg438.h" - -#elif defined (__MSP430FG439__) -#include "msp430fg439.h" - -#elif defined (__MSP430F438__) -#include "msp430f438.h" - -#elif defined (__MSP430F439__) -#include "msp430f439.h" - -#elif defined (__MSP430F477__) -#include "msp430f477.h" - -#elif defined (__MSP430F478__) -#include "msp430f478.h" - -#elif defined (__MSP430F479__) -#include "msp430f479.h" - -#elif defined (__MSP430FG477__) -#include "msp430fg477.h" - -#elif defined (__MSP430FG478__) -#include "msp430fg478.h" - -#elif defined (__MSP430FG479__) -#include "msp430fg479.h" - -#elif defined (__MSP430F46161__) -#include "msp430f46161.h" - -#elif defined (__MSP430F46171__) -#include "msp430f46171.h" - -#elif defined (__MSP430F46181__) -#include "msp430f46181.h" - -#elif defined (__MSP430F46191__) -#include "msp430f46191.h" - -#elif defined (__MSP430F4616__) -#include "msp430f4616.h" - -#elif defined (__MSP430F4617__) -#include "msp430f4617.h" - -#elif defined (__MSP430F4618__) -#include "msp430f4618.h" - -#elif defined (__MSP430F4619__) -#include "msp430f4619.h" - -#elif defined (__MSP430FG4616__) -#include "msp430fg4616.h" - -#elif defined (__MSP430FG4617__) -#include "msp430fg4617.h" - -#elif defined (__MSP430FG4618__) -#include "msp430fg4618.h" - -#elif defined (__MSP430FG4619__) -#include "msp430fg4619.h" - -#elif defined (__MSP430F5418__) -#include "msp430f5418.h" - -#elif defined (__MSP430F5419__) -#include "msp430f5419.h" - -#elif defined (__MSP430F5435__) -#include "msp430f5435.h" - -#elif defined (__MSP430F5436__) -#include "msp430f5436.h" - -#elif defined (__MSP430F5437__) -#include "msp430f5437.h" - -#elif defined (__MSP430F5438__) -#include "msp430f5438.h" - -#elif defined (__MSP430F5418A__) -#include "msp430f5418a.h" - -#elif defined (__MSP430F5419A__) -#include "msp430f5419a.h" - -#elif defined (__MSP430F5435A__) -#include "msp430f5435a.h" - -#elif defined (__MSP430F5436A__) -#include "msp430f5436a.h" - -#elif defined (__MSP430F5437A__) -#include "msp430f5437a.h" - -#elif defined (__MSP430F5438A__) -#include "msp430f5438a.h" - -#elif defined (__MSP430F5212__) -#include "msp430f5212.h" - -#elif defined (__MSP430F5213__) -#include "msp430f5213.h" - -#elif defined (__MSP430F5214__) -#include "msp430f5214.h" - -#elif defined (__MSP430F5217__) -#include "msp430f5217.h" - -#elif defined (__MSP430F5218__) -#include "msp430f5218.h" - -#elif defined (__MSP430F5219__) -#include "msp430f5219.h" - -#elif defined (__MSP430F5222__) -#include "msp430f5222.h" - -#elif defined (__MSP430F5223__) -#include "msp430f5223.h" - -#elif defined (__MSP430F5224__) -#include "msp430f5224.h" - -#elif defined (__MSP430F5227__) -#include "msp430f5227.h" - -#elif defined (__MSP430F5228__) -#include "msp430f5228.h" - -#elif defined (__MSP430F5229__) -#include "msp430f5229.h" - -#elif defined (__MSP430F5232__) -#include "msp430f5232.h" - -#elif defined (__MSP430F5234__) -#include "msp430f5234.h" - -#elif defined (__MSP430F5237__) -#include "msp430f5237.h" - -#elif defined (__MSP430F5239__) -#include "msp430f5239.h" - -#elif defined (__MSP430F5242__) -#include "msp430f5242.h" - -#elif defined (__MSP430F5244__) -#include "msp430f5244.h" - -#elif defined (__MSP430F5247__) -#include "msp430f5247.h" - -#elif defined (__MSP430F5249__) -#include "msp430f5249.h" - -#elif defined (__MSP430F5304__) -#include "msp430f5304.h" - -#elif defined (__MSP430F5308__) -#include "msp430f5308.h" - -#elif defined (__MSP430F5309__) -#include "msp430f5309.h" - -#elif defined (__MSP430F5310__) -#include "msp430f5310.h" - -#elif defined (__MSP430F5340__) -#include "msp430f5340.h" - -#elif defined (__MSP430F5341__) -#include "msp430f5341.h" - -#elif defined (__MSP430F5342__) -#include "msp430f5342.h" - -#elif defined (__MSP430F5324__) -#include "msp430f5324.h" - -#elif defined (__MSP430F5325__) -#include "msp430f5325.h" - -#elif defined (__MSP430F5326__) -#include "msp430f5326.h" - -#elif defined (__MSP430F5327__) -#include "msp430f5327.h" - -#elif defined (__MSP430F5328__) -#include "msp430f5328.h" - -#elif defined (__MSP430F5329__) -#include "msp430f5329.h" - -#elif defined (__MSP430F5500__) -#include "msp430f5500.h" - -#elif defined (__MSP430F5501__) -#include "msp430f5501.h" - -#elif defined (__MSP430F5502__) -#include "msp430f5502.h" - -#elif defined (__MSP430F5503__) -#include "msp430f5503.h" - -#elif defined (__MSP430F5504__) -#include "msp430f5504.h" - -#elif defined (__MSP430F5505__) -#include "msp430f5505.h" - -#elif defined (__MSP430F5506__) -#include "msp430f5506.h" - -#elif defined (__MSP430F5507__) -#include "msp430f5507.h" - -#elif defined (__MSP430F5508__) -#include "msp430f5508.h" - -#elif defined (__MSP430F5509__) -#include "msp430f5509.h" - -#elif defined (__MSP430F5510__) -#include "msp430f5510.h" - -#elif defined (__MSP430F5513__) -#include "msp430f5513.h" - -#elif defined (__MSP430F5514__) -#include "msp430f5514.h" - -#elif defined (__MSP430F5515__) -#include "msp430f5515.h" - -#elif defined (__MSP430F5517__) -#include "msp430f5517.h" - -#elif defined (__MSP430F5519__) -#include "msp430f5519.h" - -#elif defined (__MSP430F5521__) -#include "msp430f5521.h" - -#elif defined (__MSP430F5522__) -#include "msp430f5522.h" - -#elif defined (__MSP430F5524__) -#include "msp430f5524.h" - -#elif defined (__MSP430F5525__) -#include "msp430f5525.h" - -#elif defined (__MSP430F5526__) -#include "msp430f5526.h" - -#elif defined (__MSP430F5527__) -#include "msp430f5527.h" - -#elif defined (__MSP430F5528__) -#include "msp430f5528.h" - -#elif defined (__MSP430F5529__) -#include "msp430f5529.h" - -#elif defined (__MSP430P112__) -#include "msp430p112.h" - -#elif defined (__MSP430P313__) -#include "msp430p313.h" - -#elif defined (__MSP430P315__) -#include "msp430p315.h" - -#elif defined (__MSP430P315S__) -#include "msp430p315s.h" - -#elif defined (__MSP430P325__) -#include "msp430p325.h" - -#elif defined (__MSP430P337__) -#include "msp430p337.h" - -#elif defined (__CC430F5133__) -#include "cc430f5133.h" - -#elif defined (__CC430F5135__) -#include "cc430f5135.h" - -#elif defined (__CC430F5137__) -#include "cc430f5137.h" - -#elif defined (__CC430F6125__) -#include "cc430f6125.h" - -#elif defined (__CC430F6126__) -#include "cc430f6126.h" - -#elif defined (__CC430F6127__) -#include "cc430f6127.h" - -#elif defined (__CC430F6135__) -#include "cc430f6135.h" - -#elif defined (__CC430F6137__) -#include "cc430f6137.h" - -#elif defined (__CC430F5123__) -#include "cc430f5123.h" - -#elif defined (__CC430F5125__) -#include "cc430f5125.h" - -#elif defined (__CC430F5143__) -#include "cc430f5143.h" - -#elif defined (__CC430F5145__) -#include "cc430f5145.h" - -#elif defined (__CC430F5147__) -#include "cc430f5147.h" - -#elif defined (__CC430F6143__) -#include "cc430f6143.h" - -#elif defined (__CC430F6145__) -#include "cc430f6145.h" - -#elif defined (__CC430F6147__) -#include "cc430f6147.h" - -#elif defined (__MSP430F5333__) -#include "msp430f5333.h" - -#elif defined (__MSP430F5335__) -#include "msp430f5335.h" - -#elif defined (__MSP430F5336__) -#include "msp430f5336.h" - -#elif defined (__MSP430F5338__) -#include "msp430f5338.h" - -#elif defined (__MSP430F5630__) -#include "msp430f5630.h" - -#elif defined (__MSP430F5631__) -#include "msp430f5631.h" - -#elif defined (__MSP430F5632__) -#include "msp430f5632.h" - -#elif defined (__MSP430F5633__) -#include "msp430f5633.h" - -#elif defined (__MSP430F5634__) -#include "msp430f5634.h" - -#elif defined (__MSP430F5635__) -#include "msp430f5635.h" - -#elif defined (__MSP430F5636__) -#include "msp430f5636.h" - -#elif defined (__MSP430F5637__) -#include "msp430f5637.h" - -#elif defined (__MSP430F5638__) -#include "msp430f5638.h" - -#elif defined (__MSP430F6433__) -#include "msp430f6433.h" - -#elif defined (__MSP430F6435__) -#include "msp430f6435.h" - -#elif defined (__MSP430F6436__) -#include "msp430f6436.h" - -#elif defined (__MSP430F6438__) -#include "msp430f6438.h" - -#elif defined (__MSP430F6630__) -#include "msp430f6630.h" - -#elif defined (__MSP430F6631__) -#include "msp430f6631.h" - -#elif defined (__MSP430F6632__) -#include "msp430f6632.h" - -#elif defined (__MSP430F6633__) -#include "msp430f6633.h" - -#elif defined (__MSP430F6634__) -#include "msp430f6634.h" - -#elif defined (__MSP430F6635__) -#include "msp430f6635.h" - -#elif defined (__MSP430F6636__) -#include "msp430f6636.h" - -#elif defined (__MSP430F6637__) -#include "msp430f6637.h" - -#elif defined (__MSP430F6638__) -#include "msp430f6638.h" - -#elif defined (__MSP430F5358__) -#include "msp430f5358.h" - -#elif defined (__MSP430F5359__) -#include "msp430f5359.h" - -#elif defined (__MSP430F5658__) -#include "msp430f5658.h" - -#elif defined (__MSP430F5659__) -#include "msp430f5659.h" - -#elif defined (__MSP430F6458__) -#include "msp430f6458.h" - -#elif defined (__MSP430F6459__) -#include "msp430f6459.h" - -#elif defined (__MSP430F6658__) -#include "msp430f6658.h" - -#elif defined (__MSP430F6659__) -#include "msp430f6659.h" - -#elif defined (__MSP430FG6425__) -#include "msp430fg6425.h" - -#elif defined (__MSP430FG6426__) -#include "msp430fg6426.h" - -#elif defined (__MSP430FG6625__) -#include "msp430fg6625.h" - -#elif defined (__MSP430FG6626__) -#include "msp430fg6626.h" - -#elif defined (__MSP430L092__) -#include "msp430l092.h" - -#elif defined (__MSP430C091__) -#include "msp430c091.h" - -#elif defined (__MSP430C092__) -#include "msp430c092.h" - -#elif defined (__MSP430F5131__) -#include "msp430f5131.h" - -#elif defined (__MSP430F5151__) -#include "msp430f5151.h" - -#elif defined (__MSP430F5171__) -#include "msp430f5171.h" - -#elif defined (__MSP430F5132__) -#include "msp430f5132.h" - -#elif defined (__MSP430F5152__) -#include "msp430f5152.h" - -#elif defined (__MSP430F5172__) -#include "msp430f5172.h" - -#elif defined (__MSP430F6720__) -#include "msp430f6720.h" - -#elif defined (__MSP430F6721__) -#include "msp430f6721.h" - -#elif defined (__MSP430F6723__) -#include "msp430f6723.h" - -#elif defined (__MSP430F6724__) -#include "msp430f6724.h" - -#elif defined (__MSP430F6725__) -#include "msp430f6725.h" - -#elif defined (__MSP430F6726__) -#include "msp430f6726.h" - -#elif defined (__MSP430F6730__) -#include "msp430f6730.h" - -#elif defined (__MSP430F6731__) -#include "msp430f6731.h" - -#elif defined (__MSP430F6733__) -#include "msp430f6733.h" - -#elif defined (__MSP430F6734__) -#include "msp430f6734.h" - -#elif defined (__MSP430F6735__) -#include "msp430f6735.h" - -#elif defined (__MSP430F6736__) -#include "msp430f6736.h" - -#elif defined (__MSP430F67621__) -#include "msp430f67621.h" - -#elif defined (__MSP430F67641__) -#include "msp430f67641.h" - -#elif defined (__MSP430F6720A__) -#include "msp430f6720a.h" - -#elif defined (__MSP430F6721A__) -#include "msp430f6721a.h" - -#elif defined (__MSP430F6723A__) -#include "msp430f6723a.h" - -#elif defined (__MSP430F6724A__) -#include "msp430f6724a.h" - -#elif defined (__MSP430F6725A__) -#include "msp430f6725a.h" - -#elif defined (__MSP430F6726A__) -#include "msp430f6726a.h" - -#elif defined (__MSP430F6730A__) -#include "msp430f6730a.h" - -#elif defined (__MSP430F6731A__) -#include "msp430f6731a.h" - -#elif defined (__MSP430F6733A__) -#include "msp430f6733a.h" - -#elif defined (__MSP430F6734A__) -#include "msp430f6734a.h" - -#elif defined (__MSP430F6735A__) -#include "msp430f6735a.h" - -#elif defined (__MSP430F6736A__) -#include "msp430f6736a.h" - -#elif defined (__MSP430F67621A__) -#include "msp430f67621a.h" - -#elif defined (__MSP430F67641A__) -#include "msp430f67641a.h" - -#elif defined (__MSP430F67451__) -#include "msp430f67451.h" - -#elif defined (__MSP430F67651__) -#include "msp430f67651.h" - -#elif defined (__MSP430F67751__) -#include "msp430f67751.h" - -#elif defined (__MSP430F67461__) -#include "msp430f67461.h" - -#elif defined (__MSP430F67661__) -#include "msp430f67661.h" - -#elif defined (__MSP430F67761__) -#include "msp430f67761.h" - -#elif defined (__MSP430F67471__) -#include "msp430f67471.h" - -#elif defined (__MSP430F67671__) -#include "msp430f67671.h" - -#elif defined (__MSP430F67771__) -#include "msp430f67771.h" - -#elif defined (__MSP430F67481__) -#include "msp430f67481.h" - -#elif defined (__MSP430F67681__) -#include "msp430f67681.h" - -#elif defined (__MSP430F67781__) -#include "msp430f67781.h" - -#elif defined (__MSP430F67491__) -#include "msp430f67491.h" - -#elif defined (__MSP430F67691__) -#include "msp430f67691.h" - -#elif defined (__MSP430F67791__) -#include "msp430f67791.h" - -#elif defined (__MSP430F6745__) -#include "msp430f6745.h" - -#elif defined (__MSP430F6765__) -#include "msp430f6765.h" - -#elif defined (__MSP430F6775__) -#include "msp430f6775.h" - -#elif defined (__MSP430F6746__) -#include "msp430f6746.h" - -#elif defined (__MSP430F6766__) -#include "msp430f6766.h" - -#elif defined (__MSP430F6776__) -#include "msp430f6776.h" - -#elif defined (__MSP430F6747__) -#include "msp430f6747.h" - -#elif defined (__MSP430F6767__) -#include "msp430f6767.h" - -#elif defined (__MSP430F6777__) -#include "msp430f6777.h" - -#elif defined (__MSP430F6748__) -#include "msp430f6748.h" - -#elif defined (__MSP430F6768__) -#include "msp430f6768.h" - -#elif defined (__MSP430F6778__) -#include "msp430f6778.h" - -#elif defined (__MSP430F6749__) -#include "msp430f6749.h" - -#elif defined (__MSP430F6769__) -#include "msp430f6769.h" - -#elif defined (__MSP430F6779__) -#include "msp430f6779.h" - -#elif defined (__MSP430F67451A__) -#include "msp430f67451a.h" - -#elif defined (__MSP430F67651A__) -#include "msp430f67651a.h" - -#elif defined (__MSP430F67751A__) -#include "msp430f67751a.h" - -#elif defined (__MSP430F67461A__) -#include "msp430f67461a.h" - -#elif defined (__MSP430F67661A__) -#include "msp430f67661a.h" - -#elif defined (__MSP430F67761A__) -#include "msp430f67761a.h" - -#elif defined (__MSP430F67471A__) -#include "msp430f67471a.h" - -#elif defined (__MSP430F67671A__) -#include "msp430f67671a.h" - -#elif defined (__MSP430F67771A__) -#include "msp430f67771a.h" - -#elif defined (__MSP430F67481A__) -#include "msp430f67481a.h" - -#elif defined (__MSP430F67681A__) -#include "msp430f67681a.h" - -#elif defined (__MSP430F67781A__) -#include "msp430f67781a.h" - -#elif defined (__MSP430F67491A__) -#include "msp430f67491a.h" - -#elif defined (__MSP430F67691A__) -#include "msp430f67691a.h" - -#elif defined (__MSP430F67791A__) -#include "msp430f67791a.h" - -#elif defined (__MSP430F6745A__) -#include "msp430f6745a.h" - -#elif defined (__MSP430F6765A__) -#include "msp430f6765a.h" - -#elif defined (__MSP430F6775A__) -#include "msp430f6775a.h" - -#elif defined (__MSP430F6746A__) -#include "msp430f6746a.h" - -#elif defined (__MSP430F6766A__) -#include "msp430f6766a.h" - -#elif defined (__MSP430F6776A__) -#include "msp430f6776a.h" - -#elif defined (__MSP430F6747A__) -#include "msp430f6747a.h" - -#elif defined (__MSP430F6767A__) -#include "msp430f6767a.h" - -#elif defined (__MSP430F6777A__) -#include "msp430f6777a.h" - -#elif defined (__MSP430F6748A__) -#include "msp430f6748a.h" - -#elif defined (__MSP430F6768A__) -#include "msp430f6768a.h" - -#elif defined (__MSP430F6778A__) -#include "msp430f6778a.h" - -#elif defined (__MSP430F6749A__) -#include "msp430f6749a.h" - -#elif defined (__MSP430F6769A__) -#include "msp430f6769a.h" - -#elif defined (__MSP430F6779A__) -#include "msp430f6779a.h" - -#elif defined (__MSP430FR5720__) -#include "msp430fr5720.h" - -#elif defined (__MSP430FR5721__) -#include "msp430fr5721.h" - -#elif defined (__MSP430FR5722__) -#include "msp430fr5722.h" - -#elif defined (__MSP430FR5723__) -#include "msp430fr5723.h" - -#elif defined (__MSP430FR5724__) -#include "msp430fr5724.h" - -#elif defined (__MSP430FR5725__) -#include "msp430fr5725.h" - -#elif defined (__MSP430FR5726__) -#include "msp430fr5726.h" - -#elif defined (__MSP430FR5727__) -#include "msp430fr5727.h" - -#elif defined (__MSP430FR5728__) -#include "msp430fr5728.h" - -#elif defined (__MSP430FR5729__) -#include "msp430fr5729.h" - -#elif defined (__MSP430FR5730__) -#include "msp430fr5730.h" - -#elif defined (__MSP430FR5731__) -#include "msp430fr5731.h" - -#elif defined (__MSP430FR5732__) -#include "msp430fr5732.h" - -#elif defined (__MSP430FR5733__) -#include "msp430fr5733.h" - -#elif defined (__MSP430FR5734__) -#include "msp430fr5734.h" - -#elif defined (__MSP430FR5735__) -#include "msp430fr5735.h" - -#elif defined (__MSP430FR5736__) -#include "msp430fr5736.h" - -#elif defined (__MSP430FR5737__) -#include "msp430fr5737.h" - -#elif defined (__MSP430FR5738__) -#include "msp430fr5738.h" - -#elif defined (__MSP430FR5739__) -#include "msp430fr5739.h" - -#elif defined (__MSP430G2211__) -#include "msp430g2211.h" - -#elif defined (__MSP430G2201__) -#include "msp430g2201.h" - -#elif defined (__MSP430G2111__) -#include "msp430g2111.h" - -#elif defined (__MSP430G2101__) -#include "msp430g2101.h" - -#elif defined (__MSP430G2001__) -#include "msp430g2001.h" - -#elif defined (__MSP430G2231__) -#include "msp430g2231.h" - -#elif defined (__MSP430G2221__) -#include "msp430g2221.h" - -#elif defined (__MSP430G2131__) -#include "msp430g2131.h" - -#elif defined (__MSP430G2121__) -#include "msp430g2121.h" - -#elif defined (__MSP430AFE221__) -#include "msp430afe221.h" - -#elif defined (__MSP430AFE231__) -#include "msp430afe231.h" - -#elif defined (__MSP430AFE251__) -#include "msp430afe251.h" - -#elif defined (__MSP430AFE222__) -#include "msp430afe222.h" - -#elif defined (__MSP430AFE232__) -#include "msp430afe232.h" - -#elif defined (__MSP430AFE252__) -#include "msp430afe252.h" - -#elif defined (__MSP430AFE223__) -#include "msp430afe223.h" - -#elif defined (__MSP430AFE233__) -#include "msp430afe233.h" - -#elif defined (__MSP430AFE253__) -#include "msp430afe253.h" - -#elif defined (__MSP430G2102__) -#include "msp430g2102.h" - -#elif defined (__MSP430G2202__) -#include "msp430g2202.h" - -#elif defined (__MSP430G2302__) -#include "msp430g2302.h" - -#elif defined (__MSP430G2402__) -#include "msp430g2402.h" - -#elif defined (__MSP430G2132__) -#include "msp430g2132.h" - -#elif defined (__MSP430G2232__) -#include "msp430g2232.h" - -#elif defined (__MSP430G2332__) -#include "msp430g2332.h" - -#elif defined (__MSP430G2432__) -#include "msp430g2432.h" - -#elif defined (__MSP430G2112__) -#include "msp430g2112.h" - -#elif defined (__MSP430G2212__) -#include "msp430g2212.h" - -#elif defined (__MSP430G2312__) -#include "msp430g2312.h" - -#elif defined (__MSP430G2412__) -#include "msp430g2412.h" - -#elif defined (__MSP430G2152__) -#include "msp430g2152.h" - -#elif defined (__MSP430G2252__) -#include "msp430g2252.h" - -#elif defined (__MSP430G2352__) -#include "msp430g2352.h" - -#elif defined (__MSP430G2452__) -#include "msp430g2452.h" - -#elif defined (__MSP430G2113__) -#include "msp430g2113.h" - -#elif defined (__MSP430G2213__) -#include "msp430g2213.h" - -#elif defined (__MSP430G2313__) -#include "msp430g2313.h" - -#elif defined (__MSP430G2413__) -#include "msp430g2413.h" - -#elif defined (__MSP430G2513__) -#include "msp430g2513.h" - -#elif defined (__MSP430G2153__) -#include "msp430g2153.h" - -#elif defined (__MSP430G2253__) -#include "msp430g2253.h" - -#elif defined (__MSP430G2353__) -#include "msp430g2353.h" - -#elif defined (__MSP430G2453__) -#include "msp430g2453.h" - -#elif defined (__MSP430G2553__) -#include "msp430g2553.h" - -#elif defined (__MSP430G2203__) -#include "msp430g2203.h" - -#elif defined (__MSP430G2303__) -#include "msp430g2303.h" - -#elif defined (__MSP430G2403__) -#include "msp430g2403.h" - -#elif defined (__MSP430G2233__) -#include "msp430g2233.h" - -#elif defined (__MSP430G2333__) -#include "msp430g2333.h" - -#elif defined (__MSP430G2433__) -#include "msp430g2433.h" - -#elif defined (__MSP430G2533__) -#include "msp430g2533.h" - -#elif defined (__MSP430TCH5E__) -#include "msp430tch5e.h" - -#elif defined (__MSP430G2444__) -#include "msp430g2444.h" - -#elif defined (__MSP430G2544__) -#include "msp430g2544.h" - -#elif defined (__MSP430G2744__) -#include "msp430g2744.h" - -#elif defined (__MSP430G2755__) -#include "msp430g2755.h" - -#elif defined (__MSP430G2855__) -#include "msp430g2855.h" - -#elif defined (__MSP430G2955__) -#include "msp430g2955.h" - -#elif defined (__MSP430G2230__) -#include "msp430g2230.h" - -#elif defined (__MSP430G2210__) -#include "msp430g2210.h" - -#elif defined (__MSP430BT5190__) -#include "msp430bt5190.h" - -#elif defined (__MSP430FR5857__) -#include "msp430fr5857.h" - -#elif defined (__MSP430FR5858__) -#include "msp430fr5858.h" - -#elif defined (__MSP430FR5859__) -#include "msp430fr5859.h" - -#elif defined (__MSP430FR5847__) -#include "msp430fr5847.h" - -#elif defined (__MSP430FR58471__) -#include "msp430fr58471.h" - -#elif defined (__MSP430FR5848__) -#include "msp430fr5848.h" - -#elif defined (__MSP430FR5849__) -#include "msp430fr5849.h" - -#elif defined (__MSP430FR5867__) -#include "msp430fr5867.h" - -#elif defined (__MSP430FR58671__) -#include "msp430fr58671.h" - -#elif defined (__MSP430FR5868__) -#include "msp430fr5868.h" - -#elif defined (__MSP430FR5869__) -#include "msp430fr5869.h" - -#elif defined (__MSP430FR5957__) -#include "msp430fr5957.h" - -#elif defined (__MSP430FR5958__) -#include "msp430fr5958.h" - -#elif defined (__MSP430FR5959__) -#include "msp430fr5959.h" - -#elif defined (__MSP430FR5947__) -#include "msp430fr5947.h" - -#elif defined (__MSP430FR59471__) -#include "msp430fr59471.h" - -#elif defined (__MSP430FR5948__) -#include "msp430fr5948.h" - -#elif defined (__MSP430FR5949__) -#include "msp430fr5949.h" - -#elif defined (__MSP430FR5967__) -#include "msp430fr5967.h" - -#elif defined (__MSP430FR5968__) -#include "msp430fr5968.h" - -#elif defined (__MSP430FR5969__) -#include "msp430fr5969.h" - -#elif defined (__MSP430FR59691__) -#include "msp430fr59691.h" - -#elif defined (__MSP430FR5962__) -#include "msp430fr5962.h" - -#elif defined (__MSP430FR5964__) -#include "msp430fr5964.h" - -#elif defined (__MSP430FR5992__) -#include "msp430fr5992.h" - -#elif defined (__MSP430FR5994__) -#include "msp430fr5994.h" - -#elif defined (__MSP430FR59941__) -#include "msp430fr59941.h" - -#elif defined (__MSP430i2020__) -#include "msp430i2020.h" - -#elif defined (__MSP430i2021__) -#include "msp430i2021.h" - -#elif defined (__MSP430i2030__) -#include "msp430i2030.h" - -#elif defined (__MSP430i2031__) -#include "msp430i2031.h" - -#elif defined (__MSP430i2040__) -#include "msp430i2040.h" - -#elif defined (__MSP430i2041__) -#include "msp430i2041.h" - -#elif defined (__RF430FRL152H__) -#include "rf430frl152h.h" - -#elif defined (__RF430FRL153H__) -#include "rf430frl153h.h" - -#elif defined (__RF430FRL154H__) -#include "rf430frl154h.h" - -#elif defined (__RF430FRL152H_ROM__) -#include "rf430frl152h_rom.h" - -#elif defined (__RF430FRL153H_ROM__) -#include "rf430frl153h_rom.h" - -#elif defined (__RF430FRL154H_ROM__) -#include "rf430frl154h_rom.h" - -#elif defined (__RF430F5175__) -#include "rf430f5175.h" - -#elif defined (__RF430F5155__) -#include "rf430f5155.h" - -#elif defined (__RF430F5144__) -#include "rf430f5144.h" - -#elif defined (__MSP430FR69271__) -#include "msp430fr69271.h" - -#elif defined (__MSP430FR68791__) -#include "msp430fr68791.h" - -#elif defined (__MSP430FR69791__) -#include "msp430fr69791.h" - -#elif defined (__MSP430FR6927__) -#include "msp430fr6927.h" - -#elif defined (__MSP430FR6928__) -#include "msp430fr6928.h" - -#elif defined (__MSP430FR6877__) -#include "msp430fr6877.h" - -#elif defined (__MSP430FR6977__) -#include "msp430fr6977.h" - -#elif defined (__MSP430FR6879__) -#include "msp430fr6879.h" - -#elif defined (__MSP430FR6979__) -#include "msp430fr6979.h" - -#elif defined (__MSP430FR58891__) -#include "msp430fr58891.h" - -#elif defined (__MSP430FR68891__) -#include "msp430fr68891.h" - -#elif defined (__MSP430FR59891__) -#include "msp430fr59891.h" - -#elif defined (__MSP430FR69891__) -#include "msp430fr69891.h" - -#elif defined (__MSP430FR5887__) -#include "msp430fr5887.h" - -#elif defined (__MSP430FR5888__) -#include "msp430fr5888.h" - -#elif defined (__MSP430FR5889__) -#include "msp430fr5889.h" - -#elif defined (__MSP430FR6887__) -#include "msp430fr6887.h" - -#elif defined (__MSP430FR6888__) -#include "msp430fr6888.h" - -#elif defined (__MSP430FR6889__) -#include "msp430fr6889.h" - -#elif defined (__MSP430FR5986__) -#include "msp430fr5986.h" - -#elif defined (__MSP430FR5987__) -#include "msp430fr5987.h" - -#elif defined (__MSP430FR5988__) -#include "msp430fr5988.h" - -#elif defined (__MSP430FR5989__) -#include "msp430fr5989.h" - -#elif defined (__MSP430FR6987__) -#include "msp430fr6987.h" - -#elif defined (__MSP430FR6988__) -#include "msp430fr6988.h" - -#elif defined (__MSP430FR6989__) -#include "msp430fr6989.h" - -#elif defined (__MSP430FR5922__) -#include "msp430fr5922.h" - -#elif defined (__MSP430FR5870__) -#include "msp430fr5870.h" - -#elif defined (__MSP430FR5970__) -#include "msp430fr5970.h" - -#elif defined (__MSP430FR5872__) -#include "msp430fr5872.h" - -#elif defined (__MSP430FR5972__) -#include "msp430fr5972.h" - -#elif defined (__MSP430FR6820__) -#include "msp430fr6820.h" - -#elif defined (__MSP430FR6920__) -#include "msp430fr6920.h" - -#elif defined (__MSP430FR6822__) -#include "msp430fr6822.h" - -#elif defined (__MSP430FR6922__) -#include "msp430fr6922.h" - -#elif defined (__MSP430FR6870__) -#include "msp430fr6870.h" - -#elif defined (__MSP430FR6970__) -#include "msp430fr6970.h" - -#elif defined (__MSP430FR6872__) -#include "msp430fr6872.h" - -#elif defined (__MSP430FR6972__) -#include "msp430fr6972.h" - -#elif defined (__MSP430FR59221__) -#include "msp430fr59221.h" - -#elif defined (__MSP430FR58721__) -#include "msp430fr58721.h" - -#elif defined (__MSP430FR59721__) -#include "msp430fr59721.h" - -#elif defined (__MSP430FR68221__) -#include "msp430fr68221.h" - -#elif defined (__MSP430FR69221__) -#include "msp430fr69221.h" - -#elif defined (__MSP430FR68721__) -#include "msp430fr68721.h" - -#elif defined (__MSP430FR69721__) -#include "msp430fr69721.h" - -#elif defined (__MSP430SL5438A__) -#include "msp430sl5438a.h" - -#elif defined (__MSP430FR4131__) -#include "msp430fr4131.h" - -#elif defined (__MSP430FR4132__) -#include "msp430fr4132.h" - -#elif defined (__MSP430FR4133__) -#include "msp430fr4133.h" - -#elif defined (__MSP430FR2032__) -#include "msp430fr2032.h" - -#elif defined (__MSP430FR2033__) -#include "msp430fr2033.h" - -#elif defined (__MSP430FR2000__) -#include "msp430fr2000.h" - -#elif defined (__MSP430FR2100__) -#include "msp430fr2100.h" - -#elif defined (__MSP430FR2110__) -#include "msp430fr2110.h" - -#elif defined (__MSP430FR2111__) -#include "msp430fr2111.h" - -#elif defined (__MSP430FR2310__) -#include "msp430fr2310.h" - -#elif defined (__MSP430FR2311__) -#include "msp430fr2311.h" - -#elif defined (__MSP430FR2422__) -#include "msp430fr2422.h" - -#elif defined (__MSP430FR2433__) -#include "msp430fr2433.h" - -#elif defined (__MSP430FR2512__) -#include "msp430fr2512.h" - -#elif defined (__MSP430FR2522__) -#include "msp430fr2522.h" - -#elif defined (__MSP430FR2532__) -#include "msp430fr2532.h" - -#elif defined (__MSP430FR2533__) -#include "msp430fr2533.h" - -#elif defined (__MSP430FR2632__) -#include "msp430fr2632.h" - -#elif defined (__MSP430FR2633__) -#include "msp430fr2633.h" - -#elif defined (__MSP430F5252__) -#include "msp430f5252.h" - -#elif defined (__MSP430F5253__) -#include "msp430f5253.h" - -#elif defined (__MSP430F5254__) -#include "msp430f5254.h" - -#elif defined (__MSP430F5255__) -#include "msp430f5255.h" - -#elif defined (__MSP430F5256__) -#include "msp430f5256.h" - -#elif defined (__MSP430F5257__) -#include "msp430f5257.h" - -#elif defined (__MSP430F5258__) -#include "msp430f5258.h" - -#elif defined (__MSP430F5259__) -#include "msp430f5259.h" - -#elif defined (__MSP430FR6035__) -#include "msp430fr6035.h" - -#elif defined (__MSP430FR6037__) -#include "msp430fr6037.h" - -#elif defined (__MSP430FR60371__) -#include "msp430fr60371.h" - -#elif defined (__MSP430FR6045__) -#include "msp430fr6045.h" - -#elif defined (__MSP430FR6047__) -#include "msp430fr6047.h" - -#elif defined (__MSP430FR60471__) -#include "msp430fr60471.h" - -#elif defined (__MSP430FR5041__) -#include "msp430fr5041.h" - -#elif defined (__MSP430FR5043__) -#include "msp430fr5043.h" - -#elif defined (__MSP430FR50431__) -#include "msp430fr50431.h" - -#elif defined (__MSP430FR6041__) -#include "msp430fr6041.h" - -#elif defined (__MSP430FR6043__) -#include "msp430fr6043.h" - -#elif defined (__MSP430FR60431__) -#include "msp430fr60431.h" - -#elif defined (__MSP430FR2153__) -#include "msp430fr2153.h" - -#elif defined (__MSP430FR2155__) -#include "msp430fr2155.h" - -#elif defined (__MSP430FR2353__) -#include "msp430fr2353.h" - -#elif defined (__MSP430FR2355__) -#include "msp430fr2355.h" - -#elif defined (__MSP430FR2475__) -#include "msp430fr2475.h" - -#elif defined (__MSP430FR2476__) -#include "msp430fr2476.h" - -#elif defined (__MSP430FR2675__) -#include "msp430fr2675.h" - -#elif defined (__MSP430FR2676__) -#include "msp430fr2676.h" - -#elif defined (__MSP430XGENERIC__) -#include "msp430xgeneric.h" - -#elif defined (__MSP430F5XX_6XXGENERIC__) -#include "msp430f5xx_6xxgeneric.h" - -#elif defined (__MSP430FR5XX_6XXGENERIC__) -#include "msp430fr5xx_6xxgeneric.h" - -#elif defined (__MSP430FR2XX_4XXGENERIC__) -#include "msp430fr2xx_4xxgeneric.h" - -#elif defined (__MSP430FR57XXGENERIC__) -#include "msp430fr57xxgeneric.h" - -#elif defined (__MSP430I2XXGENERIC__) -#include "msp430i2xxgeneric.h" - -/******************************************************************** - * msp430 generic - ********************************************************************/ -#elif defined (__MSP430GENERIC__) -#error "msp430 generic device does not have a default include file" - -#elif defined (__MSP430XGENERIC__) -#error "msp430X generic device does not have a default include file" - - -/******************************************************************** - * - ********************************************************************/ -#else -#error "Failed to match a default include file" -#endif - -#endif /* #ifndef __msp430 */ - diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529.h b/hw/bsp/msp_exp430f5529lp/msp430f5529.h deleted file mode 100644 index e7e5d31fa..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430f5529.h +++ /dev/null @@ -1,4789 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2019, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/******************************************************************** -* -* Standard register and bit definitions for the Texas Instruments -* MSP430 microcontroller. -* -* This file supports assembler and C development for -* MSP430F5529 devices. -* -* Texas Instruments, Version 1.4 -* -* Rev. 1.0, Setup -* Rev. 1.1, Fixed Error in DMA Trigger Definitons -* Rev. 1.2, fixed SYSUNIV_BUSIFG definition -* fixed wrong bit definition in PM5CTL0 (LOCKLPM5) -* Rev. 1.3, Changed access type of DMAxSZ registers to word only -* Rev. 1.4 Changed access type of TimerA/B registers to word only -* -********************************************************************/ - -#ifndef __MSP430F5529 -#define __MSP430F5529 - -#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ -#define __MSP430F5XX_6XX_FAMILY__ - -#define __MSP430_HEADER_VERSION__ 1207 - -#ifdef __cplusplus -extern "C" { -#endif - - -/*----------------------------------------------------------------------------*/ -/* PERIPHERAL FILE MAP */ -/*----------------------------------------------------------------------------*/ - -#define __MSP430_TI_HEADERS__ - -#include - - -/************************************************************ -* STANDARD BITS -************************************************************/ - -#define BIT0 (0x0001) -#define BIT1 (0x0002) -#define BIT2 (0x0004) -#define BIT3 (0x0008) -#define BIT4 (0x0010) -#define BIT5 (0x0020) -#define BIT6 (0x0040) -#define BIT7 (0x0080) -#define BIT8 (0x0100) -#define BIT9 (0x0200) -#define BITA (0x0400) -#define BITB (0x0800) -#define BITC (0x1000) -#define BITD (0x2000) -#define BITE (0x4000) -#define BITF (0x8000) - -/************************************************************ -* STATUS REGISTER BITS -************************************************************/ - -#define C (0x0001) -#define Z (0x0002) -#define N (0x0004) -#define V (0x0100) -#define GIE (0x0008) -#define CPUOFF (0x0010) -#define OSCOFF (0x0020) -#define SCG0 (0x0040) -#define SCG1 (0x0080) - -/* Low Power Modes coded with Bits 4-7 in SR */ - -#ifndef __STDC__ /* Begin #defines for assembler */ -#define LPM0 (CPUOFF) -#define LPM1 (SCG0+CPUOFF) -#define LPM2 (SCG1+CPUOFF) -#define LPM3 (SCG1+SCG0+CPUOFF) -#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) -/* End #defines for assembler */ - -#else /* Begin #defines for C */ -#define LPM0_bits (CPUOFF) -#define LPM1_bits (SCG0+CPUOFF) -#define LPM2_bits (SCG1+CPUOFF) -#define LPM3_bits (SCG1+SCG0+CPUOFF) -#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) - -#include "in430.h" - -#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ -#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ -#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ -#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ -#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ -#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ -#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ -#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ -#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ -#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ -#endif /* End #defines for C */ - -/************************************************************ -* PERIPHERAL FILE MAP -************************************************************/ - -/************************************************************ -* ADC12 PLUS -************************************************************/ -#define __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_ADC12_PLUS__ 0x0700 -#define ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__ - -sfr_w(ADC12CTL0); /* ADC12+ Control 0 */ -sfr_b(ADC12CTL0_L); /* ADC12+ Control 0 */ -sfr_b(ADC12CTL0_H); /* ADC12+ Control 0 */ -sfr_w(ADC12CTL1); /* ADC12+ Control 1 */ -sfr_b(ADC12CTL1_L); /* ADC12+ Control 1 */ -sfr_b(ADC12CTL1_H); /* ADC12+ Control 1 */ -sfr_w(ADC12CTL2); /* ADC12+ Control 2 */ -sfr_b(ADC12CTL2_L); /* ADC12+ Control 2 */ -sfr_b(ADC12CTL2_H); /* ADC12+ Control 2 */ -sfr_w(ADC12IFG); /* ADC12+ Interrupt Flag */ -sfr_b(ADC12IFG_L); /* ADC12+ Interrupt Flag */ -sfr_b(ADC12IFG_H); /* ADC12+ Interrupt Flag */ -sfr_w(ADC12IE); /* ADC12+ Interrupt Enable */ -sfr_b(ADC12IE_L); /* ADC12+ Interrupt Enable */ -sfr_b(ADC12IE_H); /* ADC12+ Interrupt Enable */ -sfr_w(ADC12IV); /* ADC12+ Interrupt Vector Word */ -sfr_b(ADC12IV_L); /* ADC12+ Interrupt Vector Word */ -sfr_b(ADC12IV_H); /* ADC12+ Interrupt Vector Word */ - -sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ -sfr_b(ADC12MEM0_L); /* ADC12 Conversion Memory 0 */ -sfr_b(ADC12MEM0_H); /* ADC12 Conversion Memory 0 */ -sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ -sfr_b(ADC12MEM1_L); /* ADC12 Conversion Memory 1 */ -sfr_b(ADC12MEM1_H); /* ADC12 Conversion Memory 1 */ -sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ -sfr_b(ADC12MEM2_L); /* ADC12 Conversion Memory 2 */ -sfr_b(ADC12MEM2_H); /* ADC12 Conversion Memory 2 */ -sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ -sfr_b(ADC12MEM3_L); /* ADC12 Conversion Memory 3 */ -sfr_b(ADC12MEM3_H); /* ADC12 Conversion Memory 3 */ -sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ -sfr_b(ADC12MEM4_L); /* ADC12 Conversion Memory 4 */ -sfr_b(ADC12MEM4_H); /* ADC12 Conversion Memory 4 */ -sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ -sfr_b(ADC12MEM5_L); /* ADC12 Conversion Memory 5 */ -sfr_b(ADC12MEM5_H); /* ADC12 Conversion Memory 5 */ -sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ -sfr_b(ADC12MEM6_L); /* ADC12 Conversion Memory 6 */ -sfr_b(ADC12MEM6_H); /* ADC12 Conversion Memory 6 */ -sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ -sfr_b(ADC12MEM7_L); /* ADC12 Conversion Memory 7 */ -sfr_b(ADC12MEM7_H); /* ADC12 Conversion Memory 7 */ -sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ -sfr_b(ADC12MEM8_L); /* ADC12 Conversion Memory 8 */ -sfr_b(ADC12MEM8_H); /* ADC12 Conversion Memory 8 */ -sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ -sfr_b(ADC12MEM9_L); /* ADC12 Conversion Memory 9 */ -sfr_b(ADC12MEM9_H); /* ADC12 Conversion Memory 9 */ -sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ -sfr_b(ADC12MEM10_L); /* ADC12 Conversion Memory 10 */ -sfr_b(ADC12MEM10_H); /* ADC12 Conversion Memory 10 */ -sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ -sfr_b(ADC12MEM11_L); /* ADC12 Conversion Memory 11 */ -sfr_b(ADC12MEM11_H); /* ADC12 Conversion Memory 11 */ -sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ -sfr_b(ADC12MEM12_L); /* ADC12 Conversion Memory 12 */ -sfr_b(ADC12MEM12_H); /* ADC12 Conversion Memory 12 */ -sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ -sfr_b(ADC12MEM13_L); /* ADC12 Conversion Memory 13 */ -sfr_b(ADC12MEM13_H); /* ADC12 Conversion Memory 13 */ -sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ -sfr_b(ADC12MEM14_L); /* ADC12 Conversion Memory 14 */ -sfr_b(ADC12MEM14_H); /* ADC12 Conversion Memory 14 */ -sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ -sfr_b(ADC12MEM15_L); /* ADC12 Conversion Memory 15 */ -sfr_b(ADC12MEM15_H); /* ADC12 Conversion Memory 15 */ -#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ -#ifndef __STDC__ -#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ -#else -#define ADC12MEM ((volatile int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ -#endif - -sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ -sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ -sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ -sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ -sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ -sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ -sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ -sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ -sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ -sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ -sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ -sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ -sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ -sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ -sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ -sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ -#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ -#ifndef __STDC__ -#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ -#else -#define ADC12MCTL ((volatile char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ -#endif - -/* ADC12CTL0 Control Bits */ -#define ADC12SC (0x0001) /* ADC12 Start Conversion */ -#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ -#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */ -#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */ -#define ADC12ON (0x0010) /* ADC12 On/enable */ -#define ADC12REFON (0x0020) /* ADC12 Reference on */ -#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ -#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ -#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ -#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ -#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ -#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ -#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ -#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ -#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ -#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ - -/* ADC12CTL0 Control Bits */ -#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ -#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ -#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */ -#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */ -#define ADC12ON_L (0x0010) /* ADC12 On/enable */ -#define ADC12REFON_L (0x0020) /* ADC12 Reference on */ -#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ -#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ - -/* ADC12CTL0 Control Bits */ -#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ -#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ -#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ -#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ -#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ -#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ -#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ -#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ - -#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ -#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ -#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ -#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ -#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ -#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ -#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ -#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ -#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ -#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ -#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ -#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ -#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ -#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ -#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ -#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ - -#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ -#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ -#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ -#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ -#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ -#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ -#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ -#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ -#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ -#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ -#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ -#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ -#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ -#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ -#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ -#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ - -/* ADC12CTL1 Control Bits */ -#define ADC12BUSY (0x0001) /* ADC12 Busy */ -#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ -#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ -#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ -#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ -#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ -#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ -#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ -#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ -#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ -#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ -#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ -#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */ -#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */ -#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */ -#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */ - -/* ADC12CTL1 Control Bits */ -#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ -#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ -#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ -#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ -#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ -#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ -#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ -#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ - -/* ADC12CTL1 Control Bits */ -#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ -#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ -#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ -#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ -#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */ -#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */ -#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */ -#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */ - -#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ -#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ -#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ -#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ - -#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ -#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ -#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ -#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ - -#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ -#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ -#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ -#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ -#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ -#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ -#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ -#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ - -#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ -#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ -#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ -#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ - -#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ -#define ADC12CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ -#define ADC12CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ -#define ADC12CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ -#define ADC12CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ -#define ADC12CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ -#define ADC12CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ -#define ADC12CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ -#define ADC12CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ -#define ADC12CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ -#define ADC12CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ -#define ADC12CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ -#define ADC12CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ -#define ADC12CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ -#define ADC12CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ -#define ADC12CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ - -/* ADC12CTL2 Control Bits */ -#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */ -#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */ -#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */ -#define ADC12DF (0x0008) /* ADC12+ Data Format */ -#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */ -#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */ -#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */ -#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */ - -/* ADC12CTL2 Control Bits */ -#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */ -#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */ -#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */ -#define ADC12DF_L (0x0008) /* ADC12+ Data Format */ -#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */ -#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */ -#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */ - -/* ADC12CTL2 Control Bits */ -#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */ - -#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ -#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ -#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ -#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ - -/* ADC12MCTLx Control Bits */ -#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ -#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ -#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ -#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ -#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ -#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ -#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ -#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ - -#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ -#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ -#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ -#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ -#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ -#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ -#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ -#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ -#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ -#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ -#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ -#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ -#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ -#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ -#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ -#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ - -#define ADC12SREF_0 (0x0000) /* ADC12 Select Reference 0 */ -#define ADC12SREF_1 (0x0010) /* ADC12 Select Reference 1 */ -#define ADC12SREF_2 (0x0020) /* ADC12 Select Reference 2 */ -#define ADC12SREF_3 (0x0030) /* ADC12 Select Reference 3 */ -#define ADC12SREF_4 (0x0040) /* ADC12 Select Reference 4 */ -#define ADC12SREF_5 (0x0050) /* ADC12 Select Reference 5 */ -#define ADC12SREF_6 (0x0060) /* ADC12 Select Reference 6 */ -#define ADC12SREF_7 (0x0070) /* ADC12 Select Reference 7 */ - -#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ -#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ -#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ -#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ -#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ -#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ -#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ -#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ -#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ -#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ -#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ -#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ -#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ -#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ -#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ -#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ - -#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ -#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ -#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ -#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ -#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ -#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ -#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ -#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ - -#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ -#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ -#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ -#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ -#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ -#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ -#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ -#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ - -#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ -#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ -#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ -#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ -#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ -#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ -#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ -#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ -#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ -#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ -#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ -#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ -#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ -#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ -#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ -#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ - -#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ -#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ -#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ -#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ -#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ -#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ -#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ -#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ - -#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ -#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ -#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ -#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ -#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ -#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ -#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ -#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ - -/* ADC12IV Definitions */ -#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ -#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ -#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ -#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ -#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ -#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ -#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ -#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ -#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ -#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ -#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ -#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ -#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ -#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ -#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ -#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ -#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ -#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ -#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ - -/************************************************************ -* Comparator B -************************************************************/ -#define __MSP430_HAS_COMPB__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_COMPB__ 0x08C0 -#define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ - -sfr_w(CBCTL0); /* Comparator B Control Register 0 */ -sfr_b(CBCTL0_L); /* Comparator B Control Register 0 */ -sfr_b(CBCTL0_H); /* Comparator B Control Register 0 */ -sfr_w(CBCTL1); /* Comparator B Control Register 1 */ -sfr_b(CBCTL1_L); /* Comparator B Control Register 1 */ -sfr_b(CBCTL1_H); /* Comparator B Control Register 1 */ -sfr_w(CBCTL2); /* Comparator B Control Register 2 */ -sfr_b(CBCTL2_L); /* Comparator B Control Register 2 */ -sfr_b(CBCTL2_H); /* Comparator B Control Register 2 */ -sfr_w(CBCTL3); /* Comparator B Control Register 3 */ -sfr_b(CBCTL3_L); /* Comparator B Control Register 3 */ -sfr_b(CBCTL3_H); /* Comparator B Control Register 3 */ -sfr_w(CBINT); /* Comparator B Interrupt Register */ -sfr_b(CBINT_L); /* Comparator B Interrupt Register */ -sfr_b(CBINT_H); /* Comparator B Interrupt Register */ -sfr_w(CBIV); /* Comparator B Interrupt Vector Word */ - -/* CBCTL0 Control Bits */ -#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */ -#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */ -#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */ -#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */ -#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */ -#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */ -#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */ -#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */ - -/* CBCTL0 Control Bits */ -#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */ -#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */ -#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */ -#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ - -/* CBCTL0 Control Bits */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */ -#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */ -#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */ -#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */ - -#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */ -#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */ -#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */ -#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */ -#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */ -#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */ -#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */ -#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */ -#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */ -#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */ -#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */ -#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */ -#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */ -#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */ -#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */ -#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */ - -#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */ -#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */ -#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */ -#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */ -#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */ -#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */ -#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */ -#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */ -#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */ -#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */ -#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */ -#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */ -#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */ -#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */ -#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */ -#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */ - -/* CBCTL1 Control Bits */ -#define CBOUT (0x0001) /* Comp. B Output */ -#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */ -#define CBF (0x0004) /* Comp. B Enable Output Filter */ -#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */ -#define CBSHORT (0x0010) /* Comp. B Input Short */ -#define CBEX (0x0020) /* Comp. B Exchange Inputs */ -#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */ -#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */ -#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */ -#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */ -#define CBON (0x0400) /* Comp. B enable */ -#define CBMRVL (0x0800) /* Comp. B CBMRV Level */ -#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBCTL1 Control Bits */ -#define CBOUT_L (0x0001) /* Comp. B Output */ -#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */ -#define CBF_L (0x0004) /* Comp. B Enable Output Filter */ -#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */ -#define CBSHORT_L (0x0010) /* Comp. B Input Short */ -#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */ -#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */ -#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBCTL1 Control Bits */ -#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */ -#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */ -#define CBON_H (0x0004) /* Comp. B enable */ -#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */ -#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */ -#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */ -#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */ -#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */ - -#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */ -#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */ -#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/ -#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */ - -/* CBCTL2 Control Bits */ -#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ -#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ -#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ -#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ -#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ -#define CBRSEL (0x0020) /* Comp. B Reference select */ -#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */ -#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */ -#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */ -#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */ -#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */ -#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */ -#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */ -#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */ -#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */ -#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */ - -/* CBCTL2 Control Bits */ -#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ -#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ -#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ -#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ -#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ -#define CBRSEL_L (0x0020) /* Comp. B Reference select */ -#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */ -#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */ - -/* CBCTL2 Control Bits */ -#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */ -#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */ -#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */ -#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */ -#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */ -#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */ -#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */ -#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */ - -#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ -#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ -#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ -#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ -#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ -#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ -#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ -#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ -#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ -#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ -#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ -#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ -#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ -#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ -#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ -#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ -#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ -#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ -#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ -#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ -#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ -#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ -#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ -#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ -#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ -#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ -#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ -#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ -#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ -#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ -#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ -#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ - -#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */ -#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */ -#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */ -#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */ - -#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ -#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ -#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ -#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ -#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ -#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ -#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ -#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ -#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ -#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ -#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ -#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ -#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ -#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ -#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ -#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ -#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ -#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ -#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ -#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ -#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ -#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ -#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ -#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ -#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ -#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ -#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ -#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ -#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ -#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ -#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ -#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ - -#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */ -#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */ -#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */ -#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */ - -#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ -#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ -#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ -#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ -#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ -#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ -#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ -#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ -#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */ -#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */ -#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */ -#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */ -#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */ -#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */ -#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */ -#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */ - -#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ -#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ -#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ -#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ -#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ -#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ -#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ -#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ - -#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */ -#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */ -#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */ -#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */ -#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */ -#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */ -#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */ -#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */ - -/* CBINT Control Bits */ -#define CBIFG (0x0001) /* Comp. B Interrupt Flag */ -#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ -//#define RESERVED (0x0004) /* Comp. B */ -//#define RESERVED (0x0008) /* Comp. B */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -//#define RESERVED (0x0080) /* Comp. B */ -#define CBIE (0x0100) /* Comp. B Interrupt Enable */ -#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */ -//#define RESERVED (0x0400) /* Comp. B */ -//#define RESERVED (0x0800) /* Comp. B */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBINT Control Bits */ -#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */ -#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ -//#define RESERVED (0x0004) /* Comp. B */ -//#define RESERVED (0x0008) /* Comp. B */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -//#define RESERVED (0x0080) /* Comp. B */ -//#define RESERVED (0x0400) /* Comp. B */ -//#define RESERVED (0x0800) /* Comp. B */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBINT Control Bits */ -//#define RESERVED (0x0004) /* Comp. B */ -//#define RESERVED (0x0008) /* Comp. B */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -//#define RESERVED (0x0080) /* Comp. B */ -#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */ -#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */ -//#define RESERVED (0x0400) /* Comp. B */ -//#define RESERVED (0x0800) /* Comp. B */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBIV Definitions */ -#define CBIV_NONE (0x0000) /* No Interrupt pending */ -#define CBIV_CBIFG (0x0002) /* CBIFG */ -#define CBIV_CBIIFG (0x0004) /* CBIIFG */ - -/************************************************************* -* CRC Module -*************************************************************/ -#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_CRC__ 0x0150 -#define CRC_BASE __MSP430_BASEADDRESS_CRC__ - -sfr_w(CRCDI); /* CRC Data In Register */ -sfr_b(CRCDI_L); /* CRC Data In Register */ -sfr_b(CRCDI_H); /* CRC Data In Register */ -sfr_w(CRCDIRB); /* CRC data in reverse byte Register */ -sfr_b(CRCDIRB_L); /* CRC data in reverse byte Register */ -sfr_b(CRCDIRB_H); /* CRC data in reverse byte Register */ -sfr_w(CRCINIRES); /* CRC Initialisation Register and Result Register */ -sfr_b(CRCINIRES_L); /* CRC Initialisation Register and Result Register */ -sfr_b(CRCINIRES_H); /* CRC Initialisation Register and Result Register */ -sfr_w(CRCRESR); /* CRC reverse result Register */ -sfr_b(CRCRESR_L); /* CRC reverse result Register */ -sfr_b(CRCRESR_H); /* CRC reverse result Register */ - -/************************************************************ -* DMA_X -************************************************************/ -#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500 -#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ - -sfr_w(DMACTL0); /* DMA Module Control 0 */ -sfr_w(DMACTL1); /* DMA Module Control 1 */ -sfr_w(DMACTL2); /* DMA Module Control 2 */ -sfr_w(DMACTL3); /* DMA Module Control 3 */ -sfr_w(DMACTL4); /* DMA Module Control 4 */ -sfr_w(DMAIV); /* DMA Interrupt Vector Word */ - -sfr_w(DMA0CTL); /* DMA Channel 0 Control */ -sfr_l(DMA0SA); /* DMA Channel 0 Source Address */ -sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */ -sfr_w(DMA0SAH); /* DMA Channel 0 Source Address */ -sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */ -sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */ -sfr_w(DMA0DAH); /* DMA Channel 0 Destination Address */ -sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ - -sfr_w(DMA1CTL); /* DMA Channel 1 Control */ -sfr_l(DMA1SA); /* DMA Channel 1 Source Address */ -sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */ -sfr_w(DMA1SAH); /* DMA Channel 1 Source Address */ -sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */ -sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */ -sfr_w(DMA1DAH); /* DMA Channel 1 Destination Address */ -sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ - -sfr_w(DMA2CTL); /* DMA Channel 2 Control */ -sfr_l(DMA2SA); /* DMA Channel 2 Source Address */ -sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */ -sfr_w(DMA2SAH); /* DMA Channel 2 Source Address */ -sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */ -sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */ -sfr_w(DMA2DAH); /* DMA Channel 2 Destination Address */ -sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ - -/* DMACTL0 Control Bits */ -#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ -#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ -#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ -#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ -#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ -#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ -#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ -#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ -#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ -#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ - -/* DMACTL01 Control Bits */ -#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ -#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ -#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ -#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ -#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ - -/* DMACTL4 Control Bits */ -#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ -#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ -#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ - -/* DMAxCTL Control Bits */ -#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ -#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ -#define DMAIE (0x0004) /* DMA interrupt enable */ -#define DMAIFG (0x0008) /* DMA interrupt flag */ -#define DMAEN (0x0010) /* DMA enable */ -#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ -#define DMASRCBYTE (0x0040) /* DMA source byte */ -#define DMADSTBYTE (0x0080) /* DMA destination byte */ -#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ -#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ -#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ -#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ -#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ -#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ -#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ - -#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ -#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ -#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ -#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ - -#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ -#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ -#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ -#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ - -#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ -#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ -#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ -#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ - -#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */ -#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */ -#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */ -#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */ -#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */ -#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */ -#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */ -#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */ - -/* DMAIV Definitions */ -#define DMAIV_NONE (0x0000) /* No Interrupt pending */ -#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ -#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ -#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ - -#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ -#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ -#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ -#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ -#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ -#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ -#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ -#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ -#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ -#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ -#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ -#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ -#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ -#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ -#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ -#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ -#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ -#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ -#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ -#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ -#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: USB ready */ -#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ -#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ -#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ -#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ -#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ -#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ -#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ -#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ -#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ -#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ -#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ -#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ -#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ -#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ -#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ -#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ -#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ -#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ -#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ -#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ -#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ -#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ -#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ -#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ -#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ -#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ -#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ -#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ -#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ -#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ -#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ -#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ -#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ -#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ -#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ -#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ -#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ -#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ -#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ -#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ -#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ -#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ -#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ -#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ -#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ -#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: USB ready */ -#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ -#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ -#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA0TSEL__DMA_REQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ -#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA0TSEL__TA2CCR2 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ -#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ -#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ -#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ -#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ -#define DMA0TSEL__RES14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ -#define DMA0TSEL__RES15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ -#define DMA0TSEL__USCIA0RX (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ -#define DMA0TSEL__USCIA0TX (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ -#define DMA0TSEL__USCIB0RX (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ -#define DMA0TSEL__USCIB0TX (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ -#define DMA0TSEL__USCIA1RX (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ -#define DMA0TSEL__USCIA1TX (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ -#define DMA0TSEL__USCIB1RX (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ -#define DMA0TSEL__USCIB1TX (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ -#define DMA0TSEL__ADC12IFG (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ -#define DMA0TSEL__RES25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ -#define DMA0TSEL__RES26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ -#define DMA0TSEL__USB_FNRXD (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ -#define DMA0TSEL__USB_READY (0x001C) /* DMA channel 0 transfer select 28: USB ready */ -#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ -#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ -#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA1TSEL__DMA_REQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ -#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA1TSEL__TA2CCR2 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ -#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ -#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ -#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ -#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ -#define DMA1TSEL__RES14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ -#define DMA1TSEL__RES15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ -#define DMA1TSEL__USCIA0RX (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ -#define DMA1TSEL__USCIA0TX (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ -#define DMA1TSEL__USCIB0RX (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ -#define DMA1TSEL__USCIB0TX (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ -#define DMA1TSEL__USCIA1RX (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ -#define DMA1TSEL__USCIA1TX (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ -#define DMA1TSEL__USCIB1RX (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ -#define DMA1TSEL__USCIB1TX (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ -#define DMA1TSEL__ADC12IFG (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ -#define DMA1TSEL__RES25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ -#define DMA1TSEL__RES26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ -#define DMA1TSEL__USB_FNRXD (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ -#define DMA1TSEL__USB_READY (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ -#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ -#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ -#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA2TSEL__DMA_REQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ -#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA2TSEL__TA2CCR2 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ -#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ -#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ -#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ -#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ -#define DMA2TSEL__RES14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ -#define DMA2TSEL__RES15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ -#define DMA2TSEL__USCIA0RX (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ -#define DMA2TSEL__USCIA0TX (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ -#define DMA2TSEL__USCIB0RX (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ -#define DMA2TSEL__USCIB0TX (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ -#define DMA2TSEL__USCIA1RX (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ -#define DMA2TSEL__USCIA1TX (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ -#define DMA2TSEL__USCIB1RX (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ -#define DMA2TSEL__USCIB1TX (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ -#define DMA2TSEL__ADC12IFG (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ -#define DMA2TSEL__RES25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ -#define DMA2TSEL__RES26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ -#define DMA2TSEL__USB_FNRXD (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ -#define DMA2TSEL__USB_READY (0x001C) /* DMA channel 2 transfer select 28: USB ready */ -#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ -#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ -#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ - -/************************************************************* -* Flash Memory -*************************************************************/ -#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_FLASH__ 0x0140 -#define FLASH_BASE __MSP430_BASEADDRESS_FLASH__ - -sfr_w(FCTL1); /* FLASH Control 1 */ -sfr_b(FCTL1_L); /* FLASH Control 1 */ -sfr_b(FCTL1_H); /* FLASH Control 1 */ -//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */ -sfr_w(FCTL3); /* FLASH Control 3 */ -sfr_b(FCTL3_L); /* FLASH Control 3 */ -sfr_b(FCTL3_H); /* FLASH Control 3 */ -sfr_w(FCTL4); /* FLASH Control 4 */ -sfr_b(FCTL4_L); /* FLASH Control 4 */ -sfr_b(FCTL4_H); /* FLASH Control 4 */ - -#define FRPW (0x9600) /* Flash password returned by read */ -#define FWPW (0xA500) /* Flash password for write */ -#define FXPW (0x3300) /* for use with XOR instruction */ -#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */ -#define FWKEY (0xA500) /* (legacy definition) Flash key for write */ -#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */ - -/* FCTL1 Control Bits */ -//#define RESERVED (0x0001) /* Reserved */ -#define ERASE (0x0002) /* Enable bit for Flash segment erase */ -#define MERAS (0x0004) /* Enable bit for Flash mass erase */ -//#define RESERVED (0x0008) /* Reserved */ -//#define RESERVED (0x0010) /* Reserved */ -#define SWRT (0x0020) /* Smart Write enable */ -#define WRT (0x0040) /* Enable bit for Flash write */ -#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ - -/* FCTL1 Control Bits */ -//#define RESERVED (0x0001) /* Reserved */ -#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */ -#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */ -//#define RESERVED (0x0008) /* Reserved */ -//#define RESERVED (0x0010) /* Reserved */ -#define SWRT_L (0x0020) /* Smart Write enable */ -#define WRT_L (0x0040) /* Enable bit for Flash write */ -#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */ - -/* FCTL3 Control Bits */ -#define BUSY (0x0001) /* Flash busy: 1 */ -#define KEYV (0x0002) /* Flash Key violation flag */ -#define ACCVIFG (0x0004) /* Flash Access violation flag */ -#define WAIT (0x0008) /* Wait flag for segment write */ -#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ -#define EMEX (0x0020) /* Flash Emergency Exit */ -#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ -//#define RESERVED (0x0080) /* Reserved */ - -/* FCTL3 Control Bits */ -#define BUSY_L (0x0001) /* Flash busy: 1 */ -#define KEYV_L (0x0002) /* Flash Key violation flag */ -#define ACCVIFG_L (0x0004) /* Flash Access violation flag */ -#define WAIT_L (0x0008) /* Wait flag for segment write */ -#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ -#define EMEX_L (0x0020) /* Flash Emergency Exit */ -#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ -//#define RESERVED (0x0080) /* Reserved */ - -/* FCTL4 Control Bits */ -#define VPE (0x0001) /* Voltage Changed during Program Error Flag */ -#define MGR0 (0x0010) /* Marginal read 0 mode. */ -#define MGR1 (0x0020) /* Marginal read 1 mode. */ -#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ - -/* FCTL4 Control Bits */ -#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */ -#define MGR0_L (0x0010) /* Marginal read 0 mode. */ -#define MGR1_L (0x0020) /* Marginal read 1 mode. */ -#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ - -/************************************************************ -* HARDWARE MULTIPLIER 32Bit -************************************************************/ -#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_MPY32__ 0x04C0 -#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__ - -sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ -sfr_b(MPY_L); /* Multiply Unsigned/Operand 1 */ -sfr_b(MPY_H); /* Multiply Unsigned/Operand 1 */ -sfr_w(MPYS); /* Multiply Signed/Operand 1 */ -sfr_b(MPYS_L); /* Multiply Signed/Operand 1 */ -sfr_b(MPYS_H); /* Multiply Signed/Operand 1 */ -sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ -sfr_b(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */ -sfr_b(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */ -sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ -sfr_b(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */ -sfr_b(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */ -sfr_w(OP2); /* Operand 2 */ -sfr_b(OP2_L); /* Operand 2 */ -sfr_b(OP2_H); /* Operand 2 */ -sfr_w(RESLO); /* Result Low Word */ -sfr_b(RESLO_L); /* Result Low Word */ -sfr_b(RESLO_H); /* Result Low Word */ -sfr_w(RESHI); /* Result High Word */ -sfr_b(RESHI_L); /* Result High Word */ -sfr_b(RESHI_H); /* Result High Word */ -sfr_w(SUMEXT); /* Sum Extend */ -sfr_b(SUMEXT_L); /* Sum Extend */ -sfr_b(SUMEXT_H); /* Sum Extend */ - -sfr_w(MPY32L); /* 32-bit operand 1 - multiply - low word */ -sfr_b(MPY32L_L); /* 32-bit operand 1 - multiply - low word */ -sfr_b(MPY32L_H); /* 32-bit operand 1 - multiply - low word */ -sfr_w(MPY32H); /* 32-bit operand 1 - multiply - high word */ -sfr_b(MPY32H_L); /* 32-bit operand 1 - multiply - high word */ -sfr_b(MPY32H_H); /* 32-bit operand 1 - multiply - high word */ -sfr_w(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */ -sfr_b(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */ -sfr_b(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */ -sfr_w(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */ -sfr_b(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */ -sfr_b(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */ -sfr_w(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */ -sfr_b(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */ -sfr_b(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */ -sfr_w(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */ -sfr_b(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */ -sfr_b(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */ -sfr_w(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */ -sfr_b(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */ -sfr_b(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */ -sfr_w(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */ -sfr_b(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */ -sfr_b(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */ -sfr_w(OP2L); /* 32-bit operand 2 - low word */ -sfr_b(OP2L_L); /* 32-bit operand 2 - low word */ -sfr_b(OP2L_H); /* 32-bit operand 2 - low word */ -sfr_w(OP2H); /* 32-bit operand 2 - high word */ -sfr_b(OP2H_L); /* 32-bit operand 2 - high word */ -sfr_b(OP2H_H); /* 32-bit operand 2 - high word */ -sfr_w(RES0); /* 32x32-bit result 0 - least significant word */ -sfr_b(RES0_L); /* 32x32-bit result 0 - least significant word */ -sfr_b(RES0_H); /* 32x32-bit result 0 - least significant word */ -sfr_w(RES1); /* 32x32-bit result 1 */ -sfr_b(RES1_L); /* 32x32-bit result 1 */ -sfr_b(RES1_H); /* 32x32-bit result 1 */ -sfr_w(RES2); /* 32x32-bit result 2 */ -sfr_b(RES2_L); /* 32x32-bit result 2 */ -sfr_b(RES2_H); /* 32x32-bit result 2 */ -sfr_w(RES3); /* 32x32-bit result 3 - most significant word */ -sfr_b(RES3_L); /* 32x32-bit result 3 - most significant word */ -sfr_b(RES3_H); /* 32x32-bit result 3 - most significant word */ -sfr_w(MPY32CTL0); /* MPY32 Control Register 0 */ -sfr_b(MPY32CTL0_L); /* MPY32 Control Register 0 */ -sfr_b(MPY32CTL0_H); /* MPY32 Control Register 0 */ - -#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ -#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ -#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ -#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ -#define OP2_B OP2_L /* Operand 2 (Byte Access) */ -#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ -#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ -#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ -#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ -#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ -#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ -#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ -#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ -#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ -#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ - -/* MPY32CTL0 Control Bits */ -#define MPYC (0x0001) /* Carry of the multiplier */ -//#define RESERVED (0x0002) /* Reserved */ -#define MPYFRAC (0x0004) /* Fractional mode */ -#define MPYSAT (0x0008) /* Saturation mode */ -#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ -#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ -#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ -#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ -#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ -#define MPYDLY32 (0x0200) /* Delayed write mode */ - -/* MPY32CTL0 Control Bits */ -#define MPYC_L (0x0001) /* Carry of the multiplier */ -//#define RESERVED (0x0002) /* Reserved */ -#define MPYFRAC_L (0x0004) /* Fractional mode */ -#define MPYSAT_L (0x0008) /* Saturation mode */ -#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ -#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ -#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ -#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ - -/* MPY32CTL0 Control Bits */ -//#define RESERVED (0x0002) /* Reserved */ -#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ -#define MPYDLY32_H (0x0002) /* Delayed write mode */ - -#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ -#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ -#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ -#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ -#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ -#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ -#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ -#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ - -/************************************************************ -* DIGITAL I/O Port1/2 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200 -#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__ -#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200 -#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__ -#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200 -#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__ -#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PASEL__ /* Define for DriverLib */ - -sfr_w(PAIN); /* Port A Input */ -sfr_b(PAIN_L); /* Port A Input */ -sfr_b(PAIN_H); /* Port A Input */ -sfr_w(PAOUT); /* Port A Output */ -sfr_b(PAOUT_L); /* Port A Output */ -sfr_b(PAOUT_H); /* Port A Output */ -sfr_w(PADIR); /* Port A Direction */ -sfr_b(PADIR_L); /* Port A Direction */ -sfr_b(PADIR_H); /* Port A Direction */ -sfr_w(PAREN); /* Port A Resistor Enable */ -sfr_b(PAREN_L); /* Port A Resistor Enable */ -sfr_b(PAREN_H); /* Port A Resistor Enable */ -sfr_w(PADS); /* Port A Drive Strenght */ -sfr_b(PADS_L); /* Port A Drive Strenght */ -sfr_b(PADS_H); /* Port A Drive Strenght */ -sfr_w(PASEL); /* Port A Selection */ -sfr_b(PASEL_L); /* Port A Selection */ -sfr_b(PASEL_H); /* Port A Selection */ -sfr_w(PAIES); /* Port A Interrupt Edge Select */ -sfr_b(PAIES_L); /* Port A Interrupt Edge Select */ -sfr_b(PAIES_H); /* Port A Interrupt Edge Select */ -sfr_w(PAIE); /* Port A Interrupt Enable */ -sfr_b(PAIE_L); /* Port A Interrupt Enable */ -sfr_b(PAIE_H); /* Port A Interrupt Enable */ -sfr_w(PAIFG); /* Port A Interrupt Flag */ -sfr_b(PAIFG_L); /* Port A Interrupt Flag */ -sfr_b(PAIFG_H); /* Port A Interrupt Flag */ - - -sfr_w(P1IV); /* Port 1 Interrupt Vector Word */ -sfr_w(P2IV); /* Port 2 Interrupt Vector Word */ -#define P1IN (PAIN_L) /* Port 1 Input */ -#define P1OUT (PAOUT_L) /* Port 1 Output */ -#define P1DIR (PADIR_L) /* Port 1 Direction */ -#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ -#define P1DS (PADS_L) /* Port 1 Drive Strenght */ -#define P1SEL (PASEL_L) /* Port 1 Selection */ -#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ -#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ -#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ - -//Definitions for P1IV -#define P1IV_NONE (0x0000) /* No Interrupt pending */ -#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ -#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ -#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ -#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ -#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ -#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ -#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ -#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ - -#define P2IN (PAIN_H) /* Port 2 Input */ -#define P2OUT (PAOUT_H) /* Port 2 Output */ -#define P2DIR (PADIR_H) /* Port 2 Direction */ -#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ -#define P2DS (PADS_H) /* Port 2 Drive Strenght */ -#define P2SEL (PASEL_H) /* Port 2 Selection */ -#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ -#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ -#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ - -//Definitions for P2IV -#define P2IV_NONE (0x0000) /* No Interrupt pending */ -#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ -#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ -#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ -#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ -#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ -#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ -#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ -#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ - - -/************************************************************ -* DIGITAL I/O Port3/4 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220 -#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__ -#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220 -#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__ -#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220 -#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__ -#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PBSEL__ /* Define for DriverLib */ - -sfr_w(PBIN); /* Port B Input */ -sfr_b(PBIN_L); /* Port B Input */ -sfr_b(PBIN_H); /* Port B Input */ -sfr_w(PBOUT); /* Port B Output */ -sfr_b(PBOUT_L); /* Port B Output */ -sfr_b(PBOUT_H); /* Port B Output */ -sfr_w(PBDIR); /* Port B Direction */ -sfr_b(PBDIR_L); /* Port B Direction */ -sfr_b(PBDIR_H); /* Port B Direction */ -sfr_w(PBREN); /* Port B Resistor Enable */ -sfr_b(PBREN_L); /* Port B Resistor Enable */ -sfr_b(PBREN_H); /* Port B Resistor Enable */ -sfr_w(PBDS); /* Port B Drive Strenght */ -sfr_b(PBDS_L); /* Port B Drive Strenght */ -sfr_b(PBDS_H); /* Port B Drive Strenght */ -sfr_w(PBSEL); /* Port B Selection */ -sfr_b(PBSEL_L); /* Port B Selection */ -sfr_b(PBSEL_H); /* Port B Selection */ - - -#define P3IN (PBIN_L) /* Port 3 Input */ -#define P3OUT (PBOUT_L) /* Port 3 Output */ -#define P3DIR (PBDIR_L) /* Port 3 Direction */ -#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ -#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ -#define P3SEL (PBSEL_L) /* Port 3 Selection */ - -#define P4IN (PBIN_H) /* Port 4 Input */ -#define P4OUT (PBOUT_H) /* Port 4 Output */ -#define P4DIR (PBDIR_H) /* Port 4 Direction */ -#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ -#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ -#define P4SEL (PBSEL_H) /* Port 4 Selection */ - - -/************************************************************ -* DIGITAL I/O Port5/6 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240 -#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__ -#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240 -#define P6_BASE __MSP430_BASEADDRESS_PORT6_R__ -#define __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240 -#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__ -#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P6SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PCSEL__ /* Define for DriverLib */ - -sfr_w(PCIN); /* Port C Input */ -sfr_b(PCIN_L); /* Port C Input */ -sfr_b(PCIN_H); /* Port C Input */ -sfr_w(PCOUT); /* Port C Output */ -sfr_b(PCOUT_L); /* Port C Output */ -sfr_b(PCOUT_H); /* Port C Output */ -sfr_w(PCDIR); /* Port C Direction */ -sfr_b(PCDIR_L); /* Port C Direction */ -sfr_b(PCDIR_H); /* Port C Direction */ -sfr_w(PCREN); /* Port C Resistor Enable */ -sfr_b(PCREN_L); /* Port C Resistor Enable */ -sfr_b(PCREN_H); /* Port C Resistor Enable */ -sfr_w(PCDS); /* Port C Drive Strenght */ -sfr_b(PCDS_L); /* Port C Drive Strenght */ -sfr_b(PCDS_H); /* Port C Drive Strenght */ -sfr_w(PCSEL); /* Port C Selection */ -sfr_b(PCSEL_L); /* Port C Selection */ -sfr_b(PCSEL_H); /* Port C Selection */ - - -#define P5IN (PCIN_L) /* Port 5 Input */ -#define P5OUT (PCOUT_L) /* Port 5 Output */ -#define P5DIR (PCDIR_L) /* Port 5 Direction */ -#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ -#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ -#define P5SEL (PCSEL_L) /* Port 5 Selection */ - -#define P6IN (PCIN_H) /* Port 6 Input */ -#define P6OUT (PCOUT_H) /* Port 6 Output */ -#define P6DIR (PCDIR_H) /* Port 6 Direction */ -#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ -#define P6DS (PCDS_H) /* Port 6 Drive Strenght */ -#define P6SEL (PCSEL_H) /* Port 6 Selection */ - - -/************************************************************ -* DIGITAL I/O Port7/8 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260 -#define P7_BASE __MSP430_BASEADDRESS_PORT7_R__ -#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260 -#define P8_BASE __MSP430_BASEADDRESS_PORT8_R__ -#define __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260 -#define PD_BASE __MSP430_BASEADDRESS_PORTD_R__ -#define __MSP430_HAS_P7SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P8SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PDSEL__ /* Define for DriverLib */ - -sfr_w(PDIN); /* Port D Input */ -sfr_b(PDIN_L); /* Port D Input */ -sfr_b(PDIN_H); /* Port D Input */ -sfr_w(PDOUT); /* Port D Output */ -sfr_b(PDOUT_L); /* Port D Output */ -sfr_b(PDOUT_H); /* Port D Output */ -sfr_w(PDDIR); /* Port D Direction */ -sfr_b(PDDIR_L); /* Port D Direction */ -sfr_b(PDDIR_H); /* Port D Direction */ -sfr_w(PDREN); /* Port D Resistor Enable */ -sfr_b(PDREN_L); /* Port D Resistor Enable */ -sfr_b(PDREN_H); /* Port D Resistor Enable */ -sfr_w(PDDS); /* Port D Drive Strenght */ -sfr_b(PDDS_L); /* Port D Drive Strenght */ -sfr_b(PDDS_H); /* Port D Drive Strenght */ -sfr_w(PDSEL); /* Port D Selection */ -sfr_b(PDSEL_L); /* Port D Selection */ -sfr_b(PDSEL_H); /* Port D Selection */ - - -#define P7IN (PDIN_L) /* Port 7 Input */ -#define P7OUT (PDOUT_L) /* Port 7 Output */ -#define P7DIR (PDDIR_L) /* Port 7 Direction */ -#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ -#define P7DS (PDDS_L) /* Port 7 Drive Strenght */ -#define P7SEL (PDSEL_L) /* Port 7 Selection */ - -#define P8IN (PDIN_H) /* Port 8 Input */ -#define P8OUT (PDOUT_H) /* Port 8 Output */ -#define P8DIR (PDDIR_H) /* Port 8 Direction */ -#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ -#define P8DS (PDDS_H) /* Port 8 Drive Strenght */ -#define P8SEL (PDSEL_H) /* Port 8 Selection */ - - -/************************************************************ -* DIGITAL I/O PortJ Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320 -#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ - -sfr_w(PJIN); /* Port J Input */ -sfr_b(PJIN_L); /* Port J Input */ -sfr_b(PJIN_H); /* Port J Input */ -sfr_w(PJOUT); /* Port J Output */ -sfr_b(PJOUT_L); /* Port J Output */ -sfr_b(PJOUT_H); /* Port J Output */ -sfr_w(PJDIR); /* Port J Direction */ -sfr_b(PJDIR_L); /* Port J Direction */ -sfr_b(PJDIR_H); /* Port J Direction */ -sfr_w(PJREN); /* Port J Resistor Enable */ -sfr_b(PJREN_L); /* Port J Resistor Enable */ -sfr_b(PJREN_H); /* Port J Resistor Enable */ -sfr_w(PJDS); /* Port J Drive Strenght */ -sfr_b(PJDS_L); /* Port J Drive Strenght */ -sfr_b(PJDS_H); /* Port J Drive Strenght */ - -/************************************************************ -* PORT MAPPING CONTROLLER -************************************************************/ -#define __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0 -#define PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__ - -sfr_w(PMAPKEYID); /* Port Mapping Key register */ -sfr_b(PMAPKEYID_L); /* Port Mapping Key register */ -sfr_b(PMAPKEYID_H); /* Port Mapping Key register */ -sfr_w(PMAPCTL); /* Port Mapping control register */ -sfr_b(PMAPCTL_L); /* Port Mapping control register */ -sfr_b(PMAPCTL_H); /* Port Mapping control register */ - -#define PMAPKEY (0x2D52) /* Port Mapping Key */ -#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ -#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */ - -/* PMAPCTL Control Bits */ -#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */ -#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */ - -/* PMAPCTL Control Bits */ -#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */ -#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */ - -/************************************************************ -* PORT 4 MAPPING CONTROLLER -************************************************************/ -#define __MSP430_HAS_PORT4_MAPPING__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT4_MAPPING__ 0x01E0 -#define P4MAP_BASE __MSP430_BASEADDRESS_PORT4_MAPPING__ - -sfr_w(P4MAP01); /* Port P4.0/1 mapping register */ -sfr_b(P4MAP01_L); /* Port P4.0/1 mapping register */ -sfr_b(P4MAP01_H); /* Port P4.0/1 mapping register */ -sfr_w(P4MAP23); /* Port P4.2/3 mapping register */ -sfr_b(P4MAP23_L); /* Port P4.2/3 mapping register */ -sfr_b(P4MAP23_H); /* Port P4.2/3 mapping register */ -sfr_w(P4MAP45); /* Port P4.4/5 mapping register */ -sfr_b(P4MAP45_L); /* Port P4.4/5 mapping register */ -sfr_b(P4MAP45_H); /* Port P4.4/5 mapping register */ -sfr_w(P4MAP67); /* Port P4.6/7 mapping register */ -sfr_b(P4MAP67_L); /* Port P4.6/7 mapping register */ -sfr_b(P4MAP67_H); /* Port P4.6/7 mapping register */ - -#define P4MAP0 P4MAP01_L /* Port P4.0 mapping register */ -#define P4MAP1 P4MAP01_H /* Port P4.1 mapping register */ -#define P4MAP2 P4MAP23_L /* Port P4.2 mapping register */ -#define P4MAP3 P4MAP23_H /* Port P4.3 mapping register */ -#define P4MAP4 P4MAP45_L /* Port P4.4 mapping register */ -#define P4MAP5 P4MAP45_H /* Port P4.5 mapping register */ -#define P4MAP6 P4MAP67_L /* Port P4.6 mapping register */ -#define P4MAP7 P4MAP67_H /* Port P4.7 mapping register */ - -#define PM_NONE 0 -#define PM_CBOUT0 1 -#define PM_TB0CLK 1 -#define PM_ADC12CLK 2 -#define PM_DMAE0 2 -#define PM_SVMOUT 3 -#define PM_TB0OUTH 3 -#define PM_TB0CCR0A 4 -#define PM_TB0CCR1A 5 -#define PM_TB0CCR2A 6 -#define PM_TB0CCR3A 7 -#define PM_TB0CCR4A 8 -#define PM_TB0CCR5A 9 -#define PM_TB0CCR6A 10 -#define PM_UCA1RXD 11 -#define PM_UCA1SOMI 11 -#define PM_UCA1TXD 12 -#define PM_UCA1SIMO 12 -#define PM_UCA1CLK 13 -#define PM_UCB1STE 13 -#define PM_UCB1SOMI 14 -#define PM_UCB1SCL 14 -#define PM_UCB1SIMO 15 -#define PM_UCB1SDA 15 -#define PM_UCB1CLK 16 -#define PM_UCA1STE 16 -#define PM_CBOUT1 17 -#define PM_MCLK 18 -#define PM_ANALOG 31 - -/************************************************************ -* PMM - Power Management System -************************************************************/ -#define __MSP430_HAS_PMM__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PMM__ 0x0120 -#define PMM_BASE __MSP430_BASEADDRESS_PMM__ - -sfr_w(PMMCTL0); /* PMM Control 0 */ -sfr_b(PMMCTL0_L); /* PMM Control 0 */ -sfr_b(PMMCTL0_H); /* PMM Control 0 */ -sfr_w(PMMCTL1); /* PMM Control 1 */ -sfr_b(PMMCTL1_L); /* PMM Control 1 */ -sfr_b(PMMCTL1_H); /* PMM Control 1 */ -sfr_w(SVSMHCTL); /* SVS and SVM high side control register */ -sfr_b(SVSMHCTL_L); /* SVS and SVM high side control register */ -sfr_b(SVSMHCTL_H); /* SVS and SVM high side control register */ -sfr_w(SVSMLCTL); /* SVS and SVM low side control register */ -sfr_b(SVSMLCTL_L); /* SVS and SVM low side control register */ -sfr_b(SVSMLCTL_H); /* SVS and SVM low side control register */ -sfr_w(SVSMIO); /* SVSIN and SVSOUT control register */ -sfr_b(SVSMIO_L); /* SVSIN and SVSOUT control register */ -sfr_b(SVSMIO_H); /* SVSIN and SVSOUT control register */ -sfr_w(PMMIFG); /* PMM Interrupt Flag */ -sfr_b(PMMIFG_L); /* PMM Interrupt Flag */ -sfr_b(PMMIFG_H); /* PMM Interrupt Flag */ -sfr_w(PMMRIE); /* PMM and RESET Interrupt Enable */ -sfr_b(PMMRIE_L); /* PMM and RESET Interrupt Enable */ -sfr_b(PMMRIE_H); /* PMM and RESET Interrupt Enable */ -sfr_w(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */ -sfr_b(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */ -sfr_b(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */ - -#define PMMPW (0xA500) /* PMM Register Write Password */ -#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ - -/* PMMCTL0 Control Bits */ -#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */ -#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */ -#define PMMSWBOR (0x0004) /* PMM Software BOR */ -#define PMMSWPOR (0x0008) /* PMM Software POR */ -#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ -#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */ - -/* PMMCTL0 Control Bits */ -#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */ -#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */ -#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ -#define PMMSWPOR_L (0x0008) /* PMM Software POR */ -#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ -#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */ - -#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */ -#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */ -#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */ -#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */ - -/* PMMCTL1 Control Bits */ -#define PMMREFMD (0x0001) /* PMM Reference Mode */ -#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ -#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ - -/* PMMCTL1 Control Bits */ -#define PMMREFMD_L (0x0001) /* PMM Reference Mode */ -#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ -#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ - -/* SVSMHCTL Control Bits */ -#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ -#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ -#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ -#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */ -#define SVSHMD (0x0010) /* SVS high side mode */ -#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */ -#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */ -#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */ -#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */ -#define SVSHE (0x0400) /* SVS high side enable */ -#define SVSHFP (0x0800) /* SVS high side full performace mode */ -#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */ -#define SVMHE (0x4000) /* SVM high side enable */ -#define SVMHFP (0x8000) /* SVM high side full performace mode */ - -/* SVSMHCTL Control Bits */ -#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ -#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ -#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ -#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */ -#define SVSHMD_L (0x0010) /* SVS high side mode */ -#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */ -#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */ - -/* SVSMHCTL Control Bits */ -#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */ -#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */ -#define SVSHE_H (0x0004) /* SVS high side enable */ -#define SVSHFP_H (0x0008) /* SVS high side full performace mode */ -#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */ -#define SVMHE_H (0x0040) /* SVM high side enable */ -#define SVMHFP_H (0x0080) /* SVM high side full performace mode */ - -#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */ -#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */ -#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */ -#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */ -#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */ -#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */ -#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */ -#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */ - -#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */ -#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */ -#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */ -#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */ - -/* SVSMLCTL Control Bits */ -#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ -#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ -#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ -#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */ -#define SVSLMD (0x0010) /* SVS low side mode */ -#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */ -#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */ -#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */ -#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */ -#define SVSLE (0x0400) /* SVS low side enable */ -#define SVSLFP (0x0800) /* SVS low side full performace mode */ -#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */ -#define SVMLE (0x4000) /* SVM low side enable */ -#define SVMLFP (0x8000) /* SVM low side full performace mode */ - -/* SVSMLCTL Control Bits */ -#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ -#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ -#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ -#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */ -#define SVSLMD_L (0x0010) /* SVS low side mode */ -#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */ -#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */ - -/* SVSMLCTL Control Bits */ -#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */ -#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */ -#define SVSLE_H (0x0004) /* SVS low side enable */ -#define SVSLFP_H (0x0008) /* SVS low side full performace mode */ -#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */ -#define SVMLE_H (0x0040) /* SVM low side enable */ -#define SVMLFP_H (0x0080) /* SVM low side full performace mode */ - -#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */ -#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */ -#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */ -#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */ -#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */ -#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */ -#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */ -#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */ - -#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */ -#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */ -#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */ -#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */ - -/* SVSMIO Control Bits */ -#define SVMLOE (0x0008) /* SVM low side output enable */ -#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */ -#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */ -#define SVMHOE (0x0800) /* SVM high side output enable */ -#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */ - -/* SVSMIO Control Bits */ -#define SVMLOE_L (0x0008) /* SVM low side output enable */ -#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */ -#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */ - -/* SVSMIO Control Bits */ -#define SVMHOE_H (0x0008) /* SVM high side output enable */ -#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */ - -/* PMMIFG Control Bits */ -#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ -#define SVMLIFG (0x0002) /* SVM low side interrupt flag */ -#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ -#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ -#define SVMHIFG (0x0020) /* SVM high side interrupt flag */ -#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ -#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ -#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ -#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ -#define SVSHIFG (0x1000) /* SVS low side interrupt flag */ -#define SVSLIFG (0x2000) /* SVS high side interrupt flag */ -#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ - -/* PMMIFG Control Bits */ -#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ -#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */ -#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ -#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ -#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */ -#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ - -/* PMMIFG Control Bits */ -#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ -#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ -#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ -#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */ -#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */ -#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ - -#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ - -/* PMMIE and RESET Control Bits */ -#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ -#define SVMLIE (0x0002) /* SVM low side interrupt enable */ -#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ -#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ -#define SVMHIE (0x0020) /* SVM high side interrupt enable */ -#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ -#define SVSLPE (0x0100) /* SVS low side POR enable */ -#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */ -#define SVSHPE (0x1000) /* SVS high side POR enable */ -#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */ - -/* PMMIE and RESET Control Bits */ -#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ -#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */ -#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ -#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ -#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */ -#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ - -/* PMMIE and RESET Control Bits */ -#define SVSLPE_H (0x0001) /* SVS low side POR enable */ -#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */ -#define SVSHPE_H (0x0010) /* SVS high side POR enable */ -#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */ - -/* PM5CTL0 Power Mode 5 Control Bits */ -#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ - -/* PM5CTL0 Power Mode 5 Control Bits */ -#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ - -#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ - -/************************************************************* -* RAM Control Module -*************************************************************/ -#define __MSP430_HAS_RC__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_RC__ 0x0158 -#define RAM_BASE __MSP430_BASEADDRESS_RC__ - -sfr_w(RCCTL0); /* Ram Controller Control Register */ -sfr_b(RCCTL0_L); /* Ram Controller Control Register */ -sfr_b(RCCTL0_H); /* Ram Controller Control Register */ - -/* RCCTL0 Control Bits */ -#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */ -#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */ -#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */ -#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */ -#define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ - -/* RCCTL0 Control Bits */ -#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */ -#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */ -#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */ -#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */ -#define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ - -#define RCKEY (0x5A00) - -/************************************************************ -* Shared Reference -************************************************************/ -#define __MSP430_HAS_REF__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_REF__ 0x01B0 -#define REF_BASE __MSP430_BASEADDRESS_REF__ - -sfr_w(REFCTL0); /* REF Shared Reference control register 0 */ -sfr_b(REFCTL0_L); /* REF Shared Reference control register 0 */ -sfr_b(REFCTL0_H); /* REF Shared Reference control register 0 */ - -/* REFCTL0 Control Bits */ -#define REFON (0x0001) /* REF Reference On */ -#define REFOUT (0x0002) /* REF Reference output Buffer On */ -//#define RESERVED (0x0004) /* Reserved */ -#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ -#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ -#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ -//#define RESERVED (0x0040) /* Reserved */ -#define REFMSTR (0x0080) /* REF Master Control */ -#define REFGENACT (0x0100) /* REF Reference generator active */ -#define REFBGACT (0x0200) /* REF Reference bandgap active */ -#define REFGENBUSY (0x0400) /* REF Reference generator busy */ -#define BGMODE (0x0800) /* REF Bandgap mode */ -//#define RESERVED (0x1000) /* Reserved */ -//#define RESERVED (0x2000) /* Reserved */ -//#define RESERVED (0x4000) /* Reserved */ -//#define RESERVED (0x8000) /* Reserved */ - -/* REFCTL0 Control Bits */ -#define REFON_L (0x0001) /* REF Reference On */ -#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ -//#define RESERVED (0x0004) /* Reserved */ -#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ -#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ -#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ -//#define RESERVED (0x0040) /* Reserved */ -#define REFMSTR_L (0x0080) /* REF Master Control */ -//#define RESERVED (0x1000) /* Reserved */ -//#define RESERVED (0x2000) /* Reserved */ -//#define RESERVED (0x4000) /* Reserved */ -//#define RESERVED (0x8000) /* Reserved */ - -/* REFCTL0 Control Bits */ -//#define RESERVED (0x0004) /* Reserved */ -//#define RESERVED (0x0040) /* Reserved */ -#define REFGENACT_H (0x0001) /* REF Reference generator active */ -#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ -#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ -#define BGMODE_H (0x0008) /* REF Bandgap mode */ -//#define RESERVED (0x1000) /* Reserved */ -//#define RESERVED (0x2000) /* Reserved */ -//#define RESERVED (0x4000) /* Reserved */ -//#define RESERVED (0x8000) /* Reserved */ - -#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ -#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ -#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ -#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ - -/************************************************************ -* Real Time Clock -************************************************************/ -#define __MSP430_HAS_RTC__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_RTC__ 0x04A0 -#define RTC_A_BASE __MSP430_BASEADDRESS_RTC__ - -sfr_w(RTCCTL01); /* Real Timer Control 0/1 */ -sfr_b(RTCCTL01_L); /* Real Timer Control 0/1 */ -sfr_b(RTCCTL01_H); /* Real Timer Control 0/1 */ -sfr_w(RTCCTL23); /* Real Timer Control 2/3 */ -sfr_b(RTCCTL23_L); /* Real Timer Control 2/3 */ -sfr_b(RTCCTL23_H); /* Real Timer Control 2/3 */ -sfr_w(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */ -sfr_b(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */ -sfr_b(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */ -sfr_w(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */ -sfr_b(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */ -sfr_b(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */ -sfr_w(RTCPS); /* Real Timer Prescale Timer Control */ -sfr_b(RTCPS_L); /* Real Timer Prescale Timer Control */ -sfr_b(RTCPS_H); /* Real Timer Prescale Timer Control */ -sfr_w(RTCIV); /* Real Time Clock Interrupt Vector */ -sfr_w(RTCTIM0); /* Real Time Clock Time 0 */ -sfr_b(RTCTIM0_L); /* Real Time Clock Time 0 */ -sfr_b(RTCTIM0_H); /* Real Time Clock Time 0 */ -sfr_w(RTCTIM1); /* Real Time Clock Time 1 */ -sfr_b(RTCTIM1_L); /* Real Time Clock Time 1 */ -sfr_b(RTCTIM1_H); /* Real Time Clock Time 1 */ -sfr_w(RTCDATE); /* Real Time Clock Date */ -sfr_b(RTCDATE_L); /* Real Time Clock Date */ -sfr_b(RTCDATE_H); /* Real Time Clock Date */ -sfr_w(RTCYEAR); /* Real Time Clock Year */ -sfr_b(RTCYEAR_L); /* Real Time Clock Year */ -sfr_b(RTCYEAR_H); /* Real Time Clock Year */ -sfr_w(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */ -sfr_b(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */ -sfr_b(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */ -sfr_w(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */ -sfr_b(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */ -sfr_b(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */ - -#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ -#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ -#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ -#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ -#define RTCNT12 RTCTIM0 -#define RTCNT34 RTCTIM1 -#define RTCNT1 RTCTIM0_L -#define RTCNT2 RTCTIM0_H -#define RTCNT3 RTCTIM1_L -#define RTCNT4 RTCTIM1_H -#define RTCSEC RTCTIM0_L -#define RTCMIN RTCTIM0_H -#define RTCHOUR RTCTIM1_L -#define RTCDOW RTCTIM1_H -#define RTCDAY RTCDATE_L -#define RTCMON RTCDATE_H -#define RTCYEARL RTCYEAR_L -#define RTCYEARH RTCYEAR_H -#define RT0PS RTCPS_L -#define RT1PS RTCPS_H -#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ -#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ -#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ -#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ - -/* RTCCTL01 Control Bits */ -#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ -#define RTCHOLD (0x4000) /* RTC Hold */ -#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */ -#define RTCRDY (0x1000) /* RTC Ready */ -#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */ -#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */ -#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ -#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ -//#define Reserved (0x0080) -#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ -#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ -#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ -//#define Reserved (0x0008) -#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ -#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ -#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ - -/* RTCCTL01 Control Bits */ -//#define Reserved (0x0080) -#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ -#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ -#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ -//#define Reserved (0x0008) -#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ -#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ -#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ - -/* RTCCTL01 Control Bits */ -#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ -#define RTCHOLD_H (0x0040) /* RTC Hold */ -#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ -#define RTCRDY_H (0x0010) /* RTC Ready */ -#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */ -#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */ -#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ -#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ -//#define Reserved (0x0080) -//#define Reserved (0x0008) - -#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ -#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */ -#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */ -#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */ -#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ -#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */ -#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */ -#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ -#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ -#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ -#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ -#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ -#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ -#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ -#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ - -/* RTCCTL23 Control Bits */ -#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ -#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ -#define RTCCALS (0x0080) /* RTC Calibration Sign */ -//#define Reserved (0x0040) -#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ -#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ -#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ -#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ -#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ -#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ - -/* RTCCTL23 Control Bits */ -#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ -//#define Reserved (0x0040) -#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ -#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ -#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ -#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ -#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ -#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ - -/* RTCCTL23 Control Bits */ -#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ -#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ -//#define Reserved (0x0040) - -#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ -#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ -#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ -#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ - -#define RTCAE (0x80) /* Real Time Clock Alarm enable */ - -/* RTCPS0CTL Control Bits */ -//#define Reserved (0x8000) -#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ -#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ -#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ -#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ -#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ -#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ -#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ -#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ - -/* RTCPS0CTL Control Bits */ -//#define Reserved (0x8000) -//#define Reserved (0x0400) -//#define Reserved (0x0200) -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ -#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ -#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ -#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ -#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ - -/* RTCPS0CTL Control Bits */ -//#define Reserved (0x8000) -#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ -#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ -#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ -#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) - -#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ -#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ -#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ -#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ -#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ -#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ -#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ -#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ - -#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */ -#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */ -#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */ -#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */ -#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */ -#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */ -#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */ -#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */ - -/* RTCPS1CTL Control Bits */ -#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ -#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ -#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ -#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ -#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ -#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ -#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ -#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ -#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ - -/* RTCPS1CTL Control Bits */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ -#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ -#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ -#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ -#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ - -/* RTCPS1CTL Control Bits */ -#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ -#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ -#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ -#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ -#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) - -#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ -#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ -#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ -#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ -#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ -#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ -#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ -#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ - -#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */ -#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */ -#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */ -#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */ -#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */ -#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */ -#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */ -#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */ - -#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */ -#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */ -#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */ -#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */ - -/* RTC Definitions */ -#define RTCIV_NONE (0x0000) /* No Interrupt pending */ -#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ -#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ -#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ -#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ -#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ - -/* Legacy Definitions */ -#define RTC_NONE (0x0000) /* No Interrupt pending */ -#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ -#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ -#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ -#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ -#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ - -/************************************************************ -* SFR - Special Function Register Module -************************************************************/ -#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_SFR__ 0x0100 -#define SFR_BASE __MSP430_BASEADDRESS_SFR__ - -sfr_w(SFRIE1); /* Interrupt Enable 1 */ -sfr_b(SFRIE1_L); /* Interrupt Enable 1 */ -sfr_b(SFRIE1_H); /* Interrupt Enable 1 */ - -/* SFRIE1 Control Bits */ -#define WDTIE (0x0001) /* WDT Interrupt Enable */ -#define OFIE (0x0002) /* Osc Fault Enable */ -//#define Reserved (0x0004) -#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ -#define NMIIE (0x0010) /* NMI Interrupt Enable */ -#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */ -#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ -#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ - -#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ -#define OFIE_L (0x0002) /* Osc Fault Enable */ -//#define Reserved (0x0004) -#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ -#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ -#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */ -#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ -#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ - -sfr_w(SFRIFG1); /* Interrupt Flag 1 */ -sfr_b(SFRIFG1_L); /* Interrupt Flag 1 */ -sfr_b(SFRIFG1_H); /* Interrupt Flag 1 */ -/* SFRIFG1 Control Bits */ -#define WDTIFG (0x0001) /* WDT Interrupt Flag */ -#define OFIFG (0x0002) /* Osc Fault Flag */ -//#define Reserved (0x0004) -#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ -#define NMIIFG (0x0010) /* NMI Interrupt Flag */ -//#define Reserved (0x0020) -#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ -#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ - -#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ -#define OFIFG_L (0x0002) /* Osc Fault Flag */ -//#define Reserved (0x0004) -#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ -#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ -//#define Reserved (0x0020) -#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ -#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ - -sfr_w(SFRRPCR); /* RESET Pin Control Register */ -sfr_b(SFRRPCR_L); /* RESET Pin Control Register */ -sfr_b(SFRRPCR_H); /* RESET Pin Control Register */ -/* SFRRPCR Control Bits */ -#define SYSNMI (0x0001) /* NMI select */ -#define SYSNMIIES (0x0002) /* NMI edge select */ -#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ -#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ - -#define SYSNMI_L (0x0001) /* NMI select */ -#define SYSNMIIES_L (0x0002) /* NMI edge select */ -#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ -#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ - -/************************************************************ -* SYS - System Module -************************************************************/ -#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_SYS__ 0x0180 -#define SYS_BASE __MSP430_BASEADDRESS_SYS__ - -sfr_w(SYSCTL); /* System control */ -sfr_b(SYSCTL_L); /* System control */ -sfr_b(SYSCTL_H); /* System control */ -sfr_w(SYSBSLC); /* Boot strap configuration area */ -sfr_b(SYSBSLC_L); /* Boot strap configuration area */ -sfr_b(SYSBSLC_H); /* Boot strap configuration area */ -sfr_w(SYSJMBC); /* JTAG mailbox control */ -sfr_b(SYSJMBC_L); /* JTAG mailbox control */ -sfr_b(SYSJMBC_H); /* JTAG mailbox control */ -sfr_w(SYSJMBI0); /* JTAG mailbox input 0 */ -sfr_b(SYSJMBI0_L); /* JTAG mailbox input 0 */ -sfr_b(SYSJMBI0_H); /* JTAG mailbox input 0 */ -sfr_w(SYSJMBI1); /* JTAG mailbox input 1 */ -sfr_b(SYSJMBI1_L); /* JTAG mailbox input 1 */ -sfr_b(SYSJMBI1_H); /* JTAG mailbox input 1 */ -sfr_w(SYSJMBO0); /* JTAG mailbox output 0 */ -sfr_b(SYSJMBO0_L); /* JTAG mailbox output 0 */ -sfr_b(SYSJMBO0_H); /* JTAG mailbox output 0 */ -sfr_w(SYSJMBO1); /* JTAG mailbox output 1 */ -sfr_b(SYSJMBO1_L); /* JTAG mailbox output 1 */ -sfr_b(SYSJMBO1_H); /* JTAG mailbox output 1 */ - -sfr_w(SYSBERRIV); /* Bus Error vector generator */ -sfr_b(SYSBERRIV_L); /* Bus Error vector generator */ -sfr_b(SYSBERRIV_H); /* Bus Error vector generator */ -sfr_w(SYSUNIV); /* User NMI vector generator */ -sfr_b(SYSUNIV_L); /* User NMI vector generator */ -sfr_b(SYSUNIV_H); /* User NMI vector generator */ -sfr_w(SYSSNIV); /* System NMI vector generator */ -sfr_b(SYSSNIV_L); /* System NMI vector generator */ -sfr_b(SYSSNIV_H); /* System NMI vector generator */ -sfr_w(SYSRSTIV); /* Reset vector generator */ -sfr_b(SYSRSTIV_L); /* Reset vector generator */ -sfr_b(SYSRSTIV_H); /* Reset vector generator */ - -/* SYSCTL Control Bits */ -#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ -//#define RESERVED (0x0002) /* SYS - Reserved */ -#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ -#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - -/* SYSCTL Control Bits */ -#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ -//#define RESERVED (0x0002) /* SYS - Reserved */ -#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ -#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - -/* SYSBSLC Control Bits */ -#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ -#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ -#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -//#define RESERVED (0x0010) /* SYS - Reserved */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ -#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ - -/* SYSBSLC Control Bits */ -#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ -#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ -#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -//#define RESERVED (0x0010) /* SYS - Reserved */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ - -/* SYSBSLC Control Bits */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -//#define RESERVED (0x0010) /* SYS - Reserved */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ -#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ - -/* SYSJMBC Control Bits */ -#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ -#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ -#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ -#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ -#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ -#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - -/* SYSJMBC Control Bits */ -#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ -#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ -#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ -#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ -#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ -#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - - -/* SYSUNIV Definitions */ -#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */ -#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */ -#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */ -#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */ -#define SYSUNIV_BUSIFG (0x0008) /* SYSUNIV : Bus Error */ -#define SYSUNIV_SYSBUSIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIFG (legacy) */ - -/* SYSSNIV Definitions */ -#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */ -#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */ -#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */ -#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */ -#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */ -#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */ -#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */ -#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */ -#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */ -#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */ - -/* SYSRSTIV Definitions */ -#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */ -#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */ -#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */ -#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */ -#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */ -#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */ -#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */ -#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */ -#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */ -#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */ -#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */ -#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */ -#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */ -#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */ -//#define RESERVED (0x001C) /* SYSRSTIV : Reserved */ -#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */ -#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */ - -/************************************************************ -* Timer0_A5 -************************************************************/ -#define __MSP430_HAS_T0A5__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T0A5__ 0x0340 -#define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__ - -sfr_w(TA0CTL); /* Timer0_A5 Control */ -sfr_w(TA0CCTL0); /* Timer0_A5 Capture/Compare Control 0 */ -sfr_w(TA0CCTL1); /* Timer0_A5 Capture/Compare Control 1 */ -sfr_w(TA0CCTL2); /* Timer0_A5 Capture/Compare Control 2 */ -sfr_w(TA0CCTL3); /* Timer0_A5 Capture/Compare Control 3 */ -sfr_w(TA0CCTL4); /* Timer0_A5 Capture/Compare Control 4 */ -sfr_w(TA0R); /* Timer0_A5 */ -sfr_w(TA0CCR0); /* Timer0_A5 Capture/Compare 0 */ -sfr_w(TA0CCR1); /* Timer0_A5 Capture/Compare 1 */ -sfr_w(TA0CCR2); /* Timer0_A5 Capture/Compare 2 */ -sfr_w(TA0CCR3); /* Timer0_A5 Capture/Compare 3 */ -sfr_w(TA0CCR4); /* Timer0_A5 Capture/Compare 4 */ -sfr_w(TA0IV); /* Timer0_A5 Interrupt Vector Word */ -sfr_w(TA0EX0); /* Timer0_A5 Expansion Register 0 */ - -/* TAxCTL Control Bits */ -#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ -#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ -#define ID1 (0x0080) /* Timer A clock input divider 1 */ -#define ID0 (0x0040) /* Timer A clock input divider 0 */ -#define MC1 (0x0020) /* Timer A mode control 1 */ -#define MC0 (0x0010) /* Timer A mode control 0 */ -#define TACLR (0x0004) /* Timer A counter clear */ -#define TAIE (0x0002) /* Timer A counter interrupt enable */ -#define TAIFG (0x0001) /* Timer A counter interrupt flag */ - -#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ -#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ -#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */ -#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ -#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ -#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ -#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ -#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ -#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ -#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ -#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ -#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ -#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */ -#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ -#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */ -#define MC__CONTINOUS (0x0020) /* Legacy define */ -#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */ -#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */ -#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */ -#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */ -#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */ -#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */ -#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */ -#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */ -#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */ - -/* TAxCCTLx Control Bits */ -#define CM1 (0x8000) /* Capture mode 1 */ -#define CM0 (0x4000) /* Capture mode 0 */ -#define CCIS1 (0x2000) /* Capture input select 1 */ -#define CCIS0 (0x1000) /* Capture input select 0 */ -#define SCS (0x0800) /* Capture sychronize */ -#define SCCI (0x0400) /* Latched capture signal (read) */ -#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ -#define OUTMOD2 (0x0080) /* Output mode 2 */ -#define OUTMOD1 (0x0040) /* Output mode 1 */ -#define OUTMOD0 (0x0020) /* Output mode 0 */ -#define CCIE (0x0010) /* Capture/compare interrupt enable */ -#define CCI (0x0008) /* Capture input signal (read) */ -#define OUT (0x0004) /* PWM Output signal if output mode 0 */ -#define COV (0x0002) /* Capture/compare overflow flag */ -#define CCIFG (0x0001) /* Capture/compare interrupt flag */ - -#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ -#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ -#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ -#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ -#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ -#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ -#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ -#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ -#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ -#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ -#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ -#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ -#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ -#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ -#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ -#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ - -/* TAxEX0 Control Bits */ -#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ -#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ -#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ - -#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */ -#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */ -#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */ -#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */ -#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */ -#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */ -#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */ -#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */ - -/* T0A5IV Definitions */ -#define TA0IV_NONE (0x0000) /* No Interrupt pending */ -#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ -#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ -#define TA0IV_TACCR3 (0x0006) /* TA0CCR3_CCIFG */ -#define TA0IV_TACCR4 (0x0008) /* TA0CCR4_CCIFG */ -#define TA0IV_5 (0x000A) /* Reserved */ -#define TA0IV_6 (0x000C) /* Reserved */ -#define TA0IV_TAIFG (0x000E) /* TA0IFG */ - -/* Legacy Defines */ -#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */ -#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */ -#define TA0IV_TA0CCR3 (0x0006) /* TA0CCR3_CCIFG */ -#define TA0IV_TA0CCR4 (0x0008) /* TA0CCR4_CCIFG */ -#define TA0IV_TA0IFG (0x000E) /* TA0IFG */ - -/************************************************************ -* Timer1_A3 -************************************************************/ -#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T1A3__ 0x0380 -#define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__ - -sfr_w(TA1CTL); /* Timer1_A3 Control */ -sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */ -sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */ -sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */ -sfr_w(TA1R); /* Timer1_A3 */ -sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */ -sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */ -sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */ -sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */ -sfr_w(TA1EX0); /* Timer1_A3 Expansion Register 0 */ - -/* Bits are already defined within the Timer0_Ax */ - -/* TA1IV Definitions */ -#define TA1IV_NONE (0x0000) /* No Interrupt pending */ -#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ -#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ -#define TA1IV_3 (0x0006) /* Reserved */ -#define TA1IV_4 (0x0008) /* Reserved */ -#define TA1IV_5 (0x000A) /* Reserved */ -#define TA1IV_6 (0x000C) /* Reserved */ -#define TA1IV_TAIFG (0x000E) /* TA1IFG */ - -/* Legacy Defines */ -#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */ -#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */ -#define TA1IV_TA1IFG (0x000E) /* TA1IFG */ - -/************************************************************ -* Timer2_A3 -************************************************************/ -#define __MSP430_HAS_T2A3__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T2A3__ 0x0400 -#define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A3__ - -sfr_w(TA2CTL); /* Timer2_A3 Control */ -sfr_w(TA2CCTL0); /* Timer2_A3 Capture/Compare Control 0 */ -sfr_w(TA2CCTL1); /* Timer2_A3 Capture/Compare Control 1 */ -sfr_w(TA2CCTL2); /* Timer2_A3 Capture/Compare Control 2 */ -sfr_w(TA2R); /* Timer2_A3 */ -sfr_w(TA2CCR0); /* Timer2_A3 Capture/Compare 0 */ -sfr_w(TA2CCR1); /* Timer2_A3 Capture/Compare 1 */ -sfr_w(TA2CCR2); /* Timer2_A3 Capture/Compare 2 */ -sfr_w(TA2IV); /* Timer2_A3 Interrupt Vector Word */ -sfr_w(TA2EX0); /* Timer2_A3 Expansion Register 0 */ - -/* Bits are already defined within the Timer0_Ax */ - -/* TA2IV Definitions */ -#define TA2IV_NONE (0x0000) /* No Interrupt pending */ -#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */ -#define TA2IV_TACCR2 (0x0004) /* TA2CCR2_CCIFG */ -#define TA2IV_3 (0x0006) /* Reserved */ -#define TA2IV_4 (0x0008) /* Reserved */ -#define TA2IV_5 (0x000A) /* Reserved */ -#define TA2IV_6 (0x000C) /* Reserved */ -#define TA2IV_TAIFG (0x000E) /* TA2IFG */ - -/* Legacy Defines */ -#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */ -#define TA2IV_TA2CCR2 (0x0004) /* TA2CCR2_CCIFG */ -#define TA2IV_TA2IFG (0x000E) /* TA2IFG */ - -/************************************************************ -* Timer0_B7 -************************************************************/ -#define __MSP430_HAS_T0B7__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T0B7__ 0x03C0 -#define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__ - -sfr_w(TB0CTL); /* Timer0_B7 Control */ -sfr_w(TB0CCTL0); /* Timer0_B7 Capture/Compare Control 0 */ -sfr_w(TB0CCTL1); /* Timer0_B7 Capture/Compare Control 1 */ -sfr_w(TB0CCTL2); /* Timer0_B7 Capture/Compare Control 2 */ -sfr_w(TB0CCTL3); /* Timer0_B7 Capture/Compare Control 3 */ -sfr_w(TB0CCTL4); /* Timer0_B7 Capture/Compare Control 4 */ -sfr_w(TB0CCTL5); /* Timer0_B7 Capture/Compare Control 5 */ -sfr_w(TB0CCTL6); /* Timer0_B7 Capture/Compare Control 6 */ -sfr_w(TB0R); /* Timer0_B7 */ -sfr_w(TB0CCR0); /* Timer0_B7 Capture/Compare 0 */ -sfr_w(TB0CCR1); /* Timer0_B7 Capture/Compare 1 */ -sfr_w(TB0CCR2); /* Timer0_B7 Capture/Compare 2 */ -sfr_w(TB0CCR3); /* Timer0_B7 Capture/Compare 3 */ -sfr_w(TB0CCR4); /* Timer0_B7 Capture/Compare 4 */ -sfr_w(TB0CCR5); /* Timer0_B7 Capture/Compare 5 */ -sfr_w(TB0CCR6); /* Timer0_B7 Capture/Compare 6 */ -sfr_w(TB0EX0); /* Timer0_B7 Expansion Register 0 */ -sfr_w(TB0IV); /* Timer0_B7 Interrupt Vector Word */ - -/* Legacy Type Definitions for TimerB */ -#define TBCTL TB0CTL /* Timer0_B7 Control */ -#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */ -#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */ -#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */ -#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */ -#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */ -#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */ -#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */ -#define TBR TB0R /* Timer0_B7 */ -#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */ -#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */ -#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */ -#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */ -#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */ -#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */ -#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */ -#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */ -#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */ -#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */ -#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */ - -/* TBxCTL Control Bits */ -#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ -#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ -#define CNTL1 (0x1000) /* Counter lenght 1 */ -#define CNTL0 (0x0800) /* Counter lenght 0 */ -#define TBSSEL1 (0x0200) /* Clock source 1 */ -#define TBSSEL0 (0x0100) /* Clock source 0 */ -#define TBCLR (0x0004) /* Timer0_B7 counter clear */ -#define TBIE (0x0002) /* Timer0_B7 interrupt enable */ -#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */ - -#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ -#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ - -#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ -#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ -#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ -#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ -#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ -#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ -#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ -#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ -#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ -#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ -#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ -#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ -#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ -#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ -#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ -#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ -#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */ -#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ -#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */ -#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */ -#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */ -#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */ -#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */ -#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */ -#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */ - -/* Additional Timer B Control Register bits are defined in Timer A */ -/* TBxCCTLx Control Bits */ -#define CLLD1 (0x0400) /* Compare latch load source 1 */ -#define CLLD0 (0x0200) /* Compare latch load source 0 */ - -#define SLSHR1 (0x0400) /* Compare latch load source 1 */ -#define SLSHR0 (0x0200) /* Compare latch load source 0 */ - -#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ -#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ -#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ -#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ - -#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ -#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ -#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ -#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ - -/* TBxEX0 Control Bits */ -#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */ -#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */ -#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */ - -#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ -#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ -#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ -#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ -#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ -#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ -#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ -#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ -#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ -#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ -#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ -#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ -#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ -#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ -#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ -#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ - -/* TB0IV Definitions */ -#define TB0IV_NONE (0x0000) /* No Interrupt pending */ -#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ -#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ -#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ -#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ -#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */ -#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */ -#define TB0IV_TBIFG (0x000E) /* TB0IFG */ - -/* Legacy Defines */ -#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */ -#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */ -#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */ -#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */ -#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */ -#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */ -#define TB0IV_TB0IFG (0x000E) /* TB0IFG */ - - -/************************************************************ -* USB -************************************************************/ -#define __MSP430_HAS_USB__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USB__ 0x0900 -#define USB_BASE __MSP430_BASEADDRESS_USB__ - -/* ========================================================================= */ -/* USB Configuration Registers */ -/* ========================================================================= */ -sfr_w(USBKEYID); /* USB Controller key register */ -sfr_b(USBKEYID_L); /* USB Controller key register */ -sfr_b(USBKEYID_H); /* USB Controller key register */ -sfr_w(USBCNF); /* USB Module configuration register */ -sfr_b(USBCNF_L); /* USB Module configuration register */ -sfr_b(USBCNF_H); /* USB Module configuration register */ -sfr_w(USBPHYCTL); /* USB PHY control register */ -sfr_b(USBPHYCTL_L); /* USB PHY control register */ -sfr_b(USBPHYCTL_H); /* USB PHY control register */ -sfr_w(USBPWRCTL); /* USB Power control register */ -sfr_b(USBPWRCTL_L); /* USB Power control register */ -sfr_b(USBPWRCTL_H); /* USB Power control register */ -sfr_w(USBPLLCTL); /* USB PLL control register */ -sfr_b(USBPLLCTL_L); /* USB PLL control register */ -sfr_b(USBPLLCTL_H); /* USB PLL control register */ -sfr_w(USBPLLDIVB); /* USB PLL Clock Divider Buffer control register */ -sfr_b(USBPLLDIVB_L); /* USB PLL Clock Divider Buffer control register */ -sfr_b(USBPLLDIVB_H); /* USB PLL Clock Divider Buffer control register */ -sfr_w(USBPLLIR); /* USB PLL Interrupt control register */ -sfr_b(USBPLLIR_L); /* USB PLL Interrupt control register */ -sfr_b(USBPLLIR_H); /* USB PLL Interrupt control register */ - -#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */ -#define USBKEY (0x9628) /* USB Control Register key */ - -/* USBCNF Control Bits */ -#define USB_EN (0x0001) /* USB - Module enable */ -#define PUR_EN (0x0002) /* USB - PUR pin enable */ -#define PUR_IN (0x0004) /* USB - PUR pin input value */ -#define BLKRDY (0x0008) /* USB - Block ready signal for DMA */ -#define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBCNF Control Bits */ -#define USB_EN_L (0x0001) /* USB - Module enable */ -#define PUR_EN_L (0x0002) /* USB - PUR pin enable */ -#define PUR_IN_L (0x0004) /* USB - PUR pin input value */ -#define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */ -#define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPHYCTL Control Bits */ -#define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */ -#define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */ -#define PUIN0 (0x0004) /* USB - PU0/DP Input Data */ -#define PUIN1 (0x0008) /* USB - PU1/DM Input Data */ -//#define RESERVED (0x0010) /* USB - */ -#define PUOPE (0x0020) /* USB - USB Port Output Enable */ -//#define RESERVED (0x0040) /* USB - */ -#define PUSEL (0x0080) /* USB - USB Port Function Select */ -#define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPHYCTL Control Bits */ -#define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */ -#define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */ -#define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */ -#define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */ -//#define RESERVED (0x0010) /* USB - */ -#define PUOPE_L (0x0020) /* USB - USB Port Output Enable */ -//#define RESERVED (0x0040) /* USB - */ -#define PUSEL_L (0x0080) /* USB - USB Port Function Select */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPHYCTL Control Bits */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -#define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -#define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */ -#define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */ - -/* USBPWRCTL Control Bits */ -#define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */ -#define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ -#define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ -#define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */ -#define USBDETEN (0x0010) /* USB - VBUS on/off events enable */ -#define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */ -#define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */ -//#define RESERVED (0x0080) /* USB - */ -#define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */ -#define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */ -#define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */ -#define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */ -#define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPWRCTL Control Bits */ -#define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */ -#define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ -#define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ -#define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */ -#define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */ -#define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */ -#define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPWRCTL Control Bits */ -//#define RESERVED (0x0080) /* USB - */ -#define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */ -#define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */ -#define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */ -#define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */ -#define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLCTL Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -#define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */ -#define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */ -#define UPLLEN (0x0100) /* USB - PLL enable */ -#define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLCTL Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -#define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */ -#define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLCTL Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -#define UPLLEN_H (0x0001) /* USB - PLL enable */ -#define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -#define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */ -#define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */ -#define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */ -#define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */ - -#define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */ -#define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */ -#define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */ - -/* USBPLLDIVB Control Bits */ -#define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ -#define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ -#define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ -#define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ -#define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ -#define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */ -#define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */ -#define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLDIVB Control Bits */ -#define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ -#define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ -#define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ -#define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ -#define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ -#define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLDIVB Control Bits */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */ -#define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */ -#define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */ -#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */ -#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */ -#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */ -#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */ -#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */ -#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */ -#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */ -#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */ -#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */ -#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */ -#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */ -#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */ -#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */ -#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */ -#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */ -#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */ -#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */ -#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */ -#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */ -#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */ -#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */ -#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */ -#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */ -#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */ -#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */ -#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */ -#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */ -#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */ -#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */ -#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */ -#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */ -#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */ -#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */ -#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */ -#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */ -#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */ -#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */ -#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */ -#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */ -#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */ -#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */ -#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */ - -/* USBPLLIR Control Bits */ -#define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */ -#define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */ -#define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */ -#define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */ -#define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLIR Control Bits */ -#define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */ -#define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */ -#define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLIR Control Bits */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */ -#define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */ -#define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* ========================================================================= */ -/* USB Control Registers */ -/* ========================================================================= */ -sfr_b(USBIEPCNF_0); /* USB Input endpoint_0: Configuration */ -sfr_b(USBIEPCNT_0); /* USB Input endpoint_0: Byte Count */ -sfr_b(USBOEPCNF_0); /* USB Output endpoint_0: Configuration */ -sfr_b(USBOEPCNT_0); /* USB Output endpoint_0: byte count */ -sfr_b(USBIEPIE); /* USB Input endpoint interrupt enable flags */ -sfr_b(USBOEPIE); /* USB Output endpoint interrupt enable flags */ -sfr_b(USBIEPIFG); /* USB Input endpoint interrupt flags */ -sfr_b(USBOEPIFG); /* USB Output endpoint interrupt flags */ -sfr_w(USBVECINT); /* USB Vector interrupt register */ -sfr_b(USBVECINT_L); /* USB Vector interrupt register */ -sfr_b(USBVECINT_H); /* USB Vector interrupt register */ -sfr_w(USBMAINT); /* USB maintenance register */ -sfr_b(USBMAINT_L); /* USB maintenance register */ -sfr_b(USBMAINT_H); /* USB maintenance register */ -sfr_w(USBTSREG); /* USB Time Stamp register */ -sfr_b(USBTSREG_L); /* USB Time Stamp register */ -sfr_b(USBTSREG_H); /* USB Time Stamp register */ -sfr_w(USBFN); /* USB Frame number */ -sfr_b(USBFN_L); /* USB Frame number */ -sfr_b(USBFN_H); /* USB Frame number */ -sfr_b(USBCTL); /* USB control register */ -sfr_b(USBIE); /* USB interrupt enable register */ -sfr_b(USBIFG); /* USB interrupt flag register */ -sfr_b(USBFUNADR); /* USB Function address register */ - -#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */ - -/* USBIEPCNF_0 Control Bits */ -/* USBOEPCNF_0 Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0001) /* USB - */ -#define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */ -#define STALL (0x0008) /* USB - Stall Condition */ -//#define RESERVED (0x0010) /* USB - */ -#define TOGGLE (0x0020) /* USB - Toggle Bit */ -//#define RESERVED (0x0040) /* USB - */ -#define UBME (0x0080) /* USB - UBM In-Endpoint Enable */ - -/* USBIEPBCNT_0 Control Bits */ -/* USBOEPBCNT_0 Control Bits */ -#define CNT0 (0x0001) /* USB - Byte Count Bit 0 */ -#define CNT1 (0x0001) /* USB - Byte Count Bit 1 */ -#define CNT2 (0x0004) /* USB - Byte Count Bit 2 */ -#define CNT3 (0x0008) /* USB - Byte Count Bit 3 */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -#define NAK (0x0080) /* USB - No Acknowledge Status Bit */ - -/* USBMAINT Control Bits */ -#define UTIFG (0x0001) /* USB - Timer Interrupt Flag */ -#define UTIE (0x0002) /* USB - Timer Interrupt Enable */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */ -#define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */ -#define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */ -#define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */ -//#define RESERVED (0x1000) /* USB - */ -#define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */ -#define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */ -#define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */ - -/* USBMAINT Control Bits */ -#define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */ -#define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ - -/* USBMAINT Control Bits */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */ -#define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */ -#define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */ -#define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */ -//#define RESERVED (0x1000) /* USB - */ -#define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */ -#define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */ -#define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */ - -#define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */ -#define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */ -#define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */ -#define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */ - -#define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */ -#define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */ -#define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */ -#define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */ -#define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */ -#define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */ -#define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */ -#define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */ - -/* USBCTL Control Bits */ -#define DIR (0x0001) /* USB - Data Response Bit */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -#define FRSTE (0x0010) /* USB - Function Reset Connection Enable */ -#define RWUP (0x0020) /* USB - Device Remote Wakeup Request */ -#define FEN (0x0040) /* USB - Function Enable Bit */ -//#define RESERVED (0x0080) /* USB - */ - -/* USBIE Control Bits */ -#define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */ -//#define RESERVED (0x0002) /* USB - */ -#define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -#define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */ -#define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */ -#define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */ - -/* USBIFG Control Bits */ -#define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */ -//#define RESERVED (0x0002) /* USB - */ -#define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -#define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */ -#define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */ -#define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */ - -//values of USBVECINT when USB-interrupt occured -#define USBVECINT_NONE 0x00 -#define USBVECINT_PWR_DROP 0x02 -#define USBVECINT_PLL_LOCK 0x04 -#define USBVECINT_PLL_SIGNAL 0x06 -#define USBVECINT_PLL_RANGE 0x08 -#define USBVECINT_PWR_VBUSOn 0x0A -#define USBVECINT_PWR_VBUSOff 0x0C -#define USBVECINT_USB_TIMESTAMP 0x10 -#define USBVECINT_INPUT_ENDPOINT0 0x12 -#define USBVECINT_OUTPUT_ENDPOINT0 0x14 -#define USBVECINT_RSTR 0x16 -#define USBVECINT_SUSR 0x18 -#define USBVECINT_RESR 0x1A -#define USBVECINT_SETUP_PACKET_RECEIVED 0x20 -#define USBVECINT_STPOW_PACKET_RECEIVED 0x22 -#define USBVECINT_INPUT_ENDPOINT1 0x24 -#define USBVECINT_INPUT_ENDPOINT2 0x26 -#define USBVECINT_INPUT_ENDPOINT3 0x28 -#define USBVECINT_INPUT_ENDPOINT4 0x2A -#define USBVECINT_INPUT_ENDPOINT5 0x2C -#define USBVECINT_INPUT_ENDPOINT6 0x2E -#define USBVECINT_INPUT_ENDPOINT7 0x30 -#define USBVECINT_OUTPUT_ENDPOINT1 0x32 -#define USBVECINT_OUTPUT_ENDPOINT2 0x34 -#define USBVECINT_OUTPUT_ENDPOINT3 0x36 -#define USBVECINT_OUTPUT_ENDPOINT4 0x38 -#define USBVECINT_OUTPUT_ENDPOINT5 0x3A -#define USBVECINT_OUTPUT_ENDPOINT6 0x3C -#define USBVECINT_OUTPUT_ENDPOINT7 0x3E - - -/* ========================================================================= */ -/* USB Operation Registers */ -/* ========================================================================= */ - -sfr_b(USBIEPSIZXY_7); /* Input Endpoint_7: X/Y-buffer size */ -sfr_b(USBIEPBCTY_7); /* Input Endpoint_7: Y-byte count */ -sfr_b(USBIEPBBAY_7); /* Input Endpoint_7: Y-buffer base addr. */ -//sfrb Spare (0x23FC) /* Not used */ -//sfrb Spare (0x23FB) /* Not used */ -sfr_b(USBIEPBCTX_7); /* Input Endpoint_7: X-byte count */ -sfr_b(USBIEPBBAX_7); /* Input Endpoint_7: X-buffer base addr. */ -sfr_b(USBIEPCNF_7); /* Input Endpoint_7: Configuration */ -sfr_b(USBIEPSIZXY_6); /* Input Endpoint_6: X/Y-buffer size */ -sfr_b(USBIEPBCTY_6); /* Input Endpoint_6: Y-byte count */ -sfr_b(USBIEPBBAY_6); /* Input Endpoint_6: Y-buffer base addr. */ -//sfrb Spare (0x23F4) /* Not used */ -//sfrb Spare (0x23F3) /* Not used */ -sfr_b(USBIEPBCTX_6); /* Input Endpoint_6: X-byte count */ -sfr_b(USBIEPBBAX_6); /* Input Endpoint_6: X-buffer base addr. */ -sfr_b(USBIEPCNF_6); /* Input Endpoint_6: Configuration */ -sfr_b(USBIEPSIZXY_5); /* Input Endpoint_5: X/Y-buffer size */ -sfr_b(USBIEPBCTY_5); /* Input Endpoint_5: Y-byte count */ -sfr_b(USBIEPBBAY_5); /* Input Endpoint_5: Y-buffer base addr. */ -//sfrb Spare (0x23EC) /* Not used */ -//sfrb Spare (0x23EB) /* Not used */ -sfr_b(USBIEPBCTX_5); /* Input Endpoint_5: X-byte count */ -sfr_b(USBIEPBBAX_5); /* Input Endpoint_5: X-buffer base addr. */ -sfr_b(USBIEPCNF_5); /* Input Endpoint_5: Configuration */ -sfr_b(USBIEPSIZXY_4); /* Input Endpoint_4: X/Y-buffer size */ -sfr_b(USBIEPBCTY_4); /* Input Endpoint_4: Y-byte count */ -sfr_b(USBIEPBBAY_4); /* Input Endpoint_4: Y-buffer base addr. */ -//sfrb Spare (0x23E4) /* Not used */ -//sfrb Spare (0x23E3) /* Not used */ -sfr_b(USBIEPBCTX_4); /* Input Endpoint_4: X-byte count */ -sfr_b(USBIEPBBAX_4); /* Input Endpoint_4: X-buffer base addr. */ -sfr_b(USBIEPCNF_4); /* Input Endpoint_4: Configuration */ -sfr_b(USBIEPSIZXY_3); /* Input Endpoint_3: X/Y-buffer size */ -sfr_b(USBIEPBCTY_3); /* Input Endpoint_3: Y-byte count */ -sfr_b(USBIEPBBAY_3); /* Input Endpoint_3: Y-buffer base addr. */ -//sfrb Spare (0x23DC) /* Not used */ -//sfrb Spare (0x23DB) /* Not used */ -sfr_b(USBIEPBCTX_3); /* Input Endpoint_3: X-byte count */ -sfr_b(USBIEPBBAX_3); /* Input Endpoint_3: X-buffer base addr. */ -sfr_b(USBIEPCNF_3); /* Input Endpoint_3: Configuration */ -sfr_b(USBIEPSIZXY_2); /* Input Endpoint_2: X/Y-buffer size */ -sfr_b(USBIEPBCTY_2); /* Input Endpoint_2: Y-byte count */ -sfr_b(USBIEPBBAY_2); /* Input Endpoint_2: Y-buffer base addr. */ -//sfrb Spare (0x23D4) /* Not used */ -//sfrb Spare (0x23D3) /* Not used */ -sfr_b(USBIEPBCTX_2); /* Input Endpoint_2: X-byte count */ -sfr_b(USBIEPBBAX_2); /* Input Endpoint_2: X-buffer base addr. */ -sfr_b(USBIEPCNF_2); /* Input Endpoint_2: Configuration */ -sfr_b(USBIEPSIZXY_1); /* Input Endpoint_1: X/Y-buffer size */ -sfr_b(USBIEPBCTY_1); /* Input Endpoint_1: Y-byte count */ -sfr_b(USBIEPBBAY_1); /* Input Endpoint_1: Y-buffer base addr. */ -//sfrb Spare (0x23CC) /* Not used */ -//sfrb Spare (0x23CB) /* Not used */ -sfr_b(USBIEPBCTX_1); /* Input Endpoint_1: X-byte count */ -sfr_b(USBIEPBBAX_1); /* Input Endpoint_1: X-buffer base addr. */ -sfr_b(USBIEPCNF_1); /* Input Endpoint_1: Configuration */ -//sfrb (0x23C7) /* */ -//sfrb RESERVED (0x1C00) /* */ -//sfrb (0x23C0) /* */ -sfr_b(USBOEPSIZXY_7); /* Output Endpoint_7: X/Y-buffer size */ -sfr_b(USBOEPBCTY_7); /* Output Endpoint_7: Y-byte count */ -sfr_b(USBOEPBBAY_7); /* Output Endpoint_7: Y-buffer base addr. */ -//sfrb Spare (0x23BC) /* Not used */ -//sfrb Spare (0x23BB) /* Not used */ -sfr_b(USBOEPBCTX_7); /* Output Endpoint_7: X-byte count */ -sfr_b(USBOEPBBAX_7); /* Output Endpoint_7: X-buffer base addr. */ -sfr_b(USBOEPCNF_7); /* Output Endpoint_7: Configuration */ -sfr_b(USBOEPSIZXY_6); /* Output Endpoint_6: X/Y-buffer size */ -sfr_b(USBOEPBCTY_6); /* Output Endpoint_6: Y-byte count */ -sfr_b(USBOEPBBAY_6); /* Output Endpoint_6: Y-buffer base addr. */ -//sfrb Spare (0x23B4) /* Not used */ -//sfrb Spare (0x23B3) /* Not used */ -sfr_b(USBOEPBCTX_6); /* Output Endpoint_6: X-byte count */ -sfr_b(USBOEPBBAX_6); /* Output Endpoint_6: X-buffer base addr. */ -sfr_b(USBOEPCNF_6); /* Output Endpoint_6: Configuration */ -sfr_b(USBOEPSIZXY_5); /* Output Endpoint_5: X/Y-buffer size */ -sfr_b(USBOEPBCTY_5); /* Output Endpoint_5: Y-byte count */ -sfr_b(USBOEPBBAY_5); /* Output Endpoint_5: Y-buffer base addr. */ -//sfrb Spare (0x23AC) /* Not used */ -//sfrb Spare (0x23AB) /* Not used */ -sfr_b(USBOEPBCTX_5); /* Output Endpoint_5: X-byte count */ -sfr_b(USBOEPBBAX_5); /* Output Endpoint_5: X-buffer base addr. */ -sfr_b(USBOEPCNF_5); /* Output Endpoint_5: Configuration */ -sfr_b(USBOEPSIZXY_4); /* Output Endpoint_4: X/Y-buffer size */ -sfr_b(USBOEPBCTY_4); /* Output Endpoint_4: Y-byte count */ -sfr_b(USBOEPBBAY_4); /* Output Endpoint_4: Y-buffer base addr. */ -//sfrb Spare (0x23A4) /* Not used */ -//sfrb Spare (0x23A3) /* Not used */ -sfr_b(USBOEPBCTX_4); /* Output Endpoint_4: X-byte count */ -sfr_b(USBOEPBBAX_4); /* Output Endpoint_4: X-buffer base addr. */ -sfr_b(USBOEPCNF_4); /* Output Endpoint_4: Configuration */ -sfr_b(USBOEPSIZXY_3); /* Output Endpoint_3: X/Y-buffer size */ -sfr_b(USBOEPBCTY_3); /* Output Endpoint_3: Y-byte count */ -sfr_b(USBOEPBBAY_3); /* Output Endpoint_3: Y-buffer base addr. */ -//sfrb Spare (0x239C) /* Not used */ -//sfrb Spare (0x239B) /* Not used */ -sfr_b(USBOEPBCTX_3); /* Output Endpoint_3: X-byte count */ -sfr_b(USBOEPBBAX_3); /* Output Endpoint_3: X-buffer base addr. */ -sfr_b(USBOEPCNF_3); /* Output Endpoint_3: Configuration */ -sfr_b(USBOEPSIZXY_2); /* Output Endpoint_2: X/Y-buffer size */ -sfr_b(USBOEPBCTY_2); /* Output Endpoint_2: Y-byte count */ -sfr_b(USBOEPBBAY_2); /* Output Endpoint_2: Y-buffer base addr. */ -//sfrb Spare (0x2394) /* Not used */ -//sfrb Spare (0x2393) /* Not used */ -sfr_b(USBOEPBCTX_2); /* Output Endpoint_2: X-byte count */ -sfr_b(USBOEPBBAX_2); /* Output Endpoint_2: X-buffer base addr. */ -sfr_b(USBOEPCNF_2); /* Output Endpoint_2: Configuration */ -sfr_b(USBOEPSIZXY_1); /* Output Endpoint_1: X/Y-buffer size */ -sfr_b(USBOEPBCTY_1); /* Output Endpoint_1: Y-byte count */ -sfr_b(USBOEPBBAY_1); /* Output Endpoint_1: Y-buffer base addr. */ -//sfrb Spare (0x238C) /* Not used */ -//sfrb Spare (0x238B) /* Not used */ -sfr_b(USBOEPBCTX_1); /* Output Endpoint_1: X-byte count */ -sfr_b(USBOEPBBAX_1); /* Output Endpoint_1: X-buffer base addr. */ -sfr_b(USBOEPCNF_1); /* Output Endpoint_1: Configuration */ -sfr_b(USBSUBLK); /* Setup Packet Block */ -sfr_b(USBIEP0BUF); /* Input endpoint_0 buffer */ -sfr_b(USBOEP0BUF); /* Output endpoint_0 buffer */ -sfr_b(USBTOPBUFF); /* Top of buffer space */ -// (1904 Bytes) /* Buffer space */ -sfr_b(USBSTABUFF); /* Start of buffer space */ - -/* USBIEPCNF_n Control Bits */ -/* USBOEPCNF_n Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0001) /* USB - */ -#define DBUF (0x0010) /* USB - Double Buffer Enable */ -//#define RESERVED (0x0040) /* USB - */ - -/* USBIEPBCNT_n Control Bits */ -/* USBOEPBCNT_n Control Bits */ -#define CNT4 (0x0010) /* USB - Byte Count Bit 3 */ -#define CNT5 (0x0020) /* USB - Byte Count Bit 3 */ -#define CNT6 (0x0040) /* USB - Byte Count Bit 3 */ -/************************************************************ -* UNIFIED CLOCK SYSTEM -************************************************************/ -#define __MSP430_HAS_UCS__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_UCS__ 0x0160 -#define UCS_BASE __MSP430_BASEADDRESS_UCS__ - -sfr_w(UCSCTL0); /* UCS Control Register 0 */ -sfr_b(UCSCTL0_L); /* UCS Control Register 0 */ -sfr_b(UCSCTL0_H); /* UCS Control Register 0 */ -sfr_w(UCSCTL1); /* UCS Control Register 1 */ -sfr_b(UCSCTL1_L); /* UCS Control Register 1 */ -sfr_b(UCSCTL1_H); /* UCS Control Register 1 */ -sfr_w(UCSCTL2); /* UCS Control Register 2 */ -sfr_b(UCSCTL2_L); /* UCS Control Register 2 */ -sfr_b(UCSCTL2_H); /* UCS Control Register 2 */ -sfr_w(UCSCTL3); /* UCS Control Register 3 */ -sfr_b(UCSCTL3_L); /* UCS Control Register 3 */ -sfr_b(UCSCTL3_H); /* UCS Control Register 3 */ -sfr_w(UCSCTL4); /* UCS Control Register 4 */ -sfr_b(UCSCTL4_L); /* UCS Control Register 4 */ -sfr_b(UCSCTL4_H); /* UCS Control Register 4 */ -sfr_w(UCSCTL5); /* UCS Control Register 5 */ -sfr_b(UCSCTL5_L); /* UCS Control Register 5 */ -sfr_b(UCSCTL5_H); /* UCS Control Register 5 */ -sfr_w(UCSCTL6); /* UCS Control Register 6 */ -sfr_b(UCSCTL6_L); /* UCS Control Register 6 */ -sfr_b(UCSCTL6_H); /* UCS Control Register 6 */ -sfr_w(UCSCTL7); /* UCS Control Register 7 */ -sfr_b(UCSCTL7_L); /* UCS Control Register 7 */ -sfr_b(UCSCTL7_H); /* UCS Control Register 7 */ -sfr_w(UCSCTL8); /* UCS Control Register 8 */ -sfr_b(UCSCTL8_L); /* UCS Control Register 8 */ -sfr_b(UCSCTL8_H); /* UCS Control Register 8 */ - -/* UCSCTL0 Control Bits */ -//#define RESERVED (0x0001) /* RESERVED */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ -#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ -#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ -#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ -#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ -#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ -#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ -#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ -#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ -#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL0 Control Bits */ -//#define RESERVED (0x0001) /* RESERVED */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ -#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ -#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ -#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ -#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL0 Control Bits */ -//#define RESERVED (0x0001) /* RESERVED */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ -#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ -#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ -#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ -#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL1 Control Bits */ -#define DISMOD (0x0001) /* Disable Modulation */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ -#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ -#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL1 Control Bits */ -#define DISMOD_L (0x0001) /* Disable Modulation */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ -#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ -#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ -#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ -#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ -#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ -#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ -#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ -#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ -#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ - -/* UCSCTL2 Control Bits */ -#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ -#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ -#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ -#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ -#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ -#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ -#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ -#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ -#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ -#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ -#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ -#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL2 Control Bits */ -#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ -#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ -#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ -#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ -#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ -#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ -#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ -#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL2 Control Bits */ -#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ -#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ -#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ -#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ -#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ -#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ -#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ -#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ -#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ -#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ -#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ -#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ -#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ -#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ -#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ -#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ -#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ - -/* UCSCTL3 Control Bits */ -#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ -#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ -#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ -#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ -#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL3 Control Bits */ -#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ -#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ -#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ -#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ -#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ -#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ -#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ -#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ -#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ -#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ -#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ -#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ -#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ -#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ -#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ -#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ -#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ -#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ -#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ -#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ -#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ -#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ -#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ -#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ -#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ -#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ -#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ -#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ -#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ - -/* UCSCTL4 Control Bits */ -#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ -#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ -#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ -#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ -#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ -#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ -#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL4 Control Bits */ -#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ -#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ -#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ -#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ -#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL4 Control Bits */ -//#define RESERVED (0x0008) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ -#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ -#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define SELM_0 (0x0000) /* MCLK Source Select 0 */ -#define SELM_1 (0x0001) /* MCLK Source Select 1 */ -#define SELM_2 (0x0002) /* MCLK Source Select 2 */ -#define SELM_3 (0x0003) /* MCLK Source Select 3 */ -#define SELM_4 (0x0004) /* MCLK Source Select 4 */ -#define SELM_5 (0x0005) /* MCLK Source Select 5 */ -#define SELM_6 (0x0006) /* MCLK Source Select 6 */ -#define SELM_7 (0x0007) /* MCLK Source Select 7 */ -#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ -#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ -#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ -#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ -#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ -#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ - -#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ -#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ -#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ -#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ -#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ -#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ -#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ -#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ -#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ -#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ -#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ -#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ -#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ -#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ - -#define SELA_0 (0x0000) /* ACLK Source Select 0 */ -#define SELA_1 (0x0100) /* ACLK Source Select 1 */ -#define SELA_2 (0x0200) /* ACLK Source Select 2 */ -#define SELA_3 (0x0300) /* ACLK Source Select 3 */ -#define SELA_4 (0x0400) /* ACLK Source Select 4 */ -#define SELA_5 (0x0500) /* ACLK Source Select 5 */ -#define SELA_6 (0x0600) /* ACLK Source Select 6 */ -#define SELA_7 (0x0700) /* ACLK Source Select 7 */ -#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ -#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ -#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ -#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ -#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ -#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ - -/* UCSCTL5 Control Bits */ -#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ -#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ -#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ -#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ -#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ -#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ -#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ -#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ -#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL5 Control Bits */ -#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ -#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ -#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ -#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ -#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL5 Control Bits */ -//#define RESERVED (0x0008) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ -#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ -#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ -#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ -#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ -#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ -#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ -#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ -#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ -#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ -#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ -#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ -#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ -#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ -#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ -#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ -#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ -#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ - -#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ -#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ -#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ -#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ -#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ -#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ -#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ -#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ -#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ -#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ -#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ -#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ -#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ -#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ - -#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ -#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ -#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ -#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ -#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ -#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ -#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ -#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ -#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ -#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ -#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ -#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ -#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ -#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ - -#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ -#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ -#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ -#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ -#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ -#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ -#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ -#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ -#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ -#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ -#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ -#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ -#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ -#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ - -/* UCSCTL6 Control Bits */ -#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ -#define SMCLKOFF (0x0002) /* SMCLK Off */ -#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ -#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ -#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ -#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ -#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ -#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ -#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ -//#define RESERVED (0x2000) /* RESERVED */ -#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */ -#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */ - -/* UCSCTL6 Control Bits */ -#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ -#define SMCLKOFF_L (0x0002) /* SMCLK Off */ -#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ -#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ -#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ -#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ -#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ -#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ - -/* UCSCTL6 Control Bits */ -#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ -//#define RESERVED (0x2000) /* RESERVED */ -#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */ -#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */ - -#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ -#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ -#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ -#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ -#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ -#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ -#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ -#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ -#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */ -#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */ -#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */ -#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */ - -/* UCSCTL7 Control Bits */ -#define DCOFFG (0x0001) /* DCO Fault Flag */ -#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ -//#define RESERVED (0x0004) /* RESERVED */ -#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL7 Control Bits */ -#define DCOFFG_L (0x0001) /* DCO Fault Flag */ -#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ -//#define RESERVED (0x0004) /* RESERVED */ -#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL8 Control Bits */ -#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ -#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ -#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ -#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL8 Control Bits */ -#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ -#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ -#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ -#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/************************************************************ -* USCI A0 -************************************************************/ -#define __MSP430_HAS_USCI_A0__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0 -#define USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__ - -sfr_w(UCA0CTLW0); /* USCI A0 Control Word Register 0 */ -sfr_b(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */ -sfr_b(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */ -#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ -#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ -sfr_w(UCA0BRW); /* USCI A0 Baud Word Rate 0 */ -sfr_b(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */ -sfr_b(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */ -#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ -#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ -sfr_b(UCA0MCTL); /* USCI A0 Modulation Control */ -sfr_b(UCA0STAT); /* USCI A0 Status Register */ -sfr_b(UCA0RXBUF); /* USCI A0 Receive Buffer */ -sfr_b(UCA0TXBUF); /* USCI A0 Transmit Buffer */ -sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */ -sfr_w(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */ -sfr_b(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */ -sfr_b(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */ -#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ -#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ -sfr_w(UCA0ICTL); /* USCI A0 Interrupt Enable Register */ -sfr_b(UCA0ICTL_L); /* USCI A0 Interrupt Enable Register */ -sfr_b(UCA0ICTL_H); /* USCI A0 Interrupt Enable Register */ -#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */ -#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */ -sfr_w(UCA0IV); /* USCI A0 Interrupt Vector Register */ - - -/************************************************************ -* USCI B0 -************************************************************/ -#define __MSP430_HAS_USCI_B0__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0 -#define USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__ - - -sfr_w(UCB0CTLW0); /* USCI B0 Control Word Register 0 */ -sfr_b(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */ -sfr_b(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */ -#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ -#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ -sfr_w(UCB0BRW); /* USCI B0 Baud Word Rate 0 */ -sfr_b(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */ -sfr_b(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */ -#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ -#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ -sfr_b(UCB0STAT); /* USCI B0 Status Register */ -sfr_b(UCB0RXBUF); /* USCI B0 Receive Buffer */ -sfr_b(UCB0TXBUF); /* USCI B0 Transmit Buffer */ -sfr_w(UCB0I2COA); /* USCI B0 I2C Own Address */ -sfr_b(UCB0I2COA_L); /* USCI B0 I2C Own Address */ -sfr_b(UCB0I2COA_H); /* USCI B0 I2C Own Address */ -sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */ -sfr_b(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */ -sfr_b(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */ -sfr_w(UCB0ICTL); /* USCI B0 Interrupt Enable Register */ -sfr_b(UCB0ICTL_L); /* USCI B0 Interrupt Enable Register */ -sfr_b(UCB0ICTL_H); /* USCI B0 Interrupt Enable Register */ -#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */ -#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */ -sfr_w(UCB0IV); /* USCI B0 Interrupt Vector Register */ - -// UCAxCTL0 UART-Mode Control Bits -#define UCPEN (0x80) /* Async. Mode: Parity enable */ -#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ -#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ -#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ -#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ -#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ -#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ -#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ - -// UCxxCTL0 SPI-Mode Control Bits -#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ -#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ -#define UCMST (0x08) /* Sync. Mode: Master Select */ - -// UCBxCTL0 I2C-Mode Control Bits -#define UCA10 (0x80) /* 10-bit Address Mode */ -#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ -#define UCMM (0x20) /* Multi-Master Environment */ -//#define res (0x10) /* reserved */ -#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ -#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ -#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ -#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ - -// UCAxCTL1 UART-Mode Control Bits -#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ -#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ -#define UCRXEIE (0x20) /* RX Error interrupt enable */ -#define UCBRKIE (0x10) /* Break interrupt enable */ -#define UCDORM (0x08) /* Dormant (Sleep) Mode */ -#define UCTXADDR (0x04) /* Send next Data as Address */ -#define UCTXBRK (0x02) /* Send next Data as Break */ -#define UCSWRST (0x01) /* USCI Software Reset */ - -// UCxxCTL1 SPI-Mode Control Bits -//#define res (0x20) /* reserved */ -//#define res (0x10) /* reserved */ -//#define res (0x08) /* reserved */ -//#define res (0x04) /* reserved */ -//#define res (0x02) /* reserved */ - -// UCBxCTL1 I2C-Mode Control Bits -//#define res (0x20) /* reserved */ -#define UCTR (0x10) /* Transmit/Receive Select/Flag */ -#define UCTXNACK (0x08) /* Transmit NACK */ -#define UCTXSTP (0x04) /* Transmit STOP */ -#define UCTXSTT (0x02) /* Transmit START */ -#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ -#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ -#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ -#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ -#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ -#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ -#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ - -/* UCAxMCTL Control Bits */ -#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ -#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ -#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ -#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ -#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ -#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ -#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ -#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ - -#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ -#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ -#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ -#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ -#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ -#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ -#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ -#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ -#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ -#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ -#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ -#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ -#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ -#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ -#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ -#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ - -#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ -#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ -#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ -#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ -#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ -#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ -#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ -#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ - -/* UCAxSTAT Control Bits */ -#define UCLISTEN (0x80) /* USCI Listen mode */ -#define UCFE (0x40) /* USCI Frame Error Flag */ -#define UCOE (0x20) /* USCI Overrun Error Flag */ -#define UCPE (0x10) /* USCI Parity Error Flag */ -#define UCBRK (0x08) /* USCI Break received */ -#define UCRXERR (0x04) /* USCI RX Error Flag */ -#define UCADDR (0x02) /* USCI Address received Flag */ -#define UCBUSY (0x01) /* USCI Busy Flag */ -#define UCIDLE (0x02) /* USCI Idle line detected Flag */ - -/* UCBxSTAT Control Bits */ -#define UCSCLLOW (0x40) /* SCL low */ -#define UCGC (0x20) /* General Call address received Flag */ -#define UCBBUSY (0x10) /* Bus Busy Flag */ - -/* UCAxIRTCTL Control Bits */ -#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ -#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ -#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ -#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ -#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ -#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ -#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ -#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ - -/* UCAxIRRCTL Control Bits */ -#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ -#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ -#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ -#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ -#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ -#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ -#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ -#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ - -/* UCAxABCTL Control Bits */ -//#define res (0x80) /* reserved */ -//#define res (0x40) /* reserved */ -#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ -#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ -#define UCSTOE (0x08) /* Sync-Field Timeout error */ -#define UCBTOE (0x04) /* Break Timeout error */ -//#define res (0x02) /* reserved */ -#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ - -/* UCBxI2COA Control Bits */ -#define UCGCEN (0x8000) /* I2C General Call enable */ -#define UCOA9 (0x0200) /* I2C Own Address 9 */ -#define UCOA8 (0x0100) /* I2C Own Address 8 */ -#define UCOA7 (0x0080) /* I2C Own Address 7 */ -#define UCOA6 (0x0040) /* I2C Own Address 6 */ -#define UCOA5 (0x0020) /* I2C Own Address 5 */ -#define UCOA4 (0x0010) /* I2C Own Address 4 */ -#define UCOA3 (0x0008) /* I2C Own Address 3 */ -#define UCOA2 (0x0004) /* I2C Own Address 2 */ -#define UCOA1 (0x0002) /* I2C Own Address 1 */ -#define UCOA0 (0x0001) /* I2C Own Address 0 */ - -/* UCBxI2COA Control Bits */ -#define UCOA7_L (0x0080) /* I2C Own Address 7 */ -#define UCOA6_L (0x0040) /* I2C Own Address 6 */ -#define UCOA5_L (0x0020) /* I2C Own Address 5 */ -#define UCOA4_L (0x0010) /* I2C Own Address 4 */ -#define UCOA3_L (0x0008) /* I2C Own Address 3 */ -#define UCOA2_L (0x0004) /* I2C Own Address 2 */ -#define UCOA1_L (0x0002) /* I2C Own Address 1 */ -#define UCOA0_L (0x0001) /* I2C Own Address 0 */ - -/* UCBxI2COA Control Bits */ -#define UCGCEN_H (0x0080) /* I2C General Call enable */ -#define UCOA9_H (0x0002) /* I2C Own Address 9 */ -#define UCOA8_H (0x0001) /* I2C Own Address 8 */ - -/* UCBxI2CSA Control Bits */ -#define UCSA9 (0x0200) /* I2C Slave Address 9 */ -#define UCSA8 (0x0100) /* I2C Slave Address 8 */ -#define UCSA7 (0x0080) /* I2C Slave Address 7 */ -#define UCSA6 (0x0040) /* I2C Slave Address 6 */ -#define UCSA5 (0x0020) /* I2C Slave Address 5 */ -#define UCSA4 (0x0010) /* I2C Slave Address 4 */ -#define UCSA3 (0x0008) /* I2C Slave Address 3 */ -#define UCSA2 (0x0004) /* I2C Slave Address 2 */ -#define UCSA1 (0x0002) /* I2C Slave Address 1 */ -#define UCSA0 (0x0001) /* I2C Slave Address 0 */ - -/* UCBxI2CSA Control Bits */ -#define UCSA7_L (0x0080) /* I2C Slave Address 7 */ -#define UCSA6_L (0x0040) /* I2C Slave Address 6 */ -#define UCSA5_L (0x0020) /* I2C Slave Address 5 */ -#define UCSA4_L (0x0010) /* I2C Slave Address 4 */ -#define UCSA3_L (0x0008) /* I2C Slave Address 3 */ -#define UCSA2_L (0x0004) /* I2C Slave Address 2 */ -#define UCSA1_L (0x0002) /* I2C Slave Address 1 */ -#define UCSA0_L (0x0001) /* I2C Slave Address 0 */ - -/* UCBxI2CSA Control Bits */ -#define UCSA9_H (0x0002) /* I2C Slave Address 9 */ -#define UCSA8_H (0x0001) /* I2C Slave Address 8 */ - -/* UCAxIE Control Bits */ -#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ -#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ - -/* UCBxIE Control Bits */ -#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */ -#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */ -#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */ -#define UCSTTIE (0x0004) /* START Condition interrupt enable */ -#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ -#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ - -/* UCAxIFG Control Bits */ -#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ -#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ - -/* UCBxIFG Control Bits */ -#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */ -#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */ -#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */ -#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */ -#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ -#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ - -/* USCI Interrupt Vector Definitions */ -#define USCI_NONE (0x0000) /* No Interrupt pending */ -#define USCI_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */ -#define USCI_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */ -#define USCI_I2C_UCALIFG (0x0002) /* Interrupt Vector: I2C Mode: UCALIFG */ -#define USCI_I2C_UCNACKIFG (0x0004) /* Interrupt Vector: I2C Mode: UCNACKIFG */ -#define USCI_I2C_UCSTTIFG (0x0006) /* Interrupt Vector: I2C Mode: UCSTTIFG*/ -#define USCI_I2C_UCSTPIFG (0x0008) /* Interrupt Vector: I2C Mode: UCSTPIFG*/ -#define USCI_I2C_UCRXIFG (0x000A) /* Interrupt Vector: I2C Mode: UCRXIFG */ -#define USCI_I2C_UCTXIFG (0x000C) /* Interrupt Vector: I2C Mode: UCTXIFG */ - -/************************************************************ -* USCI A1 -************************************************************/ -#define __MSP430_HAS_USCI_A1__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_A1__ 0x0600 -#define USCI_A1_BASE __MSP430_BASEADDRESS_USCI_A1__ - -sfr_w(UCA1CTLW0); /* USCI A1 Control Word Register 0 */ -sfr_b(UCA1CTLW0_L); /* USCI A1 Control Word Register 0 */ -sfr_b(UCA1CTLW0_H); /* USCI A1 Control Word Register 0 */ -#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */ -#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */ -sfr_w(UCA1BRW); /* USCI A1 Baud Word Rate 0 */ -sfr_b(UCA1BRW_L); /* USCI A1 Baud Word Rate 0 */ -sfr_b(UCA1BRW_H); /* USCI A1 Baud Word Rate 0 */ -#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */ -#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */ -sfr_b(UCA1MCTL); /* USCI A1 Modulation Control */ -sfr_b(UCA1STAT); /* USCI A1 Status Register */ -sfr_b(UCA1RXBUF); /* USCI A1 Receive Buffer */ -sfr_b(UCA1TXBUF); /* USCI A1 Transmit Buffer */ -sfr_b(UCA1ABCTL); /* USCI A1 LIN Control */ -sfr_w(UCA1IRCTL); /* USCI A1 IrDA Transmit Control */ -sfr_b(UCA1IRCTL_L); /* USCI A1 IrDA Transmit Control */ -sfr_b(UCA1IRCTL_H); /* USCI A1 IrDA Transmit Control */ -#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */ -#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */ -sfr_w(UCA1ICTL); /* USCI A1 Interrupt Enable Register */ -sfr_b(UCA1ICTL_L); /* USCI A1 Interrupt Enable Register */ -sfr_b(UCA1ICTL_H); /* USCI A1 Interrupt Enable Register */ -#define UCA1IE UCA1ICTL_L /* USCI A1 Interrupt Enable Register */ -#define UCA1IFG UCA1ICTL_H /* USCI A1 Interrupt Flags Register */ -sfr_w(UCA1IV); /* USCI A1 Interrupt Vector Register */ - - -/************************************************************ -* USCI B1 -************************************************************/ -#define __MSP430_HAS_USCI_B1__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_B1__ 0x0620 -#define USCI_B1_BASE __MSP430_BASEADDRESS_USCI_B1__ - - -sfr_w(UCB1CTLW0); /* USCI B1 Control Word Register 0 */ -sfr_b(UCB1CTLW0_L); /* USCI B1 Control Word Register 0 */ -sfr_b(UCB1CTLW0_H); /* USCI B1 Control Word Register 0 */ -#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */ -#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */ -sfr_w(UCB1BRW); /* USCI B1 Baud Word Rate 0 */ -sfr_b(UCB1BRW_L); /* USCI B1 Baud Word Rate 0 */ -sfr_b(UCB1BRW_H); /* USCI B1 Baud Word Rate 0 */ -#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */ -#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */ -sfr_b(UCB1STAT); /* USCI B1 Status Register */ -sfr_b(UCB1RXBUF); /* USCI B1 Receive Buffer */ -sfr_b(UCB1TXBUF); /* USCI B1 Transmit Buffer */ -sfr_w(UCB1I2COA); /* USCI B1 I2C Own Address */ -sfr_b(UCB1I2COA_L); /* USCI B1 I2C Own Address */ -sfr_b(UCB1I2COA_H); /* USCI B1 I2C Own Address */ -sfr_w(UCB1I2CSA); /* USCI B1 I2C Slave Address */ -sfr_b(UCB1I2CSA_L); /* USCI B1 I2C Slave Address */ -sfr_b(UCB1I2CSA_H); /* USCI B1 I2C Slave Address */ -sfr_w(UCB1ICTL); /* USCI B1 Interrupt Enable Register */ -sfr_b(UCB1ICTL_L); /* USCI B1 Interrupt Enable Register */ -sfr_b(UCB1ICTL_H); /* USCI B1 Interrupt Enable Register */ -#define UCB1IE UCB1ICTL_L /* USCI B1 Interrupt Enable Register */ -#define UCB1IFG UCB1ICTL_H /* USCI B1 Interrupt Flags Register */ -sfr_w(UCB1IV); /* USCI B1 Interrupt Vector Register */ - -/************************************************************ -* WATCHDOG TIMER A -************************************************************/ -#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_WDT_A__ 0x0150 -#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ - -sfr_w(WDTCTL); /* Watchdog Timer Control */ -sfr_b(WDTCTL_L); /* Watchdog Timer Control */ -sfr_b(WDTCTL_H); /* Watchdog Timer Control */ -/* The bit names have been prefixed with "WDT" */ -/* WDTCTL Control Bits */ -#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ -#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ -#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ -#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ -#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ -#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ -#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ -#define WDTHOLD (0x0080) /* WDT - Timer hold */ - -/* WDTCTL Control Bits */ -#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ -#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ -#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ -#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ -#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ -#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ -#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ -#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ - -#define WDTPW (0x5A00) - -#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */ -#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */ -#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */ -#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */ -#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */ -#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */ -#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */ -#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */ -#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */ -#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */ -#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */ -#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */ -#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */ -#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */ -#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */ -#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */ - -#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ -#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */ -#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ -#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */ -#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ -#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */ -#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ - -/* WDT-interval times [1ms] coded with Bits 0-2 */ -/* WDT is clocked by fSMCLK (assumed 1MHz) */ -#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ -#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ -#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ -#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ -/* WDT is clocked by fACLK (assumed 32KHz) */ -#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ -#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ -#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ -#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ -/* Watchdog mode -> reset after expired time */ -/* WDT is clocked by fSMCLK (assumed 1MHz) */ -#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ -#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ -#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ -#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ -/* WDT is clocked by fACLK (assumed 32KHz) */ -#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ -#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ -#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ -#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ - - -/************************************************************ -* TLV Descriptors -************************************************************/ -#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ -#define TLV_BASE __MSP430_BASEADDRESS_TLV__ - -#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ -#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ -#define TLV_START (0x1A08) /* Start Address of the TLV structure */ -#define TLV_END (0x1AFF) /* End Address of the TLV structure */ - -#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ -#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ -#define TLV_Reserved3 (0x03) /* Future usage */ -#define TLV_Reserved4 (0x04) /* Future usage */ -#define TLV_BLANK (0x05) /* Blank descriptor */ -#define TLV_Reserved6 (0x06) /* Future usage */ -#define TLV_Reserved7 (0x07) /* Serial Number */ -#define TLV_DIERECORD (0x08) /* Die Record */ -#define TLV_ADCCAL (0x11) /* ADC12 calibration */ -#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ -#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ -#define TLV_REFCAL (0x12) /* REF calibration */ -#define TLV_TAGEXT (0xFE) /* Tag extender */ -#define TLV_TAGEND (0xFF) // Tag End of Table - -/************************************************************ -* Interrupt Vectors (offset from 0xFF80) -************************************************************/ - - -#define RTC_VECTOR (42) /* 0xFFD2 RTC */ -#define PORT2_VECTOR (43) /* 0xFFD4 Port 2 */ -#define TIMER2_A1_VECTOR (44) /* 0xFFD6 Timer2_A5 CC1-4, TA */ -#define TIMER2_A0_VECTOR (45) /* 0xFFD8 Timer2_A5 CC0 */ -#define USCI_B1_VECTOR (46) /* 0xFFDA USCI B1 Receive/Transmit */ -#define USCI_A1_VECTOR (47) /* 0xFFDC USCI A1 Receive/Transmit */ -#define PORT1_VECTOR (48) /* 0xFFDE Port 1 */ -#define TIMER1_A1_VECTOR (49) /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ -#define TIMER1_A0_VECTOR (50) /* 0xFFE2 Timer1_A3 CC0 */ -#define DMA_VECTOR (51) /* 0xFFE4 DMA */ -#define USB_UBM_VECTOR (52) /* 0xFFE6 USB Timer / cable event / USB reset */ -#define TIMER0_A1_VECTOR (53) /* 0xFFE8 Timer0_A5 CC1-4, TA */ -#define TIMER0_A0_VECTOR (54) /* 0xFFEA Timer0_A5 CC0 */ -#define ADC12_VECTOR (55) /* 0xFFEC ADC */ -#define USCI_B0_VECTOR (56) /* 0xFFEE USCI B0 Receive/Transmit */ -#define USCI_A0_VECTOR (57) /* 0xFFF0 USCI A0 Receive/Transmit */ -#define WDT_VECTOR (58) /* 0xFFF2 Watchdog Timer */ -#define TIMER0_B1_VECTOR (59) /* 0xFFF4 Timer0_B7 CC1-6, TB */ -#define TIMER0_B0_VECTOR (60) /* 0xFFF6 Timer0_B7 CC0 */ -#define COMP_B_VECTOR (61) /* 0xFFF8 Comparator B */ -#define UNMI_VECTOR (62) /* 0xFFFA User Non-maskable */ -#define SYSNMI_VECTOR (63) /* 0xFFFC System Non-maskable */ -#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ - -/************************************************************ -* End of Modules -************************************************************/ - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif /* #ifndef __MSP430F5529 */ - diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529.ld b/hw/bsp/msp_exp430f5529lp/msp430f5529.ld deleted file mode 100644 index 6fe18de01..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430f5529.ld +++ /dev/null @@ -1,457 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2019, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/* This file supports MSP430F5529 devices. */ -/* Version: 1.207 */ -/* Default linker script, for normal executables */ - -OUTPUT_ARCH(msp430) -ENTRY(_start) - -MEMORY { - SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ - BSL : ORIGIN = 0x1000, LENGTH = 0x0800 - RAM : ORIGIN = 0x2400, LENGTH = 0x2000 /* END=0x43FF, size 8192 */ - USBRAM : ORIGIN = 0x1C00, LENGTH = 0x0800 - INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 as 4 128-byte segments */ - INFOA : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x19FF, size 128 */ - INFOB : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x197F, size 128 */ - INFOC : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x18FF, size 128 */ - INFOD : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x187F, size 128 */ - ROM (rx) : ORIGIN = 0x4400, LENGTH = 0xBB80 /* END=0xFF7F, size 48000 */ - HIROM (rx) : ORIGIN = 0x00010000, LENGTH = 0x000143FF - VECT1 : ORIGIN = 0xFF80, LENGTH = 0x0002 - VECT2 : ORIGIN = 0xFF82, LENGTH = 0x0002 - VECT3 : ORIGIN = 0xFF84, LENGTH = 0x0002 - VECT4 : ORIGIN = 0xFF86, LENGTH = 0x0002 - VECT5 : ORIGIN = 0xFF88, LENGTH = 0x0002 - VECT6 : ORIGIN = 0xFF8A, LENGTH = 0x0002 - VECT7 : ORIGIN = 0xFF8C, LENGTH = 0x0002 - VECT8 : ORIGIN = 0xFF8E, LENGTH = 0x0002 - VECT9 : ORIGIN = 0xFF90, LENGTH = 0x0002 - VECT10 : ORIGIN = 0xFF92, LENGTH = 0x0002 - VECT11 : ORIGIN = 0xFF94, LENGTH = 0x0002 - VECT12 : ORIGIN = 0xFF96, LENGTH = 0x0002 - VECT13 : ORIGIN = 0xFF98, LENGTH = 0x0002 - VECT14 : ORIGIN = 0xFF9A, LENGTH = 0x0002 - VECT15 : ORIGIN = 0xFF9C, LENGTH = 0x0002 - VECT16 : ORIGIN = 0xFF9E, LENGTH = 0x0002 - VECT17 : ORIGIN = 0xFFA0, LENGTH = 0x0002 - VECT18 : ORIGIN = 0xFFA2, LENGTH = 0x0002 - VECT19 : ORIGIN = 0xFFA4, LENGTH = 0x0002 - VECT20 : ORIGIN = 0xFFA6, LENGTH = 0x0002 - VECT21 : ORIGIN = 0xFFA8, LENGTH = 0x0002 - VECT22 : ORIGIN = 0xFFAA, LENGTH = 0x0002 - VECT23 : ORIGIN = 0xFFAC, LENGTH = 0x0002 - VECT24 : ORIGIN = 0xFFAE, LENGTH = 0x0002 - VECT25 : ORIGIN = 0xFFB0, LENGTH = 0x0002 - VECT26 : ORIGIN = 0xFFB2, LENGTH = 0x0002 - VECT27 : ORIGIN = 0xFFB4, LENGTH = 0x0002 - VECT28 : ORIGIN = 0xFFB6, LENGTH = 0x0002 - VECT29 : ORIGIN = 0xFFB8, LENGTH = 0x0002 - VECT30 : ORIGIN = 0xFFBA, LENGTH = 0x0002 - VECT31 : ORIGIN = 0xFFBC, LENGTH = 0x0002 - VECT32 : ORIGIN = 0xFFBE, LENGTH = 0x0002 - VECT33 : ORIGIN = 0xFFC0, LENGTH = 0x0002 - VECT34 : ORIGIN = 0xFFC2, LENGTH = 0x0002 - VECT35 : ORIGIN = 0xFFC4, LENGTH = 0x0002 - VECT36 : ORIGIN = 0xFFC6, LENGTH = 0x0002 - VECT37 : ORIGIN = 0xFFC8, LENGTH = 0x0002 - VECT38 : ORIGIN = 0xFFCA, LENGTH = 0x0002 - VECT39 : ORIGIN = 0xFFCC, LENGTH = 0x0002 - VECT40 : ORIGIN = 0xFFCE, LENGTH = 0x0002 - VECT41 : ORIGIN = 0xFFD0, LENGTH = 0x0002 - VECT42 : ORIGIN = 0xFFD2, LENGTH = 0x0002 - VECT43 : ORIGIN = 0xFFD4, LENGTH = 0x0002 - VECT44 : ORIGIN = 0xFFD6, LENGTH = 0x0002 - VECT45 : ORIGIN = 0xFFD8, LENGTH = 0x0002 - VECT46 : ORIGIN = 0xFFDA, LENGTH = 0x0002 - VECT47 : ORIGIN = 0xFFDC, LENGTH = 0x0002 - VECT48 : ORIGIN = 0xFFDE, LENGTH = 0x0002 - VECT49 : ORIGIN = 0xFFE0, LENGTH = 0x0002 - VECT50 : ORIGIN = 0xFFE2, LENGTH = 0x0002 - VECT51 : ORIGIN = 0xFFE4, LENGTH = 0x0002 - VECT52 : ORIGIN = 0xFFE6, LENGTH = 0x0002 - VECT53 : ORIGIN = 0xFFE8, LENGTH = 0x0002 - VECT54 : ORIGIN = 0xFFEA, LENGTH = 0x0002 - VECT55 : ORIGIN = 0xFFEC, LENGTH = 0x0002 - VECT56 : ORIGIN = 0xFFEE, LENGTH = 0x0002 - VECT57 : ORIGIN = 0xFFF0, LENGTH = 0x0002 - VECT58 : ORIGIN = 0xFFF2, LENGTH = 0x0002 - VECT59 : ORIGIN = 0xFFF4, LENGTH = 0x0002 - VECT60 : ORIGIN = 0xFFF6, LENGTH = 0x0002 - VECT61 : ORIGIN = 0xFFF8, LENGTH = 0x0002 - VECT62 : ORIGIN = 0xFFFA, LENGTH = 0x0002 - VECT63 : ORIGIN = 0xFFFC, LENGTH = 0x0002 - RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 -} - -SECTIONS -{ - __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 - __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 - __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3 - __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4 - __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 - __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 - __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 - __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 - __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9 - __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10 - __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11 - __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 - __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 - __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 - __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15 - __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16 - __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17 - __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18 - __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19 - __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) } > VECT20 - __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) } > VECT21 - __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) } > VECT22 - __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) } > VECT23 - __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) } > VECT24 - __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) } > VECT25 - __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) } > VECT26 - __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) } > VECT27 - __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) } > VECT28 - __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) } > VECT29 - __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) } > VECT30 - __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) } > VECT31 - __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) } > VECT32 - __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) } > VECT33 - __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) } > VECT34 - __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) } > VECT35 - __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) } > VECT36 - __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) } > VECT37 - __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) } > VECT38 - __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) } > VECT39 - __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) } > VECT40 - __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) } > VECT41 - __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) KEEP (*(__interrupt_vector_rtc)) } > VECT42 - __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) KEEP (*(__interrupt_vector_port2)) } > VECT43 - __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) KEEP (*(__interrupt_vector_timer2_a1)) } > VECT44 - __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) KEEP (*(__interrupt_vector_timer2_a0)) } > VECT45 - __interrupt_vector_46 : { KEEP (*(__interrupt_vector_46)) KEEP (*(__interrupt_vector_usci_b1)) } > VECT46 - __interrupt_vector_47 : { KEEP (*(__interrupt_vector_47)) KEEP (*(__interrupt_vector_usci_a1)) } > VECT47 - __interrupt_vector_48 : { KEEP (*(__interrupt_vector_48)) KEEP (*(__interrupt_vector_port1)) } > VECT48 - __interrupt_vector_49 : { KEEP (*(__interrupt_vector_49)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT49 - __interrupt_vector_50 : { KEEP (*(__interrupt_vector_50)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT50 - __interrupt_vector_51 : { KEEP (*(__interrupt_vector_51)) KEEP (*(__interrupt_vector_dma)) } > VECT51 - __interrupt_vector_52 : { KEEP (*(__interrupt_vector_52)) KEEP (*(__interrupt_vector_usb_ubm)) } > VECT52 - __interrupt_vector_53 : { KEEP (*(__interrupt_vector_53)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT53 - __interrupt_vector_54 : { KEEP (*(__interrupt_vector_54)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT54 - __interrupt_vector_55 : { KEEP (*(__interrupt_vector_55)) KEEP (*(__interrupt_vector_adc12)) } > VECT55 - __interrupt_vector_56 : { KEEP (*(__interrupt_vector_56)) KEEP (*(__interrupt_vector_usci_b0)) } > VECT56 - __interrupt_vector_57 : { KEEP (*(__interrupt_vector_57)) KEEP (*(__interrupt_vector_usci_a0)) } > VECT57 - __interrupt_vector_58 : { KEEP (*(__interrupt_vector_58)) KEEP (*(__interrupt_vector_wdt)) } > VECT58 - __interrupt_vector_59 : { KEEP (*(__interrupt_vector_59)) KEEP (*(__interrupt_vector_timer0_b1)) } > VECT59 - __interrupt_vector_60 : { KEEP (*(__interrupt_vector_60)) KEEP (*(__interrupt_vector_timer0_b0)) } > VECT60 - __interrupt_vector_61 : { KEEP (*(__interrupt_vector_61)) KEEP (*(__interrupt_vector_comp_b)) } > VECT61 - __interrupt_vector_62 : { KEEP (*(__interrupt_vector_62)) KEEP (*(__interrupt_vector_unmi)) } > VECT62 - __interrupt_vector_63 : { KEEP (*(__interrupt_vector_63)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT63 - __reset_vector : - { - KEEP (*(__interrupt_vector_64)) - KEEP (*(__interrupt_vector_reset)) - KEEP (*(.resetvec)) - } > RESETVEC - - .lower.rodata : - { - . = ALIGN(2); - *(.lower.rodata.* .lower.rodata) - } > ROM - - .rodata : - { - . = ALIGN(2); - *(.plt) - . = ALIGN(2); - *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) - *(.rodata1) - KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) - PROVIDE (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - PROVIDE (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE (__init_array_end = .); - PROVIDE (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE (__fini_array_end = .); - } > ROM - - /* Note: This is a separate .rodata section for sections which are - read only but which older linkers treat as read-write. - This prevents older linkers from marking the entire .rodata - section as read-write. */ - .rodata2 : - { - . = ALIGN(2); - *(.eh_frame_hdr) - KEEP (*(.eh_frame)) - - /* gcc uses crtbegin.o to find the start of the constructors, so - we make sure it is first. Because this is a wildcard, it - doesn't matter if the user does not actually link against - crtbegin.o; the linker won't look for a file to match a - wildcard. The wildcard also means that it doesn't matter which - directory crtbegin.o is in. */ - KEEP (*crtbegin*.o(.ctors)) - - /* We don't want to include the .ctor section from from the - crtend.o file until after the sorted ctors. The .ctor section - from the crtend file contains the end of ctors marker and it - must be last */ - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - - KEEP (*crtbegin*.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } > ROM - - .upper.rodata : - { - *(.upper.rodata.* .upper.rodata) - } > HIROM - - .data : - { - . = ALIGN(2); - PROVIDE (__datastart = .); - *(.lower.data.* .lower.data) - - . = ALIGN(2); - *(.either.data.* .either.data) - - . = ALIGN(2); - KEEP (*(.jcr)) - *(.data.rel.ro.local) *(.data.rel.ro*) - *(.dynamic) - - . = ALIGN(2); - *(.data .data.* .gnu.linkonce.d.*) - KEEP (*(.gnu.linkonce.d.*personality*)) - SORT(CONSTRUCTORS) - *(.data1) - *(.got.plt) *(.got) - - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - . = ALIGN(2); - *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) - - . = ALIGN(2); - _edata = .; - PROVIDE (edata = .); - PROVIDE (__dataend = .); - } > RAM AT> ROM - - /* Note that crt0 assumes this is a multiple of two; all the - start/stop symbols are also assumed word-aligned. */ - PROVIDE(__romdatastart = LOADADDR(.data)); - PROVIDE (__romdatacopysize = SIZEOF(.data)); - - .bss : - { - . = ALIGN(2); - PROVIDE (__bssstart = .); - *(.lower.bss.* .lower.bss) - . = ALIGN(2); - *(.either.bss.* .either.bss) - *(.dynbss) - *(.sbss .sbss.*) - *(.bss .bss.* .gnu.linkonce.b.*) - . = ALIGN(2); - *(COMMON) - PROVIDE (__bssend = .); - } > RAM - PROVIDE (__bsssize = SIZEOF(.bss)); - - /* This section contains data that is not initialised during load - or application reset. */ - .noinit (NOLOAD) : - { - . = ALIGN(2); - PROVIDE (__noinit_start = .); - *(.noinit) - . = ALIGN(2); - PROVIDE (__noinit_end = .); - } > RAM - - /* We create this section so that "end" will always be in the - RAM region (matching .stack below), even if the .bss - section is empty. */ - .heap (NOLOAD) : - { - . = ALIGN(2); - __heap_start__ = .; - _end = __heap_start__; - PROVIDE (end = .); - KEEP (*(.heap)) - _end = .; - PROVIDE (end = .); - /* This word is here so that the section is not empty, and thus - not discarded by the linker. The actual value does not matter - and is ignored. */ - LONG(0); - __heap_end__ = .; - __HeapLimit = __heap_end__; - } > RAM - /* WARNING: Do not place anything in RAM here. - The heap section must be the last section in RAM and the stack - section must be placed at the very end of the RAM region. */ - - .stack (ORIGIN (RAM) + LENGTH(RAM)) : - { - PROVIDE (__stack = .); - *(.stack) - } - - /* This is just for crt0.S and interrupt handlers. */ - .lowtext : - { - PROVIDE (_start = .); - . = ALIGN(2); - KEEP (*(SORT(.crt_*))) - KEEP (*(.lowtext)) - } > ROM - - .lower.text : - { - . = ALIGN(2); - *(.lower.text.* .lower.text) - } > ROM - - .text : - { - . = ALIGN(2); - *(.text .stub .text.* .gnu.linkonce.t.* .text:*) - - KEEP (*(.text.*personality*)) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.interp .hash .dynsym .dynstr .gnu.version*) - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - . = ALIGN(2); - KEEP (*(.init)) - KEEP (*(.fini)) - KEEP (*(.tm_clone_table)) - } > ROM - - .upper.text : - { - . = ALIGN(2); - *(.upper.text.* .upper.text) - } > HIROM - - .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ - .infoB : {} > INFOB - .infoC : {} > INFOC - .infoD : {} > INFOD - - /* Make sure that upper data sections are not used. */ - .upper : - { - *(.upper.bss.* .upper.bss) - *(.upper.data.* .upper.data) - ASSERT (SIZEOF(.upper) == 0, "This MCU does not support placing read/write data into high memory"); - } > HIROM - - /* The rest are all not normally part of the runtime image. */ - - .MSP430.attributes 0 : - { - KEEP (*(.MSP430.attributes)) - KEEP (*(.gnu.attributes)) - KEEP (*(__TI_build_attributes)) - } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1. */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions. */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2. */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2. */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions. */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - /* DWARF Extension. */ - .debug_macro 0 : { *(.debug_macro) } - - /DISCARD/ : { *(.note.GNU-stack) } -} - - -/****************************************************************************/ -/* Include peripherals memory map */ -/****************************************************************************/ - -INCLUDE msp430f5529_symbols.ld - diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld b/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld deleted file mode 100644 index 91448ad4f..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld +++ /dev/null @@ -1,867 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2019, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/* This file supports MSP430F5529 devices. */ -/* Version: 1.207 */ - -/************************************************************ -* STANDARD BITS -************************************************************/ -/************************************************************ -* STATUS REGISTER BITS -************************************************************/ -/************************************************************ -* PERIPHERAL FILE MAP -************************************************************/ -/************************************************************ -* ADC12 PLUS -************************************************************/ -PROVIDE(ADC12CTL0 = 0x0700); -PROVIDE(ADC12CTL0_L = 0x0700); -PROVIDE(ADC12CTL0_H = 0x0701); -PROVIDE(ADC12CTL1 = 0x0702); -PROVIDE(ADC12CTL1_L = 0x0702); -PROVIDE(ADC12CTL1_H = 0x0703); -PROVIDE(ADC12CTL2 = 0x0704); -PROVIDE(ADC12CTL2_L = 0x0704); -PROVIDE(ADC12CTL2_H = 0x0705); -PROVIDE(ADC12IFG = 0x070A); -PROVIDE(ADC12IFG_L = 0x070A); -PROVIDE(ADC12IFG_H = 0x070B); -PROVIDE(ADC12IE = 0x070C); -PROVIDE(ADC12IE_L = 0x070C); -PROVIDE(ADC12IE_H = 0x070D); -PROVIDE(ADC12IV = 0x070E); -PROVIDE(ADC12IV_L = 0x070E); -PROVIDE(ADC12IV_H = 0x070F); -PROVIDE(ADC12MEM0 = 0x0720); -PROVIDE(ADC12MEM0_L = 0x0720); -PROVIDE(ADC12MEM0_H = 0x0721); -PROVIDE(ADC12MEM1 = 0x0722); -PROVIDE(ADC12MEM1_L = 0x0722); -PROVIDE(ADC12MEM1_H = 0x0723); -PROVIDE(ADC12MEM2 = 0x0724); -PROVIDE(ADC12MEM2_L = 0x0724); -PROVIDE(ADC12MEM2_H = 0x0725); -PROVIDE(ADC12MEM3 = 0x0726); -PROVIDE(ADC12MEM3_L = 0x0726); -PROVIDE(ADC12MEM3_H = 0x0727); -PROVIDE(ADC12MEM4 = 0x0728); -PROVIDE(ADC12MEM4_L = 0x0728); -PROVIDE(ADC12MEM4_H = 0x0729); -PROVIDE(ADC12MEM5 = 0x072A); -PROVIDE(ADC12MEM5_L = 0x072A); -PROVIDE(ADC12MEM5_H = 0x072B); -PROVIDE(ADC12MEM6 = 0x072C); -PROVIDE(ADC12MEM6_L = 0x072C); -PROVIDE(ADC12MEM6_H = 0x072D); -PROVIDE(ADC12MEM7 = 0x072E); -PROVIDE(ADC12MEM7_L = 0x072E); -PROVIDE(ADC12MEM7_H = 0x072F); -PROVIDE(ADC12MEM8 = 0x0730); -PROVIDE(ADC12MEM8_L = 0x0730); -PROVIDE(ADC12MEM8_H = 0x0731); -PROVIDE(ADC12MEM9 = 0x0732); -PROVIDE(ADC12MEM9_L = 0x0732); -PROVIDE(ADC12MEM9_H = 0x0733); -PROVIDE(ADC12MEM10 = 0x0734); -PROVIDE(ADC12MEM10_L = 0x0734); -PROVIDE(ADC12MEM10_H = 0x0735); -PROVIDE(ADC12MEM11 = 0x0736); -PROVIDE(ADC12MEM11_L = 0x0736); -PROVIDE(ADC12MEM11_H = 0x0737); -PROVIDE(ADC12MEM12 = 0x0738); -PROVIDE(ADC12MEM12_L = 0x0738); -PROVIDE(ADC12MEM12_H = 0x0739); -PROVIDE(ADC12MEM13 = 0x073A); -PROVIDE(ADC12MEM13_L = 0x073A); -PROVIDE(ADC12MEM13_H = 0x073B); -PROVIDE(ADC12MEM14 = 0x073C); -PROVIDE(ADC12MEM14_L = 0x073C); -PROVIDE(ADC12MEM14_H = 0x073D); -PROVIDE(ADC12MEM15 = 0x073E); -PROVIDE(ADC12MEM15_L = 0x073E); -PROVIDE(ADC12MEM15_H = 0x073F); -PROVIDE(ADC12MCTL0 = 0x0710); -PROVIDE(ADC12MCTL1 = 0x0711); -PROVIDE(ADC12MCTL2 = 0x0712); -PROVIDE(ADC12MCTL3 = 0x0713); -PROVIDE(ADC12MCTL4 = 0x0714); -PROVIDE(ADC12MCTL5 = 0x0715); -PROVIDE(ADC12MCTL6 = 0x0716); -PROVIDE(ADC12MCTL7 = 0x0717); -PROVIDE(ADC12MCTL8 = 0x0718); -PROVIDE(ADC12MCTL9 = 0x0719); -PROVIDE(ADC12MCTL10 = 0x071A); -PROVIDE(ADC12MCTL11 = 0x071B); -PROVIDE(ADC12MCTL12 = 0x071C); -PROVIDE(ADC12MCTL13 = 0x071D); -PROVIDE(ADC12MCTL14 = 0x071E); -PROVIDE(ADC12MCTL15 = 0x071F); -/************************************************************ -* Comparator B -************************************************************/ -PROVIDE(CBCTL0 = 0x08C0); -PROVIDE(CBCTL0_L = 0x08C0); -PROVIDE(CBCTL0_H = 0x08C1); -PROVIDE(CBCTL1 = 0x08C2); -PROVIDE(CBCTL1_L = 0x08C2); -PROVIDE(CBCTL1_H = 0x08C3); -PROVIDE(CBCTL2 = 0x08C4); -PROVIDE(CBCTL2_L = 0x08C4); -PROVIDE(CBCTL2_H = 0x08C5); -PROVIDE(CBCTL3 = 0x08C6); -PROVIDE(CBCTL3_L = 0x08C6); -PROVIDE(CBCTL3_H = 0x08C7); -PROVIDE(CBINT = 0x08CC); -PROVIDE(CBINT_L = 0x08CC); -PROVIDE(CBINT_H = 0x08CD); -PROVIDE(CBIV = 0x08CE); -/************************************************************* -* CRC Module -*************************************************************/ -PROVIDE(CRCDI = 0x0150); -PROVIDE(CRCDI_L = 0x0150); -PROVIDE(CRCDI_H = 0x0151); -PROVIDE(CRCDIRB = 0x0152); -PROVIDE(CRCDIRB_L = 0x0152); -PROVIDE(CRCDIRB_H = 0x0153); -PROVIDE(CRCINIRES = 0x0154); -PROVIDE(CRCINIRES_L = 0x0154); -PROVIDE(CRCINIRES_H = 0x0155); -PROVIDE(CRCRESR = 0x0156); -PROVIDE(CRCRESR_L = 0x0156); -PROVIDE(CRCRESR_H = 0x0157); -/************************************************************ -* DMA_X -************************************************************/ -PROVIDE(DMACTL0 = 0x0500); -PROVIDE(DMACTL1 = 0x0502); -PROVIDE(DMACTL2 = 0x0504); -PROVIDE(DMACTL3 = 0x0506); -PROVIDE(DMACTL4 = 0x0508); -PROVIDE(DMAIV = 0x050E); -PROVIDE(DMA0CTL = 0x0510); -PROVIDE(DMA0SA = 0x0512); -PROVIDE(DMA0SAL = 0x0512); -PROVIDE(DMA0DA = 0x0516); -PROVIDE(DMA0DAL = 0x0516); -PROVIDE(DMA0SZ = 0x051A); -PROVIDE(DMA1CTL = 0x0520); -PROVIDE(DMA1SA = 0x0522); -PROVIDE(DMA1SAL = 0x0522); -PROVIDE(DMA1DA = 0x0526); -PROVIDE(DMA1DAL = 0x0526); -PROVIDE(DMA1SZ = 0x052A); -PROVIDE(DMA2CTL = 0x0530); -PROVIDE(DMA2SA = 0x0532); -PROVIDE(DMA2SAL = 0x0532); -PROVIDE(DMA2DA = 0x0536); -PROVIDE(DMA2DAL = 0x0536); -PROVIDE(DMA2SZ = 0x053A); -/************************************************************* -* Flash Memory -*************************************************************/ -PROVIDE(FCTL1 = 0x0140); -PROVIDE(FCTL1_L = 0x0140); -PROVIDE(FCTL1_H = 0x0141); -PROVIDE(FCTL3 = 0x0144); -PROVIDE(FCTL3_L = 0x0144); -PROVIDE(FCTL3_H = 0x0145); -PROVIDE(FCTL4 = 0x0146); -PROVIDE(FCTL4_L = 0x0146); -PROVIDE(FCTL4_H = 0x0147); -/************************************************************ -* HARDWARE MULTIPLIER 32Bit -************************************************************/ -PROVIDE(MPY = 0x04C0); -PROVIDE(MPY_L = 0x04C0); -PROVIDE(MPY_H = 0x04C1); -PROVIDE(MPYS = 0x04C2); -PROVIDE(MPYS_L = 0x04C2); -PROVIDE(MPYS_H = 0x04C3); -PROVIDE(MAC = 0x04C4); -PROVIDE(MAC_L = 0x04C4); -PROVIDE(MAC_H = 0x04C5); -PROVIDE(MACS = 0x04C6); -PROVIDE(MACS_L = 0x04C6); -PROVIDE(MACS_H = 0x04C7); -PROVIDE(OP2 = 0x04C8); -PROVIDE(OP2_L = 0x04C8); -PROVIDE(OP2_H = 0x04C9); -PROVIDE(RESLO = 0x04CA); -PROVIDE(RESLO_L = 0x04CA); -PROVIDE(RESLO_H = 0x04CB); -PROVIDE(RESHI = 0x04CC); -PROVIDE(RESHI_L = 0x04CC); -PROVIDE(RESHI_H = 0x04CD); -PROVIDE(SUMEXT = 0x04CE); -PROVIDE(SUMEXT_L = 0x04CE); -PROVIDE(SUMEXT_H = 0x04CF); -PROVIDE(MPY32L = 0x04D0); -PROVIDE(MPY32L_L = 0x04D0); -PROVIDE(MPY32L_H = 0x04D1); -PROVIDE(MPY32H = 0x04D2); -PROVIDE(MPY32H_L = 0x04D2); -PROVIDE(MPY32H_H = 0x04D3); -PROVIDE(MPYS32L = 0x04D4); -PROVIDE(MPYS32L_L = 0x04D4); -PROVIDE(MPYS32L_H = 0x04D5); -PROVIDE(MPYS32H = 0x04D6); -PROVIDE(MPYS32H_L = 0x04D6); -PROVIDE(MPYS32H_H = 0x04D7); -PROVIDE(MAC32L = 0x04D8); -PROVIDE(MAC32L_L = 0x04D8); -PROVIDE(MAC32L_H = 0x04D9); -PROVIDE(MAC32H = 0x04DA); -PROVIDE(MAC32H_L = 0x04DA); -PROVIDE(MAC32H_H = 0x04DB); -PROVIDE(MACS32L = 0x04DC); -PROVIDE(MACS32L_L = 0x04DC); -PROVIDE(MACS32L_H = 0x04DD); -PROVIDE(MACS32H = 0x04DE); -PROVIDE(MACS32H_L = 0x04DE); -PROVIDE(MACS32H_H = 0x04DF); -PROVIDE(OP2L = 0x04E0); -PROVIDE(OP2L_L = 0x04E0); -PROVIDE(OP2L_H = 0x04E1); -PROVIDE(OP2H = 0x04E2); -PROVIDE(OP2H_L = 0x04E2); -PROVIDE(OP2H_H = 0x04E3); -PROVIDE(RES0 = 0x04E4); -PROVIDE(RES0_L = 0x04E4); -PROVIDE(RES0_H = 0x04E5); -PROVIDE(RES1 = 0x04E6); -PROVIDE(RES1_L = 0x04E6); -PROVIDE(RES1_H = 0x04E7); -PROVIDE(RES2 = 0x04E8); -PROVIDE(RES2_L = 0x04E8); -PROVIDE(RES2_H = 0x04E9); -PROVIDE(RES3 = 0x04EA); -PROVIDE(RES3_L = 0x04EA); -PROVIDE(RES3_H = 0x04EB); -PROVIDE(MPY32CTL0 = 0x04EC); -PROVIDE(MPY32CTL0_L = 0x04EC); -PROVIDE(MPY32CTL0_H = 0x04ED); -/************************************************************ -* DIGITAL I/O Port1/2 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PAIN = 0x0200); -PROVIDE(PAIN_L = 0x0200); -PROVIDE(PAIN_H = 0x0201); -PROVIDE(PAOUT = 0x0202); -PROVIDE(PAOUT_L = 0x0202); -PROVIDE(PAOUT_H = 0x0203); -PROVIDE(PADIR = 0x0204); -PROVIDE(PADIR_L = 0x0204); -PROVIDE(PADIR_H = 0x0205); -PROVIDE(PAREN = 0x0206); -PROVIDE(PAREN_L = 0x0206); -PROVIDE(PAREN_H = 0x0207); -PROVIDE(PADS = 0x0208); -PROVIDE(PADS_L = 0x0208); -PROVIDE(PADS_H = 0x0209); -PROVIDE(PASEL = 0x020A); -PROVIDE(PASEL_L = 0x020A); -PROVIDE(PASEL_H = 0x020B); -PROVIDE(PAIES = 0x0218); -PROVIDE(PAIES_L = 0x0218); -PROVIDE(PAIES_H = 0x0219); -PROVIDE(PAIE = 0x021A); -PROVIDE(PAIE_L = 0x021A); -PROVIDE(PAIE_H = 0x021B); -PROVIDE(PAIFG = 0x021C); -PROVIDE(PAIFG_L = 0x021C); -PROVIDE(PAIFG_H = 0x021D); -PROVIDE(P1IV = 0x020E); -PROVIDE(P2IV = 0x021E); -/************************************************************ -* DIGITAL I/O Port3/4 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PBIN = 0x0220); -PROVIDE(PBIN_L = 0x0220); -PROVIDE(PBIN_H = 0x0221); -PROVIDE(PBOUT = 0x0222); -PROVIDE(PBOUT_L = 0x0222); -PROVIDE(PBOUT_H = 0x0223); -PROVIDE(PBDIR = 0x0224); -PROVIDE(PBDIR_L = 0x0224); -PROVIDE(PBDIR_H = 0x0225); -PROVIDE(PBREN = 0x0226); -PROVIDE(PBREN_L = 0x0226); -PROVIDE(PBREN_H = 0x0227); -PROVIDE(PBDS = 0x0228); -PROVIDE(PBDS_L = 0x0228); -PROVIDE(PBDS_H = 0x0229); -PROVIDE(PBSEL = 0x022A); -PROVIDE(PBSEL_L = 0x022A); -PROVIDE(PBSEL_H = 0x022B); -/************************************************************ -* DIGITAL I/O Port5/6 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PCIN = 0x0240); -PROVIDE(PCIN_L = 0x0240); -PROVIDE(PCIN_H = 0x0241); -PROVIDE(PCOUT = 0x0242); -PROVIDE(PCOUT_L = 0x0242); -PROVIDE(PCOUT_H = 0x0243); -PROVIDE(PCDIR = 0x0244); -PROVIDE(PCDIR_L = 0x0244); -PROVIDE(PCDIR_H = 0x0245); -PROVIDE(PCREN = 0x0246); -PROVIDE(PCREN_L = 0x0246); -PROVIDE(PCREN_H = 0x0247); -PROVIDE(PCDS = 0x0248); -PROVIDE(PCDS_L = 0x0248); -PROVIDE(PCDS_H = 0x0249); -PROVIDE(PCSEL = 0x024A); -PROVIDE(PCSEL_L = 0x024A); -PROVIDE(PCSEL_H = 0x024B); -/************************************************************ -* DIGITAL I/O Port7/8 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PDIN = 0x0260); -PROVIDE(PDIN_L = 0x0260); -PROVIDE(PDIN_H = 0x0261); -PROVIDE(PDOUT = 0x0262); -PROVIDE(PDOUT_L = 0x0262); -PROVIDE(PDOUT_H = 0x0263); -PROVIDE(PDDIR = 0x0264); -PROVIDE(PDDIR_L = 0x0264); -PROVIDE(PDDIR_H = 0x0265); -PROVIDE(PDREN = 0x0266); -PROVIDE(PDREN_L = 0x0266); -PROVIDE(PDREN_H = 0x0267); -PROVIDE(PDDS = 0x0268); -PROVIDE(PDDS_L = 0x0268); -PROVIDE(PDDS_H = 0x0269); -PROVIDE(PDSEL = 0x026A); -PROVIDE(PDSEL_L = 0x026A); -PROVIDE(PDSEL_H = 0x026B); -/************************************************************ -* DIGITAL I/O PortJ Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PJIN = 0x0320); -PROVIDE(PJIN_L = 0x0320); -PROVIDE(PJIN_H = 0x0321); -PROVIDE(PJOUT = 0x0322); -PROVIDE(PJOUT_L = 0x0322); -PROVIDE(PJOUT_H = 0x0323); -PROVIDE(PJDIR = 0x0324); -PROVIDE(PJDIR_L = 0x0324); -PROVIDE(PJDIR_H = 0x0325); -PROVIDE(PJREN = 0x0326); -PROVIDE(PJREN_L = 0x0326); -PROVIDE(PJREN_H = 0x0327); -PROVIDE(PJDS = 0x0328); -PROVIDE(PJDS_L = 0x0328); -PROVIDE(PJDS_H = 0x0329); -/************************************************************ -* PORT MAPPING CONTROLLER -************************************************************/ -PROVIDE(PMAPKEYID = 0x01C0); -PROVIDE(PMAPKEYID_L = 0x01C0); -PROVIDE(PMAPKEYID_H = 0x01C1); -PROVIDE(PMAPCTL = 0x01C2); -PROVIDE(PMAPCTL_L = 0x01C2); -PROVIDE(PMAPCTL_H = 0x01C3); -/************************************************************ -* PORT 4 MAPPING CONTROLLER -************************************************************/ -PROVIDE(P4MAP01 = 0x01E0); -PROVIDE(P4MAP01_L = 0x01E0); -PROVIDE(P4MAP01_H = 0x01E1); -PROVIDE(P4MAP23 = 0x01E2); -PROVIDE(P4MAP23_L = 0x01E2); -PROVIDE(P4MAP23_H = 0x01E3); -PROVIDE(P4MAP45 = 0x01E4); -PROVIDE(P4MAP45_L = 0x01E4); -PROVIDE(P4MAP45_H = 0x01E5); -PROVIDE(P4MAP67 = 0x01E6); -PROVIDE(P4MAP67_L = 0x01E6); -PROVIDE(P4MAP67_H = 0x01E7); -/************************************************************ -* PMM - Power Management System -************************************************************/ -PROVIDE(PMMCTL0 = 0x0120); -PROVIDE(PMMCTL0_L = 0x0120); -PROVIDE(PMMCTL0_H = 0x0121); -PROVIDE(PMMCTL1 = 0x0122); -PROVIDE(PMMCTL1_L = 0x0122); -PROVIDE(PMMCTL1_H = 0x0123); -PROVIDE(SVSMHCTL = 0x0124); -PROVIDE(SVSMHCTL_L = 0x0124); -PROVIDE(SVSMHCTL_H = 0x0125); -PROVIDE(SVSMLCTL = 0x0126); -PROVIDE(SVSMLCTL_L = 0x0126); -PROVIDE(SVSMLCTL_H = 0x0127); -PROVIDE(SVSMIO = 0x0128); -PROVIDE(SVSMIO_L = 0x0128); -PROVIDE(SVSMIO_H = 0x0129); -PROVIDE(PMMIFG = 0x012C); -PROVIDE(PMMIFG_L = 0x012C); -PROVIDE(PMMIFG_H = 0x012D); -PROVIDE(PMMRIE = 0x012E); -PROVIDE(PMMRIE_L = 0x012E); -PROVIDE(PMMRIE_H = 0x012F); -PROVIDE(PM5CTL0 = 0x0130); -PROVIDE(PM5CTL0_L = 0x0130); -PROVIDE(PM5CTL0_H = 0x0131); -/************************************************************* -* RAM Control Module -*************************************************************/ -PROVIDE(RCCTL0 = 0x0158); -PROVIDE(RCCTL0_L = 0x0158); -PROVIDE(RCCTL0_H = 0x0159); -/************************************************************ -* Shared Reference -************************************************************/ -PROVIDE(REFCTL0 = 0x01B0); -PROVIDE(REFCTL0_L = 0x01B0); -PROVIDE(REFCTL0_H = 0x01B1); -/************************************************************ -* Real Time Clock -************************************************************/ -PROVIDE(RTCCTL01 = 0x04A0); -PROVIDE(RTCCTL01_L = 0x04A0); -PROVIDE(RTCCTL01_H = 0x04A1); -PROVIDE(RTCCTL23 = 0x04A2); -PROVIDE(RTCCTL23_L = 0x04A2); -PROVIDE(RTCCTL23_H = 0x04A3); -PROVIDE(RTCPS0CTL = 0x04A8); -PROVIDE(RTCPS0CTL_L = 0x04A8); -PROVIDE(RTCPS0CTL_H = 0x04A9); -PROVIDE(RTCPS1CTL = 0x04AA); -PROVIDE(RTCPS1CTL_L = 0x04AA); -PROVIDE(RTCPS1CTL_H = 0x04AB); -PROVIDE(RTCPS = 0x04AC); -PROVIDE(RTCPS_L = 0x04AC); -PROVIDE(RTCPS_H = 0x04AD); -PROVIDE(RTCIV = 0x04AE); -PROVIDE(RTCTIM0 = 0x04B0); -PROVIDE(RTCTIM0_L = 0x04B0); -PROVIDE(RTCTIM0_H = 0x04B1); -PROVIDE(RTCTIM1 = 0x04B2); -PROVIDE(RTCTIM1_L = 0x04B2); -PROVIDE(RTCTIM1_H = 0x04B3); -PROVIDE(RTCDATE = 0x04B4); -PROVIDE(RTCDATE_L = 0x04B4); -PROVIDE(RTCDATE_H = 0x04B5); -PROVIDE(RTCYEAR = 0x04B6); -PROVIDE(RTCYEAR_L = 0x04B6); -PROVIDE(RTCYEAR_H = 0x04B7); -PROVIDE(RTCAMINHR = 0x04B8); -PROVIDE(RTCAMINHR_L = 0x04B8); -PROVIDE(RTCAMINHR_H = 0x04B9); -PROVIDE(RTCADOWDAY = 0x04BA); -PROVIDE(RTCADOWDAY_L = 0x04BA); -PROVIDE(RTCADOWDAY_H = 0x04BB); -/************************************************************ -* SFR - Special Function Register Module -************************************************************/ -PROVIDE(SFRIE1 = 0x0100); -PROVIDE(SFRIE1_L = 0x0100); -PROVIDE(SFRIE1_H = 0x0101); -PROVIDE(SFRIFG1 = 0x0102); -PROVIDE(SFRIFG1_L = 0x0102); -PROVIDE(SFRIFG1_H = 0x0103); -PROVIDE(SFRRPCR = 0x0104); -PROVIDE(SFRRPCR_L = 0x0104); -PROVIDE(SFRRPCR_H = 0x0105); -/************************************************************ -* SYS - System Module -************************************************************/ -PROVIDE(SYSCTL = 0x0180); -PROVIDE(SYSCTL_L = 0x0180); -PROVIDE(SYSCTL_H = 0x0181); -PROVIDE(SYSBSLC = 0x0182); -PROVIDE(SYSBSLC_L = 0x0182); -PROVIDE(SYSBSLC_H = 0x0183); -PROVIDE(SYSJMBC = 0x0186); -PROVIDE(SYSJMBC_L = 0x0186); -PROVIDE(SYSJMBC_H = 0x0187); -PROVIDE(SYSJMBI0 = 0x0188); -PROVIDE(SYSJMBI0_L = 0x0188); -PROVIDE(SYSJMBI0_H = 0x0189); -PROVIDE(SYSJMBI1 = 0x018A); -PROVIDE(SYSJMBI1_L = 0x018A); -PROVIDE(SYSJMBI1_H = 0x018B); -PROVIDE(SYSJMBO0 = 0x018C); -PROVIDE(SYSJMBO0_L = 0x018C); -PROVIDE(SYSJMBO0_H = 0x018D); -PROVIDE(SYSJMBO1 = 0x018E); -PROVIDE(SYSJMBO1_L = 0x018E); -PROVIDE(SYSJMBO1_H = 0x018F); -PROVIDE(SYSBERRIV = 0x0198); -PROVIDE(SYSBERRIV_L = 0x0198); -PROVIDE(SYSBERRIV_H = 0x0199); -PROVIDE(SYSUNIV = 0x019A); -PROVIDE(SYSUNIV_L = 0x019A); -PROVIDE(SYSUNIV_H = 0x019B); -PROVIDE(SYSSNIV = 0x019C); -PROVIDE(SYSSNIV_L = 0x019C); -PROVIDE(SYSSNIV_H = 0x019D); -PROVIDE(SYSRSTIV = 0x019E); -PROVIDE(SYSRSTIV_L = 0x019E); -PROVIDE(SYSRSTIV_H = 0x019F); -/************************************************************ -* Timer0_A5 -************************************************************/ -PROVIDE(TA0CTL = 0x0340); -PROVIDE(TA0CCTL0 = 0x0342); -PROVIDE(TA0CCTL1 = 0x0344); -PROVIDE(TA0CCTL2 = 0x0346); -PROVIDE(TA0CCTL3 = 0x0348); -PROVIDE(TA0CCTL4 = 0x034A); -PROVIDE(TA0R = 0x0350); -PROVIDE(TA0CCR0 = 0x0352); -PROVIDE(TA0CCR1 = 0x0354); -PROVIDE(TA0CCR2 = 0x0356); -PROVIDE(TA0CCR3 = 0x0358); -PROVIDE(TA0CCR4 = 0x035A); -PROVIDE(TA0IV = 0x036E); -PROVIDE(TA0EX0 = 0x0360); -/************************************************************ -* Timer1_A3 -************************************************************/ -PROVIDE(TA1CTL = 0x0380); -PROVIDE(TA1CCTL0 = 0x0382); -PROVIDE(TA1CCTL1 = 0x0384); -PROVIDE(TA1CCTL2 = 0x0386); -PROVIDE(TA1R = 0x0390); -PROVIDE(TA1CCR0 = 0x0392); -PROVIDE(TA1CCR1 = 0x0394); -PROVIDE(TA1CCR2 = 0x0396); -PROVIDE(TA1IV = 0x03AE); -PROVIDE(TA1EX0 = 0x03A0); -/************************************************************ -* Timer2_A3 -************************************************************/ -PROVIDE(TA2CTL = 0x0400); -PROVIDE(TA2CCTL0 = 0x0402); -PROVIDE(TA2CCTL1 = 0x0404); -PROVIDE(TA2CCTL2 = 0x0406); -PROVIDE(TA2R = 0x0410); -PROVIDE(TA2CCR0 = 0x0412); -PROVIDE(TA2CCR1 = 0x0414); -PROVIDE(TA2CCR2 = 0x0416); -PROVIDE(TA2IV = 0x042E); -PROVIDE(TA2EX0 = 0x0420); -/************************************************************ -* Timer0_B7 -************************************************************/ -PROVIDE(TB0CTL = 0x03C0); -PROVIDE(TB0CCTL0 = 0x03C2); -PROVIDE(TB0CCTL1 = 0x03C4); -PROVIDE(TB0CCTL2 = 0x03C6); -PROVIDE(TB0CCTL3 = 0x03C8); -PROVIDE(TB0CCTL4 = 0x03CA); -PROVIDE(TB0CCTL5 = 0x03CC); -PROVIDE(TB0CCTL6 = 0x03CE); -PROVIDE(TB0R = 0x03D0); -PROVIDE(TB0CCR0 = 0x03D2); -PROVIDE(TB0CCR1 = 0x03D4); -PROVIDE(TB0CCR2 = 0x03D6); -PROVIDE(TB0CCR3 = 0x03D8); -PROVIDE(TB0CCR4 = 0x03DA); -PROVIDE(TB0CCR5 = 0x03DC); -PROVIDE(TB0CCR6 = 0x03DE); -PROVIDE(TB0EX0 = 0x03E0); -PROVIDE(TB0IV = 0x03EE); -/************************************************************ -* USB -************************************************************/ -PROVIDE(USBKEYID = 0x0900); -PROVIDE(USBKEYID_L = 0x0900); -PROVIDE(USBKEYID_H = 0x0901); -PROVIDE(USBCNF = 0x0902); -PROVIDE(USBCNF_L = 0x0902); -PROVIDE(USBCNF_H = 0x0903); -PROVIDE(USBPHYCTL = 0x0904); -PROVIDE(USBPHYCTL_L = 0x0904); -PROVIDE(USBPHYCTL_H = 0x0905); -PROVIDE(USBPWRCTL = 0x0908); -PROVIDE(USBPWRCTL_L = 0x0908); -PROVIDE(USBPWRCTL_H = 0x0909); -PROVIDE(USBPLLCTL = 0x0910); -PROVIDE(USBPLLCTL_L = 0x0910); -PROVIDE(USBPLLCTL_H = 0x0911); -PROVIDE(USBPLLDIVB = 0x0912); -PROVIDE(USBPLLDIVB_L = 0x0912); -PROVIDE(USBPLLDIVB_H = 0x0913); -PROVIDE(USBPLLIR = 0x0914); -PROVIDE(USBPLLIR_L = 0x0914); -PROVIDE(USBPLLIR_H = 0x0915); -PROVIDE(USBIEPCNF_0 = 0x0920); -PROVIDE(USBIEPCNT_0 = 0x0921); -PROVIDE(USBOEPCNF_0 = 0x0922); -PROVIDE(USBOEPCNT_0 = 0x0923); -PROVIDE(USBIEPIE = 0x092E); -PROVIDE(USBOEPIE = 0x092F); -PROVIDE(USBIEPIFG = 0x0930); -PROVIDE(USBOEPIFG = 0x0931); -PROVIDE(USBVECINT = 0x0932); -PROVIDE(USBVECINT_L = 0x0932); -PROVIDE(USBVECINT_H = 0x0933); -PROVIDE(USBMAINT = 0x0936); -PROVIDE(USBMAINT_L = 0x0936); -PROVIDE(USBMAINT_H = 0x0937); -PROVIDE(USBTSREG = 0x0938); -PROVIDE(USBTSREG_L = 0x0938); -PROVIDE(USBTSREG_H = 0x0939); -PROVIDE(USBFN = 0x093A); -PROVIDE(USBFN_L = 0x093A); -PROVIDE(USBFN_H = 0x093B); -PROVIDE(USBCTL = 0x093C); -PROVIDE(USBIE = 0x093D); -PROVIDE(USBIFG = 0x093E); -PROVIDE(USBFUNADR = 0x093F); -PROVIDE(USBIEPSIZXY_7 = 0x23FF); -PROVIDE(USBIEPBCTY_7 = 0x23FE); -PROVIDE(USBIEPBBAY_7 = 0x23FD); -PROVIDE(USBIEPBCTX_7 = 0x23FA); -PROVIDE(USBIEPBBAX_7 = 0x23F9); -PROVIDE(USBIEPCNF_7 = 0x23F8); -PROVIDE(USBIEPSIZXY_6 = 0x23F7); -PROVIDE(USBIEPBCTY_6 = 0x23F6); -PROVIDE(USBIEPBBAY_6 = 0x23F5); -PROVIDE(USBIEPBCTX_6 = 0x23F2); -PROVIDE(USBIEPBBAX_6 = 0x23F1); -PROVIDE(USBIEPCNF_6 = 0x23F0); -PROVIDE(USBIEPSIZXY_5 = 0x23EF); -PROVIDE(USBIEPBCTY_5 = 0x23EE); -PROVIDE(USBIEPBBAY_5 = 0x23ED); -PROVIDE(USBIEPBCTX_5 = 0x23EA); -PROVIDE(USBIEPBBAX_5 = 0x23E9); -PROVIDE(USBIEPCNF_5 = 0x23E8); -PROVIDE(USBIEPSIZXY_4 = 0x23E7); -PROVIDE(USBIEPBCTY_4 = 0x23E6); -PROVIDE(USBIEPBBAY_4 = 0x23E5); -PROVIDE(USBIEPBCTX_4 = 0x23E2); -PROVIDE(USBIEPBBAX_4 = 0x23E1); -PROVIDE(USBIEPCNF_4 = 0x23E0); -PROVIDE(USBIEPSIZXY_3 = 0x23DF); -PROVIDE(USBIEPBCTY_3 = 0x23DE); -PROVIDE(USBIEPBBAY_3 = 0x23DD); -PROVIDE(USBIEPBCTX_3 = 0x23DA); -PROVIDE(USBIEPBBAX_3 = 0x23D9); -PROVIDE(USBIEPCNF_3 = 0x23D8); -PROVIDE(USBIEPSIZXY_2 = 0x23D7); -PROVIDE(USBIEPBCTY_2 = 0x23D6); -PROVIDE(USBIEPBBAY_2 = 0x23D5); -PROVIDE(USBIEPBCTX_2 = 0x23D2); -PROVIDE(USBIEPBBAX_2 = 0x23D1); -PROVIDE(USBIEPCNF_2 = 0x23D0); -PROVIDE(USBIEPSIZXY_1 = 0x23CF); -PROVIDE(USBIEPBCTY_1 = 0x23CE); -PROVIDE(USBIEPBBAY_1 = 0x23CD); -PROVIDE(USBIEPBCTX_1 = 0x23CA); -PROVIDE(USBIEPBBAX_1 = 0x23C9); -PROVIDE(USBIEPCNF_1 = 0x23C8); -PROVIDE(USBOEPSIZXY_7 = 0x23BF); -PROVIDE(USBOEPBCTY_7 = 0x23BE); -PROVIDE(USBOEPBBAY_7 = 0x23BD); -PROVIDE(USBOEPBCTX_7 = 0x23BA); -PROVIDE(USBOEPBBAX_7 = 0x23B9); -PROVIDE(USBOEPCNF_7 = 0x23B8); -PROVIDE(USBOEPSIZXY_6 = 0x23B7); -PROVIDE(USBOEPBCTY_6 = 0x23B6); -PROVIDE(USBOEPBBAY_6 = 0x23B5); -PROVIDE(USBOEPBCTX_6 = 0x23B2); -PROVIDE(USBOEPBBAX_6 = 0x23B1); -PROVIDE(USBOEPCNF_6 = 0x23B0); -PROVIDE(USBOEPSIZXY_5 = 0x23AF); -PROVIDE(USBOEPBCTY_5 = 0x23AE); -PROVIDE(USBOEPBBAY_5 = 0x23AD); -PROVIDE(USBOEPBCTX_5 = 0x23AA); -PROVIDE(USBOEPBBAX_5 = 0x23A9); -PROVIDE(USBOEPCNF_5 = 0x23A8); -PROVIDE(USBOEPSIZXY_4 = 0x23A7); -PROVIDE(USBOEPBCTY_4 = 0x23A6); -PROVIDE(USBOEPBBAY_4 = 0x23A5); -PROVIDE(USBOEPBCTX_4 = 0x23A2); -PROVIDE(USBOEPBBAX_4 = 0x23A1); -PROVIDE(USBOEPCNF_4 = 0x23A0); -PROVIDE(USBOEPSIZXY_3 = 0x239F); -PROVIDE(USBOEPBCTY_3 = 0x239E); -PROVIDE(USBOEPBBAY_3 = 0x239D); -PROVIDE(USBOEPBCTX_3 = 0x239A); -PROVIDE(USBOEPBBAX_3 = 0x2399); -PROVIDE(USBOEPCNF_3 = 0x2398); -PROVIDE(USBOEPSIZXY_2 = 0x2397); -PROVIDE(USBOEPBCTY_2 = 0x2396); -PROVIDE(USBOEPBBAY_2 = 0x2395); -PROVIDE(USBOEPBCTX_2 = 0x2392); -PROVIDE(USBOEPBBAX_2 = 0x2391); -PROVIDE(USBOEPCNF_2 = 0x2390); -PROVIDE(USBOEPSIZXY_1 = 0x238F); -PROVIDE(USBOEPBCTY_1 = 0x238E); -PROVIDE(USBOEPBBAY_1 = 0x238D); -PROVIDE(USBOEPBCTX_1 = 0x238A); -PROVIDE(USBOEPBBAX_1 = 0x2389); -PROVIDE(USBOEPCNF_1 = 0x2388); -PROVIDE(USBSUBLK = 0x2380); -PROVIDE(USBIEP0BUF = 0x2378); -PROVIDE(USBOEP0BUF = 0x2370); -PROVIDE(USBTOPBUFF = 0x236F); -PROVIDE(USBSTABUFF = 0x1C00); -/************************************************************ -* UNIFIED CLOCK SYSTEM -************************************************************/ -PROVIDE(UCSCTL0 = 0x0160); -PROVIDE(UCSCTL0_L = 0x0160); -PROVIDE(UCSCTL0_H = 0x0161); -PROVIDE(UCSCTL1 = 0x0162); -PROVIDE(UCSCTL1_L = 0x0162); -PROVIDE(UCSCTL1_H = 0x0163); -PROVIDE(UCSCTL2 = 0x0164); -PROVIDE(UCSCTL2_L = 0x0164); -PROVIDE(UCSCTL2_H = 0x0165); -PROVIDE(UCSCTL3 = 0x0166); -PROVIDE(UCSCTL3_L = 0x0166); -PROVIDE(UCSCTL3_H = 0x0167); -PROVIDE(UCSCTL4 = 0x0168); -PROVIDE(UCSCTL4_L = 0x0168); -PROVIDE(UCSCTL4_H = 0x0169); -PROVIDE(UCSCTL5 = 0x016A); -PROVIDE(UCSCTL5_L = 0x016A); -PROVIDE(UCSCTL5_H = 0x016B); -PROVIDE(UCSCTL6 = 0x016C); -PROVIDE(UCSCTL6_L = 0x016C); -PROVIDE(UCSCTL6_H = 0x016D); -PROVIDE(UCSCTL7 = 0x016E); -PROVIDE(UCSCTL7_L = 0x016E); -PROVIDE(UCSCTL7_H = 0x016F); -PROVIDE(UCSCTL8 = 0x0170); -PROVIDE(UCSCTL8_L = 0x0170); -PROVIDE(UCSCTL8_H = 0x0171); -/************************************************************ -* USCI A0 -************************************************************/ -PROVIDE(UCA0CTLW0 = 0x05C0); -PROVIDE(UCA0CTLW0_L = 0x05C0); -PROVIDE(UCA0CTLW0_H = 0x05C1); -PROVIDE(UCA0BRW = 0x05C6); -PROVIDE(UCA0BRW_L = 0x05C6); -PROVIDE(UCA0BRW_H = 0x05C7); -PROVIDE(UCA0MCTL = 0x05C8); -PROVIDE(UCA0STAT = 0x05CA); -PROVIDE(UCA0RXBUF = 0x05CC); -PROVIDE(UCA0TXBUF = 0x05CE); -PROVIDE(UCA0ABCTL = 0x05D0); -PROVIDE(UCA0IRCTL = 0x05D2); -PROVIDE(UCA0IRCTL_L = 0x05D2); -PROVIDE(UCA0IRCTL_H = 0x05D3); -PROVIDE(UCA0ICTL = 0x05DC); -PROVIDE(UCA0ICTL_L = 0x05DC); -PROVIDE(UCA0ICTL_H = 0x05DD); -PROVIDE(UCA0IV = 0x05DE); -/************************************************************ -* USCI B0 -************************************************************/ -PROVIDE(UCB0CTLW0 = 0x05E0); -PROVIDE(UCB0CTLW0_L = 0x05E0); -PROVIDE(UCB0CTLW0_H = 0x05E1); -PROVIDE(UCB0BRW = 0x05E6); -PROVIDE(UCB0BRW_L = 0x05E6); -PROVIDE(UCB0BRW_H = 0x05E7); -PROVIDE(UCB0STAT = 0x05EA); -PROVIDE(UCB0RXBUF = 0x05EC); -PROVIDE(UCB0TXBUF = 0x05EE); -PROVIDE(UCB0I2COA = 0x05F0); -PROVIDE(UCB0I2COA_L = 0x05F0); -PROVIDE(UCB0I2COA_H = 0x05F1); -PROVIDE(UCB0I2CSA = 0x05F2); -PROVIDE(UCB0I2CSA_L = 0x05F2); -PROVIDE(UCB0I2CSA_H = 0x05F3); -PROVIDE(UCB0ICTL = 0x05FC); -PROVIDE(UCB0ICTL_L = 0x05FC); -PROVIDE(UCB0ICTL_H = 0x05FD); -PROVIDE(UCB0IV = 0x05FE); -/************************************************************ -* USCI A1 -************************************************************/ -PROVIDE(UCA1CTLW0 = 0x0600); -PROVIDE(UCA1CTLW0_L = 0x0600); -PROVIDE(UCA1CTLW0_H = 0x0601); -PROVIDE(UCA1BRW = 0x0606); -PROVIDE(UCA1BRW_L = 0x0606); -PROVIDE(UCA1BRW_H = 0x0607); -PROVIDE(UCA1MCTL = 0x0608); -PROVIDE(UCA1STAT = 0x060A); -PROVIDE(UCA1RXBUF = 0x060C); -PROVIDE(UCA1TXBUF = 0x060E); -PROVIDE(UCA1ABCTL = 0x0610); -PROVIDE(UCA1IRCTL = 0x0612); -PROVIDE(UCA1IRCTL_L = 0x0612); -PROVIDE(UCA1IRCTL_H = 0x0613); -PROVIDE(UCA1ICTL = 0x061C); -PROVIDE(UCA1ICTL_L = 0x061C); -PROVIDE(UCA1ICTL_H = 0x061D); -PROVIDE(UCA1IV = 0x061E); -/************************************************************ -* USCI B1 -************************************************************/ -PROVIDE(UCB1CTLW0 = 0x0620); -PROVIDE(UCB1CTLW0_L = 0x0620); -PROVIDE(UCB1CTLW0_H = 0x0621); -PROVIDE(UCB1BRW = 0x0626); -PROVIDE(UCB1BRW_L = 0x0626); -PROVIDE(UCB1BRW_H = 0x0627); -PROVIDE(UCB1STAT = 0x062A); -PROVIDE(UCB1RXBUF = 0x062C); -PROVIDE(UCB1TXBUF = 0x062E); -PROVIDE(UCB1I2COA = 0x0630); -PROVIDE(UCB1I2COA_L = 0x0630); -PROVIDE(UCB1I2COA_H = 0x0631); -PROVIDE(UCB1I2CSA = 0x0632); -PROVIDE(UCB1I2CSA_L = 0x0632); -PROVIDE(UCB1I2CSA_H = 0x0633); -PROVIDE(UCB1ICTL = 0x063C); -PROVIDE(UCB1ICTL_L = 0x063C); -PROVIDE(UCB1ICTL_H = 0x063D); -PROVIDE(UCB1IV = 0x063E); -/************************************************************ -* WATCHDOG TIMER A -************************************************************/ -PROVIDE(WDTCTL = 0x015C); -PROVIDE(WDTCTL_L = 0x015C); -PROVIDE(WDTCTL_H = 0x015D); -/************************************************************ -* TLV Descriptors -************************************************************/ -/************************************************************ -* Interrupt Vectors (offset from 0xFF80) -************************************************************/ -/************************************************************ -* End of Modules -************************************************************/ From 3f0f7cfd07e04e6a5a154de44b94b074ab5b4307 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 29 Oct 2019 12:52:56 -0400 Subject: [PATCH 42/71] dcd_msp430x5xx: Clarify hardware STALL behavior and current vs ideal behavior of driver in comments. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index a6efee094..e2a9a9e95 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -515,9 +515,12 @@ static void handle_setup_packet(void) _setup_packet[i] = setup_buf[i]; } - // The NAK bits must be clear to receive a SETUP packet. Clearing SETUPIFG - // by reading USBVECINT does not set NAK, so now that we have a SETUP packet - // force NAKs. + // The EP0 NAK bits must be clear to receive a SETUP packet, according to the + // manual (we don't do this right now- see below comments). + // Race conditions where the hardware STALLs can occur if the NAK bits aren't + // set for both IN/OUT EP0. Clearing SETUPIFG by reading USBVECINT does not + // set NAK, so now that we have a SETUP packet, force NAKs. + // FIXME: Explain more accurately why the STALL occurs. USBIEPCNT_0 |= NAK; USBOEPCNT_0 |= NAK; dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true); @@ -526,7 +529,7 @@ static void handle_setup_packet(void) void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) { // Setup is special- reading USBVECINT to handle setup packets is done to - // stop NAKs on EP0. + // stop hardware-generated NAKs on EP0. uint8_t setup_status = USBIFG & SETUPIFG; if(setup_status) @@ -543,7 +546,14 @@ void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); break; - // Clear the NAK on EP 0 after a SETUP packet is received. + // Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet + // is received. The NAK bits for EP0 should still be set because it's + // possible for the hardware to STALL in the middle of a control xfer + // if the EP0 NAK bits aren't set properly. + // See: https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/845259 + // FIXME: Per manual, we should be clearing the NAK bits of EP0 after the + // Status Phase of a control xfer is done, in preparation of another + // possible setup packet. No clean way to do this right now. case USBVECINT_SETUP_PACKET_RECEIVED: break; From 5d585c03bdf5059c7856d5ee32a754bd3cdbdd2f Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 29 Oct 2019 14:08:39 -0400 Subject: [PATCH 43/71] dcd_msp430x5xx: Improve comments regarding SETUP packet handling. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 35 +++++++++++++++------ 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index e2a9a9e95..3a73cf9bf 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -515,12 +515,9 @@ static void handle_setup_packet(void) _setup_packet[i] = setup_buf[i]; } - // The EP0 NAK bits must be clear to receive a SETUP packet, according to the - // manual (we don't do this right now- see below comments). - // Race conditions where the hardware STALLs can occur if the NAK bits aren't - // set for both IN/OUT EP0. Clearing SETUPIFG by reading USBVECINT does not - // set NAK, so now that we have a SETUP packet, force NAKs. - // FIXME: Explain more accurately why the STALL occurs. + // Clearing SETUPIFG by reading USBVECINT does not set NAK, so now that we + // have a SETUP packet, force NAKs until tinyusb can handle the SETUP + // packet and prepare for a new xfer. USBIEPCNT_0 |= NAK; USBOEPCNT_0 |= NAK; dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true); @@ -547,13 +544,31 @@ void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) break; // Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet - // is received. The NAK bits for EP0 should still be set because it's - // possible for the hardware to STALL in the middle of a control xfer - // if the EP0 NAK bits aren't set properly. + // is received. At this point, even though the hardware is no longer + // forcing NAKs, the EP0 NAK bits should still be set to avoid + // sending/receiving data before tinyusb is ready. + // + // Furthermore, it's possible for the hardware to STALL in the middle of + // a control xfer if the EP0 NAK bits aren't set properly. // See: https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/845259 + // From my testing, if all of the following hold: + // * OUT EP0 NAK is cleared. + // * IN EP0 NAK is set. + // * DIR bit in USBCTL is clear. + // and an IN packet is received on EP0, the USB core will STALL. Setting + // both EP0 NAKs manually when a SETUP packet is received, as is done + // in handle_setup_packet(), avoids meeting STALL conditions. + // + // TODO: Figure out/explain why the STALL condition can be reached in the + // first place. When I first noticed the STALL, the only two places I + // touched the NAK bits were in dcd_edpt_xfer() and to _set_ (sic) them in + // bus_reset(). SETUP packet handling should've been unaffected. + // // FIXME: Per manual, we should be clearing the NAK bits of EP0 after the // Status Phase of a control xfer is done, in preparation of another - // possible setup packet. No clean way to do this right now. + // possible SETUP packet. We don't do this right now, as there is no + // "Status Phase done" callback the driver can use. However, SETUP packets + // _are_ correctly handled by the USB core without clearing the NAKs. case USBVECINT_SETUP_PACKET_RECEIVED: break; From 51a834f0ae58ba68b390b2e83d28303689759f50 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 2 Nov 2019 23:04:19 +0700 Subject: [PATCH 44/71] fix travis due to msp430 gcc link changes --- .travis.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 6c63a51f2..ab84d757e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -16,9 +16,9 @@ install: - gem install ceedling before_script: - - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/exports/msp430-gcc-8.2.0.52_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.b2 - - tar -xjf /tmp/msp430-gcc.tar.b2 - - export PATH=$PATH:$PWD/msp430-gcc-8.2.0.52_linux64/bin + - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 + - tar -xjf /tmp/msp430-gcc.tar.bz2 + - export PATH=$PATH:$PWD/msp430-gcc-8.3.0.16_linux64/bin - arm-none-eabi-gcc --version - msp430-elf-gcc --version From 1b51b78eafb1a078aa7fc8caf57d01d92b84ca0f Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 3 Nov 2019 00:17:17 +0700 Subject: [PATCH 45/71] hack the request length for the first get device descriptor if EP0 size =8 or 16 to prevent usbd control send out ZLP --- src/device/usbd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/device/usbd.c b/src/device/usbd.c index 8661717f5..360881f34 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -771,9 +771,13 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const uint16_t len = sizeof(tusb_desc_device_t); // Only send up to EP0 Packet Size if not addressed + // This only happens with the very first get device descriptor and EP0 size = 8 or 16. if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed) { len = CFG_TUD_ENDPOINT0_SIZE; + + // Hack here: we modify the request length to prevent usbd_control response with zlp + ((tusb_control_request_t*) p_request)->wLength = CFG_TUD_ENDPOINT0_SIZE; } return tud_control_xfer(rhport, p_request, (void*) tud_descriptor_device_cb(), len); From 2d98dae13e5a380bcaf8033a886d1220d174710d Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 3 Nov 2019 11:45:41 +0700 Subject: [PATCH 46/71] fix travis build issue --- examples/device/dfu_rt/src/tusb_config.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/examples/device/dfu_rt/src/tusb_config.h b/examples/device/dfu_rt/src/tusb_config.h index b4f7a5562..7e79995d9 100644 --- a/examples/device/dfu_rt/src/tusb_config.h +++ b/examples/device/dfu_rt/src/tusb_config.h @@ -51,7 +51,9 @@ // DEVICE CONFIGURATION //-------------------------------------------------------------------- +#ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 +#endif //------------- CLASS -------------// From 65e96e5d525ea02e0ca7f265a4d62b4f428cc821 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 3 Nov 2019 18:00:07 +0700 Subject: [PATCH 47/71] added optional dcd_control_status_complete() --- src/device/dcd.h | 4 ++++ src/device/usbd_control.c | 1 + test/test/device/usbd/test_usbd.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/src/device/dcd.h b/src/device/dcd.h index 9fa98c669..c88465cbb 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -119,6 +119,10 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr); // clear stall, data toggle is also reset to DATA0 void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr); +// Invoked when a control transfer's status stage is complete. +// May help DCD to prepare for next control transfer, this API is optional. +void dcd_control_status_complete(uint8_t rhport) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // Event API //--------------------------------------------------------------------+ diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index f41614ef1..d37e9ec2a 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -129,6 +129,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction ) { TU_ASSERT(0 == xferred_bytes); + if (dcd_control_status_complete) dcd_control_status_complete(rhport); return true; } diff --git a/test/test/device/usbd/test_usbd.c b/test/test/device/usbd/test_usbd.c index add947b3d..a4063a488 100644 --- a/test/test/device/usbd/test_usbd.c +++ b/test/test/device/usbd/test_usbd.c @@ -231,5 +231,7 @@ void test_usbd_control_in_zlp(void) dcd_edpt_xfer_ExpectAndReturn(rhport, EDPT_CTRL_OUT, NULL, 0, true); dcd_event_xfer_complete(rhport, EDPT_CTRL_OUT, 0, 0, false); + dcd_control_status_complete_Expect(rhport); + tud_task(); } From acbb535668e9dec53d49cfeff0fcbf3df458eda3 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 19:11:24 +0700 Subject: [PATCH 48/71] change msp430 flash tool from mspdebug to TI MSP430Flasher --- hw/bsp/msp_exp430f5529lp/board.mk | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index 95192a990..ec393e0fc 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -16,9 +16,11 @@ INC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include VENDOR = ti CHIP_FAMILY = msp430x5xx -# Path to mspdebug, should be added into system path -MSPDEBUG = mspdebug +# export for libmsp430.so to same installation +export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher)) -# flash target using mspdebug. -flash: $(BUILD)/$(BOARD)-firmware.elf - $(MSPDEBUG) tilib "prog $<" --allow-fw-update +# flash target using TI MSP430-Flasher +# http://www.ti.com/tool/MSP430-FLASHER +# Please add its installation dir to PATH +flash: $(BUILD)/$(BOARD)-firmware.hex + MSP430Flasher -w $< -z [VCC] From 5cb6500ac8730179978a9baecebcc0874fde946e Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 19:24:03 +0700 Subject: [PATCH 49/71] fix msp430 ci build --- .github/workflows/build.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 4cf2f1390..66fea6916 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -39,8 +39,11 @@ jobs: npm install --global xpm xpm install --global @xpack-dev-tools/arm-none-eabi-gcc@latest xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest + wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 + tar -xjf /tmp/msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" + echo "::add-path::$GITHUB_WORKSPACE/msp430-gcc-8.3.0.16_linux64/bin" - name: Checkout TinyUSB uses: actions/checkout@v2 From da3184624638e409daf8370a969c757b923d5869 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 19:26:40 +0700 Subject: [PATCH 50/71] fix unit test --- test/test/device/usbd/test_usbd.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/test/test/device/usbd/test_usbd.c b/test/test/device/usbd/test_usbd.c index 546bc885c..af30aaf8f 100644 --- a/test/test/device/usbd/test_usbd.c +++ b/test/test/device/usbd/test_usbd.c @@ -239,7 +239,5 @@ void test_usbd_control_in_zlp(void) dcd_event_xfer_complete(rhport, EDPT_CTRL_OUT, 0, 0, false); dcd_edpt0_status_complete_ExpectWithArray(rhport, &req_get_desc_configuration, 1); - dcd_control_status_complete_Expect(rhport); - tud_task(); } From cf0074e5dac34f122686f8ec14644c30b326e56b Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 20:20:36 +0700 Subject: [PATCH 51/71] try to fix msp430 gcc install --- .github/workflows/build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 66fea6916..f6f9e2e24 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -39,8 +39,8 @@ jobs: npm install --global xpm xpm install --global @xpack-dev-tools/arm-none-eabi-gcc@latest xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 - tar -xjf /tmp/msp430-gcc.tar.bz2 + wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O msp430-gcc.tar.bz2 + tar -xjf msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" echo "::add-path::$GITHUB_WORKSPACE/msp430-gcc-8.3.0.16_linux64/bin" From e710f7a47b0630b5f72df2fc57a13beab7eb1d8c Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 20:33:59 +0700 Subject: [PATCH 52/71] more on ci --- .github/workflows/build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index f6f9e2e24..ef2e6d524 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -40,7 +40,7 @@ jobs: xpm install --global @xpack-dev-tools/arm-none-eabi-gcc@latest xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O msp430-gcc.tar.bz2 - tar -xjf msp430-gcc.tar.bz2 + tar -xaf msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" echo "::add-path::$GITHUB_WORKSPACE/msp430-gcc-8.3.0.16_linux64/bin" From 922763490500ca75158771230001f7c08fbcbc00 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 20:49:13 +0700 Subject: [PATCH 53/71] test ci pwd before checkout --- .github/workflows/build.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index ef2e6d524..a7e86c53c 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -41,6 +41,7 @@ jobs: xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O msp430-gcc.tar.bz2 tar -xaf msp430-gcc.tar.bz2 + echo $PWD echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" echo "::add-path::$GITHUB_WORKSPACE/msp430-gcc-8.3.0.16_linux64/bin" From c34e03986cdc1aa8b9a80067b9141c94500b536a Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 21:00:53 +0700 Subject: [PATCH 54/71] more ci test --- .github/workflows/build.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index a7e86c53c..4d3a97f57 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -39,12 +39,12 @@ jobs: npm install --global xpm xpm install --global @xpack-dev-tools/arm-none-eabi-gcc@latest xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O msp430-gcc.tar.bz2 - tar -xaf msp430-gcc.tar.bz2 + wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 + tar -C $HOME -vxaf /tmp/msp430-gcc.tar.bz2 echo $PWD echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" - echo "::add-path::$GITHUB_WORKSPACE/msp430-gcc-8.3.0.16_linux64/bin" + echo "::add-path::$HOME/msp430-gcc-8.3.0.16_linux64/bin" - name: Checkout TinyUSB uses: actions/checkout@v2 From a101a4f0987fc40a99b71f103cff3143b5bc5e2a Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 21:07:14 +0700 Subject: [PATCH 55/71] finally fixed the ci, clean up --- .github/workflows/build.yml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 4d3a97f57..589c74d2d 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -40,11 +40,10 @@ jobs: xpm install --global @xpack-dev-tools/arm-none-eabi-gcc@latest xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 - tar -C $HOME -vxaf /tmp/msp430-gcc.tar.bz2 - echo $PWD + tar -C $HOME -xaf /tmp/msp430-gcc.tar.bz2 echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/arm-none-eabi-gcc/*/.content/bin`" echo "::add-path::`echo $HOME/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/*/.content/bin`" - echo "::add-path::$HOME/msp430-gcc-8.3.0.16_linux64/bin" + echo "::add-path::`echo $HOME/msp430-gcc-*_linux64/bin`" - name: Checkout TinyUSB uses: actions/checkout@v2 From ef5789d7c95445fb5093ad4e2342b49526a77e29 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 22 Mar 2020 21:29:13 +0700 Subject: [PATCH 56/71] skip freertos and lwip webserver example for msp430 --- examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx | 0 examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx | 1 + examples/device/net_lwip_webserver/Makefile | 2 ++ 3 files changed, 3 insertions(+) create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx create mode 100644 examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx b/examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx new file mode 100644 index 000000000..e69de29bb diff --git a/examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx b/examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx new file mode 100644 index 000000000..17600f062 --- /dev/null +++ b/examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx @@ -0,0 +1 @@ +too many warnings for 16-bit integer overflow diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile index a153c30be..fa93cf87f 100644 --- a/examples/device/net_lwip_webserver/Makefile +++ b/examples/device/net_lwip_webserver/Makefile @@ -17,6 +17,8 @@ INC += \ # Example source EXAMPLE_SOURCE += $(wildcard src/*.c) SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) + +# lwip sources SRC_C += \ lib/lwip/src/core/altcp.c \ lib/lwip/src/core/altcp_alloc.c \ From c47d9c3c683c2be632b0d9e99eb0698973fe1795 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 23 Mar 2020 19:21:44 +0700 Subject: [PATCH 57/71] upgrade nrfx from 2.0.0 to 2.1.0 --- hw/mcu/nordic/nrfx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mcu/nordic/nrfx b/hw/mcu/nordic/nrfx index 7a4c9d946..281cc2e17 160000 --- a/hw/mcu/nordic/nrfx +++ b/hw/mcu/nordic/nrfx @@ -1 +1 @@ -Subproject commit 7a4c9d946cf1801771fc180acdbf7b878f270093 +Subproject commit 281cc2e178fd9a470d844b3afdea9eb322a0b0e8 From feff6aafd5a2ed4826d3de07ad2e33695e1cabc8 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 23 Mar 2020 22:36:21 +0700 Subject: [PATCH 58/71] add CMSIS_5 as submodule --- .gitmodules | 3 +++ lib/CMSIS_5 | 1 + 2 files changed, 4 insertions(+) create mode 160000 lib/CMSIS_5 diff --git a/.gitmodules b/.gitmodules index 0f9ad34c7..60cec00d0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -28,3 +28,6 @@ [submodule "lib/FreeRTOS"] path = lib/FreeRTOS url = https://github.com/FreeRTOS/FreeRTOS.git +[submodule "lib/CMSIS_5"] + path = lib/CMSIS_5 + url = https://github.com/ARM-software/CMSIS_5.git diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 new file mode 160000 index 000000000..3ae681dae --- /dev/null +++ b/lib/CMSIS_5 @@ -0,0 +1 @@ +Subproject commit 3ae681dae15bfb76ca7601efad2f88834249baad From 9e0ffbe30f09f279be5e31f0041efaebd8b27f56 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 23 Mar 2020 22:51:17 +0700 Subject: [PATCH 59/71] house keeping --- hw/bsp/mimxrt1020_evk/board.mk | 1 - hw/bsp/mimxrt1050_evkb/board.mk | 1 - hw/bsp/mimxrt1060_evk/board.mk | 1 - hw/bsp/mimxrt1064_evk/board.mk | 1 - hw/bsp/teensy_40/board.mk | 1 - 5 files changed, 5 deletions(-) diff --git a/hw/bsp/mimxrt1020_evk/board.mk b/hw/bsp/mimxrt1020_evk/board.mk index 5720da955..52148b684 100644 --- a/hw/bsp/mimxrt1020_evk/board.mk +++ b/hw/bsp/mimxrt1020_evk/board.mk @@ -11,7 +11,6 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX # mcu driver cause following warnings -#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs CFLAGS += -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1021 diff --git a/hw/bsp/mimxrt1050_evkb/board.mk b/hw/bsp/mimxrt1050_evkb/board.mk index de07cdb0a..4b642085d 100644 --- a/hw/bsp/mimxrt1050_evkb/board.mk +++ b/hw/bsp/mimxrt1050_evkb/board.mk @@ -11,7 +11,6 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX # mcu driver cause following warnings -#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs CFLAGS += -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1052 diff --git a/hw/bsp/mimxrt1060_evk/board.mk b/hw/bsp/mimxrt1060_evk/board.mk index 2f6d0f7a3..fae0ad0ae 100644 --- a/hw/bsp/mimxrt1060_evk/board.mk +++ b/hw/bsp/mimxrt1060_evk/board.mk @@ -11,7 +11,6 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX # mcu driver cause following warnings -#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs CFLAGS += -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1062 diff --git a/hw/bsp/mimxrt1064_evk/board.mk b/hw/bsp/mimxrt1064_evk/board.mk index 6ebf23271..d8a892442 100644 --- a/hw/bsp/mimxrt1064_evk/board.mk +++ b/hw/bsp/mimxrt1064_evk/board.mk @@ -11,7 +11,6 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX # mcu driver cause following warnings -#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs CFLAGS += -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1064 diff --git a/hw/bsp/teensy_40/board.mk b/hw/bsp/teensy_40/board.mk index 6ec04a47b..0a19fe63a 100644 --- a/hw/bsp/teensy_40/board.mk +++ b/hw/bsp/teensy_40/board.mk @@ -11,7 +11,6 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX # mcu driver cause following warnings -#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs CFLAGS += -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1062 From 056d0bb4bfd8fe1aca7227cd613a3ae85bed28ee Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 23 Mar 2020 22:52:59 +0700 Subject: [PATCH 60/71] remove -Wnested-externs since many driver does this including CMSIS_5 --- examples/make.mk | 1 - hw/bsp/lpcxpresso11u37/board.mk | 2 +- hw/bsp/lpcxpresso1347/board.mk | 2 +- hw/bsp/lpcxpresso51u68/board.mk | 2 +- hw/bsp/lpcxpresso55s69/board.mk | 2 +- hw/bsp/mbed1768/board.mk | 2 +- 6 files changed, 5 insertions(+), 6 deletions(-) diff --git a/examples/make.mk b/examples/make.mk index 12ce3fd0c..3c2db88c4 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -72,7 +72,6 @@ CFLAGS += \ -Wsign-compare \ -Wmissing-format-attribute \ -Wno-deprecated-declarations \ - -Wnested-externs \ -Wunreachable-code \ -Wno-error=lto-type-mismatch \ -ffunction-sections \ diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk index 790516c7d..d1c48a2e5 100644 --- a/hw/bsp/lpcxpresso11u37/board.mk +++ b/hw/bsp/lpcxpresso11u37/board.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' # mcu driver cause following warnings -CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes -Wno-error=unused-parameter +CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk index 6a72a7987..6dc3937f6 100644 --- a/hw/bsp/lpcxpresso1347/board.mk +++ b/hw/bsp/lpcxpresso1347/board.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' # startup.c and lpc_types.h cause following errors -CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes +CFLAGS += -Wno-error=strict-prototypes MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpcxpresso51u68/board.mk index 61fbc0623..7dc7de341 100644 --- a/hw/bsp/lpcxpresso51u68/board.mk +++ b/hw/bsp/lpcxpresso51u68/board.mk @@ -9,7 +9,7 @@ CFLAGS += \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' # mcu driver cause following warnings -CFLAGS += -Wno-error=nested-externs -Wno-error=unused-parameter +CFLAGS += -Wno-error=unused-parameter MCU_DIR = hw/mcu/nxp/sdk/devices/LPC51U68 diff --git a/hw/bsp/lpcxpresso55s69/board.mk b/hw/bsp/lpcxpresso55s69/board.mk index 4cb2d00e5..24c5ae89c 100644 --- a/hw/bsp/lpcxpresso55s69/board.mk +++ b/hw/bsp/lpcxpresso55s69/board.mk @@ -11,7 +11,7 @@ CFLAGS += \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal -Wno-error=nested-externs +CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal MCU_DIR = hw/mcu/nxp/sdk/devices/LPC55S69 diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk index 60beb5e39..3bdc8a27a 100644 --- a/hw/bsp/mbed1768/board.mk +++ b/hw/bsp/mbed1768/board.mk @@ -10,7 +10,7 @@ CFLAGS += \ -DRTC_EV_SUPPORT=0 # startup.c and lpc_types.h cause following errors -CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes +CFLAGS += -Wno-error=strict-prototypes MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x From 9f5042399eb2f866be2ebaf22c283b80b878f5ba Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 08:49:48 +0700 Subject: [PATCH 61/71] add cmsis_4 as submodule --- .gitmodules | 3 +++ lib/CMSIS_4 | 1 + 2 files changed, 4 insertions(+) create mode 160000 lib/CMSIS_4 diff --git a/.gitmodules b/.gitmodules index 60cec00d0..c1c5cefe7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,3 +31,6 @@ [submodule "lib/CMSIS_5"] path = lib/CMSIS_5 url = https://github.com/ARM-software/CMSIS_5.git +[submodule "lib/CMSIS_4"] + path = lib/CMSIS_4 + url = https://github.com/ARM-software/CMSIS.git diff --git a/lib/CMSIS_4 b/lib/CMSIS_4 new file mode 160000 index 000000000..f2cad4345 --- /dev/null +++ b/lib/CMSIS_4 @@ -0,0 +1 @@ +Subproject commit f2cad4345783c948ed4a7f5cdb02cdc0856366f1 From 905c4b71d1409abf0d107adc0d5df6eedde3e3cf Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 08:51:11 +0700 Subject: [PATCH 62/71] nrf use new cmsis_4 submodule for core header --- hw/bsp/adafruit_clue/board.mk | 2 +- hw/bsp/circuitplayground_bluefruit/board.mk | 2 +- hw/bsp/feather_nrf52840_express/board.mk | 2 +- hw/bsp/feather_nrf52840_sense/board.mk | 2 +- hw/bsp/nrf52840_mdk_dongle/board.mk | 2 +- hw/bsp/pca10056/board.mk | 2 +- hw/bsp/pca10059/board.mk | 2 +- hw/bsp/pca10100/board.mk | 2 +- hw/bsp/raytac_mdbt50q_rx/board.mk | 2 +- .../nordic/cmsis/Include/arm_common_tables.h | 136 - .../nordic/cmsis/Include/arm_const_structs.h | 79 - hw/mcu/nordic/cmsis/Include/arm_math.h | 7154 ----------------- hw/mcu/nordic/cmsis/Include/cmsis_armcc.h | 734 -- hw/mcu/nordic/cmsis/Include/cmsis_armcc_V6.h | 1800 ----- hw/mcu/nordic/cmsis/Include/cmsis_gcc.h | 1373 ---- hw/mcu/nordic/cmsis/Include/core_cm0.h | 798 -- hw/mcu/nordic/cmsis/Include/core_cm0plus.h | 914 --- hw/mcu/nordic/cmsis/Include/core_cm3.h | 1763 ---- hw/mcu/nordic/cmsis/Include/core_cm4.h | 1937 ----- hw/mcu/nordic/cmsis/Include/core_cm7.h | 2512 ------ hw/mcu/nordic/cmsis/Include/core_cmFunc.h | 87 - hw/mcu/nordic/cmsis/Include/core_cmInstr.h | 87 - hw/mcu/nordic/cmsis/Include/core_cmSimd.h | 96 - hw/mcu/nordic/cmsis/Include/core_sc000.h | 926 --- hw/mcu/nordic/cmsis/Include/core_sc300.h | 1745 ---- 25 files changed, 9 insertions(+), 22150 deletions(-) delete mode 100644 hw/mcu/nordic/cmsis/Include/arm_common_tables.h delete mode 100644 hw/mcu/nordic/cmsis/Include/arm_const_structs.h delete mode 100644 hw/mcu/nordic/cmsis/Include/arm_math.h delete mode 100644 hw/mcu/nordic/cmsis/Include/cmsis_armcc.h delete mode 100644 hw/mcu/nordic/cmsis/Include/cmsis_armcc_V6.h delete mode 100644 hw/mcu/nordic/cmsis/Include/cmsis_gcc.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cm0.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cm0plus.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cm3.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cm4.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cm7.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cmFunc.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cmInstr.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_cmSimd.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_sc000.h delete mode 100644 hw/mcu/nordic/cmsis/Include/core_sc300.h diff --git a/hw/bsp/adafruit_clue/board.mk b/hw/bsp/adafruit_clue/board.mk index 3b2137d74..be8c5bf56 100644 --- a/hw/bsp/adafruit_clue/board.mk +++ b/hw/bsp/adafruit_clue/board.mk @@ -28,7 +28,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/circuitplayground_bluefruit/board.mk b/hw/bsp/circuitplayground_bluefruit/board.mk index 3b2137d74..be8c5bf56 100644 --- a/hw/bsp/circuitplayground_bluefruit/board.mk +++ b/hw/bsp/circuitplayground_bluefruit/board.mk @@ -28,7 +28,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/feather_nrf52840_express/board.mk b/hw/bsp/feather_nrf52840_express/board.mk index 8b32253db..9f38d6796 100644 --- a/hw/bsp/feather_nrf52840_express/board.mk +++ b/hw/bsp/feather_nrf52840_express/board.mk @@ -29,7 +29,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/feather_nrf52840_sense/board.mk b/hw/bsp/feather_nrf52840_sense/board.mk index 3b2137d74..be8c5bf56 100644 --- a/hw/bsp/feather_nrf52840_sense/board.mk +++ b/hw/bsp/feather_nrf52840_sense/board.mk @@ -28,7 +28,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/nrf52840_mdk_dongle/board.mk b/hw/bsp/nrf52840_mdk_dongle/board.mk index b92556002..0ab5ff2e1 100644 --- a/hw/bsp/nrf52840_mdk_dongle/board.mk +++ b/hw/bsp/nrf52840_mdk_dongle/board.mk @@ -27,7 +27,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/pca10056/board.mk b/hw/bsp/pca10056/board.mk index c34b451ce..b2f119626 100644 --- a/hw/bsp/pca10056/board.mk +++ b/hw/bsp/pca10056/board.mk @@ -29,7 +29,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/pca10059/board.mk b/hw/bsp/pca10059/board.mk index 19ec3eaea..8cce65eb9 100644 --- a/hw/bsp/pca10059/board.mk +++ b/hw/bsp/pca10059/board.mk @@ -28,7 +28,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/pca10100/board.mk b/hw/bsp/pca10100/board.mk index d7ac7ec4f..0ec8f0f69 100644 --- a/hw/bsp/pca10100/board.mk +++ b/hw/bsp/pca10100/board.mk @@ -29,7 +29,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52833.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/bsp/raytac_mdbt50q_rx/board.mk b/hw/bsp/raytac_mdbt50q_rx/board.mk index d446d3de7..0960ffe55 100644 --- a/hw/bsp/raytac_mdbt50q_rx/board.mk +++ b/hw/bsp/raytac_mdbt50q_rx/board.mk @@ -27,7 +27,7 @@ SRC_C += \ hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \ INC += \ - $(TOP)/hw/mcu/nordic/cmsis/Include \ + $(TOP)/lib/CMSIS_4/CMSIS/Include \ $(TOP)/hw/mcu/nordic \ $(TOP)/hw/mcu/nordic/nrfx \ $(TOP)/hw/mcu/nordic/nrfx/mdk \ diff --git a/hw/mcu/nordic/cmsis/Include/arm_common_tables.h b/hw/mcu/nordic/cmsis/Include/arm_common_tables.h deleted file mode 100644 index 8742a5699..000000000 --- a/hw/mcu/nordic/cmsis/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/hw/mcu/nordic/cmsis/Include/arm_const_structs.h b/hw/mcu/nordic/cmsis/Include/arm_const_structs.h deleted file mode 100644 index 726d06eb6..000000000 --- a/hw/mcu/nordic/cmsis/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/hw/mcu/nordic/cmsis/Include/arm_math.h b/hw/mcu/nordic/cmsis/Include/arm_math.h deleted file mode 100644 index d33f8a9b3..000000000 --- a/hw/mcu/nordic/cmsis/Include/arm_math.h +++ /dev/null @@ -1,7154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/hw/mcu/nordic/cmsis/Include/cmsis_armcc.h b/hw/mcu/nordic/cmsis/Include/cmsis_armcc.h deleted file mode 100644 index 74c49c67d..000000000 --- a/hw/mcu/nordic/cmsis/Include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/hw/mcu/nordic/cmsis/Include/cmsis_armcc_V6.h b/hw/mcu/nordic/cmsis/Include/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce..000000000 --- a/hw/mcu/nordic/cmsis/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/hw/mcu/nordic/cmsis/Include/cmsis_gcc.h b/hw/mcu/nordic/cmsis/Include/cmsis_gcc.h deleted file mode 100644 index bb89fbba9..000000000 --- a/hw/mcu/nordic/cmsis/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cm0.h b/hw/mcu/nordic/cmsis/Include/core_cm0.h deleted file mode 100644 index 711dad551..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cm0plus.h b/hw/mcu/nordic/cmsis/Include/core_cm0plus.h deleted file mode 100644 index b04aa3905..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cm3.h b/hw/mcu/nordic/cmsis/Include/core_cm3.h deleted file mode 100644 index b4ac4c7b0..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cm4.h b/hw/mcu/nordic/cmsis/Include/core_cm4.h deleted file mode 100644 index dc840ebf2..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cm7.h b/hw/mcu/nordic/cmsis/Include/core_cm7.h deleted file mode 100644 index 3b7530ad5..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cmFunc.h b/hw/mcu/nordic/cmsis/Include/core_cmFunc.h deleted file mode 100644 index 652a48af0..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cmInstr.h b/hw/mcu/nordic/cmsis/Include/core_cmInstr.h deleted file mode 100644 index f474b0e6f..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/hw/mcu/nordic/cmsis/Include/core_cmSimd.h b/hw/mcu/nordic/cmsis/Include/core_cmSimd.h deleted file mode 100644 index 66bf5c2a7..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/hw/mcu/nordic/cmsis/Include/core_sc000.h b/hw/mcu/nordic/cmsis/Include/core_sc000.h deleted file mode 100644 index 514dbd81b..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/nordic/cmsis/Include/core_sc300.h b/hw/mcu/nordic/cmsis/Include/core_sc300.h deleted file mode 100644 index 8bd18aa31..000000000 --- a/hw/mcu/nordic/cmsis/Include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ From a2aa50d2ef0095ccccc4797ad8da028c00c9e86a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 09:33:11 +0700 Subject: [PATCH 63/71] update cmsis_5 --- lib/CMSIS_5 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 index 3ae681dae..02459e61c 160000 --- a/lib/CMSIS_5 +++ b/lib/CMSIS_5 @@ -1 +1 @@ -Subproject commit 3ae681dae15bfb76ca7601efad2f88834249baad +Subproject commit 02459e61c2941a4c1f6e8462500faac4c31ed654 From c05990af959d5f505899e3122fbe34cd7f24e77e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 09:52:48 +0700 Subject: [PATCH 64/71] change cmsis5 to master --- .gitmodules | 1 + lib/CMSIS_5 | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index c1c5cefe7..32e537dce 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,6 +31,7 @@ [submodule "lib/CMSIS_5"] path = lib/CMSIS_5 url = https://github.com/ARM-software/CMSIS_5.git + branch = master [submodule "lib/CMSIS_4"] path = lib/CMSIS_4 url = https://github.com/ARM-software/CMSIS.git diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 index 02459e61c..4a65d8801 160000 --- a/lib/CMSIS_5 +++ b/lib/CMSIS_5 @@ -1 +1 @@ -Subproject commit 02459e61c2941a4c1f6e8462500faac4c31ed654 +Subproject commit 4a65d88011a1595b7c8b42fa0d70b7bdfc132acc From 94528ff65bc984093a39ae102507f94f61af068c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 10:13:48 +0700 Subject: [PATCH 65/71] checkout v2 with submodule --- .github/workflows/build.yml | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 4cf2f1390..ba1008aee 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -44,13 +44,15 @@ jobs: - name: Checkout TinyUSB uses: actions/checkout@v2 + with: + submodules: 'recursive' - - name: Checkout submodules - shell: bash - run: | - auth_header="$(git config --local --get http.https://github.com/.extraheader)" - git submodule sync --recursive - git -c "http.extraheader=$auth_header" -c protocol.version=2 submodule update --init --force --recursive + #- name: Checkout Submodules + # shell: bash + # run: | + # auth_header="$(git config --local --get http.https://github.com/.extraheader)" + # git submodule sync --recursive + # git -c "http.extraheader=$auth_header" -c protocol.version=2 submodule update --init --force --recursive - name: Build run: python3 tools/build_all.py ${{ matrix.example }} From 86a8ffa4309eec6c67763e9fa1c3ef014424e856 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 10:24:38 +0700 Subject: [PATCH 66/71] ci checkout submodules --- .github/workflows/build.yml | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index ba1008aee..966f190f3 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -44,15 +44,14 @@ jobs: - name: Checkout TinyUSB uses: actions/checkout@v2 - with: - submodules: 'recursive' - #- name: Checkout Submodules - # shell: bash - # run: | - # auth_header="$(git config --local --get http.https://github.com/.extraheader)" - # git submodule sync --recursive - # git -c "http.extraheader=$auth_header" -c protocol.version=2 submodule update --init --force --recursive + - name: Checkout Submodules + shell: bash + run: | + #auth_header="$(git config --local --get http.https://github.com/.extraheader)" + git submodule sync --recursive + #git -c "http.extraheader=$auth_header" -c protocol.version=2 submodule update --init --force --recursive + git submodule update --init --recursive - name: Build run: python3 tools/build_all.py ${{ matrix.example }} From 16d6da18e3215608e30ad23897162f65740530cd Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 10:28:34 +0700 Subject: [PATCH 67/71] clean up action checkout for sbumodules --- .github/workflows/build.yml | 3 --- .gitmodules | 1 - 2 files changed, 4 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 966f190f3..8005c114d 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -46,11 +46,8 @@ jobs: uses: actions/checkout@v2 - name: Checkout Submodules - shell: bash run: | - #auth_header="$(git config --local --get http.https://github.com/.extraheader)" git submodule sync --recursive - #git -c "http.extraheader=$auth_header" -c protocol.version=2 submodule update --init --force --recursive git submodule update --init --recursive - name: Build diff --git a/.gitmodules b/.gitmodules index 32e537dce..c1c5cefe7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,7 +31,6 @@ [submodule "lib/CMSIS_5"] path = lib/CMSIS_5 url = https://github.com/ARM-software/CMSIS_5.git - branch = master [submodule "lib/CMSIS_4"] path = lib/CMSIS_4 url = https://github.com/ARM-software/CMSIS.git From 27efedc9e6304d429dbf9b4f481d1241cf310210 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Mon, 23 Mar 2020 23:45:22 -0400 Subject: [PATCH 68/71] msp_exp430f5529lp: Allow user to choose mspdebug as alternate programmer. --- hw/bsp/msp_exp430f5529lp/board.mk | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index ec393e0fc..b1264d346 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -16,11 +16,17 @@ INC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include VENDOR = ti CHIP_FAMILY = msp430x5xx +# Allow user to use mspdebug if set on make command line. +ifdef MSPDEBUG +# flash target using mspdebug. +flash: $(BUILD)/$(BOARD)-firmware.elf + $(MSPDEBUG) tilib "prog $<" --allow-fw-update +else # export for libmsp430.so to same installation export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher)) - # flash target using TI MSP430-Flasher # http://www.ti.com/tool/MSP430-FLASHER # Please add its installation dir to PATH flash: $(BUILD)/$(BOARD)-firmware.hex MSP430Flasher -w $< -z [VCC] +endif From 6b5157fd28a9495ee37fb2c84d29c1a61bb7c68b Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 24 Mar 2020 00:03:12 -0400 Subject: [PATCH 69/71] dcd_msp430x5xx: Add dummy dcd_edpt0_status_complete handler. Add comment which describes why it might be needed. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 26 ++++++++++++++------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 3a73cf9bf..d50fa17fe 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -1,8 +1,8 @@ /* * The MIT License (MIT) * - * Copyright (c) 2019 William D. Jones - * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2019-2020 William D. Jones + * Copyright (c) 2019-2020 Ha Thach (tinyusb.org) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -384,6 +384,22 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) } } +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) +{ + (void) rhport; + (void) request; + + // FIXME: Per manual, we should be clearing the NAK bits of EP0 after the + // Status Phase of a control xfer is done, in preparation of another possible + // SETUP packet. However, from my own testing, SETUP packets _are_ correctly + // handled by the USB core without clearing the NAKs. + // + // Right now, clearing NAKs in this callbacks causes a direction mismatch + // between host and device on EP0. Figure out why and come back to this. + // USBOEPCNT_0 &= ~NAK; + // USBIEPCNT_0 &= ~NAK; +} + /*------------------------------------------------------------------*/ static void receive_packet(uint8_t ep_num) @@ -563,12 +579,6 @@ void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void) // first place. When I first noticed the STALL, the only two places I // touched the NAK bits were in dcd_edpt_xfer() and to _set_ (sic) them in // bus_reset(). SETUP packet handling should've been unaffected. - // - // FIXME: Per manual, we should be clearing the NAK bits of EP0 after the - // Status Phase of a control xfer is done, in preparation of another - // possible SETUP packet. We don't do this right now, as there is no - // "Status Phase done" callback the driver can use. However, SETUP packets - // _are_ correctly handled by the USB core without clearing the NAKs. case USBVECINT_SETUP_PACKET_RECEIVED: break; From 7e78e47444c29b4d0c804877b28aa778fa0576c3 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 24 Mar 2020 00:40:25 -0400 Subject: [PATCH 70/71] msp_exp430f5529lp: Fix board.mk, remove .travis.yml.bck. --- .travis.yml.bck | 34 ------------------------------- examples/rules.mk | 1 - hw/bsp/msp_exp430f5529lp/board.mk | 15 +++++++------- 3 files changed, 8 insertions(+), 42 deletions(-) delete mode 100644 .travis.yml.bck diff --git a/.travis.yml.bck b/.travis.yml.bck deleted file mode 100644 index ab84d757e..000000000 --- a/.travis.yml.bck +++ /dev/null @@ -1,34 +0,0 @@ -language: c -dist: bionic -compiler: - - gcc - -addons: - apt: - sources: - - sourceline: "ppa:team-gcc-arm-embedded/ppa" - packages: - - python3 - - ruby - - gcc-arm-embedded - -install: - - gem install ceedling - -before_script: - - wget http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/8_3_0_0/exports/msp430-gcc-8.3.0.16_linux64.tar.bz2 -O /tmp/msp430-gcc.tar.bz2 - - tar -xjf /tmp/msp430-gcc.tar.bz2 - - export PATH=$PATH:$PWD/msp430-gcc-8.3.0.16_linux64/bin - - arm-none-eabi-gcc --version - - msp430-elf-gcc --version - -script: - # Build all examples - - python3 tools/build_all.py - # Run unit tests - - cd test - - ceedling test:all - - cd .. - -after_success: - - source tools/build_success.sh diff --git a/examples/rules.mk b/examples/rules.mk index 04cdef2d2..0343391cb 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -35,7 +35,6 @@ ifeq ($(BOARD), msp_exp430f5529lp) else LDFLAGS += $(CFLAGS) -fshort-enums -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nosys.specs -specs=nano.specs endif -LDFLAGS += $(addprefix -L,$(LDINC)) ASFLAGS += $(CFLAGS) # Assembly files can be name with upper case .S, convert it to .s diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index b1264d346..13e3b7217 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -9,6 +9,7 @@ CFLAGS += \ # All source paths should be relative to the top level. LD_FILE = hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld LDINC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include +LDFLAGS += $(addprefix -L,$(LDINC)) INC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include @@ -16,17 +17,17 @@ INC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include VENDOR = ti CHIP_FAMILY = msp430x5xx -# Allow user to use mspdebug if set on make command line. -ifdef MSPDEBUG -# flash target using mspdebug. -flash: $(BUILD)/$(BOARD)-firmware.elf - $(MSPDEBUG) tilib "prog $<" --allow-fw-update -else # export for libmsp430.so to same installation +ifneq ($(OS),Windows_NT) export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher)) +endif + # flash target using TI MSP430-Flasher # http://www.ti.com/tool/MSP430-FLASHER # Please add its installation dir to PATH flash: $(BUILD)/$(BOARD)-firmware.hex MSP430Flasher -w $< -z [VCC] -endif + +# flash target using mspdebug. +flash-mspdebug: $(BUILD)/$(BOARD)-firmware.elf + $(MSPDEBUG) tilib "prog $<" --allow-fw-update From 27ec8451a4104bdf03505c8bbd6d59d89e60273b Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Mar 2020 12:12:38 +0700 Subject: [PATCH 71/71] update doc for MSP430 --- CONTRIBUTORS.md | 6 +++--- README.md | 3 ++- docs/boards.md | 4 ++++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md index 6c83ef9c0..9802b162d 100644 --- a/CONTRIBUTORS.md +++ b/CONTRIBUTORS.md @@ -10,7 +10,7 @@ * **[Ha Thach](https://github.com/hathach)** * Author and maintainer - * Most features develpopment + * Most features development * **[Jeff Epler](https://github.com/jepler)** * Improvement to MIDI device driver @@ -54,8 +54,8 @@ * **[William D. Jones](https://github.com/cr1901)** * Synopsys DesignWare device driver port for STM32 L4, F2, F4, F7, H7 etc ... - * MSP430 device driver port (WIP) - * Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1 + * TI MSP430 device driver port + * Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1, msp_exp430f5529lp etc ... **[Full contributors list](https://github.com/hathach/tinyusb/contributors).** diff --git a/README.md b/README.md index 19106db3e..7d777b422 100644 --- a/README.md +++ b/README.md @@ -31,13 +31,14 @@ Special thanks to all the people who spent their precious time and effort to hel The stack supports the following MCUs: - **MicroChip:** SAMD21, SAMD51 (device only) -- **Nordic:** nRF52840, nRF52833 +- **NordicSemi:** nRF52840, nRF52833 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505 - **NXP:** - LPC Series: 11Uxx, 13xx, 175x_6x, 177x_8x, 18xx, 40xx, 43xx, 51Uxx, 54xxx, 55xx - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064 - **Sony:** CXD56 - **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 (device only) +- **TI:** MSP430 - **[ValentyUSB](https://github.com/im-tomu/valentyusb)** eptri [Here is the list of supported Boards](docs/boards.md) that can be used with provided examples. diff --git a/docs/boards.md b/docs/boards.md index 9667f6944..57e18950d 100644 --- a/docs/boards.md +++ b/docs/boards.md @@ -86,6 +86,10 @@ This code base already had supported for a handful of following boards (sorted a - [STM32 F767zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html) - [STM32 H743zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) +### TI + + - [MSP430F5529 USB LaunchPad Evaluation Kit](http://www.ti.com/tool/MSP-EXP430F5529LP) + ### Tomu - [Fomu](https://www.crowdsupply.com/sutajio-kosagi/fomu)