able to response with good crc

examples/typec/power_delivery/src/main.c

@@ -54,7 +54,7 @@ int main(void)
   board_init();
   board_led_write(true);
 
-  tuc_init(0, TYPEC_PORT_SNK);
+  tuc_init(0, TUSB_TYPEC_PORT_SNK);
 
   uint32_t start_ms = 0;
   bool led_state = false;

src/common/tusb_mcu.h

@@ -197,12 +197,17 @@
   #define TUP_DCD_ENDPOINT_MAX    9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  // Device controller
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
+
+  // TypeC controller
   #define TUP_USBIP_TYPEC_STM32
 
   #define TUP_DCD_ENDPOINT_MAX    8
 
+  #define TUP_TYPEC_RHPORTS_NUM 1
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32G0)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32

src/common/tusb_types.h

@@ -504,67 +504,75 @@ TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 //--------------------------------------------------------------------+
 
 typedef enum {
-  TYPEC_PORT_SRC,
+  TUSB_TYPEC_PORT_SRC,
-  TYPEC_PORT_SNK,
+  TUSB_TYPEC_PORT_SNK,
-  TYPEC_PORT_DRP
+  TUSB_TYPEC_PORT_DRP
-} typec_port_type_t;
+} tusb_typec_port_type_t;
 
 typedef enum {
-  TYPEC_MSG_CTRL_RESERVED = 0,            // 0b00000: 0
+  TUSB_PD_CTRL_RESERVED = 0,            // 0b00000: 0
-  TYPEC_MSG_CTRL_GOOD_CRC,                // 0b00001: 1
+  TUSB_PD_CTRL_GOOD_CRC,                // 0b00001: 1
-  TYPEC_MSG_CTRL_GO_TO_MIN,               // 0b00010: 2
+  TUSB_PD_CTRL_GO_TO_MIN,               // 0b00010: 2
-  TYPEC_MSG_CTRL_ACCEPT,                  // 0b00011: 3
+  TUSB_PD_CTRL_ACCEPT,                  // 0b00011: 3
-  TYPEC_MSG_CTRL_REJECT,                  // 0b00100: 4
+  TUSB_PD_CTRL_REJECT,                  // 0b00100: 4
-  TYPEC_MSG_CTRL_PING,                    // 0b00101: 5
+  TUSB_PD_CTRL_PING,                    // 0b00101: 5
-  TYPEC_MSG_CTRL_PS_RDY,                  // 0b00110: 6
+  TUSB_PD_CTRL_PS_RDY,                  // 0b00110: 6
-  TYPEC_MSG_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
+  TUSB_PD_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
-  TYPEC_MSG_CTRL_GET_SINK_CAP,            // 0b01000: 8
+  TUSB_PD_CTRL_GET_SINK_CAP,            // 0b01000: 8
-  TYPEC_MSG_CTRL_DR_SWAP,                 // 0b01001: 9
+  TUSB_PD_CTRL_DR_SWAP,                 // 0b01001: 9
-  TYPEC_MSG_CTRL_PR_SWAP,                 // 0b01010: 10
+  TUSB_PD_CTRL_PR_SWAP,                 // 0b01010: 10
-  TYPEC_MSG_CTRL_VCONN_SWAP,              // 0b01011: 11
+  TUSB_PD_CTRL_VCONN_SWAP,              // 0b01011: 11
-  TYPEC_MSG_CTRL_WAIT,                    // 0b01100: 12
+  TUSB_PD_CTRL_WAIT,                    // 0b01100: 12
-  TYPEC_MSG_CTRL_SOFT_RESET,              // 0b01101: 13
+  TUSB_PD_CTRL_SOFT_RESET,              // 0b01101: 13
-  TYPEC_MSG_CTRL_DATA_RESET,              // 0b01110: 14
+  TUSB_PD_CTRL_DATA_RESET,              // 0b01110: 14
-  TYPEC_MSG_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
+  TUSB_PD_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
-  TYPEC_MSG_CTRL_NOT_SUPPORTED,           // 0b10000: 16
+  TUSB_PD_CTRL_NOT_SUPPORTED,           // 0b10000: 16
-  TYPEC_MSG_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
+  TUSB_PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
-  TYPEC_MSG_CTRL_GET_STATUS,              // 0b10010: 18
+  TUSB_PD_CTRL_GET_STATUS,              // 0b10010: 18
-  TYPEC_MSG_CTRL_FR_SWAP,                 // 0b10011: 19
+  TUSB_PD_CTRL_FR_SWAP,                 // 0b10011: 19
-  TYPEC_MSG_CTRL_GET_PPS_STATUS,          // 0b10100: 20
+  TUSB_PD_CTRL_GET_PPS_STATUS,          // 0b10100: 20
-  TYPEC_MSG_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
+  TUSB_PD_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
-  TYPEC_MSG_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
+  TUSB_PD_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
-  TYPEC_MSG_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
+  TUSB_PD_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
-  TYPEC_MSG_CTRL_REVISION,                // 0b11000: 24
+  TUSB_PD_CTRL_REVISION,                // 0b11000: 24
-} typec_msg_ctrl_type_t;
+} tusb_pd_ctrl_type_t;
 
 typedef enum {
-  TYPEC_MSG_DATA_RESERVED = 0,     // 0b00000: 0
+  TUSB_PD_DATA_RESERVED = 0,     // 0b00000: 0
-  TYPEC_MSG_DATA_SOURCE_CAP,       // 0b00001: 1
+  TUSB_PD_DATA_SOURCE_CAP,       // 0b00001: 1
-  TYPEC_MSG_DATA_REQUEST,          // 0b00010: 2
+  TUSB_PD_DATA_REQUEST,          // 0b00010: 2
-  TYPEC_MSG_DATA_BIST,             // 0b00011: 3
+  TUSB_PD_DATA_BIST,             // 0b00011: 3
-  TYPEC_MSG_DATA_SINK_CAP,         // 0b00100: 4
+  TUSB_PD_DATA_SINK_CAP,         // 0b00100: 4
-  TYPEC_MSG_DATA_BATTERY_STATUS,   // 0b00101: 5
+  TUSB_PD_DATA_BATTERY_STATUS,   // 0b00101: 5
-  TYPEC_MSG_DATA_ALERT,            // 0b00110: 6
+  TUSB_PD_DATA_ALERT,            // 0b00110: 6
-  TYPEC_MSG_DATA_GET_COUNTRY_INFO, // 0b00111: 7
+  TUSB_PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7
-  TYPEC_MSG_DATA_ENTER_USB,        // 0b01000: 8
+  TUSB_PD_DATA_ENTER_USB,        // 0b01000: 8
-  TYPEC_MSG_DATA_EPR_REQUEST,      // 0b01001: 9
+  TUSB_PD_DATA_EPR_REQUEST,      // 0b01001: 9
-  TYPEC_MSG_DATA_EPR_MODE,         // 0b01010: 10
+  TUSB_PD_DATA_EPR_MODE,         // 0b01010: 10
-  TYPEC_MSG_DATA_SRC_INFO,         // 0b01011: 11
+  TUSB_PD_DATA_SRC_INFO,         // 0b01011: 11
-  TYPEC_MSG_DATA_REVISION,         // 0b01100: 12
+  TUSB_PD_DATA_REVISION,         // 0b01100: 12
-  TYPEC_MSG_DATA_RESERVED_13,      // 0b01101: 13
+  TUSB_PD_DATA_RESERVED_13,      // 0b01101: 13
-  TYPEC_MSG_DATA_RESERVED_14,      // 0b01110: 14
+  TUSB_PD_DATA_RESERVED_14,      // 0b01110: 14
-  TYPEC_MSG_DATA_VENDOR_DEFINED,   // 0b01111: 15
+  TUSB_PD_DATA_VENDOR_DEFINED,   // 0b01111: 15
-} typec_msg_data_type_t;
+} tusb_pd_data_type_t;
+
+enum {
+  TUSB_PD_REV10	= 0x0,
+  TUSB_PD_REV20	= 0x1,
+  TUSB_PD_REV30	= 0x2,
+};
 
 typedef struct TU_ATTR_PACKED {
   uint16_t msg_type   : 5; // [0:4]
-  uint16_t data_role  : 1; // [5] SOP only
+  uint16_t data_role  : 1; // [5] SOP only: 0 UFP, 1 DFP
   uint16_t specs_rev  : 2; // [6:7]
-  uint16_t power_role : 1; // [8] SOP only
+  uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source
   uint16_t msg_id     : 3; // [9:11]
   uint16_t n_data_obj : 3; // [12:14]
   uint16_t extended   : 1; // [15]
-} tusb_typec_message_header_t;
+} tusb_pd_header_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_pd_header_t) == 2, "size is not correct");
 
 typedef struct TU_ATTR_PACKED {
   uint16_t data_size     : 9; // [0:8]
@@ -572,7 +580,9 @@ typedef struct TU_ATTR_PACKED {
   uint16_t request_chunk : 1; // [10]
   uint16_t chunk_number  : 4; // [11:14]
   uint16_t chunked       : 1; // [15]
-} tusb_typec_message_header_extended_t;
+} tusb_pd_header_extended_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_pd_header_extended_t) == 2, "size is not correct");
 
 
 TU_ATTR_PACKED_END  // End of all packed definitions

src/device/usbd.c

@@ -252,9 +252,19 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
     drvid -= _app_driver_count;
   }
 
+  // when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wtype-limits"
+#endif
+
   // Built-in drivers
   if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
   return NULL;
 }
 

src/host/usbh.c

@@ -724,7 +724,7 @@ uint8_t* usbh_get_enum_buf(void)
 
 void usbh_int_set(bool enabled)
 {
-  // TODO all host controller if multiple is used
+  // TODO all host controller if multiple are used since they shared the same event queue
   if (enabled)
   {
     hcd_int_enable(_usbh_controller);

src/portable/st/typec/typec_stm32.c

@@ -29,20 +29,43 @@
 
 #include "common/tusb_common.h"
 
+#if CFG_TUSB_MCU == OPT_MCU_STM32G4
   #include "stm32g4xx.h"
-
+#else
-//--------------------------------------------------------------------+
+  #error "Unsupported STM32 family"
-//
+#endif
-//--------------------------------------------------------------------+
-uint8_t pd_rx_buf[262];
-uint32_t pd_rx_count = 0;
-uint8_t pd_rx_order_set;
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
-bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
+#define PHY_SYNC1 0x18u
+#define PHY_SYNC2 0x11u
+#define PHY_SYNC3 0x06u
+#define PHY_RST1  0x07u
+#define PHY_RST2  0x19u
+#define PHY_EOP   0x0Du
+
+#define PHY_ORDERED_SET_SOP          (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC2<<15u)) // SOP Ordered set coding
+#define PHY_ORDERED_SET_SOP_P        (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC3<<15u)) // SOP' Ordered set coding
+#define PHY_ORDERED_SET_SOP_PP       (PHY_SYNC1 | (PHY_SYNC3<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC3<<15u)) // SOP'' Ordered set coding
+#define PHY_ORDERED_SET_HARD_RESET   (PHY_RST1  | (PHY_RST1<<5u)  | (PHY_RST1<<10u)  | (PHY_RST2<<15u )) // Hard Reset Ordered set coding
+#define PHY_ORDERED_SET_CABLE_RESET  (PHY_RST1  | (PHY_SYNC1<<5u) | (PHY_RST1<<10u)  | (PHY_SYNC3<<15u)) // Cable Reset Ordered set coding
+#define PHY_ORDERED_SET_SOP_P_DEBUG  (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_RST2<<10u)  | (PHY_SYNC3<<15u)) // SOP' Debug Ordered set coding
+#define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding
+
+
+static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4);
+static uint32_t rx_count = 0;
+
+static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
+static uint32_t tx_count;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   (void) rhport;
 
   // Initialization phase: CFG1
@@ -52,7 +75,7 @@ bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
   UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
 
   // General programming sequence (with UCPD configured then enabled)
-  if (port_type == TYPEC_PORT_SNK) {
+  if (port_type == TUSB_TYPEC_PORT_SNK) {
     // Enable both CC Phy
     UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
 
@@ -83,6 +106,19 @@ void tcd_int_disable(uint8_t rhport) {
   NVIC_DisableIRQ(UCPD1_IRQn);
 }
 
+bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
+  (void) rhport;
+
+  return true;
+}
+
+bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
+  (void) rhport;
+  (void) buffer;
+  (void) total_bytes;
+  return false;
+}
+
 void tcd_int_handler(uint8_t rhport) {
   (void) rhport;
 
@@ -116,7 +152,7 @@ void tcd_int_handler(uint8_t rhport) {
 
     if (cr & UCPD_CR_PHYRXEN) {
       // Enable Interrupt
-      UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+      UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
                     UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
                     UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
     }
@@ -128,13 +164,13 @@ void tcd_int_handler(uint8_t rhport) {
     UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
   }
 
-  //------------- Receive -------------//
+  //------------- RX -------------//
   if (sr & UCPD_SR_RXORDDET) {
     // SOP: Start of Packet.
-    pd_rx_order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
+    // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
 
     // reset count when received SOP
-    pd_rx_count = 0;
+    rx_count = 0;
 
     // ack
     UCPD1->ICR = UCPD_ICR_RXORDDETCF;
@@ -143,17 +179,38 @@ void tcd_int_handler(uint8_t rhport) {
   if (sr & UCPD_SR_RXNE) {
     // TODO DMA later
     do {
-      pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
+      rx_buf[rx_count++] = UCPD1->RXDR;
     } while (UCPD1->SR & UCPD_SR_RXNE);
+
+    // no ack needed
   }
 
-  if (sr & UCPD_SR_RXMSGEND) {
   // End of message
+  if (sr & UCPD_SR_RXMSGEND) {
 
     // Skip if CRC failed
     if (!(sr & UCPD_SR_RXERR)) {
       uint32_t payload_size = UCPD1->RX_PAYSZ;
-      TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
+      // TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
+
+      tusb_pd_header_t const* rx_header = (tusb_pd_header_t const*) rx_buf;
+      (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) {
+          .msg_type = TUSB_PD_CTRL_GOOD_CRC,
+          .data_role = 0, // UFP
+          .specs_rev = TUSB_PD_REV30,
+          .power_role = 0, // Sink
+          .msg_id = rx_header->msg_id,
+          .n_data_obj = 0,
+          .extended = 0
+      };
+      tx_count = 0;
+
+      // response with good crc
+      UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
+      UCPD1->TX_PAYSZ = 2;
+      UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt
+
+      // notify stack after good crc ?
     }
 
     // ack
@@ -162,11 +219,31 @@ void tcd_int_handler(uint8_t rhport) {
 
   if (sr & UCPD_SR_RXOVR) {
     TU_LOG1("RXOVR\n");
-    TU_LOG1_HEX(pd_rx_count);
+    TU_LOG1_HEX(rx_count);
     // ack
     UCPD1->ICR = UCPD_ICR_RXOVRCF;
   }
 
+  //------------- TX -------------//
+  if (sr & UCPD_SR_TXIS) {
+    // TU_LOG1("TXIS\n");
+
+    // TODO DMA later
+    do {
+      UCPD1->TXDR = tx_buf[tx_count++];
+    } while (UCPD1->SR & UCPD_SR_TXIS);
+
+    // no ack needed
+  }
+
+  if (sr & UCPD_SR_TXMSGSENT) {
+    // all byte sent
+    TU_LOG1("TXMSGSENT\n");
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
+  }
+
 //  if (sr & UCPD_SR_RXNE) {
 //    uint8_t data = UCPD1->RXDR;
 //    pd_rx_buf[pd_rx_count++] = data;

src/typec/tcd.h

@@ -38,13 +38,19 @@ extern "C" {
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+typedef struct {
+  uint8_t rhport;
+  uint8_t event_id;
+
+
+} tcd_event_t;;
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
 // Initialize controller
-bool tcd_init(uint8_t rhport, typec_port_type_t port_type);
+bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type);
 
 // Enable interrupt
 void tcd_int_enable (uint8_t rhport);
@@ -55,4 +61,11 @@ void tcd_int_disable(uint8_t rhport);
 // Interrupt Handler
 void tcd_int_handler(uint8_t rhport);
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
+bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
+
 #endif

src/typec/utcd.c

@@ -29,20 +29,75 @@
 #if CFG_TUC_ENABLED
 
 #include "tcd.h"
+#include "utcd.h"
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
+// Debug level of USBD
+#define UTCD_DEBUG   2
+#define TU_LOG_UTCD(...)   TU_LOG(UTCD_DEBUG, __VA_ARGS__)
+
+// Event queue
+// utcd_int_set() is used as mutex in OS NONE config
+void utcd_int_set(bool enabled);
+OSAL_QUEUE_DEF(utcd_int_set, utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
+tu_static osal_queue_t utcd_q;
+
+// if stack is initialized
+static bool utcd_inited = false;
+
+// if port is initialized
+static bool port_inited[TUP_TYPEC_RHPORTS_NUM];
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+bool tuc_inited(uint8_t rhport) {
+  return utcd_inited && port_inited[rhport];
+}
 
-bool tuc_init(uint8_t rhport, typec_port_type_t port_type) {
+bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
-  TU_ASSERT(tcd_init(rhport, port_type));
+  // Initialize stack
-  tcd_int_enable(rhport);
+  if (!utcd_inited) {
+    tu_memclr(port_inited, sizeof(port_inited));
+
+    utcd_q = osal_queue_create(&utcd_qdef);
+    TU_ASSERT(utcd_q != NULL);
+
+    utcd_inited = true;
+  }
+
+  // skip if port already initialized
+  if ( port_inited[rhport] ) {
     return true;
   }
 
+  TU_LOG_UTCD("UTCD init on port %u\r\n", rhport);
+
+  TU_ASSERT(tcd_init(rhport, port_type));
+  tcd_int_enable(rhport);
+
+  port_inited[rhport] = true;
+  return true;
+}
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+void utcd_int_set(bool enabled) {
+  // Disable all controllers since they shared the same event queue
+  for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) {
+    if ( port_inited[p] ) {
+      if (enabled) {
+        tcd_int_enable(p);
+      }else {
+        tcd_int_disable(p);
+      }
+    }
+  }
+}
+
 #endif

src/typec/utcd.h

@@ -33,12 +33,24 @@
 extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// TypeC Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUC_TASK_QUEUE_SZ
+#define CFG_TUC_TASK_QUEUE_SZ   16
+#endif
+
+
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
 
-// init typec stack
+// Init typec stack on a port
-bool tuc_init(uint8_t rhport, typec_port_type_t port_type);
+bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type);
+
+// Check if typec port is initialized
+bool tuc_inited(uint8_t rhport);
 
 #ifndef _TUSB_TCD_H_
 extern void tcd_int_handler(uint8_t rhport);