add CFG_TUD_DWC2_SLAVE_ENABLE = 1 as default

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hathach 2024-11-18 23:15:17 +07:00
parent 6d4a60d8ac
commit ac9bc01132
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@ -247,6 +247,10 @@
// USBIP
//--------------------------------------------------------------------+
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
#define CFG_TUD_DWC2_SLAVE_ENABLE 1
#endif
// DWC2 controller: use DMA for data transfer
// For processors with data cache enabled, USB endpoint buffer region
// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.