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Merge pull request #2466 from wavenumber-eng/MCX

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TinyUSB stack ported to MCXA and MXCN freedom boards.
This commit is contained in:
Ha Thach 2024-04-08 12:30:25 +07:00 committed by GitHub
commit af1346c748
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30 changed files with 1919 additions and 64 deletions
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2
README.rst
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@ -139,7 +139,7 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l
| +---------+--------------------------------------------------+
| | LPC | 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55 |
| +---------+--------------------------------------------------+
| | MCX | N9 |
| | MCX | A15, N9 |
+--------------+---------+--------------------------------------------------+
| Raspberry Pi | RP2040 |
+--------------+-----+------------------------------------------------------+

4
examples/build_system/cmake/cpu/cortex-m23.cmake
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@ -5,13 +5,13 @@ if (TOOLCHAIN STREQUAL "gcc")
-mfloat-abi=soft
)
set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
set(FREERTOS_PORT GCC_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
elseif (TOOLCHAIN STREQUAL "iar")
set(TOOLCHAIN_COMMON_FLAGS
--cpu cortex-m23
)
set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
set(FREERTOS_PORT IAR_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
endif ()

17
examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake Normal file
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@ -0,0 +1,17 @@
if (TOOLCHAIN STREQUAL "gcc")
set(TOOLCHAIN_COMMON_FLAGS
-mthumb
-mcpu=cortex-m33+nodsp
-mfloat-abi=soft
)
set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
elseif (TOOLCHAIN STREQUAL "iar")
set(TOOLCHAIN_COMMON_FLAGS
--cpu cortex-m33+nodsp
)
set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
endif ()

2
examples/build_system/cmake/cpu/cortex-m33.cmake
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@ -14,6 +14,6 @@ elseif (TOOLCHAIN STREQUAL "iar")
--fpu VFPv5-SP
)
set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
endif ()

16
examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk Normal file
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@ -0,0 +1,16 @@
ifeq ($(TOOLCHAIN),gcc)
CFLAGS += \
-mthumb \
-mcpu=cortex-m33+nodsp \
-mfloat-abi=soft \
else ifeq ($(TOOLCHAIN),iar)
CFLAGS += \
--cpu cortex-m33+nodsp \
ASFLAGS += \
--cpu cortex-m33+nodsp \
endif
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure

6
hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
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@ -49,7 +49,11 @@
/* Cortex M23/M33 port configuration. */
#define configENABLE_MPU 0
#define configENABLE_FPU 1
#if defined(__ARM_FP) && __ARM_FP >= 4
#define configENABLE_FPU 1
#else
#define configENABLE_FPU 0
#endif
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE (1024)

21
hw/bsp/mcx/boards/frdm_mcxa153/board.cmake Normal file
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@ -0,0 +1,21 @@
set(MCU_VARIANT MCXA153)
set(MCU_CORE MCXA153)
set(JLINK_DEVICE MCXA153_M33)
set(PYOCD_TARGET MCXA153)
set(NXPLINK_DEVICE MCXA153:MCXA153)
set(PORT 0)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXA153VLH
BOARD_TUD_RHPORT=0
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
CFG_EXAMPLE_VIDEO_READONLY
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
endfunction()

64
hw/bsp/mcx/boards/frdm_mcxa153/board.h Normal file
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@ -0,0 +1,64 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO3
#define LED_CLK kCLOCK_GateGPIO3
#define LED_PIN 12 // red
#define LED_STATE_ON 0
// ISP button (Dummy, use unused pin
#define BUTTON_GPIO GPIO3
#define BUTTON_CLK kCLOCK_GateGPIO3
#define BUTTON_PIN 29 //sw2
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART0
static inline void board_uart_init_clock(void) {
/* attach 12 MHz clock to LPUART0 (debug console) */
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
}
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

14
hw/bsp/mcx/boards/frdm_mcxa153/board.mk Normal file
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@ -0,0 +1,14 @@
MCU_VARIANT = MCXA153
MCU_CORE = MCXA153
PORT = 0
CPU_CORE = cortex-m33-nodsp-nofp
CFLAGS += \
-DCPU_MCXA153VLH \
-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
JLINK_DEVICE = MCXA153
PYOCD_TARGET = MCXA153
# flash using pyocd
flash: flash-jlink

468
hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c Normal file
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@ -0,0 +1,468 @@
/*
* Copyright 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v12.0
processor: MCXA153
package_id: MCXA153VLH
mcu_data: ksdk2_0
processor_version: 0.13.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_clock.h"
#include "clock_config.h"
#include "fsl_spc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
//uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockFRO96M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CPU_clock.outFreq, value: 12 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO24M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 6 MHz}
- {id: System_clock.outFreq, value: 24 MHz}
settings:
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO24M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO24M configuration
******************************************************************************/
void BOARD_BootClockFRO24M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO48M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO48M configuration
******************************************************************************/
void BOARD_BootClockFRO48M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO64M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 64 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
- {id: FRO_HF_clock.outFreq, value: 64 MHz}
- {id: MAIN_clock.outFreq, value: 64 MHz}
- {id: Slow_clock.outFreq, value: 16 MHz}
- {id: System_clock.outFreq, value: 64 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 64 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO64M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO64M configuration
******************************************************************************/
void BOARD_BootClockFRO64M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO96M
called_from_default_init: true
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 96 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
- {id: FRO_HF_clock.outFreq, value: 96 MHz}
- {id: MAIN_clock.outFreq, value: 96 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 96 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: CLKOUTDIV_HALT, value: Enable}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 96 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO96M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO96M configuration
******************************************************************************/
void BOARD_BootClockFRO96M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
}

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/*
* Copyright 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO24M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO24M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO24M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO64M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO64M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO64M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO96M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO96M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO96M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/*
* Copyright 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v14.0
processor: MCXA153
package_id: MCXA153VLH
mcu_data: ksdk2_0
processor_version: 0.14.3
pin_labels:
- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
/* write to PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* Write to GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO3);
/* Write to PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT3);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as P3_12 */
kPORT_MuxAlt0,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT3_12 (pin 38) is configured as P3_12 */
PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_RXD */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_2 (pin 51) is configured as LPUART0_RXD */
PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config);
const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_TXD */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_3 (pin 52) is configured as LPUART0_TXD */
PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

47
hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h Normal file
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/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

21
hw/bsp/mcx/boards/frdm_mcxn947/board.cmake Normal file
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set(MCU_VARIANT MCXN947)
set(MCU_CORE MCXN947_cm33_core0)
set(JLINK_DEVICE MCXN947_M33_0)
set(PYOCD_TARGET MCXN947)
set(NXPLINK_DEVICE MCXN947:MCXN947)
set(PORT 1)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXN947VDF_cm33_core0
BOARD_TUD_RHPORT=${PORT}
# port 0 is fullspeed, port 1 is highspeed
BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
endfunction()

66
hw/bsp/mcx/boards/frdm_mcxn947/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO0
#define LED_CLK kCLOCK_Gpio0
#define LED_PIN 10 // red
#define LED_STATE_ON 0
// WAKE button (Dummy, use unused pin
#define BUTTON_GPIO GPIO0
#define BUTTON_CLK kCLOCK_Gpio0
#define BUTTON_PIN 23
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART4
static inline void board_uart_init_clock(void) {
/* attach FRO 12M to FLEXCOMM4 */
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
}
//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN
//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

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hw/bsp/mcx/boards/frdm_mcxn947/board.mk Normal file
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MCU_VARIANT = MCXN947
MCU_CORE = MCXN947_cm33_core0
PORT ?= 1
CPU_CORE = cortex-m33
CFLAGS += \
-DCPU_MCXN947VDF_cm33_core0 \
-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
JLINK_DEVICE = MCXN947_M33_0
PYOCD_TARGET = MCXN947
# flash using pyocd
flash: flash-jlink

338
hw/bsp/mcx/boards/frdm_mcxn947/clock_config.c Normal file
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/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v10.0
processor: MCXN947
package_id: MCXN947VDF
mcu_data: ksdk2_0
processor_version: 0.12.3
board: MCX-N9XX-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "clock_config.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
// extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockPLL150M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF48M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF48M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF48M configuration
******************************************************************************/
void BOARD_BootClockFROHF48M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF144M ********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF144M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 144 MHz}
- {id: MAIN_clock.outFreq, value: 144 MHz}
- {id: Slow_clock.outFreq, value: 18 MHz}
- {id: System_clock.outFreq, value: 72 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
sources:
- {id: SCG.FIRC.outFreq, value: 144 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF144M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF144M configuration
******************************************************************************/
void BOARD_BootClockFROHF144M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U); /*!< Set AHBCLKDIV divider to value 2 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL150M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL150M
called_from_default_init: true
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 150 MHz}
- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
- {id: Slow_clock.outFreq, value: 37.5 MHz}
- {id: System_clock.outFreq, value: 150 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: RunPowerMode, value: OD}
- {id: SCGMode, value: PLL0}
- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL150M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL150M configuration
******************************************************************************/
void BOARD_BootClockPLL150M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
/*!< Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL100M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CLK_IN_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 100 MHz}
- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
- {id: Slow_clock.outFreq, value: 25 MHz}
- {id: System_clock.outFreq, value: 100 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: PLL1_Mode, value: Normal}
- {id: SCGMode, value: PLL1}
- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
sources:
- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL100M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL100M configuration
******************************************************************************/
void BOARD_BootClockPLL100M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupExtClocking(24000000U);
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
/*!< Set up PLL1 */
const pll_setup_t pll1Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
.pllndiv = SCG_SPLLNDIV_NDIV(6U),
.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
.pllRate = 100000000U
};
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
}

177
hw/bsp/mcx/boards/frdm_mcxn947/clock_config.h Normal file
View File

@ -0,0 +1,177 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF48M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF144M ********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF144M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF144M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF144M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL150M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL150M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL150M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL150M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL100M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL100M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL100M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

143
hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.c Normal file
View File

@ -0,0 +1,143 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v12.0
processor: MCXN947
package_id: MCXN947VDF
mcu_data: ksdk2_0
processor_version: 0.12.3
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
invert_input: normal}
- {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
/* Enables the clock for PORT0: Enables clock */
CLOCK_EnableClock(kCLOCK_Port0);
/* Enables the clock for PORT1: Enables clock */
CLOCK_EnableClock(kCLOCK_Port1);
const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as FC4_P0 */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT1_8 (pin A1) is configured as FC4_P0 */
PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as FC4_P1 */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT1_9 (pin B1) is configured as FC4_P1 */
PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PIO0_23 */
kPORT_MuxAlt0,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_23 (pin B7) is configured as PIO0_23 */
PORT_SetPinConfig(PORT0, 23U, &SW2);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

51
hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.h Normal file
View File

@ -0,0 +1,51 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

5
hw/bsp/mcx/boards/mcxn947brk/board.mk
View File

@ -2,7 +2,10 @@ MCU_VARIANT = MCXN947
MCU_CORE = MCXN947_cm33_core0
PORT ?= 1
CFLAGS += -DCPU_MCXN947VDF_cm33_core0
CPU_CORE = cortex-m33
CFLAGS += \
-DCPU_MCXN947VDF_cm33_core0 \
-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
JLINK_DEVICE = MCXN947_M33_0
PYOCD_TARGET = MCXN947

86
hw/bsp/mcx/family.c
View File

@ -33,6 +33,10 @@
#include "pin_mux.h"
#include "clock_config.h"
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
#ifdef BOARD_TUD_RHPORT
#define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
#else
@ -45,44 +49,50 @@
#define PORT_SUPPORT_HOST(_n) 0
#endif
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
void USB0_FS_IRQHandler(void)
{
#if CFG_TUSB_MCU == OPT_MCU_MCXN9
void USB0_FS_IRQHandler(void) {
tud_int_handler(0);
}
void USB1_HS_IRQHandler(void)
{
void USB1_HS_IRQHandler(void) {
tud_int_handler(1);
}
void board_init(void)
{
#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
void USB0_IRQHandler(void) {
tud_int_handler(0);
}
#endif
void board_init(void) {
BOARD_InitPins();
BOARD_InitBootClocks();
CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#if CFG_TUSB_OS == OPT_OS_FREERTOS
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#if CFG_TUSB_MCU == OPT_MCU_MCXN9
NVIC_SetPriority(USB0_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#else
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
#endif
// LED
CLOCK_EnableClock(LED_CLK);
gpio_pin_config_t led_config = {
kGPIO_DigitalOutput,
0,
};
GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
board_led_write(0);
#ifdef NEOPIXEL_PIN
@ -100,7 +110,7 @@ void board_init(void)
// Button
#ifdef BUTTON_GPIO
CLOCK_EnableClock(BUTTON_CLK);
gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
#endif
@ -115,8 +125,8 @@ void board_init(void)
lpuart_config_t uart_config;
LPUART_GetDefaultConfig(&uart_config);
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
uart_config.enableTx = true;
uart_config.enableRx = true;
uart_config.enableTx = true;
uart_config.enableRx = true;
LPUART_Init(UART_DEV, &uart_config, 12000000u);
#endif
@ -126,13 +136,18 @@ void board_init(void)
#if PORT_SUPPORT_DEVICE(0)
// Port0 is Full Speed
#if CFG_TUSB_MCU == OPT_MCU_MCXA15
RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
#elif CFG_TUSB_MCU == OPT_MCU_MCXN9
CLOCK_AttachClk(kCLK_48M_to_USB0);
CLOCK_EnableClock(kCLOCK_Usb0Ram);
CLOCK_EnableClock(kCLOCK_Usb0Fs);
#endif
CLOCK_EnableUsbfsClock();
#endif
#if PORT_SUPPORT_DEVICE(1)
#if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
// Port1 is High Speed
// Power
@ -191,9 +206,8 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
void board_led_write(bool state) {
GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
#ifdef NEOPIXEL_PIN
if (state) {
@ -207,23 +221,21 @@ void board_led_write(bool state)
#endif
}
uint32_t board_button_read(void)
{
uint32_t board_button_read(void) {
#ifdef BUTTON_GPIO
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
#endif
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf; (void) len;
int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
int board_uart_write(void const* buf, int len) {
#ifdef UART_DEV
LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
LPUART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
return len;
#else
(void) buf; (void) len;
@ -233,13 +245,13 @@ int board_uart_write(void const * buf, int len)
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler(void)
{
void SysTick_Handler(void) {
system_ticks++;
}
uint32_t board_millis(void)
{
uint32_t board_millis(void) {
return system_ticks;
}
#endif

34
hw/bsp/mcx/family.cmake
View File

@ -11,12 +11,18 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
if (MCU_VARIANT STREQUAL "MCXA153")
set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
elseif (MCU_VARIANT STREQUAL "MCXN947")
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
else()
message(FATAL_ERROR "MCU_VARIANT not supported")
endif()
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
#------------------------------------
# BOARD_TARGET
#------------------------------------
@ -31,12 +37,23 @@ function(add_board_target BOARD_TARGET)
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
)
if (${FAMILY_MCUS} STREQUAL "MCXN9")
target_sources(${BOARD_TARGET} PRIVATE
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
)
elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
target_sources(${BOARD_TARGET} PRIVATE
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c
)
endif()
# target_compile_definitions(${BOARD_TARGET} PUBLIC
# )
target_include_directories(${BOARD_TARGET} PUBLIC
@ -93,7 +110,12 @@ function(family_configure_example TARGET RTOS)
)
# Add TinyUSB target and port source
family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
if (${FAMILY_MCUS} STREQUAL "MCXN9")
family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
family_add_tinyusb(${TARGET} OPT_MCU_MCXA15 ${RTOS})
endif()
target_sources(${TARGET}-tinyusb PUBLIC
# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>

15
hw/bsp/mcx/family.mk
View File

@ -4,14 +4,12 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m33
# Default to Highspeed PORT1
PORT ?= 1
CFLAGS += \
-flto \
-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
-DBOARD_TUD_RHPORT=$(PORT) \
# mcu driver cause following warnings
@ -38,9 +36,18 @@ SRC_C += \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
# fsl_lpflexcomm for MCXN9
ifeq ($(MCU_VARIANT), MCXN947)
SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
endif
# fsl_spc for MCXNA15
ifeq ($(MCU_VARIANT), MCXA153)
SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
endif
INC += \
$(TOP)/$(BOARD_PATH) \

6
hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
View File

@ -64,7 +64,11 @@
/* Cortex M23/M33 port configuration. */
#define configENABLE_MPU 0
#define configENABLE_FPU 1
#if defined(__ARM_FP) && __ARM_FP >= 4
#define configENABLE_FPU 1
#else
#define configENABLE_FPU 0
#endif
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE (1024)

7
src/common/tusb_mcu.h
View File

@ -100,6 +100,13 @@
#define TUP_DCD_ENDPOINT_MAX 8
#define TUP_RHPORT_HIGHSPEED 1
#elif TU_CHECK_MCU(OPT_MCU_MCXA15)
// USB0 is chipidea FS
#define TUP_USBIP_CHIPIDEA_FS
#define TUP_USBIP_CHIPIDEA_FS_MCX
#define TUP_DCD_ENDPOINT_MAX 16
#elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
#define TUP_USBIP_CHIPIDEA_HS
#define TUP_USBIP_EHCI

25
src/portable/chipidea/ci_fs/ci_fs_mcx.h
View File

@ -29,19 +29,28 @@
#include "fsl_device_registers.h"
#define CI_FS_REG(_port) ((ci_fs_regs_t*) USBFS0_BASE)
#define CI_REG CI_FS_REG(0)
#if CFG_TUSB_MCU == OPT_MCU_MCXN9
#define CI_FS_REG(_port) ((ci_fs_regs_t*) USBFS0_BASE)
#define CIFS_IRQN USB0_FS_IRQn
void dcd_int_enable(uint8_t rhport)
{
#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
#define CI_FS_REG(_port) ((ci_fs_regs_t*) USB0_BASE)
#define CIFS_IRQN USB0_IRQn
#else
#error "MCU is not supported"
#endif
#define CI_REG CI_FS_REG(0)
void dcd_int_enable(uint8_t rhport) {
(void) rhport;
NVIC_EnableIRQ(USB0_FS_IRQn);
NVIC_EnableIRQ(CIFS_IRQN);
}
void dcd_int_disable(uint8_t rhport)
{
void dcd_int_disable(uint8_t rhport) {
(void) rhport;
NVIC_DisableIRQ(USB0_FS_IRQn);
NVIC_DisableIRQ(CIFS_IRQN);
}
#endif

2
src/portable/chipidea/ci_fs/dcd_ci_fs.c
View File

@ -295,7 +295,7 @@ void dcd_init(uint8_t rhport)
CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK;
dcd_connect(rhport);
// NVIC_ClearPendingIRQ(USB0_IRQn);
// NVIC_ClearPendingIRQ(CIFS_IRQN);
}
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)

1
src/tusb_option.h
View File

@ -180,6 +180,7 @@
// NXP LPC MCX
#define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series
#define OPT_MCU_MCXA15 2301 ///< NXP MCX A15 Series
// Check if configured MCU is one of listed
// Apply _TU_CHECK_MCU with || as separator to list of input

2
tools/get_deps.py
View File

@ -51,7 +51,7 @@ deps_optional = {
'84e0bd3e43910aaf71eefd62075cf57495418312',
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
'950819b7de9b32f92c3edf396bc5ffb8d66e7009',
'144f1eb7ea8c06512e12f12b27383601c0272410',
'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
'0f747aaa0c16f750bdfa2ba37ec25d6c8e1bc117',